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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
da34e65c | 30 | #include "qapi/error.h" |
f5d8c8cd | 31 | #include "qemu-common.h" |
f5d8c8cd SZ |
32 | #include "qemu/bitmap.h" |
33 | #include "trace.h" | |
34 | #include "qom/cpu.h" | |
fcf5ef2a | 35 | #include "target/arm/cpu.h" |
f5d8c8cd SZ |
36 | #include "hw/acpi/acpi-defs.h" |
37 | #include "hw/acpi/acpi.h" | |
38 | #include "hw/nvram/fw_cfg.h" | |
39 | #include "hw/acpi/bios-linker-loader.h" | |
40 | #include "hw/loader.h" | |
41 | #include "hw/hw.h" | |
42 | #include "hw/acpi/aml-build.h" | |
84344884 | 43 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 44 | #include "hw/pci/pci.h" |
d05fdab4 | 45 | #include "hw/arm/virt.h" |
2b302e1e | 46 | #include "sysemu/numa.h" |
13e5c54d | 47 | #include "kvm_arm.h" |
f5d8c8cd | 48 | |
dfccd8cf | 49 | #define ARM_SPI_BASE 32 |
ac6aa59a | 50 | #define ACPI_POWER_BUTTON_DEVICE "PWRB" |
dfccd8cf SZ |
51 | |
52 | static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) | |
53 | { | |
54 | uint16_t i; | |
55 | ||
56 | for (i = 0; i < smp_cpus; i++) { | |
f460be43 | 57 | Aml *dev = aml_device("C%.03X", i); |
dfccd8cf SZ |
58 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); |
59 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
60 | aml_append(scope, dev); | |
61 | } | |
62 | } | |
63 | ||
64 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 65 | uint32_t uart_irq) |
dfccd8cf SZ |
66 | { |
67 | Aml *dev = aml_device("COM0"); | |
68 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
69 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
70 | ||
71 | Aml *crs = aml_resource_template(); | |
72 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
73 | uart_memmap->size, AML_READ_WRITE)); | |
74 | aml_append(crs, | |
75 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 76 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 77 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d AJ |
78 | |
79 | /* The _ADR entry is used to link this device to the UART described | |
80 | * in the SPCR table, i.e. SPCR.base_address.address == _ADR. | |
81 | */ | |
82 | aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); | |
83 | ||
dfccd8cf SZ |
84 | aml_append(scope, dev); |
85 | } | |
86 | ||
70bee80d GS |
87 | static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) |
88 | { | |
89 | Aml *dev = aml_device("FWCF"); | |
90 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); | |
91 | /* device present, functioning, decoding, not shown in UI */ | |
92 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
93 | ||
94 | Aml *crs = aml_resource_template(); | |
95 | aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, | |
96 | fw_cfg_memmap->size, AML_READ_WRITE)); | |
97 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
98 | aml_append(scope, dev); | |
99 | } | |
100 | ||
dfccd8cf SZ |
101 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
102 | { | |
103 | Aml *dev, *crs; | |
104 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 105 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
106 | |
107 | dev = aml_device("FLS0"); | |
108 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
109 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
110 | ||
111 | crs = aml_resource_template(); | |
112 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
113 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
114 | aml_append(scope, dev); | |
115 | ||
116 | dev = aml_device("FLS1"); | |
117 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
118 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
119 | crs = aml_resource_template(); | |
120 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
121 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
122 | aml_append(scope, dev); | |
123 | } | |
124 | ||
125 | static void acpi_dsdt_add_virtio(Aml *scope, | |
126 | const MemMapEntry *virtio_mmio_memmap, | |
45fcf539 | 127 | uint32_t mmio_irq, int num) |
dfccd8cf SZ |
128 | { |
129 | hwaddr base = virtio_mmio_memmap->base; | |
130 | hwaddr size = virtio_mmio_memmap->size; | |
dfccd8cf SZ |
131 | int i; |
132 | ||
133 | for (i = 0; i < num; i++) { | |
45fcf539 | 134 | uint32_t irq = mmio_irq + i; |
dfccd8cf SZ |
135 | Aml *dev = aml_device("VR%02u", i); |
136 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | |
137 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
76266d99 | 138 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
dfccd8cf SZ |
139 | |
140 | Aml *crs = aml_resource_template(); | |
141 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
142 | aml_append(crs, | |
143 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 144 | AML_EXCLUSIVE, &irq, 1)); |
dfccd8cf SZ |
145 | aml_append(dev, aml_name_decl("_CRS", crs)); |
146 | aml_append(scope, dev); | |
147 | base += size; | |
148 | } | |
149 | } | |
150 | ||
45fcf539 IM |
151 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
152 | uint32_t irq, bool use_highmem) | |
d4e5de1a SZ |
153 | { |
154 | Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; | |
155 | int i, bus_no; | |
156 | hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; | |
157 | hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; | |
158 | hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; | |
159 | hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; | |
160 | hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; | |
161 | hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; | |
162 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
163 | ||
164 | Aml *dev = aml_device("%s", "PCI0"); | |
165 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); | |
166 | aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); | |
167 | aml_append(dev, aml_name_decl("_SEG", aml_int(0))); | |
168 | aml_append(dev, aml_name_decl("_BBN", aml_int(0))); | |
169 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
170 | aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); | |
171 | aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); | |
bc64b96c | 172 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
d4e5de1a SZ |
173 | |
174 | /* Declare the PCI Routing Table. */ | |
175 | Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); | |
176 | for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { | |
177 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
178 | int gsi = (i + bus_no) % PCI_NUM_PINS; | |
179 | Aml *pkg = aml_package(4); | |
180 | aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); | |
181 | aml_append(pkg, aml_int(i)); | |
182 | aml_append(pkg, aml_name("GSI%d", gsi)); | |
183 | aml_append(pkg, aml_int(0)); | |
184 | aml_append(rt_pkg, pkg); | |
185 | } | |
186 | } | |
187 | aml_append(dev, aml_name_decl("_PRT", rt_pkg)); | |
188 | ||
189 | /* Create GSI link device */ | |
190 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
45fcf539 | 191 | uint32_t irqs = irq + i; |
d4e5de1a SZ |
192 | Aml *dev_gsi = aml_device("GSI%d", i); |
193 | aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); | |
194 | aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); | |
195 | crs = aml_resource_template(); | |
196 | aml_append(crs, | |
197 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 198 | AML_EXCLUSIVE, &irqs, 1)); |
d4e5de1a SZ |
199 | aml_append(dev_gsi, aml_name_decl("_PRS", crs)); |
200 | crs = aml_resource_template(); | |
201 | aml_append(crs, | |
202 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 203 | AML_EXCLUSIVE, &irqs, 1)); |
d4e5de1a | 204 | aml_append(dev_gsi, aml_name_decl("_CRS", crs)); |
4dbfc881 | 205 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
d4e5de1a SZ |
206 | aml_append(dev_gsi, method); |
207 | aml_append(dev, dev_gsi); | |
208 | } | |
209 | ||
4dbfc881 | 210 | method = aml_method("_CBA", 0, AML_NOTSERIALIZED); |
d4e5de1a SZ |
211 | aml_append(method, aml_return(aml_int(base_ecam))); |
212 | aml_append(dev, method); | |
213 | ||
4dbfc881 | 214 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); |
d4e5de1a SZ |
215 | Aml *rbuf = aml_resource_template(); |
216 | aml_append(rbuf, | |
217 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, | |
218 | 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, | |
219 | nr_pcie_buses)); | |
220 | aml_append(rbuf, | |
221 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
222 | AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, | |
223 | base_mmio + size_mmio - 1, 0x0000, size_mmio)); | |
224 | aml_append(rbuf, | |
225 | aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, | |
226 | AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, | |
227 | size_pio)); | |
228 | ||
5125f9cd PF |
229 | if (use_highmem) { |
230 | hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; | |
231 | hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; | |
232 | ||
233 | aml_append(rbuf, | |
234 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
235 | AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, | |
e40c3d2e AB |
236 | base_mmio_high, |
237 | base_mmio_high + size_mmio_high - 1, 0x0000, | |
5125f9cd PF |
238 | size_mmio_high)); |
239 | } | |
240 | ||
d4e5de1a SZ |
241 | aml_append(method, aml_name_decl("RBUF", rbuf)); |
242 | aml_append(method, aml_return(rbuf)); | |
243 | aml_append(dev, method); | |
244 | ||
245 | /* Declare an _OSC (OS Control Handoff) method */ | |
246 | aml_append(dev, aml_name_decl("SUPP", aml_int(0))); | |
247 | aml_append(dev, aml_name_decl("CTRL", aml_int(0))); | |
4dbfc881 | 248 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); |
d4e5de1a SZ |
249 | aml_append(method, |
250 | aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
251 | ||
252 | /* PCI Firmware Specification 3.0 | |
253 | * 4.5.1. _OSC Interface for PCI Host Bridge Devices | |
254 | * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is | |
255 | * identified by the Universal Unique IDentifier (UUID) | |
256 | * 33DB4D5B-1FF7-401C-9657-7441C03DD766 | |
257 | */ | |
258 | UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); | |
259 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | |
260 | aml_append(ifctx, | |
261 | aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
262 | aml_append(ifctx, | |
263 | aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
264 | aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); | |
265 | aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); | |
5530427f | 266 | aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), |
d4e5de1a SZ |
267 | aml_name("CTRL"))); |
268 | ||
269 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); | |
ca3df95d | 270 | aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), |
d4e5de1a SZ |
271 | aml_name("CDW1"))); |
272 | aml_append(ifctx, ifctx1); | |
273 | ||
274 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); | |
ca3df95d | 275 | aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), |
d4e5de1a SZ |
276 | aml_name("CDW1"))); |
277 | aml_append(ifctx, ifctx1); | |
278 | ||
279 | aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); | |
280 | aml_append(ifctx, aml_return(aml_arg(3))); | |
281 | aml_append(method, ifctx); | |
282 | ||
283 | elsectx = aml_else(); | |
ca3df95d | 284 | aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), |
d4e5de1a SZ |
285 | aml_name("CDW1"))); |
286 | aml_append(elsectx, aml_return(aml_arg(3))); | |
287 | aml_append(method, elsectx); | |
288 | aml_append(dev, method); | |
289 | ||
4dbfc881 | 290 | method = aml_method("_DSM", 4, AML_NOTSERIALIZED); |
d4e5de1a SZ |
291 | |
292 | /* PCI Firmware Specification 3.0 | |
293 | * 4.6.1. _DSM for PCI Express Slot Information | |
294 | * The UUID in _DSM in this context is | |
295 | * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} | |
296 | */ | |
297 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | |
298 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | |
299 | ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); | |
300 | uint8_t byte_list[1] = {1}; | |
301 | buf = aml_buffer(1, byte_list); | |
302 | aml_append(ifctx1, aml_return(buf)); | |
303 | aml_append(ifctx, ifctx1); | |
304 | aml_append(method, ifctx); | |
305 | ||
306 | byte_list[0] = 0; | |
307 | buf = aml_buffer(1, byte_list); | |
308 | aml_append(method, aml_return(buf)); | |
309 | aml_append(dev, method); | |
310 | ||
311 | Aml *dev_rp0 = aml_device("%s", "RP0"); | |
312 | aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); | |
313 | aml_append(dev, dev_rp0); | |
ebfcc03b AB |
314 | |
315 | Aml *dev_res0 = aml_device("%s", "RES0"); | |
316 | aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); | |
317 | crs = aml_resource_template(); | |
318 | aml_append(crs, aml_memory32_fixed(base_ecam, size_ecam, AML_READ_WRITE)); | |
319 | aml_append(dev_res0, aml_name_decl("_CRS", crs)); | |
320 | aml_append(dev, dev_res0); | |
d4e5de1a SZ |
321 | aml_append(scope, dev); |
322 | } | |
323 | ||
aeb1a36d SZ |
324 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
325 | uint32_t gpio_irq) | |
326 | { | |
327 | Aml *dev = aml_device("GPO0"); | |
328 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
329 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
330 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
331 | ||
332 | Aml *crs = aml_resource_template(); | |
333 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
334 | AML_READ_WRITE)); | |
335 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
336 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
337 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
338 | |
339 | Aml *aei = aml_resource_template(); | |
340 | /* Pin 3 for power button */ | |
341 | const uint32_t pin_list[1] = {3}; | |
342 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
343 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
344 | "GPO0", NULL, 0)); | |
345 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
346 | ||
347 | /* _E03 is handle for power button */ | |
348 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
349 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
350 | aml_int(0x80))); | |
351 | aml_append(dev, method); | |
aeb1a36d SZ |
352 | aml_append(scope, dev); |
353 | } | |
354 | ||
ac6aa59a SZ |
355 | static void acpi_dsdt_add_power_button(Aml *scope) |
356 | { | |
357 | Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); | |
358 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); | |
359 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
360 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
361 | aml_append(scope, dev); | |
362 | } | |
363 | ||
d4bec5d8 SZ |
364 | /* RSDP */ |
365 | static GArray * | |
4678124b | 366 | build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset) |
d4bec5d8 SZ |
367 | { |
368 | AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); | |
4678124b IM |
369 | unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address); |
370 | unsigned rsdt_pa_offset = | |
371 | (char *)&rsdp->rsdt_physical_address - rsdp_table->data; | |
d4bec5d8 | 372 | |
ad9671b8 | 373 | bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16, |
d4bec5d8 SZ |
374 | true /* fseg memory */); |
375 | ||
376 | memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); | |
377 | memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); | |
378 | rsdp->length = cpu_to_le32(sizeof(*rsdp)); | |
379 | rsdp->revision = 0x02; | |
380 | ||
d4bec5d8 | 381 | /* Address to be filled by Guest linker */ |
4678124b IM |
382 | bios_linker_loader_add_pointer(linker, |
383 | ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size, | |
384 | ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset); | |
385 | ||
d4bec5d8 SZ |
386 | /* Checksum to be filled by Guest linker */ |
387 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, | |
28213cb6 IM |
388 | (char *)rsdp - rsdp_table->data, sizeof *rsdp, |
389 | (char *)&rsdp->checksum - rsdp_table->data); | |
d4bec5d8 SZ |
390 | |
391 | return rsdp_table; | |
392 | } | |
393 | ||
e78f1222 | 394 | static void |
da4f09a7 | 395 | build_iort(GArray *table_data, BIOSLinker *linker) |
e78f1222 PM |
396 | { |
397 | int iort_start = table_data->len; | |
398 | AcpiIortIdMapping *idmap; | |
399 | AcpiIortItsGroup *its; | |
400 | AcpiIortTable *iort; | |
401 | size_t node_size, iort_length; | |
402 | AcpiIortRC *rc; | |
403 | ||
404 | iort = acpi_data_push(table_data, sizeof(*iort)); | |
405 | ||
406 | iort_length = sizeof(*iort); | |
407 | iort->node_count = cpu_to_le32(2); /* RC and ITS nodes */ | |
408 | iort->node_offset = cpu_to_le32(sizeof(*iort)); | |
409 | ||
410 | /* ITS group node */ | |
411 | node_size = sizeof(*its) + sizeof(uint32_t); | |
412 | iort_length += node_size; | |
413 | its = acpi_data_push(table_data, node_size); | |
414 | ||
415 | its->type = ACPI_IORT_NODE_ITS_GROUP; | |
416 | its->length = cpu_to_le16(node_size); | |
417 | its->its_count = cpu_to_le32(1); | |
418 | its->identifiers[0] = 0; /* MADT translation_id */ | |
419 | ||
420 | /* Root Complex Node */ | |
421 | node_size = sizeof(*rc) + sizeof(*idmap); | |
422 | iort_length += node_size; | |
423 | rc = acpi_data_push(table_data, node_size); | |
424 | ||
425 | rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; | |
426 | rc->length = cpu_to_le16(node_size); | |
427 | rc->mapping_count = cpu_to_le32(1); | |
428 | rc->mapping_offset = cpu_to_le32(sizeof(*rc)); | |
429 | ||
430 | /* fully coherent device */ | |
431 | rc->memory_properties.cache_coherency = cpu_to_le32(1); | |
432 | rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ | |
433 | rc->pci_segment_number = 0; /* MCFG pci_segment */ | |
434 | ||
435 | /* Identity RID mapping covering the whole input RID range */ | |
436 | idmap = &rc->id_mapping_array[0]; | |
437 | idmap->input_base = 0; | |
438 | idmap->id_count = cpu_to_le32(0xFFFF); | |
439 | idmap->output_base = 0; | |
440 | /* output IORT node is the ITS group node (the first node) */ | |
441 | idmap->output_reference = cpu_to_le32(iort->node_offset); | |
442 | ||
443 | iort->length = cpu_to_le32(iort_length); | |
444 | ||
445 | build_header(linker, table_data, (void *)(table_data->data + iort_start), | |
446 | "IORT", table_data->len - iort_start, 0, NULL, NULL); | |
447 | } | |
448 | ||
f264d51d | 449 | static void |
da4f09a7 | 450 | build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
f264d51d AJ |
451 | { |
452 | AcpiSerialPortConsoleRedirection *spcr; | |
da4f09a7 AJ |
453 | const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; |
454 | int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; | |
f264d51d AJ |
455 | |
456 | spcr = acpi_data_push(table_data, sizeof(*spcr)); | |
457 | ||
458 | spcr->interface_type = 0x3; /* ARM PL011 UART */ | |
459 | ||
460 | spcr->base_address.space_id = AML_SYSTEM_MEMORY; | |
461 | spcr->base_address.bit_width = 8; | |
462 | spcr->base_address.bit_offset = 0; | |
463 | spcr->base_address.access_width = 1; | |
464 | spcr->base_address.address = cpu_to_le64(uart_memmap->base); | |
465 | ||
466 | spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ | |
467 | spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ | |
468 | ||
469 | spcr->baud = 3; /* Baud Rate: 3 = 9600 */ | |
470 | spcr->parity = 0; /* No Parity */ | |
471 | spcr->stopbits = 1; /* 1 Stop bit */ | |
472 | spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ | |
473 | spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ | |
474 | ||
475 | spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ | |
476 | spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ | |
477 | ||
8870ca0e | 478 | build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2, |
37ad223c | 479 | NULL, NULL); |
f264d51d AJ |
480 | } |
481 | ||
2b302e1e | 482 | static void |
da4f09a7 | 483 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
2b302e1e SZ |
484 | { |
485 | AcpiSystemResourceAffinityTable *srat; | |
486 | AcpiSratProcessorGiccAffinity *core; | |
487 | AcpiSratMemoryAffinity *numamem; | |
488 | int i, j, srat_start; | |
489 | uint64_t mem_base; | |
da4f09a7 | 490 | uint32_t *cpu_node = g_malloc0(vms->smp_cpus * sizeof(uint32_t)); |
2b302e1e | 491 | |
da4f09a7 | 492 | for (i = 0; i < vms->smp_cpus; i++) { |
6bea1ddf IM |
493 | j = numa_get_node_for_cpu(i); |
494 | if (j < nb_numa_nodes) { | |
2b302e1e | 495 | cpu_node[i] = j; |
2b302e1e SZ |
496 | } |
497 | } | |
498 | ||
499 | srat_start = table_data->len; | |
500 | srat = acpi_data_push(table_data, sizeof(*srat)); | |
501 | srat->reserved1 = cpu_to_le32(1); | |
502 | ||
da4f09a7 | 503 | for (i = 0; i < vms->smp_cpus; ++i) { |
2b302e1e SZ |
504 | core = acpi_data_push(table_data, sizeof(*core)); |
505 | core->type = ACPI_SRAT_PROCESSOR_GICC; | |
506 | core->length = sizeof(*core); | |
507 | core->proximity = cpu_to_le32(cpu_node[i]); | |
508 | core->acpi_processor_uid = cpu_to_le32(i); | |
509 | core->flags = cpu_to_le32(1); | |
510 | } | |
511 | g_free(cpu_node); | |
512 | ||
da4f09a7 | 513 | mem_base = vms->memmap[VIRT_MEM].base; |
2b302e1e SZ |
514 | for (i = 0; i < nb_numa_nodes; ++i) { |
515 | numamem = acpi_data_push(table_data, sizeof(*numamem)); | |
516 | build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i, | |
517 | MEM_AFFINITY_ENABLED); | |
518 | mem_base += numa_info[i].node_mem; | |
519 | } | |
520 | ||
0e9b9eda | 521 | build_header(linker, table_data, (void *)srat, "SRAT", |
2b302e1e SZ |
522 | table_data->len - srat_start, 3, NULL, NULL); |
523 | } | |
524 | ||
84344884 | 525 | static void |
da4f09a7 | 526 | build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
84344884 SZ |
527 | { |
528 | AcpiTableMcfg *mcfg; | |
da4f09a7 | 529 | const MemMapEntry *memmap = vms->memmap; |
84344884 SZ |
530 | int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); |
531 | ||
532 | mcfg = acpi_data_push(table_data, len); | |
533 | mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); | |
534 | ||
535 | /* Only a single allocation so no need to play with segments */ | |
536 | mcfg->allocation[0].pci_segment = cpu_to_le16(0); | |
537 | mcfg->allocation[0].start_bus_number = 0; | |
538 | mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size | |
539 | / PCIE_MMCFG_SIZE_MIN) - 1; | |
540 | ||
37ad223c | 541 | build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL); |
84344884 SZ |
542 | } |
543 | ||
ee246400 SZ |
544 | /* GTDT */ |
545 | static void | |
8dd845d3 | 546 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
ee246400 | 547 | { |
8dd845d3 | 548 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
ee246400 SZ |
549 | int gtdt_start = table_data->len; |
550 | AcpiGenericTimerTable *gtdt; | |
8dd845d3 AJ |
551 | uint32_t irqflags; |
552 | ||
553 | if (vmc->claim_edge_triggered_timers) { | |
554 | irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; | |
555 | } else { | |
556 | irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; | |
557 | } | |
ee246400 SZ |
558 | |
559 | gtdt = acpi_data_push(table_data, sizeof *gtdt); | |
560 | /* The interrupt values are the same with the device tree when adding 16 */ | |
330afe05 | 561 | gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); |
8dd845d3 | 562 | gtdt->secure_el1_flags = cpu_to_le32(irqflags); |
ee246400 | 563 | |
330afe05 | 564 | gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); |
8dd845d3 | 565 | gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | |
aca4bbf4 | 566 | ACPI_GTDT_CAP_ALWAYS_ON); |
ee246400 | 567 | |
330afe05 | 568 | gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); |
8dd845d3 | 569 | gtdt->virtual_timer_flags = cpu_to_le32(irqflags); |
ee246400 | 570 | |
330afe05 | 571 | gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); |
8dd845d3 | 572 | gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); |
ee246400 SZ |
573 | |
574 | build_header(linker, table_data, | |
575 | (void *)(table_data->data + gtdt_start), "GTDT", | |
37ad223c | 576 | table_data->len - gtdt_start, 2, NULL, NULL); |
ee246400 SZ |
577 | } |
578 | ||
982d06c5 SZ |
579 | /* MADT */ |
580 | static void | |
da4f09a7 | 581 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
982d06c5 | 582 | { |
da4f09a7 | 583 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
982d06c5 | 584 | int madt_start = table_data->len; |
da4f09a7 AJ |
585 | const MemMapEntry *memmap = vms->memmap; |
586 | const int *irqmap = vms->irqmap; | |
982d06c5 SZ |
587 | AcpiMultipleApicTable *madt; |
588 | AcpiMadtGenericDistributor *gicd; | |
ca793736 | 589 | AcpiMadtGenericMsiFrame *gic_msi; |
982d06c5 SZ |
590 | int i; |
591 | ||
592 | madt = acpi_data_push(table_data, sizeof *madt); | |
593 | ||
982d06c5 SZ |
594 | gicd = acpi_data_push(table_data, sizeof *gicd); |
595 | gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; | |
596 | gicd->length = sizeof(*gicd); | |
330afe05 | 597 | gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); |
da4f09a7 | 598 | gicd->version = vms->gic_version; |
982d06c5 | 599 | |
da4f09a7 | 600 | for (i = 0; i < vms->smp_cpus; i++) { |
6e2ed65f AJ |
601 | AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, |
602 | sizeof(*gicc)); | |
5d9c1756 SZ |
603 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
604 | ||
6e2ed65f | 605 | gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; |
f2fbface | 606 | gicc->length = sizeof(*gicc); |
da4f09a7 | 607 | if (vms->gic_version == 2) { |
330afe05 | 608 | gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); |
f2fbface | 609 | } |
330afe05 AJ |
610 | gicc->cpu_interface_number = cpu_to_le32(i); |
611 | gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); | |
612 | gicc->uid = cpu_to_le32(i); | |
6e2ed65f | 613 | gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); |
8433dee0 | 614 | |
929e754d | 615 | if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { |
8433dee0 SZ |
616 | gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); |
617 | } | |
f29cacfb PM |
618 | if (vms->virt && vms->gic_version == 3) { |
619 | gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)); | |
620 | } | |
f2fbface SZ |
621 | } |
622 | ||
da4f09a7 | 623 | if (vms->gic_version == 3) { |
13e5c54d | 624 | AcpiMadtGenericTranslator *gic_its; |
b92ad394 PF |
625 | AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, |
626 | sizeof *gicr); | |
627 | ||
628 | gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; | |
629 | gicr->length = sizeof(*gicr); | |
630 | gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); | |
631 | gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); | |
13e5c54d | 632 | |
da4f09a7 | 633 | if (its_class_name() && !vmc->no_its) { |
13cda487 AJ |
634 | gic_its = acpi_data_push(table_data, sizeof *gic_its); |
635 | gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; | |
636 | gic_its->length = sizeof(*gic_its); | |
637 | gic_its->translation_id = 0; | |
638 | gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); | |
13e5c54d | 639 | } |
b92ad394 | 640 | } else { |
b92ad394 PF |
641 | gic_msi = acpi_data_push(table_data, sizeof *gic_msi); |
642 | gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; | |
643 | gic_msi->length = sizeof(*gic_msi); | |
644 | gic_msi->gic_msi_frame_id = 0; | |
645 | gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); | |
646 | gic_msi->flags = cpu_to_le32(1); | |
647 | gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); | |
648 | gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); | |
649 | } | |
ca793736 | 650 | |
982d06c5 SZ |
651 | build_header(linker, table_data, |
652 | (void *)(table_data->data + madt_start), "APIC", | |
37ad223c | 653 | table_data->len - madt_start, 3, NULL, NULL); |
982d06c5 SZ |
654 | } |
655 | ||
c2f7c0c3 | 656 | /* FADT */ |
79e993a0 AJ |
657 | static void build_fadt(GArray *table_data, BIOSLinker *linker, |
658 | VirtMachineState *vms, unsigned dsdt_tbl_offset) | |
c2f7c0c3 SZ |
659 | { |
660 | AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); | |
4678124b | 661 | unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data; |
79e993a0 AJ |
662 | uint16_t bootflags; |
663 | ||
664 | switch (vms->psci_conduit) { | |
665 | case QEMU_PSCI_CONDUIT_DISABLED: | |
666 | bootflags = 0; | |
667 | break; | |
668 | case QEMU_PSCI_CONDUIT_HVC: | |
669 | bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT | ACPI_FADT_ARM_PSCI_USE_HVC; | |
670 | break; | |
671 | case QEMU_PSCI_CONDUIT_SMC: | |
672 | bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT; | |
673 | break; | |
674 | default: | |
675 | g_assert_not_reached(); | |
676 | } | |
c2f7c0c3 | 677 | |
79e993a0 | 678 | /* Hardware Reduced = 1 and use PSCI 0.2+ */ |
c2f7c0c3 | 679 | fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); |
79e993a0 | 680 | fadt->arm_boot_flags = cpu_to_le16(bootflags); |
c2f7c0c3 SZ |
681 | |
682 | /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ | |
683 | fadt->minor_revision = 0x1; | |
684 | ||
c2f7c0c3 | 685 | /* DSDT address to be filled by Guest linker */ |
4678124b IM |
686 | bios_linker_loader_add_pointer(linker, |
687 | ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt), | |
688 | ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); | |
c2f7c0c3 SZ |
689 | |
690 | build_header(linker, table_data, | |
37ad223c | 691 | (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL); |
c2f7c0c3 SZ |
692 | } |
693 | ||
dfccd8cf SZ |
694 | /* DSDT */ |
695 | static void | |
da4f09a7 | 696 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
dfccd8cf SZ |
697 | { |
698 | Aml *scope, *dsdt; | |
da4f09a7 AJ |
699 | const MemMapEntry *memmap = vms->memmap; |
700 | const int *irqmap = vms->irqmap; | |
dfccd8cf SZ |
701 | |
702 | dsdt = init_aml_allocator(); | |
703 | /* Reserve space for header */ | |
704 | acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); | |
705 | ||
67736a25 SZ |
706 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
707 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
708 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
709 | * the RTC ACPI device at all when using UEFI. | |
710 | */ | |
dfccd8cf | 711 | scope = aml_scope("\\_SB"); |
da4f09a7 | 712 | acpi_dsdt_add_cpus(scope, vms->smp_cpus); |
dfccd8cf SZ |
713 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], |
714 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
dfccd8cf | 715 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); |
70bee80d | 716 | acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); |
dfccd8cf SZ |
717 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], |
718 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | |
5125f9cd | 719 | acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), |
da4f09a7 | 720 | vms->highmem); |
aeb1a36d SZ |
721 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], |
722 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
ac6aa59a | 723 | acpi_dsdt_add_power_button(scope); |
d4e5de1a | 724 | |
dfccd8cf SZ |
725 | aml_append(dsdt, scope); |
726 | ||
727 | /* copy AML table into ACPI tables blob and patch header there */ | |
728 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); | |
729 | build_header(linker, table_data, | |
730 | (void *)(table_data->data + table_data->len - dsdt->buf->len), | |
37ad223c | 731 | "DSDT", dsdt->buf->len, 2, NULL, NULL); |
dfccd8cf SZ |
732 | free_aml_allocator(); |
733 | } | |
734 | ||
f5d8c8cd SZ |
735 | typedef |
736 | struct AcpiBuildState { | |
737 | /* Copy of table in RAM (for patching). */ | |
738 | MemoryRegion *table_mr; | |
739 | MemoryRegion *rsdp_mr; | |
740 | MemoryRegion *linker_mr; | |
741 | /* Is table patched? */ | |
742 | bool patched; | |
f5d8c8cd SZ |
743 | } AcpiBuildState; |
744 | ||
745 | static | |
da4f09a7 | 746 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
f5d8c8cd | 747 | { |
da4f09a7 | 748 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
f5d8c8cd | 749 | GArray *table_offsets; |
d4bec5d8 | 750 | unsigned dsdt, rsdt; |
dfccd8cf | 751 | GArray *tables_blob = tables->table_data; |
f5d8c8cd SZ |
752 | |
753 | table_offsets = g_array_new(false, true /* clear */, | |
754 | sizeof(uint32_t)); | |
755 | ||
ad9671b8 IM |
756 | bios_linker_loader_alloc(tables->linker, |
757 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
f5d8c8cd SZ |
758 | 64, false /* high memory */); |
759 | ||
dfccd8cf | 760 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 761 | dsdt = tables_blob->len; |
da4f09a7 | 762 | build_dsdt(tables_blob, tables->linker, vms); |
dfccd8cf | 763 | |
d0652b57 | 764 | /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ |
c2f7c0c3 | 765 | acpi_add_table(table_offsets, tables_blob); |
79e993a0 | 766 | build_fadt(tables_blob, tables->linker, vms, dsdt); |
c2f7c0c3 | 767 | |
982d06c5 | 768 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 769 | build_madt(tables_blob, tables->linker, vms); |
982d06c5 | 770 | |
ee246400 | 771 | acpi_add_table(table_offsets, tables_blob); |
8dd845d3 | 772 | build_gtdt(tables_blob, tables->linker, vms); |
ee246400 | 773 | |
84344884 | 774 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 775 | build_mcfg(tables_blob, tables->linker, vms); |
84344884 | 776 | |
f264d51d | 777 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 778 | build_spcr(tables_blob, tables->linker, vms); |
f264d51d | 779 | |
2b302e1e SZ |
780 | if (nb_numa_nodes > 0) { |
781 | acpi_add_table(table_offsets, tables_blob); | |
da4f09a7 | 782 | build_srat(tables_blob, tables->linker, vms); |
2b302e1e SZ |
783 | } |
784 | ||
da4f09a7 | 785 | if (its_class_name() && !vmc->no_its) { |
e78f1222 | 786 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 787 | build_iort(tables_blob, tables->linker); |
e78f1222 PM |
788 | } |
789 | ||
243bdb79 | 790 | /* RSDT is pointed to by RSDP */ |
d4bec5d8 | 791 | rsdt = tables_blob->len; |
51513558 | 792 | build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); |
243bdb79 | 793 | |
d4bec5d8 SZ |
794 | /* RSDP is in FSEG memory, so allocate it separately */ |
795 | build_rsdp(tables->rsdp, tables->linker, rsdt); | |
796 | ||
f5d8c8cd SZ |
797 | /* Cleanup memory that's no longer used. */ |
798 | g_array_free(table_offsets, true); | |
799 | } | |
800 | ||
801 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
802 | { | |
803 | uint32_t size = acpi_data_len(data); | |
804 | ||
805 | /* Make sure RAM size is correct - in case it got changed | |
806 | * e.g. by migration */ | |
807 | memory_region_ram_resize(mr, size, &error_abort); | |
808 | ||
809 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
810 | memory_region_set_dirty(mr, 0, size); | |
811 | } | |
812 | ||
3f8752b4 | 813 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
814 | { |
815 | AcpiBuildState *build_state = build_opaque; | |
816 | AcpiBuildTables tables; | |
817 | ||
818 | /* No state to update or already patched? Nothing to do. */ | |
819 | if (!build_state || build_state->patched) { | |
820 | return; | |
821 | } | |
822 | build_state->patched = true; | |
823 | ||
824 | acpi_build_tables_init(&tables); | |
825 | ||
4dad9e74 | 826 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); |
f5d8c8cd SZ |
827 | |
828 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
829 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
0e9b9eda | 830 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
f5d8c8cd | 831 | |
f5d8c8cd SZ |
832 | acpi_build_tables_cleanup(&tables, true); |
833 | } | |
834 | ||
835 | static void virt_acpi_build_reset(void *build_opaque) | |
836 | { | |
837 | AcpiBuildState *build_state = build_opaque; | |
838 | build_state->patched = false; | |
839 | } | |
840 | ||
841 | static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, | |
842 | GArray *blob, const char *name, | |
843 | uint64_t max_size) | |
844 | { | |
845 | return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, | |
baf2d5bf | 846 | name, virt_acpi_build_update, build_state, NULL, true); |
f5d8c8cd SZ |
847 | } |
848 | ||
849 | static const VMStateDescription vmstate_virt_acpi_build = { | |
850 | .name = "virt_acpi_build", | |
851 | .version_id = 1, | |
852 | .minimum_version_id = 1, | |
853 | .fields = (VMStateField[]) { | |
854 | VMSTATE_BOOL(patched, AcpiBuildState), | |
855 | VMSTATE_END_OF_LIST() | |
856 | }, | |
857 | }; | |
858 | ||
e9a8e474 | 859 | void virt_acpi_setup(VirtMachineState *vms) |
f5d8c8cd SZ |
860 | { |
861 | AcpiBuildTables tables; | |
862 | AcpiBuildState *build_state; | |
863 | ||
af1f60a4 | 864 | if (!vms->fw_cfg) { |
f5d8c8cd SZ |
865 | trace_virt_acpi_setup(); |
866 | return; | |
867 | } | |
868 | ||
869 | if (!acpi_enabled) { | |
870 | trace_virt_acpi_setup(); | |
871 | return; | |
872 | } | |
873 | ||
874 | build_state = g_malloc0(sizeof *build_state); | |
f5d8c8cd SZ |
875 | |
876 | acpi_build_tables_init(&tables); | |
da4f09a7 | 877 | virt_acpi_build(vms, &tables); |
f5d8c8cd SZ |
878 | |
879 | /* Now expose it all to Guest */ | |
880 | build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, | |
881 | ACPI_BUILD_TABLE_FILE, | |
882 | ACPI_BUILD_TABLE_MAX_SIZE); | |
883 | assert(build_state->table_mr != NULL); | |
884 | ||
885 | build_state->linker_mr = | |
0e9b9eda IM |
886 | acpi_add_rom_blob(build_state, tables.linker->cmd_blob, |
887 | "etc/table-loader", 0); | |
f5d8c8cd | 888 | |
af1f60a4 AJ |
889 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, |
890 | acpi_data_len(tables.tcpalog)); | |
f5d8c8cd SZ |
891 | |
892 | build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, | |
893 | ACPI_BUILD_RSDP_FILE, 0); | |
894 | ||
895 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
896 | virt_acpi_build_reset(build_state); | |
897 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
898 | ||
899 | /* Cleanup tables but don't free the memory: we track it | |
900 | * in build_state. | |
901 | */ | |
902 | acpi_build_tables_cleanup(&tables, false); | |
903 | } |