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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
da34e65c | 30 | #include "qapi/error.h" |
f5d8c8cd | 31 | #include "qemu/bitmap.h" |
13a63743 | 32 | #include "qemu/error-report.h" |
f5d8c8cd | 33 | #include "trace.h" |
2e5b09fd | 34 | #include "hw/core/cpu.h" |
f5d8c8cd SZ |
35 | #include "hw/acpi/acpi-defs.h" |
36 | #include "hw/acpi/acpi.h" | |
4c7f4f4f | 37 | #include "hw/nvram/fw_cfg_acpi.h" |
f5d8c8cd | 38 | #include "hw/acpi/bios-linker-loader.h" |
f5d8c8cd | 39 | #include "hw/acpi/aml-build.h" |
82f76c67 | 40 | #include "hw/acpi/utils.h" |
48cefd94 | 41 | #include "hw/acpi/pci.h" |
cff51ac9 SK |
42 | #include "hw/acpi/memory_hotplug.h" |
43 | #include "hw/acpi/generic_event_device.h" | |
80bde693 | 44 | #include "hw/acpi/tpm.h" |
7cbd3fd3 | 45 | #include "hw/acpi/hmat.h" |
84344884 | 46 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 47 | #include "hw/pci/pci.h" |
42e0f050 | 48 | #include "hw/pci/pci_bus.h" |
06d2dd49 | 49 | #include "hw/pci-host/gpex.h" |
d05fdab4 | 50 | #include "hw/arm/virt.h" |
0c40daf0 | 51 | #include "hw/intc/arm_gicv3_its_common.h" |
b5a60bee | 52 | #include "hw/mem/nvdimm.h" |
5ab540e9 | 53 | #include "hw/platform-bus.h" |
2b302e1e | 54 | #include "sysemu/numa.h" |
71e8a915 | 55 | #include "sysemu/reset.h" |
80bde693 | 56 | #include "sysemu/tpm.h" |
d6454270 | 57 | #include "migration/vmstate.h" |
aa16508f | 58 | #include "hw/acpi/ghes.h" |
cf1a5cc9 | 59 | #include "hw/acpi/viot.h" |
0a5b5acd | 60 | #include "hw/acpi/acpi_generic_initiator.h" |
57ba8436 | 61 | #include "hw/virtio/virtio-acpi.h" |
e2d8cf9b | 62 | #include "target/arm/multiprocessing.h" |
f5d8c8cd | 63 | |
dfccd8cf SZ |
64 | #define ARM_SPI_BASE 32 |
65 | ||
451b1570 YM |
66 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
67 | ||
9cd07db9 | 68 | static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) |
dfccd8cf | 69 | { |
9cd07db9 | 70 | MachineState *ms = MACHINE(vms); |
dfccd8cf SZ |
71 | uint16_t i; |
72 | ||
9cd07db9 | 73 | for (i = 0; i < ms->smp.cpus; i++) { |
f460be43 | 74 | Aml *dev = aml_device("C%.03X", i); |
dfccd8cf SZ |
75 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); |
76 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
77 | aml_append(scope, dev); | |
78 | } | |
79 | } | |
80 | ||
81 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 82 | uint32_t uart_irq) |
dfccd8cf SZ |
83 | { |
84 | Aml *dev = aml_device("COM0"); | |
85 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
86 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
87 | ||
88 | Aml *crs = aml_resource_template(); | |
89 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
90 | uart_memmap->size, AML_READ_WRITE)); | |
91 | aml_append(crs, | |
92 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 93 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 94 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d | 95 | |
dfccd8cf SZ |
96 | aml_append(scope, dev); |
97 | } | |
98 | ||
dfccd8cf SZ |
99 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
100 | { | |
101 | Aml *dev, *crs; | |
102 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 103 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
104 | |
105 | dev = aml_device("FLS0"); | |
106 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
107 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
108 | ||
109 | crs = aml_resource_template(); | |
110 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
111 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
112 | aml_append(scope, dev); | |
113 | ||
114 | dev = aml_device("FLS1"); | |
115 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
116 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
117 | crs = aml_resource_template(); | |
118 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
119 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
120 | aml_append(scope, dev); | |
121 | } | |
122 | ||
45fcf539 | 123 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
c8f008c4 | 124 | uint32_t irq, VirtMachineState *vms) |
d4e5de1a | 125 | { |
c8f008c4 | 126 | int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); |
06d2dd49 GH |
127 | struct GPEXConfig cfg = { |
128 | .mmio32 = memmap[VIRT_PCIE_MMIO], | |
129 | .pio = memmap[VIRT_PCIE_PIO], | |
130 | .ecam = memmap[ecam_id], | |
131 | .irq = irq, | |
6f9765fb | 132 | .bus = vms->bus, |
06d2dd49 | 133 | }; |
d4e5de1a | 134 | |
c8f008c4 | 135 | if (vms->highmem_mmio) { |
06d2dd49 | 136 | cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; |
5125f9cd PF |
137 | } |
138 | ||
06d2dd49 | 139 | acpi_dsdt_add_gpex(scope, &cfg); |
d4e5de1a SZ |
140 | } |
141 | ||
aeb1a36d SZ |
142 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
143 | uint32_t gpio_irq) | |
144 | { | |
145 | Aml *dev = aml_device("GPO0"); | |
146 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
aeb1a36d SZ |
147 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
148 | ||
149 | Aml *crs = aml_resource_template(); | |
150 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
151 | AML_READ_WRITE)); | |
152 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
153 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
154 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
155 | |
156 | Aml *aei = aml_resource_template(); | |
157 | /* Pin 3 for power button */ | |
158 | const uint32_t pin_list[1] = {3}; | |
159 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
160 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
161 | "GPO0", NULL, 0)); | |
162 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
163 | ||
164 | /* _E03 is handle for power button */ | |
165 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
166 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
167 | aml_int(0x80))); | |
168 | aml_append(dev, method); | |
aeb1a36d SZ |
169 | aml_append(scope, dev); |
170 | } | |
171 | ||
f50be48a | 172 | #ifdef CONFIG_TPM |
5ab540e9 EA |
173 | static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) |
174 | { | |
175 | PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); | |
176 | hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; | |
177 | SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); | |
178 | MemoryRegion *sbdev_mr; | |
179 | hwaddr tpm_base; | |
180 | ||
181 | if (!sbdev) { | |
182 | return; | |
183 | } | |
184 | ||
185 | tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
186 | assert(tpm_base != -1); | |
187 | ||
188 | tpm_base += pbus_base; | |
189 | ||
190 | sbdev_mr = sysbus_mmio_get_region(sbdev, 0); | |
191 | ||
192 | Aml *dev = aml_device("TPM0"); | |
193 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
5903646d | 194 | aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); |
5ab540e9 EA |
195 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
196 | ||
197 | Aml *crs = aml_resource_template(); | |
198 | aml_append(crs, | |
199 | aml_memory32_fixed(tpm_base, | |
200 | (uint32_t)memory_region_size(sbdev_mr), | |
201 | AML_READ_WRITE)); | |
202 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
203 | aml_append(scope, dev); | |
204 | } | |
f50be48a | 205 | #endif |
5ab540e9 | 206 | |
271cbb2f | 207 | #define ID_MAPPING_ENTRY_SIZE 20 |
1c2cb7e0 EA |
208 | #define SMMU_V3_ENTRY_SIZE 68 |
209 | #define ROOT_COMPLEX_ENTRY_SIZE 36 | |
271cbb2f IM |
210 | #define IORT_NODE_OFFSET 48 |
211 | ||
212 | static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, | |
213 | uint32_t id_count, uint32_t out_ref) | |
214 | { | |
1c2cb7e0 | 215 | /* Table 4 ID mapping format */ |
271cbb2f IM |
216 | build_append_int_noprefix(table_data, input_base, 4); /* Input base */ |
217 | build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ | |
218 | build_append_int_noprefix(table_data, input_base, 4); /* Output base */ | |
219 | build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ | |
1c2cb7e0 EA |
220 | /* Flags */ |
221 | build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); | |
271cbb2f IM |
222 | } |
223 | ||
224 | struct AcpiIortIdMapping { | |
225 | uint32_t input_base; | |
226 | uint32_t id_count; | |
227 | }; | |
228 | typedef struct AcpiIortIdMapping AcpiIortIdMapping; | |
229 | ||
42e0f050 XW |
230 | /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ |
231 | static int | |
232 | iort_host_bridges(Object *obj, void *opaque) | |
233 | { | |
234 | GArray *idmap_blob = opaque; | |
235 | ||
236 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
237 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
238 | ||
239 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
240 | int min_bus, max_bus; | |
241 | ||
242 | pci_bus_range(bus, &min_bus, &max_bus); | |
243 | ||
244 | AcpiIortIdMapping idmap = { | |
245 | .input_base = min_bus << 8, | |
246 | .id_count = (max_bus - min_bus + 1) << 8, | |
247 | }; | |
248 | g_array_append_val(idmap_blob, idmap); | |
249 | } | |
250 | } | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | static int iort_idmap_compare(gconstpointer a, gconstpointer b) | |
256 | { | |
257 | AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; | |
258 | AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; | |
259 | ||
260 | return idmap_a->input_base - idmap_b->input_base; | |
261 | } | |
262 | ||
3548494e IM |
263 | /* |
264 | * Input Output Remapping Table (IORT) | |
265 | * Conforms to "IO Remapping Table System Software on ARM Platforms", | |
1c2cb7e0 | 266 | * Document number: ARM DEN 0049E.b, Feb 2021 |
3548494e | 267 | */ |
e78f1222 | 268 | static void |
a703b4f6 | 269 | build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
e78f1222 | 270 | { |
3548494e | 271 | int i, nb_nodes, rc_mapping_count; |
271cbb2f | 272 | const uint32_t iort_node_offset = IORT_NODE_OFFSET; |
3548494e | 273 | size_t node_size, smmu_offset = 0; |
271cbb2f | 274 | AcpiIortIdMapping *idmap; |
1c2cb7e0 | 275 | uint32_t id = 0; |
42e0f050 XW |
276 | GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); |
277 | GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); | |
e78f1222 | 278 | |
1c2cb7e0 | 279 | AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, |
3548494e | 280 | .oem_table_id = vms->oem_table_id }; |
271cbb2f IM |
281 | /* Table 2 The IORT */ |
282 | acpi_table_begin(&table, table_data); | |
e78f1222 | 283 | |
a703b4f6 | 284 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
285 | AcpiIortIdMapping next_range = {0}; |
286 | ||
287 | object_child_foreach_recursive(object_get_root(), | |
288 | iort_host_bridges, smmu_idmaps); | |
289 | ||
290 | /* Sort the smmu idmap by input_base */ | |
291 | g_array_sort(smmu_idmaps, iort_idmap_compare); | |
292 | ||
293 | /* | |
294 | * Split the whole RIDs by mapping from RC to SMMU, | |
295 | * build the ID mapping from RC to ITS directly. | |
296 | */ | |
297 | for (i = 0; i < smmu_idmaps->len; i++) { | |
298 | idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); | |
299 | ||
300 | if (next_range.input_base < idmap->input_base) { | |
301 | next_range.id_count = idmap->input_base - next_range.input_base; | |
302 | g_array_append_val(its_idmaps, next_range); | |
303 | } | |
304 | ||
305 | next_range.input_base = idmap->input_base + idmap->id_count; | |
306 | } | |
307 | ||
308 | /* Append the last RC -> ITS ID mapping */ | |
309 | if (next_range.input_base < 0xFFFF) { | |
310 | next_range.id_count = 0xFFFF - next_range.input_base; | |
311 | g_array_append_val(its_idmaps, next_range); | |
312 | } | |
313 | ||
a703b4f6 | 314 | nb_nodes = 3; /* RC, ITS, SMMUv3 */ |
42e0f050 | 315 | rc_mapping_count = smmu_idmaps->len + its_idmaps->len; |
a703b4f6 PM |
316 | } else { |
317 | nb_nodes = 2; /* RC, ITS */ | |
42e0f050 | 318 | rc_mapping_count = 1; |
a703b4f6 | 319 | } |
3548494e IM |
320 | /* Number of IORT Nodes */ |
321 | build_append_int_noprefix(table_data, nb_nodes, 4); | |
271cbb2f | 322 | |
3548494e | 323 | /* Offset to Array of IORT Nodes */ |
271cbb2f | 324 | build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); |
3548494e | 325 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
e78f1222 | 326 | |
1c2cb7e0 | 327 | /* Table 12 ITS Group Format */ |
271cbb2f IM |
328 | build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ |
329 | node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; | |
330 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
331 | build_append_int_noprefix(table_data, 1, 1); /* Revision */ |
332 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
333 | build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ |
334 | build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ | |
335 | build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ | |
336 | /* GIC ITS Identifier Array */ | |
337 | build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); | |
e78f1222 | 338 | |
a703b4f6 | 339 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
41c4fb94 | 340 | int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; |
a703b4f6 | 341 | |
271cbb2f | 342 | smmu_offset = table_data->len - table.table_offset; |
1c2cb7e0 | 343 | /* Table 9 SMMUv3 Format */ |
271cbb2f IM |
344 | build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ |
345 | node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; | |
346 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
347 | build_append_int_noprefix(table_data, 4, 1); /* Revision */ |
348 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
349 | build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ |
350 | /* Reference to ID Array */ | |
351 | build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); | |
352 | /* Base address */ | |
353 | build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); | |
354 | /* Flags */ | |
1c2cb7e0 | 355 | build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); |
271cbb2f IM |
356 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
357 | build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ | |
358 | /* Model */ | |
359 | build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); | |
360 | build_append_int_noprefix(table_data, irq, 4); /* Event */ | |
361 | build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ | |
362 | build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ | |
363 | build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ | |
1c2cb7e0 EA |
364 | build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ |
365 | /* DeviceID mapping index (ignored since interrupts are GSIV based) */ | |
366 | build_append_int_noprefix(table_data, 0, 4); | |
271cbb2f | 367 | |
a703b4f6 | 368 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f | 369 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 PM |
370 | } |
371 | ||
1c2cb7e0 | 372 | /* Table 17 Root Complex Node */ |
271cbb2f IM |
373 | build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ |
374 | node_size = ROOT_COMPLEX_ENTRY_SIZE + | |
375 | ID_MAPPING_ENTRY_SIZE * rc_mapping_count; | |
376 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
377 | build_append_int_noprefix(table_data, 3, 1); /* Revision */ |
378 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
379 | /* Number of ID mappings */ |
380 | build_append_int_noprefix(table_data, rc_mapping_count, 4); | |
381 | /* Reference to ID Array */ | |
382 | build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); | |
383 | ||
1c2cb7e0 | 384 | /* Table 14 Memory access properties */ |
271cbb2f IM |
385 | /* CCA: Cache Coherent Attribute */ |
386 | build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); | |
387 | build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ | |
388 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
1c2cb7e0 EA |
389 | /* Table 15 Memory Access Flags */ |
390 | build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); | |
271cbb2f IM |
391 | |
392 | build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ | |
393 | /* MCFG pci_segment */ | |
394 | build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ | |
395 | ||
1c2cb7e0 EA |
396 | /* Memory address size limit */ |
397 | build_append_int_noprefix(table_data, 64, 1); | |
398 | ||
399 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
400 | ||
271cbb2f | 401 | /* Output Reference */ |
a703b4f6 | 402 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
403 | AcpiIortIdMapping *range; |
404 | ||
405 | /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ | |
406 | for (i = 0; i < smmu_idmaps->len; i++) { | |
42e0f050 | 407 | range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 408 | /* output IORT node is the smmuv3 node */ |
271cbb2f IM |
409 | build_iort_id_mapping(table_data, range->input_base, |
410 | range->id_count, smmu_offset); | |
42e0f050 XW |
411 | } |
412 | ||
413 | /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ | |
414 | for (i = 0; i < its_idmaps->len; i++) { | |
42e0f050 | 415 | range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 416 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f IM |
417 | build_iort_id_mapping(table_data, range->input_base, |
418 | range->id_count, iort_node_offset); | |
42e0f050 | 419 | } |
a703b4f6 PM |
420 | } else { |
421 | /* output IORT node is the ITS group node (the first node) */ | |
271cbb2f | 422 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 | 423 | } |
e78f1222 | 424 | |
3548494e | 425 | acpi_table_end(linker, &table); |
42e0f050 XW |
426 | g_array_free(smmu_idmaps, true); |
427 | g_array_free(its_idmaps, true); | |
e78f1222 PM |
428 | } |
429 | ||
a86d86ac IM |
430 | /* |
431 | * Serial Port Console Redirection Table (SPCR) | |
432 | * Rev: 1.07 | |
433 | */ | |
f264d51d | 434 | static void |
7dd0b070 | 435 | spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
f264d51d | 436 | { |
7dd0b070 SJH |
437 | AcpiSpcrData serial = { |
438 | .interface_type = 3, /* ARM PL011 UART */ | |
439 | .base_addr.id = AML_AS_SYSTEM_MEMORY, | |
440 | .base_addr.width = 32, | |
441 | .base_addr.offset = 0, | |
442 | .base_addr.size = 3, | |
443 | .base_addr.addr = vms->memmap[VIRT_UART].base, | |
444 | .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ | |
445 | .pc_interrupt = 0, /* IRQ */ | |
446 | .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE), | |
447 | .baud_rate = 3, /* 9600 */ | |
448 | .parity = 0, /* No Parity */ | |
449 | .stop_bits = 1, /* 1 Stop bit */ | |
450 | .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ | |
451 | .terminal_type = 0, /* VT100 */ | |
452 | .language = 0, /* Language */ | |
453 | .pci_device_id = 0xffff, /* not a PCI device*/ | |
454 | .pci_vendor_id = 0xffff, /* not a PCI device*/ | |
455 | .pci_bus = 0, | |
456 | .pci_device = 0, | |
457 | .pci_function = 0, | |
458 | .pci_flags = 0, | |
459 | .pci_segment = 0, | |
460 | }; | |
f264d51d | 461 | |
7dd0b070 | 462 | build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id); |
f264d51d AJ |
463 | } |
464 | ||
e5b6d55a IM |
465 | /* |
466 | * ACPI spec, Revision 5.1 | |
467 | * 5.2.16 System Resource Affinity Table (SRAT) | |
468 | */ | |
2b302e1e | 469 | static void |
da4f09a7 | 470 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
2b302e1e | 471 | { |
255bf20f | 472 | int i; |
2b302e1e | 473 | uint64_t mem_base; |
4ccf5826 | 474 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
aa570207 TX |
475 | MachineState *ms = MACHINE(vms); |
476 | const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); | |
255bf20f IM |
477 | AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, |
478 | .oem_table_id = vms->oem_table_id }; | |
2b302e1e | 479 | |
255bf20f IM |
480 | acpi_table_begin(&table, table_data); |
481 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
482 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
2b302e1e | 483 | |
4ccf5826 | 484 | for (i = 0; i < cpu_list->len; ++i) { |
e5b6d55a IM |
485 | uint32_t nodeid = cpu_list->cpus[i].props.node_id; |
486 | /* | |
487 | * 5.2.16.4 GICC Affinity Structure | |
488 | */ | |
489 | build_append_int_noprefix(table_data, 3, 1); /* Type */ | |
490 | build_append_int_noprefix(table_data, 18, 1); /* Length */ | |
491 | build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ | |
492 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
493 | /* Flags, Table 5-76 */ | |
494 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
495 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
2b302e1e | 496 | } |
2b302e1e | 497 | |
da4f09a7 | 498 | mem_base = vms->memmap[VIRT_MEM].base; |
aa570207 | 499 | for (i = 0; i < ms->numa_state->num_nodes; ++i) { |
7e721e7b | 500 | if (ms->numa_state->nodes[i].node_mem > 0) { |
e5b6d55a | 501 | build_srat_memory(table_data, mem_base, |
7e721e7b | 502 | ms->numa_state->nodes[i].node_mem, i, |
66c353ce | 503 | MEM_AFFINITY_ENABLED); |
7e721e7b | 504 | mem_base += ms->numa_state->nodes[i].node_mem; |
66c353ce | 505 | } |
2b302e1e SZ |
506 | } |
507 | ||
0a5b5acd AA |
508 | build_srat_generic_pci_initiator(table_data); |
509 | ||
c3b0cf6e VV |
510 | if (ms->nvdimms_state->is_enabled) { |
511 | nvdimm_build_srat(table_data); | |
512 | } | |
513 | ||
442da7dc | 514 | if (ms->device_memory) { |
e5b6d55a | 515 | build_srat_memory(table_data, ms->device_memory->base, |
442da7dc SK |
516 | memory_region_size(&ms->device_memory->mr), |
517 | ms->numa_state->num_nodes - 1, | |
518 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
519 | } | |
520 | ||
255bf20f | 521 | acpi_table_end(linker, &table); |
2b302e1e SZ |
522 | } |
523 | ||
41041e57 | 524 | /* |
1ec896fe PM |
525 | * ACPI spec, Revision 6.5 |
526 | * 5.2.25 Generic Timer Description Table (GTDT) | |
41041e57 | 527 | */ |
ee246400 | 528 | static void |
8dd845d3 | 529 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
ee246400 | 530 | { |
8dd845d3 | 531 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
41041e57 IM |
532 | /* |
533 | * Table 5-117 Flag Definitions | |
534 | * set only "Timer interrupt Mode" and assume "Timer Interrupt | |
535 | * polarity" bit as '0: Interrupt is Active high' | |
536 | */ | |
537 | uint32_t irqflags = vmc->claim_edge_triggered_timers ? | |
538 | 1 : /* Interrupt is Edge triggered */ | |
539 | 0; /* Interrupt is Level triggered */ | |
1ec896fe | 540 | AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, |
41041e57 | 541 | .oem_table_id = vms->oem_table_id }; |
ee246400 | 542 | |
41041e57 | 543 | acpi_table_begin(&table, table_data); |
ee246400 | 544 | |
41041e57 | 545 | /* CntControlBase Physical Address */ |
5dbc9a27 | 546 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); |
41041e57 IM |
547 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
548 | /* | |
549 | * FIXME: clarify comment: | |
550 | * The interrupt values are the same with the device tree when adding 16 | |
551 | */ | |
552 | /* Secure EL1 timer GSIV */ | |
9036e917 | 553 | build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); |
41041e57 IM |
554 | /* Secure EL1 timer Flags */ |
555 | build_append_int_noprefix(table_data, irqflags, 4); | |
556 | /* Non-Secure EL1 timer GSIV */ | |
9036e917 | 557 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); |
41041e57 IM |
558 | /* Non-Secure EL1 timer Flags */ |
559 | build_append_int_noprefix(table_data, irqflags | | |
560 | 1UL << 2, /* Always-on Capability */ | |
561 | 4); | |
562 | /* Virtual timer GSIV */ | |
9036e917 | 563 | build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); |
41041e57 IM |
564 | /* Virtual Timer Flags */ |
565 | build_append_int_noprefix(table_data, irqflags, 4); | |
566 | /* Non-Secure EL2 timer GSIV */ | |
9036e917 | 567 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); |
41041e57 IM |
568 | /* Non-Secure EL2 timer Flags */ |
569 | build_append_int_noprefix(table_data, irqflags, 4); | |
570 | /* CntReadBase Physical address */ | |
5dbc9a27 | 571 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); |
41041e57 IM |
572 | /* Platform Timer Count */ |
573 | build_append_int_noprefix(table_data, 0, 4); | |
574 | /* Platform Timer Offset */ | |
575 | build_append_int_noprefix(table_data, 0, 4); | |
1ec896fe PM |
576 | if (vms->ns_el2_virt_timer_irq) { |
577 | /* Virtual EL2 Timer GSIV */ | |
578 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); | |
579 | /* Virtual EL2 Timer Flags */ | |
580 | build_append_int_noprefix(table_data, irqflags, 4); | |
581 | } else { | |
582 | build_append_int_noprefix(table_data, 0, 4); | |
583 | build_append_int_noprefix(table_data, 0, 4); | |
584 | } | |
41041e57 | 585 | acpi_table_end(linker, &table); |
ee246400 SZ |
586 | } |
587 | ||
f0dc9a5d EA |
588 | /* Debug Port Table 2 (DBG2) */ |
589 | static void | |
590 | build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
591 | { | |
592 | AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, | |
593 | .oem_table_id = vms->oem_table_id }; | |
594 | int dbg2devicelength; | |
595 | const char name[] = "COM0"; | |
596 | const int namespace_length = sizeof(name); | |
597 | ||
598 | acpi_table_begin(&table, table_data); | |
599 | ||
600 | dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ | |
601 | 12 + /* BaseAddressRegister[] */ | |
602 | 4 + /* AddressSize[] */ | |
603 | namespace_length /* NamespaceString[] */; | |
604 | ||
605 | /* OffsetDbgDeviceInfo */ | |
606 | build_append_int_noprefix(table_data, 44, 4); | |
607 | /* NumberDbgDeviceInfo */ | |
608 | build_append_int_noprefix(table_data, 1, 4); | |
609 | ||
610 | /* Table 2. Debug Device Information structure format */ | |
611 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
612 | build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ | |
613 | /* NumberofGenericAddressRegisters */ | |
614 | build_append_int_noprefix(table_data, 1, 1); | |
615 | /* NameSpaceStringLength */ | |
616 | build_append_int_noprefix(table_data, namespace_length, 2); | |
617 | build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ | |
618 | build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ | |
619 | /* OemDataOffset (0 means no OEM data) */ | |
620 | build_append_int_noprefix(table_data, 0, 2); | |
621 | ||
622 | /* Port Type */ | |
623 | build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); | |
624 | /* Port Subtype */ | |
625 | build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); | |
626 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
627 | /* BaseAddressRegisterOffset */ | |
628 | build_append_int_noprefix(table_data, 22, 2); | |
629 | /* AddressSizeOffset */ | |
630 | build_append_int_noprefix(table_data, 34, 2); | |
631 | ||
632 | /* BaseAddressRegister[] */ | |
41f7b58b | 633 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, |
f0dc9a5d EA |
634 | vms->memmap[VIRT_UART].base); |
635 | ||
636 | /* AddressSize[] */ | |
637 | build_append_int_noprefix(table_data, | |
638 | vms->memmap[VIRT_UART].size, 4); | |
639 | ||
640 | /* NamespaceString[] */ | |
641 | g_array_append_vals(table_data, name, namespace_length); | |
642 | ||
643 | acpi_table_end(linker, &table); | |
644 | }; | |
645 | ||
99a7545f | 646 | /* |
7fe4c35c | 647 | * ACPI spec, Revision 6.0 Errata A |
99a7545f IM |
648 | * 5.2.12 Multiple APIC Description Table (MADT) |
649 | */ | |
37f33084 IM |
650 | static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) |
651 | { | |
652 | build_append_int_noprefix(table_data, 0xE, 1); /* Type */ | |
653 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
654 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
b3db996f | 655 | /* Discovery Range Base Address */ |
37f33084 IM |
656 | build_append_int_noprefix(table_data, base, 8); |
657 | build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ | |
658 | } | |
659 | ||
982d06c5 | 660 | static void |
da4f09a7 | 661 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
982d06c5 | 662 | { |
37f33084 | 663 | int i; |
da4f09a7 | 664 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
da4f09a7 | 665 | const MemMapEntry *memmap = vms->memmap; |
7fe4c35c | 666 | AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, |
99a7545f | 667 | .oem_table_id = vms->oem_table_id }; |
982d06c5 | 668 | |
99a7545f IM |
669 | acpi_table_begin(&table, table_data); |
670 | /* Local Interrupt Controller Address */ | |
671 | build_append_int_noprefix(table_data, 0, 4); | |
37f33084 IM |
672 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ |
673 | ||
674 | /* 5.2.12.15 GIC Distributor Structure */ | |
675 | build_append_int_noprefix(table_data, 0xC, 1); /* Type */ | |
676 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
677 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
678 | build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ | |
679 | /* Physical Base Address */ | |
680 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); | |
681 | build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ | |
682 | /* GIC version */ | |
683 | build_append_int_noprefix(table_data, vms->gic_version, 1); | |
684 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
982d06c5 | 685 | |
9cd07db9 | 686 | for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { |
5d9c1756 | 687 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
37f33084 | 688 | uint64_t physical_base_address = 0, gich = 0, gicv = 0; |
9036e917 | 689 | uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; |
37f33084 | 690 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? |
9036e917 | 691 | VIRTUAL_PMU_IRQ : 0; |
5d9c1756 | 692 | |
e1f04578 | 693 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
37f33084 IM |
694 | physical_base_address = memmap[VIRT_GIC_CPU].base; |
695 | gicv = memmap[VIRT_GIC_VCPU].base; | |
696 | gich = memmap[VIRT_GIC_HYP].base; | |
f2fbface | 697 | } |
8433dee0 | 698 | |
37f33084 IM |
699 | /* 5.2.12.14 GIC Structure */ |
700 | build_append_int_noprefix(table_data, 0xB, 1); /* Type */ | |
7fe4c35c | 701 | build_append_int_noprefix(table_data, 80, 1); /* Length */ |
37f33084 IM |
702 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ |
703 | build_append_int_noprefix(table_data, i, 4); /* GIC ID */ | |
704 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
705 | /* Flags */ | |
706 | build_append_int_noprefix(table_data, 1, 4); /* Enabled */ | |
707 | /* Parking Protocol Version */ | |
708 | build_append_int_noprefix(table_data, 0, 4); | |
709 | /* Performance Interrupt GSIV */ | |
710 | build_append_int_noprefix(table_data, pmu_interrupt, 4); | |
711 | build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ | |
712 | /* Physical Base Address */ | |
713 | build_append_int_noprefix(table_data, physical_base_address, 8); | |
714 | build_append_int_noprefix(table_data, gicv, 8); /* GICV */ | |
715 | build_append_int_noprefix(table_data, gich, 8); /* GICH */ | |
716 | /* VGIC Maintenance interrupt */ | |
717 | build_append_int_noprefix(table_data, vgic_interrupt, 4); | |
718 | build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ | |
719 | /* MPIDR */ | |
c4380f7b | 720 | build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); |
7fe4c35c ML |
721 | /* Processor Power Efficiency Class */ |
722 | build_append_int_noprefix(table_data, 0, 1); | |
723 | /* Reserved */ | |
724 | build_append_int_noprefix(table_data, 0, 3); | |
f2fbface SZ |
725 | } |
726 | ||
e1f04578 | 727 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
37f33084 IM |
728 | build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, |
729 | memmap[VIRT_GIC_REDIST].size); | |
730 | if (virt_gicv3_redist_region_count(vms) == 2) { | |
731 | build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, | |
732 | memmap[VIRT_HIGH_GIC_REDIST2].size); | |
a1de312f EA |
733 | } |
734 | ||
da4f09a7 | 735 | if (its_class_name() && !vmc->no_its) { |
37f33084 IM |
736 | /* |
737 | * ACPI spec, Revision 6.0 Errata A | |
738 | * (original 6.0 definition has invalid Length) | |
739 | * 5.2.12.18 GIC ITS Structure | |
740 | */ | |
741 | build_append_int_noprefix(table_data, 0xF, 1); /* Type */ | |
742 | build_append_int_noprefix(table_data, 20, 1); /* Length */ | |
743 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
744 | build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ | |
745 | /* Physical Base Address */ | |
746 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); | |
747 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
13e5c54d | 748 | } |
b92ad394 | 749 | } else { |
37f33084 IM |
750 | const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; |
751 | ||
752 | /* 5.2.12.16 GIC MSI Frame Structure */ | |
753 | build_append_int_noprefix(table_data, 0xD, 1); /* Type */ | |
754 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
755 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
756 | build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ | |
757 | /* Physical Base Address */ | |
758 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); | |
759 | build_append_int_noprefix(table_data, 1, 4); /* Flags */ | |
760 | /* SPI Count */ | |
761 | build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); | |
762 | build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ | |
b92ad394 | 763 | } |
99a7545f | 764 | acpi_table_end(linker, &table); |
982d06c5 SZ |
765 | } |
766 | ||
c2f7c0c3 | 767 | /* FADT */ |
4496d1d3 | 768 | static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, |
8612f8bd | 769 | VirtMachineState *vms, unsigned dsdt_tbl_offset) |
c2f7c0c3 | 770 | { |
1ec896fe | 771 | /* ACPI v6.3 */ |
dd1b2037 | 772 | AcpiFadtData fadt = { |
4496d1d3 | 773 | .rev = 6, |
1ec896fe | 774 | .minor_ver = 3, |
dd1b2037 IM |
775 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, |
776 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
777 | }; | |
79e993a0 AJ |
778 | |
779 | switch (vms->psci_conduit) { | |
780 | case QEMU_PSCI_CONDUIT_DISABLED: | |
dd1b2037 | 781 | fadt.arm_boot_arch = 0; |
79e993a0 AJ |
782 | break; |
783 | case QEMU_PSCI_CONDUIT_HVC: | |
dd1b2037 IM |
784 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | |
785 | ACPI_FADT_ARM_PSCI_USE_HVC; | |
79e993a0 AJ |
786 | break; |
787 | case QEMU_PSCI_CONDUIT_SMC: | |
dd1b2037 | 788 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; |
79e993a0 AJ |
789 | break; |
790 | default: | |
791 | g_assert_not_reached(); | |
792 | } | |
c2f7c0c3 | 793 | |
602b4582 | 794 | build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); |
c2f7c0c3 SZ |
795 | } |
796 | ||
dfccd8cf SZ |
797 | /* DSDT */ |
798 | static void | |
da4f09a7 | 799 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
dfccd8cf | 800 | { |
2c1fb4d5 | 801 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
dfccd8cf | 802 | Aml *scope, *dsdt; |
cff51ac9 | 803 | MachineState *ms = MACHINE(vms); |
da4f09a7 AJ |
804 | const MemMapEntry *memmap = vms->memmap; |
805 | const int *irqmap = vms->irqmap; | |
fc02b869 IM |
806 | AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, |
807 | .oem_table_id = vms->oem_table_id }; | |
dfccd8cf | 808 | |
fc02b869 | 809 | acpi_table_begin(&table, table_data); |
dfccd8cf | 810 | dsdt = init_aml_allocator(); |
dfccd8cf | 811 | |
67736a25 SZ |
812 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
813 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
814 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
815 | * the RTC ACPI device at all when using UEFI. | |
816 | */ | |
dfccd8cf | 817 | scope = aml_scope("\\_SB"); |
9cd07db9 | 818 | acpi_dsdt_add_cpus(scope, vms); |
dfccd8cf SZ |
819 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], |
820 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
2c1fb4d5 AJ |
821 | if (vmc->acpi_expose_flash) { |
822 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | |
823 | } | |
4c7f4f4f | 824 | fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); |
57ba8436 S |
825 | virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, |
826 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), | |
827 | 0, NUM_VIRTIO_TRANSPORTS); | |
c8f008c4 | 828 | acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); |
cff51ac9 SK |
829 | if (vms->acpi_dev) { |
830 | build_ged_aml(scope, "\\_SB."GED_DEVICE, | |
831 | HOTPLUG_HANDLER(vms->acpi_dev), | |
832 | irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, | |
833 | memmap[VIRT_ACPI_GED].base); | |
1962f31b SK |
834 | } else { |
835 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], | |
836 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
cff51ac9 SK |
837 | } |
838 | ||
839 | if (vms->acpi_dev) { | |
840 | uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), | |
841 | "ged-event", &error_abort); | |
842 | ||
843 | if (event & ACPI_GED_MEM_HOTPLUG_EVT) { | |
844 | build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, | |
845 | AML_SYSTEM_MEMORY, | |
846 | memmap[VIRT_PCDIMM_ACPI].base); | |
847 | } | |
848 | } | |
849 | ||
ac6aa59a | 850 | acpi_dsdt_add_power_button(scope); |
f50be48a | 851 | #ifdef CONFIG_TPM |
5ab540e9 | 852 | acpi_dsdt_add_tpm(scope, vms); |
f50be48a | 853 | #endif |
d4e5de1a | 854 | |
dfccd8cf SZ |
855 | aml_append(dsdt, scope); |
856 | ||
fc02b869 | 857 | /* copy AML table into ACPI tables blob */ |
dfccd8cf | 858 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
fc02b869 IM |
859 | |
860 | acpi_table_end(linker, &table); | |
dfccd8cf SZ |
861 | free_aml_allocator(); |
862 | } | |
863 | ||
f5d8c8cd SZ |
864 | typedef |
865 | struct AcpiBuildState { | |
866 | /* Copy of table in RAM (for patching). */ | |
867 | MemoryRegion *table_mr; | |
868 | MemoryRegion *rsdp_mr; | |
869 | MemoryRegion *linker_mr; | |
870 | /* Is table patched? */ | |
871 | bool patched; | |
f5d8c8cd SZ |
872 | } AcpiBuildState; |
873 | ||
451b1570 YM |
874 | static void acpi_align_size(GArray *blob, unsigned align) |
875 | { | |
876 | /* | |
877 | * Align size to multiple of given size. This reduces the chance | |
878 | * we need to change size in the future (breaking cross version migration). | |
879 | */ | |
880 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); | |
881 | } | |
882 | ||
f5d8c8cd | 883 | static |
da4f09a7 | 884 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
f5d8c8cd | 885 | { |
da4f09a7 | 886 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
f5d8c8cd | 887 | GArray *table_offsets; |
cb51ac2f | 888 | unsigned dsdt, xsdt; |
dfccd8cf | 889 | GArray *tables_blob = tables->table_data; |
aa570207 | 890 | MachineState *ms = MACHINE(vms); |
f5d8c8cd SZ |
891 | |
892 | table_offsets = g_array_new(false, true /* clear */, | |
893 | sizeof(uint32_t)); | |
894 | ||
ad9671b8 IM |
895 | bios_linker_loader_alloc(tables->linker, |
896 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
f5d8c8cd SZ |
897 | 64, false /* high memory */); |
898 | ||
dfccd8cf | 899 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 900 | dsdt = tables_blob->len; |
da4f09a7 | 901 | build_dsdt(tables_blob, tables->linker, vms); |
dfccd8cf | 902 | |
70d23ed5 | 903 | /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ |
c2f7c0c3 | 904 | acpi_add_table(table_offsets, tables_blob); |
4496d1d3 | 905 | build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); |
c2f7c0c3 | 906 | |
982d06c5 | 907 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 908 | build_madt(tables_blob, tables->linker, vms); |
982d06c5 | 909 | |
70d23ed5 YW |
910 | if (!vmc->no_cpu_topology) { |
911 | acpi_add_table(table_offsets, tables_blob); | |
912 | build_pptt(tables_blob, tables->linker, ms, | |
913 | vms->oem_id, vms->oem_table_id); | |
914 | } | |
915 | ||
ee246400 | 916 | acpi_add_table(table_offsets, tables_blob); |
8dd845d3 | 917 | build_gtdt(tables_blob, tables->linker, vms); |
ee246400 | 918 | |
84344884 | 919 | acpi_add_table(table_offsets, tables_blob); |
48cefd94 WY |
920 | { |
921 | AcpiMcfgInfo mcfg = { | |
922 | .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, | |
923 | .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, | |
924 | }; | |
602b4582 MP |
925 | build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, |
926 | vms->oem_table_id); | |
48cefd94 | 927 | } |
84344884 | 928 | |
f264d51d | 929 | acpi_add_table(table_offsets, tables_blob); |
7dd0b070 | 930 | spcr_setup(tables_blob, tables->linker, vms); |
f264d51d | 931 | |
f0dc9a5d EA |
932 | acpi_add_table(table_offsets, tables_blob); |
933 | build_dbg2(tables_blob, tables->linker, vms); | |
934 | ||
aa16508f DG |
935 | if (vms->ras) { |
936 | build_ghes_error_table(tables->hardware_errors, tables->linker); | |
205cc75d | 937 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
938 | acpi_build_hest(tables_blob, tables->linker, vms->oem_id, |
939 | vms->oem_table_id); | |
aa16508f DG |
940 | } |
941 | ||
aa570207 | 942 | if (ms->numa_state->num_nodes > 0) { |
2b302e1e | 943 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 944 | build_srat(tables_blob, tables->linker, vms); |
118154b7 | 945 | if (ms->numa_state->have_numa_distance) { |
94a66456 | 946 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
947 | build_slit(tables_blob, tables->linker, ms, vms->oem_id, |
948 | vms->oem_table_id); | |
94a66456 | 949 | } |
7cbd3fd3 XC |
950 | |
951 | if (ms->numa_state->hmat_enabled) { | |
952 | acpi_add_table(table_offsets, tables_blob); | |
953 | build_hmat(tables_blob, tables->linker, ms->numa_state, | |
954 | vms->oem_id, vms->oem_table_id); | |
955 | } | |
2b302e1e SZ |
956 | } |
957 | ||
b5a60bee KL |
958 | if (ms->nvdimms_state->is_enabled) { |
959 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, | |
602b4582 MP |
960 | ms->nvdimms_state, ms->ram_slots, vms->oem_id, |
961 | vms->oem_table_id); | |
b5a60bee KL |
962 | } |
963 | ||
da4f09a7 | 964 | if (its_class_name() && !vmc->no_its) { |
e78f1222 | 965 | acpi_add_table(table_offsets, tables_blob); |
a703b4f6 | 966 | build_iort(tables_blob, tables->linker, vms); |
e78f1222 PM |
967 | } |
968 | ||
f50be48a | 969 | #ifdef CONFIG_TPM |
80bde693 EA |
970 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { |
971 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 MP |
972 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, |
973 | vms->oem_table_id); | |
80bde693 | 974 | } |
f50be48a | 975 | #endif |
80bde693 | 976 | |
cf1a5cc9 JPB |
977 | if (vms->iommu == VIRT_IOMMU_VIRTIO) { |
978 | acpi_add_table(table_offsets, tables_blob); | |
979 | build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, | |
980 | vms->oem_id, vms->oem_table_id); | |
981 | } | |
982 | ||
cb51ac2f AB |
983 | /* XSDT is pointed to by RSDP */ |
984 | xsdt = tables_blob->len; | |
602b4582 MP |
985 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
986 | vms->oem_table_id); | |
243bdb79 | 987 | |
d4bec5d8 | 988 | /* RSDP is in FSEG memory, so allocate it separately */ |
5c5fce1a SO |
989 | { |
990 | AcpiRsdpData rsdp_data = { | |
991 | .revision = 2, | |
602b4582 | 992 | .oem_id = vms->oem_id, |
5c5fce1a SO |
993 | .xsdt_tbl_offset = &xsdt, |
994 | .rsdt_tbl_offset = NULL, | |
995 | }; | |
996 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
997 | } | |
d4bec5d8 | 998 | |
451b1570 YM |
999 | /* |
1000 | * The align size is 128, warn if 64k is not enough therefore | |
1001 | * the align size could be resized. | |
1002 | */ | |
1003 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { | |
1004 | warn_report("ACPI table size %u exceeds %d bytes," | |
1005 | " migration may not work", | |
1006 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
1007 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
cd25f5d3 | 1008 | " or PCI bridges.\n"); |
451b1570 YM |
1009 | } |
1010 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); | |
1011 | ||
1012 | ||
f5d8c8cd SZ |
1013 | /* Cleanup memory that's no longer used. */ |
1014 | g_array_free(table_offsets, true); | |
1015 | } | |
1016 | ||
1017 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
1018 | { | |
1019 | uint32_t size = acpi_data_len(data); | |
1020 | ||
1021 | /* Make sure RAM size is correct - in case it got changed | |
1022 | * e.g. by migration */ | |
1023 | memory_region_ram_resize(mr, size, &error_abort); | |
1024 | ||
1025 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
1026 | memory_region_set_dirty(mr, 0, size); | |
1027 | } | |
1028 | ||
3f8752b4 | 1029 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
1030 | { |
1031 | AcpiBuildState *build_state = build_opaque; | |
1032 | AcpiBuildTables tables; | |
1033 | ||
1034 | /* No state to update or already patched? Nothing to do. */ | |
1035 | if (!build_state || build_state->patched) { | |
1036 | return; | |
1037 | } | |
1038 | build_state->patched = true; | |
1039 | ||
1040 | acpi_build_tables_init(&tables); | |
1041 | ||
4dad9e74 | 1042 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); |
f5d8c8cd SZ |
1043 | |
1044 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
1045 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
0e9b9eda | 1046 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
f5d8c8cd | 1047 | |
f5d8c8cd SZ |
1048 | acpi_build_tables_cleanup(&tables, true); |
1049 | } | |
1050 | ||
1051 | static void virt_acpi_build_reset(void *build_opaque) | |
1052 | { | |
1053 | AcpiBuildState *build_state = build_opaque; | |
1054 | build_state->patched = false; | |
1055 | } | |
1056 | ||
f5d8c8cd SZ |
1057 | static const VMStateDescription vmstate_virt_acpi_build = { |
1058 | .name = "virt_acpi_build", | |
1059 | .version_id = 1, | |
1060 | .minimum_version_id = 1, | |
607ef570 | 1061 | .fields = (const VMStateField[]) { |
f5d8c8cd SZ |
1062 | VMSTATE_BOOL(patched, AcpiBuildState), |
1063 | VMSTATE_END_OF_LIST() | |
1064 | }, | |
1065 | }; | |
1066 | ||
e9a8e474 | 1067 | void virt_acpi_setup(VirtMachineState *vms) |
f5d8c8cd SZ |
1068 | { |
1069 | AcpiBuildTables tables; | |
1070 | AcpiBuildState *build_state; | |
a08a6462 | 1071 | AcpiGedState *acpi_ged_state; |
f5d8c8cd | 1072 | |
af1f60a4 | 1073 | if (!vms->fw_cfg) { |
f5d8c8cd SZ |
1074 | trace_virt_acpi_setup(); |
1075 | return; | |
1076 | } | |
1077 | ||
17e89077 | 1078 | if (!virt_is_acpi_enabled(vms)) { |
f5d8c8cd SZ |
1079 | trace_virt_acpi_setup(); |
1080 | return; | |
1081 | } | |
1082 | ||
1083 | build_state = g_malloc0(sizeof *build_state); | |
f5d8c8cd SZ |
1084 | |
1085 | acpi_build_tables_init(&tables); | |
da4f09a7 | 1086 | virt_acpi_build(vms, &tables); |
f5d8c8cd SZ |
1087 | |
1088 | /* Now expose it all to Guest */ | |
82f76c67 WY |
1089 | build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1090 | build_state, tables.table_data, | |
6930ba0d | 1091 | ACPI_BUILD_TABLE_FILE); |
f5d8c8cd SZ |
1092 | assert(build_state->table_mr != NULL); |
1093 | ||
6930ba0d DH |
1094 | build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1095 | build_state, | |
1096 | tables.linker->cmd_blob, | |
1097 | ACPI_BUILD_LOADER_FILE); | |
f5d8c8cd | 1098 | |
af1f60a4 AJ |
1099 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, |
1100 | acpi_data_len(tables.tcpalog)); | |
f5d8c8cd | 1101 | |
a08a6462 DG |
1102 | if (vms->ras) { |
1103 | assert(vms->acpi_dev); | |
1104 | acpi_ged_state = ACPI_GED(vms->acpi_dev); | |
1105 | acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, | |
1106 | vms->fw_cfg, tables.hardware_errors); | |
1107 | } | |
1108 | ||
82f76c67 WY |
1109 | build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1110 | build_state, tables.rsdp, | |
6930ba0d | 1111 | ACPI_BUILD_RSDP_FILE); |
f5d8c8cd SZ |
1112 | |
1113 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
1114 | virt_acpi_build_reset(build_state); | |
1115 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
1116 | ||
1117 | /* Cleanup tables but don't free the memory: we track it | |
1118 | * in build_state. | |
1119 | */ | |
1120 | acpi_build_tables_cleanup(&tables, false); | |
1121 | } |