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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
f5d8c8cd SZ |
30 | #include "qemu-common.h" |
31 | #include "hw/arm/virt-acpi-build.h" | |
32 | #include "qemu/bitmap.h" | |
33 | #include "trace.h" | |
34 | #include "qom/cpu.h" | |
35 | #include "target-arm/cpu.h" | |
36 | #include "hw/acpi/acpi-defs.h" | |
37 | #include "hw/acpi/acpi.h" | |
38 | #include "hw/nvram/fw_cfg.h" | |
39 | #include "hw/acpi/bios-linker-loader.h" | |
40 | #include "hw/loader.h" | |
41 | #include "hw/hw.h" | |
42 | #include "hw/acpi/aml-build.h" | |
84344884 | 43 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 44 | #include "hw/pci/pci.h" |
f5d8c8cd | 45 | |
dfccd8cf | 46 | #define ARM_SPI_BASE 32 |
ac6aa59a | 47 | #define ACPI_POWER_BUTTON_DEVICE "PWRB" |
dfccd8cf SZ |
48 | |
49 | static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) | |
50 | { | |
51 | uint16_t i; | |
52 | ||
53 | for (i = 0; i < smp_cpus; i++) { | |
54 | Aml *dev = aml_device("C%03x", i); | |
55 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); | |
56 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
57 | aml_append(scope, dev); | |
58 | } | |
59 | } | |
60 | ||
61 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 62 | uint32_t uart_irq) |
dfccd8cf SZ |
63 | { |
64 | Aml *dev = aml_device("COM0"); | |
65 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
66 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
67 | ||
68 | Aml *crs = aml_resource_template(); | |
69 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
70 | uart_memmap->size, AML_READ_WRITE)); | |
71 | aml_append(crs, | |
72 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 73 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 74 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d AJ |
75 | |
76 | /* The _ADR entry is used to link this device to the UART described | |
77 | * in the SPCR table, i.e. SPCR.base_address.address == _ADR. | |
78 | */ | |
79 | aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); | |
80 | ||
dfccd8cf SZ |
81 | aml_append(scope, dev); |
82 | } | |
83 | ||
dfccd8cf SZ |
84 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
85 | { | |
86 | Aml *dev, *crs; | |
87 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 88 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
89 | |
90 | dev = aml_device("FLS0"); | |
91 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
92 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
93 | ||
94 | crs = aml_resource_template(); | |
95 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
96 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
97 | aml_append(scope, dev); | |
98 | ||
99 | dev = aml_device("FLS1"); | |
100 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
101 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
102 | crs = aml_resource_template(); | |
103 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
104 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
105 | aml_append(scope, dev); | |
106 | } | |
107 | ||
108 | static void acpi_dsdt_add_virtio(Aml *scope, | |
109 | const MemMapEntry *virtio_mmio_memmap, | |
45fcf539 | 110 | uint32_t mmio_irq, int num) |
dfccd8cf SZ |
111 | { |
112 | hwaddr base = virtio_mmio_memmap->base; | |
113 | hwaddr size = virtio_mmio_memmap->size; | |
dfccd8cf SZ |
114 | int i; |
115 | ||
116 | for (i = 0; i < num; i++) { | |
45fcf539 | 117 | uint32_t irq = mmio_irq + i; |
dfccd8cf SZ |
118 | Aml *dev = aml_device("VR%02u", i); |
119 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | |
120 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
121 | ||
122 | Aml *crs = aml_resource_template(); | |
123 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
124 | aml_append(crs, | |
125 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 126 | AML_EXCLUSIVE, &irq, 1)); |
dfccd8cf SZ |
127 | aml_append(dev, aml_name_decl("_CRS", crs)); |
128 | aml_append(scope, dev); | |
129 | base += size; | |
130 | } | |
131 | } | |
132 | ||
45fcf539 IM |
133 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
134 | uint32_t irq, bool use_highmem) | |
d4e5de1a SZ |
135 | { |
136 | Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; | |
137 | int i, bus_no; | |
138 | hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; | |
139 | hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; | |
140 | hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; | |
141 | hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; | |
142 | hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; | |
143 | hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; | |
144 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
145 | ||
146 | Aml *dev = aml_device("%s", "PCI0"); | |
147 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); | |
148 | aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); | |
149 | aml_append(dev, aml_name_decl("_SEG", aml_int(0))); | |
150 | aml_append(dev, aml_name_decl("_BBN", aml_int(0))); | |
151 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
152 | aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); | |
153 | aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); | |
bc64b96c | 154 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
d4e5de1a SZ |
155 | |
156 | /* Declare the PCI Routing Table. */ | |
157 | Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); | |
158 | for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { | |
159 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
160 | int gsi = (i + bus_no) % PCI_NUM_PINS; | |
161 | Aml *pkg = aml_package(4); | |
162 | aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); | |
163 | aml_append(pkg, aml_int(i)); | |
164 | aml_append(pkg, aml_name("GSI%d", gsi)); | |
165 | aml_append(pkg, aml_int(0)); | |
166 | aml_append(rt_pkg, pkg); | |
167 | } | |
168 | } | |
169 | aml_append(dev, aml_name_decl("_PRT", rt_pkg)); | |
170 | ||
171 | /* Create GSI link device */ | |
172 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
45fcf539 | 173 | uint32_t irqs = irq + i; |
d4e5de1a SZ |
174 | Aml *dev_gsi = aml_device("GSI%d", i); |
175 | aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); | |
176 | aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); | |
177 | crs = aml_resource_template(); | |
178 | aml_append(crs, | |
179 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 180 | AML_EXCLUSIVE, &irqs, 1)); |
d4e5de1a SZ |
181 | aml_append(dev_gsi, aml_name_decl("_PRS", crs)); |
182 | crs = aml_resource_template(); | |
183 | aml_append(crs, | |
184 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 185 | AML_EXCLUSIVE, &irqs, 1)); |
d4e5de1a | 186 | aml_append(dev_gsi, aml_name_decl("_CRS", crs)); |
4dbfc881 | 187 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
d4e5de1a SZ |
188 | aml_append(dev_gsi, method); |
189 | aml_append(dev, dev_gsi); | |
190 | } | |
191 | ||
4dbfc881 | 192 | method = aml_method("_CBA", 0, AML_NOTSERIALIZED); |
d4e5de1a SZ |
193 | aml_append(method, aml_return(aml_int(base_ecam))); |
194 | aml_append(dev, method); | |
195 | ||
4dbfc881 | 196 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); |
d4e5de1a SZ |
197 | Aml *rbuf = aml_resource_template(); |
198 | aml_append(rbuf, | |
199 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, | |
200 | 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, | |
201 | nr_pcie_buses)); | |
202 | aml_append(rbuf, | |
203 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
204 | AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, | |
205 | base_mmio + size_mmio - 1, 0x0000, size_mmio)); | |
206 | aml_append(rbuf, | |
207 | aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, | |
208 | AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, | |
209 | size_pio)); | |
210 | ||
5125f9cd PF |
211 | if (use_highmem) { |
212 | hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; | |
213 | hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; | |
214 | ||
215 | aml_append(rbuf, | |
216 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
217 | AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, | |
218 | base_mmio_high, base_mmio_high, 0x0000, | |
219 | size_mmio_high)); | |
220 | } | |
221 | ||
d4e5de1a SZ |
222 | aml_append(method, aml_name_decl("RBUF", rbuf)); |
223 | aml_append(method, aml_return(rbuf)); | |
224 | aml_append(dev, method); | |
225 | ||
226 | /* Declare an _OSC (OS Control Handoff) method */ | |
227 | aml_append(dev, aml_name_decl("SUPP", aml_int(0))); | |
228 | aml_append(dev, aml_name_decl("CTRL", aml_int(0))); | |
4dbfc881 | 229 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); |
d4e5de1a SZ |
230 | aml_append(method, |
231 | aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
232 | ||
233 | /* PCI Firmware Specification 3.0 | |
234 | * 4.5.1. _OSC Interface for PCI Host Bridge Devices | |
235 | * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is | |
236 | * identified by the Universal Unique IDentifier (UUID) | |
237 | * 33DB4D5B-1FF7-401C-9657-7441C03DD766 | |
238 | */ | |
239 | UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); | |
240 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | |
241 | aml_append(ifctx, | |
242 | aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
243 | aml_append(ifctx, | |
244 | aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
245 | aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); | |
246 | aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); | |
5530427f | 247 | aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), |
d4e5de1a SZ |
248 | aml_name("CTRL"))); |
249 | ||
250 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); | |
ca3df95d | 251 | aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), |
d4e5de1a SZ |
252 | aml_name("CDW1"))); |
253 | aml_append(ifctx, ifctx1); | |
254 | ||
255 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); | |
ca3df95d | 256 | aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), |
d4e5de1a SZ |
257 | aml_name("CDW1"))); |
258 | aml_append(ifctx, ifctx1); | |
259 | ||
260 | aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); | |
261 | aml_append(ifctx, aml_return(aml_arg(3))); | |
262 | aml_append(method, ifctx); | |
263 | ||
264 | elsectx = aml_else(); | |
ca3df95d | 265 | aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), |
d4e5de1a SZ |
266 | aml_name("CDW1"))); |
267 | aml_append(elsectx, aml_return(aml_arg(3))); | |
268 | aml_append(method, elsectx); | |
269 | aml_append(dev, method); | |
270 | ||
4dbfc881 | 271 | method = aml_method("_DSM", 4, AML_NOTSERIALIZED); |
d4e5de1a SZ |
272 | |
273 | /* PCI Firmware Specification 3.0 | |
274 | * 4.6.1. _DSM for PCI Express Slot Information | |
275 | * The UUID in _DSM in this context is | |
276 | * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} | |
277 | */ | |
278 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | |
279 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | |
280 | ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); | |
281 | uint8_t byte_list[1] = {1}; | |
282 | buf = aml_buffer(1, byte_list); | |
283 | aml_append(ifctx1, aml_return(buf)); | |
284 | aml_append(ifctx, ifctx1); | |
285 | aml_append(method, ifctx); | |
286 | ||
287 | byte_list[0] = 0; | |
288 | buf = aml_buffer(1, byte_list); | |
289 | aml_append(method, aml_return(buf)); | |
290 | aml_append(dev, method); | |
291 | ||
292 | Aml *dev_rp0 = aml_device("%s", "RP0"); | |
293 | aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); | |
294 | aml_append(dev, dev_rp0); | |
295 | aml_append(scope, dev); | |
296 | } | |
297 | ||
aeb1a36d SZ |
298 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
299 | uint32_t gpio_irq) | |
300 | { | |
301 | Aml *dev = aml_device("GPO0"); | |
302 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
303 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
304 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
305 | ||
306 | Aml *crs = aml_resource_template(); | |
307 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
308 | AML_READ_WRITE)); | |
309 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
310 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
311 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
312 | |
313 | Aml *aei = aml_resource_template(); | |
314 | /* Pin 3 for power button */ | |
315 | const uint32_t pin_list[1] = {3}; | |
316 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
317 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
318 | "GPO0", NULL, 0)); | |
319 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
320 | ||
321 | /* _E03 is handle for power button */ | |
322 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
323 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
324 | aml_int(0x80))); | |
325 | aml_append(dev, method); | |
aeb1a36d SZ |
326 | aml_append(scope, dev); |
327 | } | |
328 | ||
ac6aa59a SZ |
329 | static void acpi_dsdt_add_power_button(Aml *scope) |
330 | { | |
331 | Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); | |
332 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); | |
333 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
334 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
335 | aml_append(scope, dev); | |
336 | } | |
337 | ||
d4bec5d8 SZ |
338 | /* RSDP */ |
339 | static GArray * | |
340 | build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) | |
341 | { | |
342 | AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); | |
343 | ||
344 | bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, | |
345 | true /* fseg memory */); | |
346 | ||
347 | memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); | |
348 | memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); | |
349 | rsdp->length = cpu_to_le32(sizeof(*rsdp)); | |
350 | rsdp->revision = 0x02; | |
351 | ||
352 | /* Point to RSDT */ | |
353 | rsdp->rsdt_physical_address = cpu_to_le32(rsdt); | |
354 | /* Address to be filled by Guest linker */ | |
355 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, | |
356 | ACPI_BUILD_TABLE_FILE, | |
357 | rsdp_table, &rsdp->rsdt_physical_address, | |
358 | sizeof rsdp->rsdt_physical_address); | |
359 | rsdp->checksum = 0; | |
360 | /* Checksum to be filled by Guest linker */ | |
361 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, | |
b54ca0c3 MT |
362 | rsdp_table, rsdp, sizeof *rsdp, |
363 | &rsdp->checksum); | |
d4bec5d8 SZ |
364 | |
365 | return rsdp_table; | |
366 | } | |
367 | ||
f264d51d AJ |
368 | static void |
369 | build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) | |
370 | { | |
371 | AcpiSerialPortConsoleRedirection *spcr; | |
372 | const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; | |
373 | int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; | |
374 | ||
375 | spcr = acpi_data_push(table_data, sizeof(*spcr)); | |
376 | ||
377 | spcr->interface_type = 0x3; /* ARM PL011 UART */ | |
378 | ||
379 | spcr->base_address.space_id = AML_SYSTEM_MEMORY; | |
380 | spcr->base_address.bit_width = 8; | |
381 | spcr->base_address.bit_offset = 0; | |
382 | spcr->base_address.access_width = 1; | |
383 | spcr->base_address.address = cpu_to_le64(uart_memmap->base); | |
384 | ||
385 | spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ | |
386 | spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ | |
387 | ||
388 | spcr->baud = 3; /* Baud Rate: 3 = 9600 */ | |
389 | spcr->parity = 0; /* No Parity */ | |
390 | spcr->stopbits = 1; /* 1 Stop bit */ | |
391 | spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ | |
392 | spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ | |
393 | ||
394 | spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ | |
395 | spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ | |
396 | ||
8870ca0e | 397 | build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2, |
37ad223c | 398 | NULL, NULL); |
f264d51d AJ |
399 | } |
400 | ||
84344884 SZ |
401 | static void |
402 | build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) | |
403 | { | |
404 | AcpiTableMcfg *mcfg; | |
405 | const MemMapEntry *memmap = guest_info->memmap; | |
406 | int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); | |
407 | ||
408 | mcfg = acpi_data_push(table_data, len); | |
409 | mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); | |
410 | ||
411 | /* Only a single allocation so no need to play with segments */ | |
412 | mcfg->allocation[0].pci_segment = cpu_to_le16(0); | |
413 | mcfg->allocation[0].start_bus_number = 0; | |
414 | mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size | |
415 | / PCIE_MMCFG_SIZE_MIN) - 1; | |
416 | ||
37ad223c | 417 | build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL); |
84344884 SZ |
418 | } |
419 | ||
ee246400 SZ |
420 | /* GTDT */ |
421 | static void | |
422 | build_gtdt(GArray *table_data, GArray *linker) | |
423 | { | |
424 | int gtdt_start = table_data->len; | |
425 | AcpiGenericTimerTable *gtdt; | |
426 | ||
427 | gtdt = acpi_data_push(table_data, sizeof *gtdt); | |
428 | /* The interrupt values are the same with the device tree when adding 16 */ | |
429 | gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; | |
430 | gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; | |
431 | ||
432 | gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; | |
a43e68a0 | 433 | gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON; |
ee246400 SZ |
434 | |
435 | gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; | |
436 | gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; | |
437 | ||
438 | gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; | |
439 | gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; | |
440 | ||
441 | build_header(linker, table_data, | |
442 | (void *)(table_data->data + gtdt_start), "GTDT", | |
37ad223c | 443 | table_data->len - gtdt_start, 2, NULL, NULL); |
ee246400 SZ |
444 | } |
445 | ||
982d06c5 SZ |
446 | /* MADT */ |
447 | static void | |
6d152eba | 448 | build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) |
982d06c5 SZ |
449 | { |
450 | int madt_start = table_data->len; | |
451 | const MemMapEntry *memmap = guest_info->memmap; | |
ca793736 | 452 | const int *irqmap = guest_info->irqmap; |
982d06c5 SZ |
453 | AcpiMultipleApicTable *madt; |
454 | AcpiMadtGenericDistributor *gicd; | |
ca793736 | 455 | AcpiMadtGenericMsiFrame *gic_msi; |
982d06c5 SZ |
456 | int i; |
457 | ||
458 | madt = acpi_data_push(table_data, sizeof *madt); | |
459 | ||
982d06c5 SZ |
460 | gicd = acpi_data_push(table_data, sizeof *gicd); |
461 | gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; | |
462 | gicd->length = sizeof(*gicd); | |
463 | gicd->base_address = memmap[VIRT_GIC_DIST].base; | |
464 | ||
f2fbface SZ |
465 | for (i = 0; i < guest_info->smp_cpus; i++) { |
466 | AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, | |
467 | sizeof *gicc); | |
5d9c1756 SZ |
468 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
469 | ||
f2fbface SZ |
470 | gicc->type = ACPI_APIC_GENERIC_INTERRUPT; |
471 | gicc->length = sizeof(*gicc); | |
472 | if (guest_info->gic_version == 2) { | |
473 | gicc->base_address = memmap[VIRT_GIC_CPU].base; | |
474 | } | |
475 | gicc->cpu_interface_number = i; | |
5d9c1756 | 476 | gicc->arm_mpidr = armcpu->mp_affinity; |
f2fbface | 477 | gicc->uid = i; |
6d152eba | 478 | gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); |
f2fbface SZ |
479 | } |
480 | ||
b92ad394 PF |
481 | if (guest_info->gic_version == 3) { |
482 | AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, | |
483 | sizeof *gicr); | |
484 | ||
485 | gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; | |
486 | gicr->length = sizeof(*gicr); | |
487 | gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); | |
488 | gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); | |
489 | } else { | |
b92ad394 PF |
490 | gic_msi = acpi_data_push(table_data, sizeof *gic_msi); |
491 | gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; | |
492 | gic_msi->length = sizeof(*gic_msi); | |
493 | gic_msi->gic_msi_frame_id = 0; | |
494 | gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); | |
495 | gic_msi->flags = cpu_to_le32(1); | |
496 | gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); | |
497 | gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); | |
498 | } | |
ca793736 | 499 | |
982d06c5 SZ |
500 | build_header(linker, table_data, |
501 | (void *)(table_data->data + madt_start), "APIC", | |
37ad223c | 502 | table_data->len - madt_start, 3, NULL, NULL); |
982d06c5 SZ |
503 | } |
504 | ||
c2f7c0c3 SZ |
505 | /* FADT */ |
506 | static void | |
507 | build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) | |
508 | { | |
509 | AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); | |
510 | ||
511 | /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ | |
512 | fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); | |
513 | fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | | |
514 | (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); | |
515 | ||
516 | /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ | |
517 | fadt->minor_revision = 0x1; | |
518 | ||
519 | fadt->dsdt = cpu_to_le32(dsdt); | |
520 | /* DSDT address to be filled by Guest linker */ | |
521 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
522 | ACPI_BUILD_TABLE_FILE, | |
523 | table_data, &fadt->dsdt, | |
524 | sizeof fadt->dsdt); | |
525 | ||
526 | build_header(linker, table_data, | |
37ad223c | 527 | (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL); |
c2f7c0c3 SZ |
528 | } |
529 | ||
dfccd8cf SZ |
530 | /* DSDT */ |
531 | static void | |
532 | build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) | |
533 | { | |
534 | Aml *scope, *dsdt; | |
535 | const MemMapEntry *memmap = guest_info->memmap; | |
536 | const int *irqmap = guest_info->irqmap; | |
537 | ||
538 | dsdt = init_aml_allocator(); | |
539 | /* Reserve space for header */ | |
540 | acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); | |
541 | ||
67736a25 SZ |
542 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
543 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
544 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
545 | * the RTC ACPI device at all when using UEFI. | |
546 | */ | |
dfccd8cf SZ |
547 | scope = aml_scope("\\_SB"); |
548 | acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); | |
549 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], | |
550 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
dfccd8cf SZ |
551 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); |
552 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], | |
553 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | |
5125f9cd PF |
554 | acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), |
555 | guest_info->use_highmem); | |
aeb1a36d SZ |
556 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], |
557 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
ac6aa59a | 558 | acpi_dsdt_add_power_button(scope); |
d4e5de1a | 559 | |
dfccd8cf SZ |
560 | aml_append(dsdt, scope); |
561 | ||
562 | /* copy AML table into ACPI tables blob and patch header there */ | |
563 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); | |
564 | build_header(linker, table_data, | |
565 | (void *)(table_data->data + table_data->len - dsdt->buf->len), | |
37ad223c | 566 | "DSDT", dsdt->buf->len, 2, NULL, NULL); |
dfccd8cf SZ |
567 | free_aml_allocator(); |
568 | } | |
569 | ||
f5d8c8cd SZ |
570 | typedef |
571 | struct AcpiBuildState { | |
572 | /* Copy of table in RAM (for patching). */ | |
573 | MemoryRegion *table_mr; | |
574 | MemoryRegion *rsdp_mr; | |
575 | MemoryRegion *linker_mr; | |
576 | /* Is table patched? */ | |
577 | bool patched; | |
578 | VirtGuestInfo *guest_info; | |
579 | } AcpiBuildState; | |
580 | ||
581 | static | |
582 | void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) | |
583 | { | |
584 | GArray *table_offsets; | |
d4bec5d8 | 585 | unsigned dsdt, rsdt; |
dfccd8cf | 586 | GArray *tables_blob = tables->table_data; |
f5d8c8cd SZ |
587 | |
588 | table_offsets = g_array_new(false, true /* clear */, | |
589 | sizeof(uint32_t)); | |
590 | ||
591 | bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, | |
592 | 64, false /* high memory */); | |
593 | ||
594 | /* | |
595 | * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: | |
596 | * RSDP | |
597 | * RSDT | |
598 | * FADT | |
599 | * GTDT | |
600 | * MADT | |
d0652b57 | 601 | * MCFG |
f5d8c8cd SZ |
602 | * DSDT |
603 | */ | |
604 | ||
dfccd8cf | 605 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 606 | dsdt = tables_blob->len; |
dfccd8cf SZ |
607 | build_dsdt(tables_blob, tables->linker, guest_info); |
608 | ||
d0652b57 | 609 | /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ |
c2f7c0c3 SZ |
610 | acpi_add_table(table_offsets, tables_blob); |
611 | build_fadt(tables_blob, tables->linker, dsdt); | |
612 | ||
982d06c5 | 613 | acpi_add_table(table_offsets, tables_blob); |
6d152eba | 614 | build_madt(tables_blob, tables->linker, guest_info); |
982d06c5 | 615 | |
ee246400 SZ |
616 | acpi_add_table(table_offsets, tables_blob); |
617 | build_gtdt(tables_blob, tables->linker); | |
618 | ||
84344884 SZ |
619 | acpi_add_table(table_offsets, tables_blob); |
620 | build_mcfg(tables_blob, tables->linker, guest_info); | |
621 | ||
f264d51d AJ |
622 | acpi_add_table(table_offsets, tables_blob); |
623 | build_spcr(tables_blob, tables->linker, guest_info); | |
624 | ||
243bdb79 | 625 | /* RSDT is pointed to by RSDP */ |
d4bec5d8 | 626 | rsdt = tables_blob->len; |
51513558 | 627 | build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); |
243bdb79 | 628 | |
d4bec5d8 SZ |
629 | /* RSDP is in FSEG memory, so allocate it separately */ |
630 | build_rsdp(tables->rsdp, tables->linker, rsdt); | |
631 | ||
f5d8c8cd SZ |
632 | /* Cleanup memory that's no longer used. */ |
633 | g_array_free(table_offsets, true); | |
634 | } | |
635 | ||
636 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
637 | { | |
638 | uint32_t size = acpi_data_len(data); | |
639 | ||
640 | /* Make sure RAM size is correct - in case it got changed | |
641 | * e.g. by migration */ | |
642 | memory_region_ram_resize(mr, size, &error_abort); | |
643 | ||
644 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
645 | memory_region_set_dirty(mr, 0, size); | |
646 | } | |
647 | ||
3f8752b4 | 648 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
649 | { |
650 | AcpiBuildState *build_state = build_opaque; | |
651 | AcpiBuildTables tables; | |
652 | ||
653 | /* No state to update or already patched? Nothing to do. */ | |
654 | if (!build_state || build_state->patched) { | |
655 | return; | |
656 | } | |
657 | build_state->patched = true; | |
658 | ||
659 | acpi_build_tables_init(&tables); | |
660 | ||
661 | virt_acpi_build(build_state->guest_info, &tables); | |
662 | ||
663 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
664 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
665 | acpi_ram_update(build_state->linker_mr, tables.linker); | |
666 | ||
667 | ||
668 | acpi_build_tables_cleanup(&tables, true); | |
669 | } | |
670 | ||
671 | static void virt_acpi_build_reset(void *build_opaque) | |
672 | { | |
673 | AcpiBuildState *build_state = build_opaque; | |
674 | build_state->patched = false; | |
675 | } | |
676 | ||
677 | static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, | |
678 | GArray *blob, const char *name, | |
679 | uint64_t max_size) | |
680 | { | |
681 | return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, | |
682 | name, virt_acpi_build_update, build_state); | |
683 | } | |
684 | ||
685 | static const VMStateDescription vmstate_virt_acpi_build = { | |
686 | .name = "virt_acpi_build", | |
687 | .version_id = 1, | |
688 | .minimum_version_id = 1, | |
689 | .fields = (VMStateField[]) { | |
690 | VMSTATE_BOOL(patched, AcpiBuildState), | |
691 | VMSTATE_END_OF_LIST() | |
692 | }, | |
693 | }; | |
694 | ||
695 | void virt_acpi_setup(VirtGuestInfo *guest_info) | |
696 | { | |
697 | AcpiBuildTables tables; | |
698 | AcpiBuildState *build_state; | |
699 | ||
700 | if (!guest_info->fw_cfg) { | |
701 | trace_virt_acpi_setup(); | |
702 | return; | |
703 | } | |
704 | ||
705 | if (!acpi_enabled) { | |
706 | trace_virt_acpi_setup(); | |
707 | return; | |
708 | } | |
709 | ||
710 | build_state = g_malloc0(sizeof *build_state); | |
711 | build_state->guest_info = guest_info; | |
712 | ||
713 | acpi_build_tables_init(&tables); | |
714 | virt_acpi_build(build_state->guest_info, &tables); | |
715 | ||
716 | /* Now expose it all to Guest */ | |
717 | build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, | |
718 | ACPI_BUILD_TABLE_FILE, | |
719 | ACPI_BUILD_TABLE_MAX_SIZE); | |
720 | assert(build_state->table_mr != NULL); | |
721 | ||
722 | build_state->linker_mr = | |
723 | acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); | |
724 | ||
725 | fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, | |
726 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); | |
727 | ||
728 | build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, | |
729 | ACPI_BUILD_RSDP_FILE, 0); | |
730 | ||
731 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
732 | virt_acpi_build_reset(build_state); | |
733 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
734 | ||
735 | /* Cleanup tables but don't free the memory: we track it | |
736 | * in build_state. | |
737 | */ | |
738 | acpi_build_tables_cleanup(&tables, false); | |
739 | } |