[qemu.git] / hw / arm11mpcore.c

/*
 * ARM11MPCore internal peripheral emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"
#include "qemu-timer.h"

/* MPCore private memory region.  */

typedef struct mpcore_priv_state {
    SysBusDevice busdev;
    uint32_t scu_control;
    int iomemtype;
    uint32_t old_timer_status[8];
    uint32_t num_cpu;
    MemoryRegion iomem;
    MemoryRegion container;
    DeviceState *mptimer;
    DeviceState *gic;
    uint32_t num_irq;
} mpcore_priv_state;

/* Per-CPU private memory mapped IO.  */

static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
                                unsigned size)
{
    mpcore_priv_state *s = (mpcore_priv_state *)opaque;
    int id;
    /* SCU */
    switch (offset) {
    case 0x00: /* Control.  */
        return s->scu_control;
    case 0x04: /* Configuration.  */
        id = ((1 << s->num_cpu) - 1) << 4;
        return id | (s->num_cpu - 1);
    case 0x08: /* CPU status.  */
        return 0;
    case 0x0c: /* Invalidate all.  */
        return 0;
    default:
        hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
    }
}

static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
                             uint64_t value, unsigned size)
{
    mpcore_priv_state *s = (mpcore_priv_state *)opaque;
    /* SCU */
    switch (offset) {
    case 0: /* Control register.  */
        s->scu_control = value & 1;
        break;
    case 0x0c: /* Invalidate all.  */
        /* This is a no-op as cache is not emulated.  */
        break;
    default:
        hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
    }
}

static const MemoryRegionOps mpcore_scu_ops = {
    .read = mpcore_scu_read,
    .write = mpcore_scu_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
    mpcore_priv_state *s = (mpcore_priv_state *)opaque;
    qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}

static void mpcore_priv_map_setup(mpcore_priv_state *s)
{
    int i;
    SysBusDevice *gicbusdev = sysbus_from_qdev(s->gic);
    SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
    memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
    memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
    memory_region_add_subregion(&s->container, 0, &s->iomem);
    /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
     * at 0x200, 0x300...
     */
    for (i = 0; i < (s->num_cpu + 1); i++) {
        target_phys_addr_t offset = 0x100 + (i * 0x100);
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(gicbusdev, i + 1));
    }
    /* Add the regions for timer and watchdog for "current CPU" and
     * for each specific CPU.
     */
    for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
        /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
        target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(busdev, i));
    }
    memory_region_add_subregion(&s->container, 0x1000,
                                sysbus_mmio_get_region(gicbusdev, 0));
    /* Wire up the interrupt from each watchdog and timer.
     * For each core the timer is PPI 29 and the watchdog PPI 30.
     */
    for (i = 0; i < s->num_cpu; i++) {
        int ppibase = (s->num_irq - 32) + i * 32;
        sysbus_connect_irq(busdev, i * 2,
                           qdev_get_gpio_in(s->gic, ppibase + 29));
        sysbus_connect_irq(busdev, i * 2 + 1,
                           qdev_get_gpio_in(s->gic, ppibase + 30));
    }
}

static int mpcore_priv_init(SysBusDevice *dev)
{
    mpcore_priv_state *s = FROM_SYSBUS(mpcore_priv_state, dev);

    s->gic = qdev_create(NULL, "arm_gic");
    qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
    qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
    /* Request the legacy 11MPCore GIC behaviour: */
    qdev_prop_set_uint32(s->gic, "revision", 0);
    qdev_init_nofail(s->gic);

    /* Pass through outbound IRQ lines from the GIC */
    sysbus_pass_irq(dev, sysbus_from_qdev(s->gic));

    /* Pass through inbound GPIO lines to the GIC */
    qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);

    s->mptimer = qdev_create(NULL, "arm_mptimer");
    qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
    qdev_init_nofail(s->mptimer);
    mpcore_priv_map_setup(s);
    sysbus_init_mmio(dev, &s->container);
    return 0;
}

/* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
   controllers.  The output of these, plus some of the raw input lines
   are fed into a single SMP-aware interrupt controller on the CPU.  */
typedef struct {
    SysBusDevice busdev;
    SysBusDevice *priv;
    qemu_irq cpuic[32];
    qemu_irq rvic[4][64];
    uint32_t num_cpu;
} mpcore_rirq_state;

/* Map baseboard IRQs onto CPU IRQ lines.  */
static const int mpcore_irq_map[32] = {
    -1, -1, -1, -1,  1,  2, -1, -1,
    -1, -1,  6, -1,  4,  5, -1, -1,
    -1, 14, 15,  0,  7,  8, -1, -1,
    -1, -1, -1, -1,  9,  3, -1, -1,
};

static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
{
    mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
    int i;

    for (i = 0; i < 4; i++) {
        qemu_set_irq(s->rvic[i][irq], level);
    }
    if (irq < 32) {
        irq = mpcore_irq_map[irq];
        if (irq >= 0) {
            qemu_set_irq(s->cpuic[irq], level);
        }
    }
}

static int realview_mpcore_init(SysBusDevice *dev)
{
    mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
    DeviceState *gic;
    DeviceState *priv;
    int n;
    int i;

    priv = qdev_create(NULL, "arm11mpcore_priv");
    qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
    qdev_init_nofail(priv);
    s->priv = sysbus_from_qdev(priv);
    sysbus_pass_irq(dev, s->priv);
    for (i = 0; i < 32; i++) {
        s->cpuic[i] = qdev_get_gpio_in(priv, i);
    }
    /* ??? IRQ routing is hardcoded to "normal" mode.  */
    for (n = 0; n < 4; n++) {
        gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
                                   s->cpuic[10 + n]);
        for (i = 0; i < 64; i++) {
            s->rvic[n][i] = qdev_get_gpio_in(gic, i);
        }
    }
    qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
    sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
    return 0;
}

static Property mpcore_rirq_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = realview_mpcore_init;
    dc->props = mpcore_rirq_properties;
}

static TypeInfo mpcore_rirq_info = {
    .name          = "realview_mpcore",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mpcore_rirq_state),
    .class_init    = mpcore_rirq_class_init,
};

static Property mpcore_priv_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
    /* The ARM11 MPCORE TRM says the on-chip controller may have
     * anything from 0 to 224 external interrupt IRQ lines (with another
     * 32 internal). We default to 32+32, which is the number provided by
     * the ARM11 MPCore test chip in the Realview Versatile Express
     * coretile. Other boards may differ and should set this property
     * appropriately. Some Linux kernels may not boot if the hardware
     * has more IRQ lines than the kernel expects.
     */
    DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_priv_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mpcore_priv_init;
    dc->props = mpcore_priv_properties;
}

static TypeInfo mpcore_priv_info = {
    .name          = "arm11mpcore_priv",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mpcore_priv_state),
    .class_init    = mpcore_priv_class_init,
};

static void arm11mpcore_register_types(void)
{
    type_register_static(&mpcore_rirq_info);
    type_register_static(&mpcore_priv_info);
}

type_init(arm11mpcore_register_types)
Commit	Line	Data
f7c70325 PB	1	/*
	2	* ARM11MPCore internal peripheral emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
f7c70325 PB	8	*/
f7c70325 PB	9
2a6ab1e3 PM	10	#include "sysbus.h"
	11	#include "qemu-timer.h"
	12
2a6ab1e3 PM	13	/* MPCore private memory region. */
	14
	15	typedef struct mpcore_priv_state {
2e9dfe20	16	SysBusDevice busdev;
2a6ab1e3 PM	17	uint32_t scu_control;
	18	int iomemtype;
	19	uint32_t old_timer_status[8];
	20	uint32_t num_cpu;
2a6ab1e3 PM	21	MemoryRegion iomem;
	22	MemoryRegion container;
	23	DeviceState *mptimer;
2e9dfe20	24	DeviceState *gic;
a32134aa	25	uint32_t num_irq;
2a6ab1e3 PM	26	} mpcore_priv_state;
	27
	28	/* Per-CPU private memory mapped IO. */
	29
	30	static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
	31	unsigned size)
	32	{
	33	mpcore_priv_state s = (mpcore_priv_state )opaque;
	34	int id;
2a6ab1e3 PM	35	/* SCU */
	36	switch (offset) {
	37	case 0x00: /* Control. */
	38	return s->scu_control;
	39	case 0x04: /* Configuration. */
	40	id = ((1 << s->num_cpu) - 1) << 4;
	41	return id \| (s->num_cpu - 1);
	42	case 0x08: /* CPU status. */
	43	return 0;
	44	case 0x0c: /* Invalidate all. */
	45	return 0;
	46	default:
	47	hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
	48	}
	49	}
	50
	51	static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
	52	uint64_t value, unsigned size)
	53	{
	54	mpcore_priv_state s = (mpcore_priv_state )opaque;
2a6ab1e3 PM	55	/* SCU */
	56	switch (offset) {
	57	case 0: /* Control register. */
	58	s->scu_control = value & 1;
	59	break;
	60	case 0x0c: /* Invalidate all. */
	61	/* This is a no-op as cache is not emulated. */
	62	break;
	63	default:
	64	hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
	65	}
	66	}
	67
	68	static const MemoryRegionOps mpcore_scu_ops = {
	69	.read = mpcore_scu_read,
	70	.write = mpcore_scu_write,
	71	.endianness = DEVICE_NATIVE_ENDIAN,
	72	};
	73
2e9dfe20	74	static void mpcore_priv_set_irq(void *opaque, int irq, int level)
2a6ab1e3 PM	75	{
2a6ab1e3 PM	76	mpcore_priv_state s = (mpcore_priv_state )opaque;
2e9dfe20	77	qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
2a6ab1e3 PM	78	}
	79
	80	static void mpcore_priv_map_setup(mpcore_priv_state *s)
	81	{
	82	int i;
2e9dfe20	83	SysBusDevice *gicbusdev = sysbus_from_qdev(s->gic);
2a6ab1e3 PM	84	SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
	85	memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
	86	memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
	87	memory_region_add_subregion(&s->container, 0, &s->iomem);
	88	/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
	89	* at 0x200, 0x300...
	90	*/
	91	for (i = 0; i < (s->num_cpu + 1); i++) {
	92	target_phys_addr_t offset = 0x100 + (i * 0x100);
2e9dfe20 PM	93	memory_region_add_subregion(&s->container, offset,
2e9dfe20 PM	94	sysbus_mmio_get_region(gicbusdev, i + 1));
2a6ab1e3 PM	95	}
	96	/* Add the regions for timer and watchdog for "current CPU" and
	97	* for each specific CPU.
	98	*/
2a6ab1e3 PM	99	for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
	100	/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
	101	target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
	102	memory_region_add_subregion(&s->container, offset,
	103	sysbus_mmio_get_region(busdev, i));
	104	}
2e9dfe20 PM	105	memory_region_add_subregion(&s->container, 0x1000,
	106	sysbus_mmio_get_region(gicbusdev, 0));
	107	/* Wire up the interrupt from each watchdog and timer.
	108	* For each core the timer is PPI 29 and the watchdog PPI 30.
	109	*/
	110	for (i = 0; i < s->num_cpu; i++) {
	111	int ppibase = (s->num_irq - 32) + i * 32;
	112	sysbus_connect_irq(busdev, i * 2,
	113	qdev_get_gpio_in(s->gic, ppibase + 29));
	114	sysbus_connect_irq(busdev, i * 2 + 1,
	115	qdev_get_gpio_in(s->gic, ppibase + 30));
2a6ab1e3 PM	116	}
	117	}
	118
	119	static int mpcore_priv_init(SysBusDevice *dev)
	120	{
2e9dfe20 PM	121	mpcore_priv_state *s = FROM_SYSBUS(mpcore_priv_state, dev);
	122
	123	s->gic = qdev_create(NULL, "arm_gic");
	124	qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
	125	qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
306a571a PM	126	/* Request the legacy 11MPCore GIC behaviour: */
306a571a PM	127	qdev_prop_set_uint32(s->gic, "revision", 0);
2e9dfe20 PM	128	qdev_init_nofail(s->gic);
	129
	130	/* Pass through outbound IRQ lines from the GIC */
	131	sysbus_pass_irq(dev, sysbus_from_qdev(s->gic));
	132
	133	/* Pass through inbound GPIO lines to the GIC */
	134	qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);
2a6ab1e3	135
2a6ab1e3 PM	136	s->mptimer = qdev_create(NULL, "arm_mptimer");
	137	qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
	138	qdev_init_nofail(s->mptimer);
	139	mpcore_priv_map_setup(s);
	140	sysbus_init_mmio(dev, &s->container);
	141	return 0;
	142	}
f7c70325 PB	143
	144	/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
	145	controllers. The output of these, plus some of the raw input lines
	146	are fed into a single SMP-aware interrupt controller on the CPU. */
	147	typedef struct {
	148	SysBusDevice busdev;
	149	SysBusDevice *priv;
	150	qemu_irq cpuic[32];
	151	qemu_irq rvic[4][64];
	152	uint32_t num_cpu;
	153	} mpcore_rirq_state;
	154
	155	/* Map baseboard IRQs onto CPU IRQ lines. */
	156	static const int mpcore_irq_map[32] = {
	157	-1, -1, -1, -1, 1, 2, -1, -1,
	158	-1, -1, 6, -1, 4, 5, -1, -1,
	159	-1, 14, 15, 0, 7, 8, -1, -1,
	160	-1, -1, -1, -1, 9, 3, -1, -1,
	161	};
	162
	163	static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
	164	{
	165	mpcore_rirq_state s = (mpcore_rirq_state )opaque;
	166	int i;
	167
	168	for (i = 0; i < 4; i++) {
	169	qemu_set_irq(s->rvic[i][irq], level);
	170	}
	171	if (irq < 32) {
	172	irq = mpcore_irq_map[irq];
	173	if (irq >= 0) {
	174	qemu_set_irq(s->cpuic[irq], level);
	175	}
	176	}
	177	}
	178
f7c70325 PB	179	static int realview_mpcore_init(SysBusDevice *dev)
	180	{
	181	mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
	182	DeviceState *gic;
	183	DeviceState *priv;
	184	int n;
	185	int i;
	186
	187	priv = qdev_create(NULL, "arm11mpcore_priv");
	188	qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
	189	qdev_init_nofail(priv);
	190	s->priv = sysbus_from_qdev(priv);
	191	sysbus_pass_irq(dev, s->priv);
	192	for (i = 0; i < 32; i++) {
	193	s->cpuic[i] = qdev_get_gpio_in(priv, i);
	194	}
	195	/* ??? IRQ routing is hardcoded to "normal" mode. */
	196	for (n = 0; n < 4; n++) {
	197	gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
	198	s->cpuic[10 + n]);
	199	for (i = 0; i < 64; i++) {
	200	s->rvic[n][i] = qdev_get_gpio_in(gic, i);
	201	}
	202	}
	203	qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
750ecd44	204	sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
f7c70325 PB	205	return 0;
	206	}
	207
999e12bb	208	static Property mpcore_rirq_properties[] = {
0f58a188	209	DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
999e12bb	210	DEFINE_PROP_END_OF_LIST(),
f7c70325 PB	211	};
f7c70325 PB	212
999e12bb AL	213	static void mpcore_rirq_class_init(ObjectClass klass, void data)
999e12bb AL	214	{
39bffca2	215	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	216	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	217
	218	k->init = realview_mpcore_init;
39bffca2	219	dc->props = mpcore_rirq_properties;
999e12bb AL	220	}
999e12bb AL	221
39bffca2 AL	222	static TypeInfo mpcore_rirq_info = {
	223	.name = "realview_mpcore",
	224	.parent = TYPE_SYS_BUS_DEVICE,
	225	.instance_size = sizeof(mpcore_rirq_state),
	226	.class_init = mpcore_rirq_class_init,
999e12bb AL	227	};
	228
	229	static Property mpcore_priv_properties[] = {
	230	DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
0f58a188 PM	231	/* The ARM11 MPCORE TRM says the on-chip controller may have
	232	* anything from 0 to 224 external interrupt IRQ lines (with another
	233	* 32 internal). We default to 32+32, which is the number provided by
	234	* the ARM11 MPCore test chip in the Realview Versatile Express
	235	* coretile. Other boards may differ and should set this property
	236	* appropriately. Some Linux kernels may not boot if the hardware
	237	* has more IRQ lines than the kernel expects.
	238	*/
	239	DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
999e12bb AL	240	DEFINE_PROP_END_OF_LIST(),
	241	};
	242
	243	static void mpcore_priv_class_init(ObjectClass klass, void data)
	244	{
39bffca2	245	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	246	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	247
	248	k->init = mpcore_priv_init;
39bffca2	249	dc->props = mpcore_priv_properties;
999e12bb AL	250	}
999e12bb AL	251
39bffca2 AL	252	static TypeInfo mpcore_priv_info = {
	253	.name = "arm11mpcore_priv",
	254	.parent = TYPE_SYS_BUS_DEVICE,
	255	.instance_size = sizeof(mpcore_priv_state),
	256	.class_init = mpcore_priv_class_init,
f7c70325 PB	257	};
f7c70325 PB	258
83f7d43a	259	static void arm11mpcore_register_types(void)
f7c70325	260	{
39bffca2 AL	261	type_register_static(&mpcore_rirq_info);
39bffca2 AL	262	type_register_static(&mpcore_priv_info);
f7c70325 PB	263	}
f7c70325 PB	264
83f7d43a	265	type_init(arm11mpcore_register_types)