[qemu.git] / hw / arm_boot.c

/*
 * ARM kernel loader.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "config.h"
#include "hw.h"
#include "arm-misc.h"
#include "sysemu.h"
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "device_tree.h"

#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x00010000
#define INITRD_LOAD_ADDR 0x00d00000

/* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */
static uint32_t bootloader[] = {
  0xe3a00000, /* mov     r0, #0 */
  0xe59f1004, /* ldr     r1, [pc, #4] */
  0xe59f2004, /* ldr     r2, [pc, #4] */
  0xe59ff004, /* ldr     pc, [pc, #4] */
  0, /* Board ID */
  0, /* Address of kernel args.  Set by integratorcp_init.  */
  0  /* Kernel entry point.  Set by integratorcp_init.  */
};

/* Handling for secondary CPU boot in a multicore system.
 * Unlike the uniprocessor/primary CPU boot, this is platform
 * dependent. The default code here is based on the secondary
 * CPU boot protocol used on realview/vexpress boards, with
 * some parameterisation to increase its flexibility.
 * QEMU platform models for which this code is not appropriate
 * should override write_secondary_boot and secondary_cpu_reset_hook
 * instead.
 *
 * This code enables the interrupt controllers for the secondary
 * CPUs and then puts all the secondary CPUs into a loop waiting
 * for an interprocessor interrupt and polling a configurable
 * location for the kernel secondary CPU entry point.
 */
static uint32_t smpboot[] = {
  0xe59f201c, /* ldr r2, gic_cpu_if */
  0xe59f001c, /* ldr r0, startaddr */
  0xe3a01001, /* mov r1, #1 */
  0xe5821000, /* str r1, [r2] */
  0xe320f003, /* wfi */
  0xe5901000, /* ldr     r1, [r0] */
  0xe1110001, /* tst     r1, r1 */
  0x0afffffb, /* beq     <wfi> */
  0xe12fff11, /* bx      r1 */
  0,          /* gic_cpu_if: base address of GIC CPU interface */
  0           /* bootreg: Boot register address is held here */
};

static void default_write_secondary(CPUARMState *env,
                                    const struct arm_boot_info *info)
{
    int n;
    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
                       info->smp_loader_start);
}

static void default_reset_secondary(CPUARMState *env,
                                    const struct arm_boot_info *info)
{
    stl_phys_notdirty(info->smp_bootreg_addr, 0);
    env->regs[15] = info->smp_loader_start;
}

#define WRITE_WORD(p, value) do { \
    stl_phys_notdirty(p, value);  \
    p += 4;                       \
} while (0)

static void set_kernel_args(const struct arm_boot_info *info)
{
    int initrd_size = info->initrd_size;
    target_phys_addr_t base = info->loader_start;
    target_phys_addr_t p;

    p = base + KERNEL_ARGS_ADDR;
    /* ATAG_CORE */
    WRITE_WORD(p, 5);
    WRITE_WORD(p, 0x54410001);
    WRITE_WORD(p, 1);
    WRITE_WORD(p, 0x1000);
    WRITE_WORD(p, 0);
    /* ATAG_MEM */
    /* TODO: handle multiple chips on one ATAG list */
    WRITE_WORD(p, 4);
    WRITE_WORD(p, 0x54410002);
    WRITE_WORD(p, info->ram_size);
    WRITE_WORD(p, info->loader_start);
    if (initrd_size) {
        /* ATAG_INITRD2 */
        WRITE_WORD(p, 4);
        WRITE_WORD(p, 0x54420005);
        WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
        WRITE_WORD(p, initrd_size);
    }
    if (info->kernel_cmdline && *info->kernel_cmdline) {
        /* ATAG_CMDLINE */
        int cmdline_size;

        cmdline_size = strlen(info->kernel_cmdline);
        cpu_physical_memory_write(p + 8, (void *)info->kernel_cmdline,
                                  cmdline_size + 1);
        cmdline_size = (cmdline_size >> 2) + 1;
        WRITE_WORD(p, cmdline_size + 2);
        WRITE_WORD(p, 0x54410009);
        p += cmdline_size * 4;
    }
    if (info->atag_board) {
        /* ATAG_BOARD */
        int atag_board_len;
        uint8_t atag_board_buf[0x1000];

        atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
        WRITE_WORD(p, (atag_board_len + 8) >> 2);
        WRITE_WORD(p, 0x414f4d50);
        cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
        p += atag_board_len;
    }
    /* ATAG_END */
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
}

static void set_kernel_args_old(const struct arm_boot_info *info)
{
    target_phys_addr_t p;
    const char *s;
    int initrd_size = info->initrd_size;
    target_phys_addr_t base = info->loader_start;

    /* see linux/include/asm-arm/setup.h */
    p = base + KERNEL_ARGS_ADDR;
    /* page_size */
    WRITE_WORD(p, 4096);
    /* nr_pages */
    WRITE_WORD(p, info->ram_size / 4096);
    /* ramdisk_size */
    WRITE_WORD(p, 0);
#define FLAG_READONLY	1
#define FLAG_RDLOAD	4
#define FLAG_RDPROMPT	8
    /* flags */
    WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
    /* rootdev */
    WRITE_WORD(p, (31 << 8) | 0);	/* /dev/mtdblock0 */
    /* video_num_cols */
    WRITE_WORD(p, 0);
    /* video_num_rows */
    WRITE_WORD(p, 0);
    /* video_x */
    WRITE_WORD(p, 0);
    /* video_y */
    WRITE_WORD(p, 0);
    /* memc_control_reg */
    WRITE_WORD(p, 0);
    /* unsigned char sounddefault */
    /* unsigned char adfsdrives */
    /* unsigned char bytes_per_char_h */
    /* unsigned char bytes_per_char_v */
    WRITE_WORD(p, 0);
    /* pages_in_bank[4] */
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    /* pages_in_vram */
    WRITE_WORD(p, 0);
    /* initrd_start */
    if (initrd_size)
        WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
    else
        WRITE_WORD(p, 0);
    /* initrd_size */
    WRITE_WORD(p, initrd_size);
    /* rd_start */
    WRITE_WORD(p, 0);
    /* system_rev */
    WRITE_WORD(p, 0);
    /* system_serial_low */
    WRITE_WORD(p, 0);
    /* system_serial_high */
    WRITE_WORD(p, 0);
    /* mem_fclk_21285 */
    WRITE_WORD(p, 0);
    /* zero unused fields */
    while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
        WRITE_WORD(p, 0);
    }
    s = info->kernel_cmdline;
    if (s) {
        cpu_physical_memory_write(p, (void *)s, strlen(s) + 1);
    } else {
        WRITE_WORD(p, 0);
    }
}

static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
{
#ifdef CONFIG_FDT
    uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start),
                                    cpu_to_be32(binfo->ram_size) };
    void *fdt = NULL;
    char *filename;
    int size, rc;

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
    if (!filename) {
        fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
        return -1;
    }

    fdt = load_device_tree(filename, &size);
    if (!fdt) {
        fprintf(stderr, "Couldn't open dtb file %s\n", filename);
        g_free(filename);
        return -1;
    }
    g_free(filename);

    rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
                               sizeof(mem_reg_property));
    if (rc < 0) {
        fprintf(stderr, "couldn't set /memory/reg\n");
    }

    rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
                                      binfo->kernel_cmdline);
    if (rc < 0) {
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    }

    if (binfo->initrd_size) {
        rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
                binfo->loader_start + INITRD_LOAD_ADDR);
        if (rc < 0) {
            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
        }

        rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                    binfo->loader_start + INITRD_LOAD_ADDR +
                    binfo->initrd_size);
        if (rc < 0) {
            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
        }
    }

    cpu_physical_memory_write(addr, fdt, size);

    return 0;

#else
    fprintf(stderr, "Device tree requested, "
                "but qemu was compiled without fdt support\n");
    return -1;
#endif
}

static void do_cpu_reset(void *opaque)
{
    CPUARMState *env = opaque;
    const struct arm_boot_info *info = env->boot_info;

    cpu_state_reset(env);
    if (info) {
        if (!info->is_linux) {
            /* Jump to the entry point.  */
            env->regs[15] = info->entry & 0xfffffffe;
            env->thumb = info->entry & 1;
        } else {
            if (env == first_cpu) {
                env->regs[15] = info->loader_start;
                if (!info->dtb_filename) {
                    if (old_param) {
                        set_kernel_args_old(info);
                    } else {
                        set_kernel_args(info);
                    }
                }
            } else {
                info->secondary_cpu_reset_hook(env, info);
            }
        }
    }
}

void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
    int kernel_size;
    int initrd_size;
    int n;
    int is_linux = 0;
    uint64_t elf_entry;
    target_phys_addr_t entry;
    int big_endian;
    QemuOpts *machine_opts;

    /* Load the kernel.  */
    if (!info->kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
    if (machine_opts) {
        info->dtb_filename = qemu_opt_get(machine_opts, "dtb");
    } else {
        info->dtb_filename = NULL;
    }

    if (!info->secondary_cpu_reset_hook) {
        info->secondary_cpu_reset_hook = default_reset_secondary;
    }
    if (!info->write_secondary_boot) {
        info->write_secondary_boot = default_write_secondary;
    }

    if (info->nb_cpus == 0)
        info->nb_cpus = 1;

#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

    /* Assume that raw images are linux kernels, and ELF images are not.  */
    kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
                           NULL, NULL, big_endian, ELF_MACHINE, 1);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
                                  &is_linux);
    }
    if (kernel_size < 0) {
        entry = info->loader_start + KERNEL_LOAD_ADDR;
        kernel_size = load_image_targphys(info->kernel_filename, entry,
                                          ram_size - KERNEL_LOAD_ADDR);
        is_linux = 1;
    }
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                info->kernel_filename);
        exit(1);
    }
    info->entry = entry;
    if (is_linux) {
        if (info->initrd_filename) {
            initrd_size = load_image_targphys(info->initrd_filename,
                                              info->loader_start
                                              + INITRD_LOAD_ADDR,
                                              ram_size - INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initrd '%s'\n",
                        info->initrd_filename);
                exit(1);
            }
        } else {
            initrd_size = 0;
        }
        info->initrd_size = initrd_size;

        bootloader[4] = info->board_id;

        /* for device tree boot, we pass the DTB directly in r2. Otherwise
         * we point to the kernel args.
         */
        if (info->dtb_filename) {
            /* Place the DTB after the initrd in memory */
            target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
                                                             + INITRD_LOAD_ADDR
                                                             + initrd_size);
            if (load_dtb(dtb_start, info)) {
                exit(1);
            }
            bootloader[5] = dtb_start;
        } else {
            bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
        }
        bootloader[6] = entry;
        for (n = 0; n < sizeof(bootloader) / 4; n++) {
            bootloader[n] = tswap32(bootloader[n]);
        }
        rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
                           info->loader_start);
        if (info->nb_cpus > 1) {
            info->write_secondary_boot(env, info);
        }
    }
    info->is_linux = is_linux;

    for (; env; env = env->next_cpu) {
        env->boot_info = info;
        qemu_register_reset(do_cpu_reset, env);
    }
}
Commit	Line	Data
5fafdf24	1	/*
16406950 PB	2	* ARM kernel loader.
16406950 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
16406950 PB	5	* Written by Paul Brook
16406950 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
16406950 PB	8	*/
16406950 PB	9
412beee6	10	#include "config.h"
87ecb68b PB	11	#include "hw.h"
	12	#include "arm-misc.h"
	13	#include "sysemu.h"
412beee6	14	#include "boards.h"
ca20cf32 BS	15	#include "loader.h"
ca20cf32 BS	16	#include "elf.h"
412beee6	17	#include "device_tree.h"
16406950 PB	18
	19	#define KERNEL_ARGS_ADDR 0x100
	20	#define KERNEL_LOAD_ADDR 0x00010000
756ba3b0	21	#define INITRD_LOAD_ADDR 0x00d00000
16406950 PB	22
	23	/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
	24	static uint32_t bootloader[] = {
	25	0xe3a00000, /* mov r0, #0 */
f8414cb5 PM	26	0xe59f1004, /* ldr r1, [pc, #4] */
	27	0xe59f2004, /* ldr r2, [pc, #4] */
	28	0xe59ff004, /* ldr pc, [pc, #4] */
	29	0, /* Board ID */
16406950 PB	30	0, /* Address of kernel args. Set by integratorcp_init. */
	31	0 /* Kernel entry point. Set by integratorcp_init. */
	32	};
	33
9d5ba9bf ML	34	/* Handling for secondary CPU boot in a multicore system.
	35	* Unlike the uniprocessor/primary CPU boot, this is platform
	36	* dependent. The default code here is based on the secondary
	37	* CPU boot protocol used on realview/vexpress boards, with
	38	* some parameterisation to increase its flexibility.
	39	* QEMU platform models for which this code is not appropriate
	40	* should override write_secondary_boot and secondary_cpu_reset_hook
	41	* instead.
	42	*
	43	* This code enables the interrupt controllers for the secondary
	44	* CPUs and then puts all the secondary CPUs into a loop waiting
	45	* for an interprocessor interrupt and polling a configurable
	46	* location for the kernel secondary CPU entry point.
	47	*/
9ee6e8bb	48	static uint32_t smpboot[] = {
96eacf64	49	0xe59f201c, /* ldr r2, gic_cpu_if */
078758d0 EV	50	0xe59f001c, /* ldr r0, startaddr */
078758d0 EV	51	0xe3a01001, /* mov r1, #1 */
96eacf64	52	0xe5821000, /* str r1, [r2] */
9ee6e8bb PB	53	0xe320f003, /* wfi */
9ee6e8bb PB	54	0xe5901000, /* ldr r1, [r0] */
be0f204a PB	55	0xe1110001, /* tst r1, r1 */
be0f204a PB	56	0x0afffffb, /* beq <wfi> */
f7c70325	57	0xe12fff11, /* bx r1 */
96eacf64	58	0, /* gic_cpu_if: base address of GIC CPU interface */
078758d0	59	0 /* bootreg: Boot register address is held here */
9ee6e8bb PB	60	};
9ee6e8bb PB	61
5ae93306	62	static void default_write_secondary(CPUARMState *env,
9d5ba9bf ML	63	const struct arm_boot_info *info)
	64	{
	65	int n;
	66	smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
96eacf64	67	smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
9d5ba9bf ML	68	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	69	smpboot[n] = tswap32(smpboot[n]);
	70	}
	71	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
	72	info->smp_loader_start);
	73	}
	74
5ae93306	75	static void default_reset_secondary(CPUARMState *env,
9d5ba9bf ML	76	const struct arm_boot_info *info)
	77	{
	78	stl_phys_notdirty(info->smp_bootreg_addr, 0);
	79	env->regs[15] = info->smp_loader_start;
	80	}
	81
52b43737 PB	82	#define WRITE_WORD(p, value) do { \
	83	stl_phys_notdirty(p, value); \
	84	p += 4; \
	85	} while (0)
	86
761c9eb0	87	static void set_kernel_args(const struct arm_boot_info *info)
16406950	88	{
761c9eb0 SW	89	int initrd_size = info->initrd_size;
761c9eb0 SW	90	target_phys_addr_t base = info->loader_start;
c227f099	91	target_phys_addr_t p;
16406950	92
52b43737	93	p = base + KERNEL_ARGS_ADDR;
16406950	94	/* ATAG_CORE */
52b43737 PB	95	WRITE_WORD(p, 5);
	96	WRITE_WORD(p, 0x54410001);
	97	WRITE_WORD(p, 1);
	98	WRITE_WORD(p, 0x1000);
	99	WRITE_WORD(p, 0);
16406950	100	/* ATAG_MEM */
f93eb9ff	101	/* TODO: handle multiple chips on one ATAG list */
52b43737 PB	102	WRITE_WORD(p, 4);
	103	WRITE_WORD(p, 0x54410002);
	104	WRITE_WORD(p, info->ram_size);
	105	WRITE_WORD(p, info->loader_start);
16406950 PB	106	if (initrd_size) {
16406950 PB	107	/* ATAG_INITRD2 */
52b43737 PB	108	WRITE_WORD(p, 4);
	109	WRITE_WORD(p, 0x54420005);
	110	WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
	111	WRITE_WORD(p, initrd_size);
16406950	112	}
f93eb9ff	113	if (info->kernel_cmdline && *info->kernel_cmdline) {
16406950 PB	114	/* ATAG_CMDLINE */
	115	int cmdline_size;
	116
f93eb9ff	117	cmdline_size = strlen(info->kernel_cmdline);
52b43737 PB	118	cpu_physical_memory_write(p + 8, (void *)info->kernel_cmdline,
52b43737 PB	119	cmdline_size + 1);
16406950	120	cmdline_size = (cmdline_size >> 2) + 1;
52b43737 PB	121	WRITE_WORD(p, cmdline_size + 2);
	122	WRITE_WORD(p, 0x54410009);
	123	p += cmdline_size * 4;
16406950	124	}
f93eb9ff AZ	125	if (info->atag_board) {
	126	/* ATAG_BOARD */
	127	int atag_board_len;
52b43737	128	uint8_t atag_board_buf[0x1000];
f93eb9ff	129
52b43737 PB	130	atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
	131	WRITE_WORD(p, (atag_board_len + 8) >> 2);
	132	WRITE_WORD(p, 0x414f4d50);
	133	cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
f93eb9ff AZ	134	p += atag_board_len;
f93eb9ff AZ	135	}
16406950	136	/* ATAG_END */
52b43737 PB	137	WRITE_WORD(p, 0);
52b43737 PB	138	WRITE_WORD(p, 0);
16406950 PB	139	}
16406950 PB	140
761c9eb0	141	static void set_kernel_args_old(const struct arm_boot_info *info)
2b8f2d41	142	{
c227f099	143	target_phys_addr_t p;
52b43737	144	const char *s;
761c9eb0 SW	145	int initrd_size = info->initrd_size;
761c9eb0 SW	146	target_phys_addr_t base = info->loader_start;
2b8f2d41 AZ	147
2b8f2d41 AZ	148	/* see linux/include/asm-arm/setup.h */
52b43737	149	p = base + KERNEL_ARGS_ADDR;
2b8f2d41	150	/* page_size */
52b43737	151	WRITE_WORD(p, 4096);
2b8f2d41	152	/* nr_pages */
52b43737	153	WRITE_WORD(p, info->ram_size / 4096);
2b8f2d41	154	/* ramdisk_size */
52b43737	155	WRITE_WORD(p, 0);
2b8f2d41 AZ	156	#define FLAG_READONLY 1
	157	#define FLAG_RDLOAD 4
	158	#define FLAG_RDPROMPT 8
	159	/* flags */
52b43737	160	WRITE_WORD(p, FLAG_READONLY \| FLAG_RDLOAD \| FLAG_RDPROMPT);
2b8f2d41	161	/* rootdev */
52b43737	162	WRITE_WORD(p, (31 << 8) \| 0); /* /dev/mtdblock0 */
2b8f2d41	163	/* video_num_cols */
52b43737	164	WRITE_WORD(p, 0);
2b8f2d41	165	/* video_num_rows */
52b43737	166	WRITE_WORD(p, 0);
2b8f2d41	167	/* video_x */
52b43737	168	WRITE_WORD(p, 0);
2b8f2d41	169	/* video_y */
52b43737	170	WRITE_WORD(p, 0);
2b8f2d41	171	/* memc_control_reg */
52b43737	172	WRITE_WORD(p, 0);
2b8f2d41 AZ	173	/* unsigned char sounddefault */
	174	/* unsigned char adfsdrives */
	175	/* unsigned char bytes_per_char_h */
	176	/* unsigned char bytes_per_char_v */
52b43737	177	WRITE_WORD(p, 0);
2b8f2d41	178	/* pages_in_bank[4] */
52b43737 PB	179	WRITE_WORD(p, 0);
	180	WRITE_WORD(p, 0);
	181	WRITE_WORD(p, 0);
	182	WRITE_WORD(p, 0);
2b8f2d41	183	/* pages_in_vram */
52b43737	184	WRITE_WORD(p, 0);
2b8f2d41 AZ	185	/* initrd_start */
2b8f2d41 AZ	186	if (initrd_size)
52b43737	187	WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
2b8f2d41	188	else
52b43737	189	WRITE_WORD(p, 0);
2b8f2d41	190	/* initrd_size */
52b43737	191	WRITE_WORD(p, initrd_size);
2b8f2d41	192	/* rd_start */
52b43737	193	WRITE_WORD(p, 0);
2b8f2d41	194	/* system_rev */
52b43737	195	WRITE_WORD(p, 0);
2b8f2d41	196	/* system_serial_low */
52b43737	197	WRITE_WORD(p, 0);
2b8f2d41	198	/* system_serial_high */
52b43737	199	WRITE_WORD(p, 0);
2b8f2d41	200	/* mem_fclk_21285 */
52b43737	201	WRITE_WORD(p, 0);
2b8f2d41	202	/* zero unused fields */
52b43737 PB	203	while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
	204	WRITE_WORD(p, 0);
	205	}
	206	s = info->kernel_cmdline;
	207	if (s) {
	208	cpu_physical_memory_write(p, (void *)s, strlen(s) + 1);
	209	} else {
	210	WRITE_WORD(p, 0);
	211	}
2b8f2d41 AZ	212	}
2b8f2d41 AZ	213
412beee6 GL	214	static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
	215	{
	216	#ifdef CONFIG_FDT
	217	uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start),
	218	cpu_to_be32(binfo->ram_size) };
	219	void *fdt = NULL;
	220	char *filename;
	221	int size, rc;
	222
	223	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
	224	if (!filename) {
	225	fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
	226	return -1;
	227	}
	228
	229	fdt = load_device_tree(filename, &size);
	230	if (!fdt) {
	231	fprintf(stderr, "Couldn't open dtb file %s\n", filename);
	232	g_free(filename);
	233	return -1;
	234	}
	235	g_free(filename);
	236
	237	rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
	238	sizeof(mem_reg_property));
	239	if (rc < 0) {
	240	fprintf(stderr, "couldn't set /memory/reg\n");
	241	}
	242
	243	rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
	244	binfo->kernel_cmdline);
	245	if (rc < 0) {
	246	fprintf(stderr, "couldn't set /chosen/bootargs\n");
	247	}
	248
	249	if (binfo->initrd_size) {
	250	rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
	251	binfo->loader_start + INITRD_LOAD_ADDR);
	252	if (rc < 0) {
	253	fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
	254	}
	255
	256	rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	257	binfo->loader_start + INITRD_LOAD_ADDR +
	258	binfo->initrd_size);
	259	if (rc < 0) {
	260	fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
	261	}
	262	}
	263
	264	cpu_physical_memory_write(addr, fdt, size);
	265
	266	return 0;
	267
	268	#else
	269	fprintf(stderr, "Device tree requested, "
	270	"but qemu was compiled without fdt support\n");
	271	return -1;
	272	#endif
	273	}
	274
6ed221b6	275	static void do_cpu_reset(void *opaque)
f2d74978	276	{
5ae93306	277	CPUARMState *env = opaque;
462a8bc6	278	const struct arm_boot_info *info = env->boot_info;
f2d74978	279
1bba0dc9	280	cpu_state_reset(env);
f2d74978 PB	281	if (info) {
	282	if (!info->is_linux) {
	283	/* Jump to the entry point. */
	284	env->regs[15] = info->entry & 0xfffffffe;
	285	env->thumb = info->entry & 1;
	286	} else {
6ed221b6 AL	287	if (env == first_cpu) {
6ed221b6 AL	288	env->regs[15] = info->loader_start;
412beee6 GL	289	if (!info->dtb_filename) {
	290	if (old_param) {
	291	set_kernel_args_old(info);
	292	} else {
	293	set_kernel_args(info);
	294	}
6ed221b6	295	}
f2d74978	296	} else {
9d5ba9bf	297	info->secondary_cpu_reset_hook(env, info);
f2d74978 PB	298	}
	299	}
	300	}
f2d74978 PB	301	}
f2d74978 PB	302
5ae93306	303	void arm_load_kernel(CPUARMState env, struct arm_boot_info info)
16406950 PB	304	{
	305	int kernel_size;
	306	int initrd_size;
	307	int n;
1c7b3754 PB	308	int is_linux = 0;
1c7b3754 PB	309	uint64_t elf_entry;
c227f099	310	target_phys_addr_t entry;
ca20cf32	311	int big_endian;
412beee6	312	QemuOpts *machine_opts;
16406950 PB	313
16406950 PB	314	/* Load the kernel. */
f93eb9ff	315	if (!info->kernel_filename) {
16406950 PB	316	fprintf(stderr, "Kernel image must be specified\n");
	317	exit(1);
	318	}
daf90626	319
412beee6 GL	320	machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
	321	if (machine_opts) {
	322	info->dtb_filename = qemu_opt_get(machine_opts, "dtb");
	323	} else {
	324	info->dtb_filename = NULL;
	325	}
	326
9d5ba9bf ML	327	if (!info->secondary_cpu_reset_hook) {
	328	info->secondary_cpu_reset_hook = default_reset_secondary;
	329	}
	330	if (!info->write_secondary_boot) {
	331	info->write_secondary_boot = default_write_secondary;
	332	}
	333
f2d74978 PB	334	if (info->nb_cpus == 0)
f2d74978 PB	335	info->nb_cpus = 1;
f93eb9ff	336
ca20cf32 BS	337	#ifdef TARGET_WORDS_BIGENDIAN
	338	big_endian = 1;
	339	#else
	340	big_endian = 0;
	341	#endif
	342
1c7b3754	343	/* Assume that raw images are linux kernels, and ELF images are not. */
409dbce5 AJ	344	kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
409dbce5 AJ	345	NULL, NULL, big_endian, ELF_MACHINE, 1);
1c7b3754 PB	346	entry = elf_entry;
1c7b3754 PB	347	if (kernel_size < 0) {
5a9154e0 AL	348	kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
5a9154e0 AL	349	&is_linux);
1c7b3754 PB	350	}
1c7b3754 PB	351	if (kernel_size < 0) {
f93eb9ff	352	entry = info->loader_start + KERNEL_LOAD_ADDR;
3b760e04 PB	353	kernel_size = load_image_targphys(info->kernel_filename, entry,
3b760e04 PB	354	ram_size - KERNEL_LOAD_ADDR);
1c7b3754 PB	355	is_linux = 1;
	356	}
	357	if (kernel_size < 0) {
f93eb9ff AZ	358	fprintf(stderr, "qemu: could not load kernel '%s'\n",
f93eb9ff AZ	359	info->kernel_filename);
1c7b3754 PB	360	exit(1);
1c7b3754 PB	361	}
f2d74978 PB	362	info->entry = entry;
f2d74978 PB	363	if (is_linux) {
f93eb9ff	364	if (info->initrd_filename) {
3b760e04 PB	365	initrd_size = load_image_targphys(info->initrd_filename,
	366	info->loader_start
	367	+ INITRD_LOAD_ADDR,
	368	ram_size - INITRD_LOAD_ADDR);
daf90626 PB	369	if (initrd_size < 0) {
daf90626 PB	370	fprintf(stderr, "qemu: could not load initrd '%s'\n",
f93eb9ff	371	info->initrd_filename);
daf90626 PB	372	exit(1);
	373	}
	374	} else {
	375	initrd_size = 0;
	376	}
412beee6 GL	377	info->initrd_size = initrd_size;
412beee6 GL	378
f8414cb5	379	bootloader[4] = info->board_id;
412beee6 GL	380
	381	/* for device tree boot, we pass the DTB directly in r2. Otherwise
	382	* we point to the kernel args.
	383	*/
	384	if (info->dtb_filename) {
	385	/* Place the DTB after the initrd in memory */
	386	target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
	387	+ INITRD_LOAD_ADDR
	388	+ initrd_size);
	389	if (load_dtb(dtb_start, info)) {
	390	exit(1);
	391	}
	392	bootloader[5] = dtb_start;
	393	} else {
	394	bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
	395	}
1c7b3754	396	bootloader[6] = entry;
52b43737	397	for (n = 0; n < sizeof(bootloader) / 4; n++) {
f2d74978	398	bootloader[n] = tswap32(bootloader[n]);
52b43737	399	}
f2d74978 PB	400	rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
f2d74978 PB	401	info->loader_start);
52b43737	402	if (info->nb_cpus > 1) {
9d5ba9bf	403	info->write_secondary_boot(env, info);
52b43737	404	}
16406950	405	}
f2d74978	406	info->is_linux = is_linux;
6ed221b6 AL	407
	408	for (; env; env = env->next_cpu) {
	409	env->boot_info = info;
	410	qemu_register_reset(do_cpu_reset, env);
	411	}
16406950	412	}