[qemu.git] / hw / armv7m.c

/*
 * ARMV7M System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "sysemu.h"
#include "loader.h"
#include "elf.h"

/* Bitbanded IO.  Each word corresponds to a single bit.  */

/* Get the byte address of the real memory for a bitband acess.  */
static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
{
    uint32_t res;

    res = *(uint32_t *)opaque;
    res |= (addr & 0x1ffffff) >> 5;
    return res;

}

static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
{
    uint8_t v;
    cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
    return (v & (1 << ((offset >> 2) & 7))) != 0;
}

static void bitband_writeb(void *opaque, a_target_phys_addr offset,
                           uint32_t value)
{
    uint32_t addr;
    uint8_t mask;
    uint8_t v;
    addr = bitband_addr(opaque, offset);
    mask = (1 << ((offset >> 2) & 7));
    cpu_physical_memory_read(addr, &v, 1);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, &v, 1);
}

static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
{
    uint32_t addr;
    uint16_t mask;
    uint16_t v;
    addr = bitband_addr(opaque, offset) & ~1;
    mask = (1 << ((offset >> 2) & 15));
    mask = tswap16(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
    return (v & mask) != 0;
}

static void bitband_writew(void *opaque, a_target_phys_addr offset,
                           uint32_t value)
{
    uint32_t addr;
    uint16_t mask;
    uint16_t v;
    addr = bitband_addr(opaque, offset) & ~1;
    mask = (1 << ((offset >> 2) & 15));
    mask = tswap16(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}

static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
{
    uint32_t addr;
    uint32_t mask;
    uint32_t v;
    addr = bitband_addr(opaque, offset) & ~3;
    mask = (1 << ((offset >> 2) & 31));
    mask = tswap32(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
    return (v & mask) != 0;
}

static void bitband_writel(void *opaque, a_target_phys_addr offset,
                           uint32_t value)
{
    uint32_t addr;
    uint32_t mask;
    uint32_t v;
    addr = bitband_addr(opaque, offset) & ~3;
    mask = (1 << ((offset >> 2) & 31));
    mask = tswap32(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}

static CPUReadMemoryFunc * const bitband_readfn[] = {
   bitband_readb,
   bitband_readw,
   bitband_readl
};

static CPUWriteMemoryFunc * const bitband_writefn[] = {
   bitband_writeb,
   bitband_writew,
   bitband_writel
};

typedef struct {
    SysBusDevice busdev;
    uint32_t base;
} BitBandState;

static int bitband_init(SysBusDevice *dev)
{
    BitBandState *s = FROM_SYSBUS(BitBandState, dev);
    int iomemtype;

    iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
                                       &s->base);
    sysbus_init_mmio(dev, 0x02000000, iomemtype);
    return 0;
}

static void armv7m_bitband_init(void)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "ARM,bitband-memory");
    qdev_prop_set_uint32(dev, "base", 0x20000000);
    qdev_init(dev);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000);

    dev = qdev_create(NULL, "ARM,bitband-memory");
    qdev_prop_set_uint32(dev, "base", 0x40000000);
    qdev_init(dev);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000);
}

/* Board init.  */
/* Init CPU and memory for a v7-M based board.
   flash_size and sram_size are in kb.
   Returns the NVIC array.  */

qemu_irq *armv7m_init(int flash_size, int sram_size,
                      const char *kernel_filename, const char *cpu_model)
{
    CPUState *env;
    DeviceState *nvic;
    /* FIXME: make this local state.  */
    static qemu_irq pic[64];
    qemu_irq *cpu_pic;
    uint32_t pc;
    int image_size;
    uint64_t entry;
    uint64_t lowaddr;
    int i;
    int big_endian;

    flash_size *= 1024;
    sram_size *= 1024;

    if (!cpu_model)
	cpu_model = "cortex-m3";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }

#if 0
    /* > 32Mb SRAM gets complicated because it overlaps the bitband area.
       We don't have proper commandline options, so allocate half of memory
       as SRAM, up to a maximum of 32Mb, and the rest as code.  */
    if (ram_size > (512 + 32) * 1024 * 1024)
        ram_size = (512 + 32) * 1024 * 1024;
    sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
    if (sram_size > 32 * 1024 * 1024)
        sram_size = 32 * 1024 * 1024;
    code_size = ram_size - sram_size;
#endif

    /* Flash programming is done via the SCU, so pretend it is ROM.  */
    cpu_register_physical_memory(0, flash_size,
                                 qemu_ram_alloc(flash_size) | IO_MEM_ROM);
    cpu_register_physical_memory(0x20000000, sram_size,
                                 qemu_ram_alloc(sram_size) | IO_MEM_RAM);
    armv7m_bitband_init();

    nvic = qdev_create(NULL, "armv7m_nvic");
    env->v7m.nvic = nvic;
    qdev_init(nvic);
    cpu_pic = arm_pic_init_cpu(env);
    sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
    for (i = 0; i < 64; i++) {
        pic[i] = qdev_get_gpio_in(nvic, i);
    }

#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

    image_size = load_elf(kernel_filename, 0, &entry, &lowaddr, NULL,
                          big_endian, ELF_MACHINE, 1);
    if (image_size < 0) {
        image_size = load_image_targphys(kernel_filename, 0, flash_size);
	lowaddr = 0;
    }
    if (image_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                kernel_filename);
        exit(1);
    }

    /* If the image was loaded at address zero then assume it is a
       regular ROM image and perform the normal CPU reset sequence.
       Otherwise jump directly to the entry point.  */
    if (lowaddr == 0) {
	env->regs[13] = ldl_phys(0);
	pc = ldl_phys(4);
    } else {
	pc = entry;
    }
    env->thumb = pc & 1;
    env->regs[15] = pc & ~1;

    /* Hack to map an additional page of ram at the top of the address
       space.  This stops qemu complaining about executing code outside RAM
       when returning from an exception.  */
    cpu_register_physical_memory(0xfffff000, 0x1000,
                                 qemu_ram_alloc(0x1000) | IO_MEM_RAM);

    return pic;
}

static SysBusDeviceInfo bitband_info = {
    .init = bitband_init,
    .qdev.name  = "ARM,bitband-memory",
    .qdev.size  = sizeof(BitBandState),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("base", BitBandState, base, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void armv7m_register_devices(void)
{
    sysbus_register_withprop(&bitband_info);
}

device_init(armv7m_register_devices)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* ARMV7M System emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
fe7e8758	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
87ecb68b PB	12	#include "sysemu.h"
ca20cf32 BS	13	#include "loader.h"
ca20cf32 BS	14	#include "elf.h"
9ee6e8bb PB	15
	16	/* Bitbanded IO. Each word corresponds to a single bit. */
	17
	18	/* Get the byte address of the real memory for a bitband acess. */
8da3ff18	19	static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
9ee6e8bb PB	20	{
	21	uint32_t res;
	22
8da3ff18	23	res = (uint32_t )opaque;
9ee6e8bb PB	24	res \|= (addr & 0x1ffffff) >> 5;
	25	return res;
	26
	27	}
	28
99a0949b	29	static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
9ee6e8bb PB	30	{
9ee6e8bb PB	31	uint8_t v;
8da3ff18	32	cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
9ee6e8bb PB	33	return (v & (1 << ((offset >> 2) & 7))) != 0;
	34	}
	35
99a0949b	36	static void bitband_writeb(void *opaque, a_target_phys_addr offset,
9ee6e8bb PB	37	uint32_t value)
	38	{
	39	uint32_t addr;
	40	uint8_t mask;
	41	uint8_t v;
8da3ff18	42	addr = bitband_addr(opaque, offset);
9ee6e8bb PB	43	mask = (1 << ((offset >> 2) & 7));
	44	cpu_physical_memory_read(addr, &v, 1);
	45	if (value & 1)
	46	v \|= mask;
	47	else
	48	v &= ~mask;
	49	cpu_physical_memory_write(addr, &v, 1);
	50	}
	51
99a0949b	52	static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
9ee6e8bb PB	53	{
	54	uint32_t addr;
	55	uint16_t mask;
	56	uint16_t v;
8da3ff18	57	addr = bitband_addr(opaque, offset) & ~1;
9ee6e8bb PB	58	mask = (1 << ((offset >> 2) & 15));
	59	mask = tswap16(mask);
	60	cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
	61	return (v & mask) != 0;
	62	}
	63
99a0949b	64	static void bitband_writew(void *opaque, a_target_phys_addr offset,
9ee6e8bb PB	65	uint32_t value)
	66	{
	67	uint32_t addr;
	68	uint16_t mask;
	69	uint16_t v;
8da3ff18	70	addr = bitband_addr(opaque, offset) & ~1;
9ee6e8bb PB	71	mask = (1 << ((offset >> 2) & 15));
	72	mask = tswap16(mask);
	73	cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
	74	if (value & 1)
	75	v \|= mask;
	76	else
	77	v &= ~mask;
	78	cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
	79	}
	80
99a0949b	81	static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
9ee6e8bb PB	82	{
	83	uint32_t addr;
	84	uint32_t mask;
	85	uint32_t v;
8da3ff18	86	addr = bitband_addr(opaque, offset) & ~3;
9ee6e8bb PB	87	mask = (1 << ((offset >> 2) & 31));
	88	mask = tswap32(mask);
	89	cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
	90	return (v & mask) != 0;
	91	}
	92
99a0949b	93	static void bitband_writel(void *opaque, a_target_phys_addr offset,
9ee6e8bb PB	94	uint32_t value)
	95	{
	96	uint32_t addr;
	97	uint32_t mask;
	98	uint32_t v;
8da3ff18	99	addr = bitband_addr(opaque, offset) & ~3;
9ee6e8bb PB	100	mask = (1 << ((offset >> 2) & 31));
	101	mask = tswap32(mask);
	102	cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
	103	if (value & 1)
	104	v \|= mask;
	105	else
	106	v &= ~mask;
	107	cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
	108	}
	109
d60efc6b	110	static CPUReadMemoryFunc * const bitband_readfn[] = {
9ee6e8bb PB	111	bitband_readb,
	112	bitband_readw,
	113	bitband_readl
	114	};
	115
d60efc6b	116	static CPUWriteMemoryFunc * const bitband_writefn[] = {
9ee6e8bb PB	117	bitband_writeb,
	118	bitband_writew,
	119	bitband_writel
	120	};
	121
40905a6a PB	122	typedef struct {
	123	SysBusDevice busdev;
	124	uint32_t base;
	125	} BitBandState;
	126
81a322d4	127	static int bitband_init(SysBusDevice *dev)
9ee6e8bb	128	{
40905a6a	129	BitBandState *s = FROM_SYSBUS(BitBandState, dev);
9ee6e8bb PB	130	int iomemtype;
9ee6e8bb PB	131
1eed09cb	132	iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
40905a6a PB	133	&s->base);
40905a6a PB	134	sysbus_init_mmio(dev, 0x02000000, iomemtype);
81a322d4	135	return 0;
40905a6a PB	136	}
	137
	138	static void armv7m_bitband_init(void)
	139	{
	140	DeviceState *dev;
	141
	142	dev = qdev_create(NULL, "ARM,bitband-memory");
ee6847d1	143	qdev_prop_set_uint32(dev, "base", 0x20000000);
40905a6a PB	144	qdev_init(dev);
	145	sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000);
	146
	147	dev = qdev_create(NULL, "ARM,bitband-memory");
ee6847d1	148	qdev_prop_set_uint32(dev, "base", 0x40000000);
40905a6a PB	149	qdev_init(dev);
40905a6a PB	150	sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000);
9ee6e8bb PB	151	}
	152
	153	/* Board init. */
	154	/* Init CPU and memory for a v7-M based board.
	155	flash_size and sram_size are in kb.
	156	Returns the NVIC array. */
	157
	158	qemu_irq *armv7m_init(int flash_size, int sram_size,
	159	const char kernel_filename, const char cpu_model)
	160	{
	161	CPUState *env;
fe7e8758 PB	162	DeviceState *nvic;
	163	/* FIXME: make this local state. */
	164	static qemu_irq pic[64];
	165	qemu_irq *cpu_pic;
9ee6e8bb PB	166	uint32_t pc;
	167	int image_size;
	168	uint64_t entry;
	169	uint64_t lowaddr;
fe7e8758	170	int i;
ca20cf32	171	int big_endian;
9ee6e8bb PB	172
	173	flash_size *= 1024;
	174	sram_size *= 1024;
	175
	176	if (!cpu_model)
	177	cpu_model = "cortex-m3";
	178	env = cpu_init(cpu_model);
	179	if (!env) {
	180	fprintf(stderr, "Unable to find CPU definition\n");
	181	exit(1);
	182	}
	183
	184	#if 0
	185	/* > 32Mb SRAM gets complicated because it overlaps the bitband area.
	186	We don't have proper commandline options, so allocate half of memory
	187	as SRAM, up to a maximum of 32Mb, and the rest as code. */
	188	if (ram_size > (512 + 32) * 1024 * 1024)
	189	ram_size = (512 + 32) * 1024 * 1024;
	190	sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
	191	if (sram_size > 32 * 1024 * 1024)
	192	sram_size = 32 * 1024 * 1024;
	193	code_size = ram_size - sram_size;
	194	#endif
	195
	196	/* Flash programming is done via the SCU, so pretend it is ROM. */
dcac9679 PB	197	cpu_register_physical_memory(0, flash_size,
dcac9679 PB	198	qemu_ram_alloc(flash_size) \| IO_MEM_ROM);
9ee6e8bb	199	cpu_register_physical_memory(0x20000000, sram_size,
dcac9679	200	qemu_ram_alloc(sram_size) \| IO_MEM_RAM);
9ee6e8bb PB	201	armv7m_bitband_init();
9ee6e8bb PB	202
fe7e8758	203	nvic = qdev_create(NULL, "armv7m_nvic");
bdb11366	204	env->v7m.nvic = nvic;
fe7e8758 PB	205	qdev_init(nvic);
	206	cpu_pic = arm_pic_init_cpu(env);
	207	sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
	208	for (i = 0; i < 64; i++) {
067a3ddc	209	pic[i] = qdev_get_gpio_in(nvic, i);
fe7e8758	210	}
9ee6e8bb	211
ca20cf32 BS	212	#ifdef TARGET_WORDS_BIGENDIAN
	213	big_endian = 1;
	214	#else
	215	big_endian = 0;
	216	#endif
	217
	218	image_size = load_elf(kernel_filename, 0, &entry, &lowaddr, NULL,
	219	big_endian, ELF_MACHINE, 1);
9ee6e8bb	220	if (image_size < 0) {
dcac9679	221	image_size = load_image_targphys(kernel_filename, 0, flash_size);
9ee6e8bb PB	222	lowaddr = 0;
	223	}
	224	if (image_size < 0) {
	225	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	226	kernel_filename);
	227	exit(1);
	228	}
	229
	230	/* If the image was loaded at address zero then assume it is a
	231	regular ROM image and perform the normal CPU reset sequence.
	232	Otherwise jump directly to the entry point. */
	233	if (lowaddr == 0) {
44654490 PB	234	env->regs[13] = ldl_phys(0);
44654490 PB	235	pc = ldl_phys(4);
9ee6e8bb PB	236	} else {
	237	pc = entry;
	238	}
	239	env->thumb = pc & 1;
	240	env->regs[15] = pc & ~1;
	241
	242	/* Hack to map an additional page of ram at the top of the address
	243	space. This stops qemu complaining about executing code outside RAM
	244	when returning from an exception. */
dcac9679 PB	245	cpu_register_physical_memory(0xfffff000, 0x1000,
dcac9679 PB	246	qemu_ram_alloc(0x1000) \| IO_MEM_RAM);
9ee6e8bb PB	247
	248	return pic;
	249	}
40905a6a	250
ee6847d1 GH	251	static SysBusDeviceInfo bitband_info = {
	252	.init = bitband_init,
	253	.qdev.name = "ARM,bitband-memory",
	254	.qdev.size = sizeof(BitBandState),
	255	.qdev.props = (Property[]) {
1832efa2 GH	256	DEFINE_PROP_UINT32("base", BitBandState, base, 0),
1832efa2 GH	257	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	258	}
	259	};
	260
40905a6a PB	261	static void armv7m_register_devices(void)
40905a6a PB	262	{
ee6847d1	263	sysbus_register_withprop(&bitband_info);
40905a6a PB	264	}
	265
	266	device_init(armv7m_register_devices)