[qemu.git] / hw / armv7m_nvic.c

/*
 * ARM Nested Vectored Interrupt Controller
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 *
 * The ARMv7M System controller is fairly tightly tied in with the
 * NVIC.  Much of that is also implemented here.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "arm-misc.h"

#define GIC_NIRQ 64
#define NCPU 1
#define NVIC 1

/* Only a single "CPU" interface is present.  */
static inline int
gic_get_current_cpu(void)
{
    return 0;
}

static uint32_t nvic_readl(void *opaque, uint32_t offset);
static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);

#include "arm_gic.c"

typedef struct {
    struct {
        uint32_t control;
        uint32_t reload;
        int64_t tick;
        QEMUTimer *timer;
    } systick;
    gic_state *gic;
} nvic_state;

/* qemu timers run at 1GHz.   We want something closer to 1MHz.  */
#define SYSTICK_SCALE 1000ULL

#define SYSTICK_ENABLE    (1 << 0)
#define SYSTICK_TICKINT   (1 << 1)
#define SYSTICK_CLKSOURCE (1 << 2)
#define SYSTICK_COUNTFLAG (1 << 16)

/* Conversion factor from qemu timer to SysTick frequencies.
   QEMU uses a base of 1GHz, so these give 20MHz and 1MHz for core and
   reference frequencies.  */

static inline int64_t systick_scale(nvic_state *s)
{
    if (s->systick.control & SYSTICK_CLKSOURCE)
        return 50;
    else
        return 1000;
}

static void systick_reload(nvic_state *s, int reset)
{
    if (reset)
        s->systick.tick = qemu_get_clock(vm_clock);
    s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
    qemu_mod_timer(s->systick.timer, s->systick.tick);
}

static void systick_timer_tick(void * opaque)
{
    nvic_state *s = (nvic_state *)opaque;
    s->systick.control |= SYSTICK_COUNTFLAG;
    if (s->systick.control & SYSTICK_TICKINT) {
        /* Trigger the interrupt.  */
        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
    }
    if (s->systick.reload == 0) {
        s->systick.control &= ~SYSTICK_ENABLE;
    } else {
        systick_reload(s, 0);
    }
}

/* The external routines use the hardware vector numbering, ie. the first
   IRQ is #16.  The internal GIC routines use #32 as the first IRQ.  */
void armv7m_nvic_set_pending(void *opaque, int irq)
{
    nvic_state *s = (nvic_state *)opaque;
    if (irq >= 16)
        irq += 16;
    gic_set_pending_private(s->gic, 0, irq);
}

/* Make pending IRQ active.  */
int armv7m_nvic_acknowledge_irq(void *opaque)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t irq;

    irq = gic_acknowledge_irq(s->gic, 0);
    if (irq == 1023)
        cpu_abort(cpu_single_env, "Interrupt but no vector\n");
    if (irq >= 32)
        irq -= 16;
    return irq;
}

void armv7m_nvic_complete_irq(void *opaque, int irq)
{
    nvic_state *s = (nvic_state *)opaque;
    if (irq >= 16)
        irq += 16;
    gic_complete_irq(s->gic, 0, irq);
}

static uint32_t nvic_readl(void *opaque, uint32_t offset)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t val;
    int irq;

    switch (offset) {
    case 4: /* Interrupt Control Type.  */
        return (GIC_NIRQ / 32) - 1;
    case 0x10: /* SysTick Control and Status.  */
        val = s->systick.control;
        s->systick.control &= ~SYSTICK_COUNTFLAG;
        return val;
    case 0x14: /* SysTick Reload Value.  */
        return s->systick.reload;
    case 0x18: /* SysTick Current Value.  */
        {
            int64_t t;
            if ((s->systick.control & SYSTICK_ENABLE) == 0)
                return 0;
            t = qemu_get_clock(vm_clock);
            if (t >= s->systick.tick)
                return 0;
            val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
            /* The interrupt in triggered when the timer reaches zero.
               However the counter is not reloaded until the next clock
               tick.  This is a hack to return zero during the first tick.  */
            if (val > s->systick.reload)
                val = 0;
            return val;
        }
    case 0x1c: /* SysTick Calibration Value.  */
        return 10000;
    case 0xd00: /* CPUID Base.  */
        return cpu_single_env->cp15.c0_cpuid;
    case 0xd04: /* Interrypt Control State.  */
        /* VECTACTIVE */
        val = s->gic->running_irq[0];
        if (val == 1023) {
            val = 0;
        } else if (val >= 32) {
            val -= 16;
        }
        /* RETTOBASE */
        if (s->gic->running_irq[0] == 1023
                || s->gic->last_active[s->gic->running_irq[0]][0] == 1023) {
            val |= (1 << 11);
        }
        /* VECTPENDING */
        if (s->gic->current_pending[0] != 1023)
            val |= (s->gic->current_pending[0] << 12);
        /* ISRPENDING */
        for (irq = 32; irq < GIC_NIRQ; irq++) {
            if (s->gic->irq_state[irq].pending) {
                val |= (1 << 22);
                break;
            }
        }
        /* PENDSTSET */
        if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending)
            val |= (1 << 26);
        /* PENDSVSET */
        if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending)
            val |= (1 << 28);
        /* NMIPENDSET */
        if (s->gic->irq_state[ARMV7M_EXCP_NMI].pending)
            val |= (1 << 31);
        return val;
    case 0xd08: /* Vector Table Offset.  */
        return cpu_single_env->v7m.vecbase;
    case 0xd0c: /* Application Interrupt/Reset Control.  */
        return 0xfa05000;
    case 0xd10: /* System Control.  */
        /* TODO: Implement SLEEPONEXIT.  */
        return 0;
    case 0xd14: /* Configuration Control.  */
        /* TODO: Implement Configuration Control bits.  */
        return 0;
    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
        irq = offset - 0xd14;
        val = 0;
        val = s->gic->priority1[irq++][0];
        val = s->gic->priority1[irq++][0] << 8;
        val = s->gic->priority1[irq++][0] << 16;
        val = s->gic->priority1[irq][0] << 24;
        return val;
    case 0xd24: /* System Handler Status.  */
        val = 0;
        if (s->gic->irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
        if (s->gic->irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
        if (s->gic->irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
        if (s->gic->irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
        if (s->gic->irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
        if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
        if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
        if (s->gic->irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
        if (s->gic->irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
        if (s->gic->irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
        if (s->gic->irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
        if (s->gic->irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
        if (s->gic->irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
        if (s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
        return val;
    case 0xd28: /* Configurable Fault Status.  */
        /* TODO: Implement Fault Status.  */
        cpu_abort(cpu_single_env,
                  "Not implemented: Configurable Fault Status.");
        return 0;
    case 0xd2c: /* Hard Fault Status.  */
    case 0xd30: /* Debug Fault Status.  */
    case 0xd34: /* Mem Manage Address.  */
    case 0xd38: /* Bus Fault Address.  */
    case 0xd3c: /* Aux Fault Status.  */
        /* TODO: Implement fault status registers.  */
        goto bad_reg;
    case 0xd40: /* PFR0.  */
        return 0x00000030;
    case 0xd44: /* PRF1.  */
        return 0x00000200;
    case 0xd48: /* DFR0.  */
        return 0x00100000;
    case 0xd4c: /* AFR0.  */
        return 0x00000000;
    case 0xd50: /* MMFR0.  */
        return 0x00000030;
    case 0xd54: /* MMFR1.  */
        return 0x00000000;
    case 0xd58: /* MMFR2.  */
        return 0x00000000;
    case 0xd5c: /* MMFR3.  */
        return 0x00000000;
    case 0xd60: /* ISAR0.  */
        return 0x01141110;
    case 0xd64: /* ISAR1.  */
        return 0x02111000;
    case 0xd68: /* ISAR2.  */
        return 0x21112231;
    case 0xd6c: /* ISAR3.  */
        return 0x01111110;
    case 0xd70: /* ISAR4.  */
        return 0x01310102;
    /* TODO: Implement debug registers.  */
    default:
    bad_reg:
        cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
    }
}

static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t oldval;
    switch (offset) {
    case 0x10: /* SysTick Control and Status.  */
        oldval = s->systick.control;
        s->systick.control &= 0xfffffff8;
        s->systick.control |= value & 7;
        if ((oldval ^ value) & SYSTICK_ENABLE) {
            int64_t now = qemu_get_clock(vm_clock);
            if (value & SYSTICK_ENABLE) {
                if (s->systick.tick) {
                    s->systick.tick += now;
                    qemu_mod_timer(s->systick.timer, s->systick.tick);
                } else {
                    systick_reload(s, 1);
                }
            } else {
                qemu_del_timer(s->systick.timer);
                s->systick.tick -= now;
                if (s->systick.tick < 0)
                  s->systick.tick = 0;
            }
        } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
            /* This is a hack. Force the timer to be reloaded
               when the reference clock is changed.  */
            systick_reload(s, 1);
        }
        break;
    case 0x14: /* SysTick Reload Value.  */
        s->systick.reload = value;
        break;
    case 0x18: /* SysTick Current Value.  Writes reload the timer.  */
        systick_reload(s, 1);
        s->systick.control &= ~SYSTICK_COUNTFLAG;
        break;
    case 0xd04: /* Interrupt Control State.  */
        if (value & (1 << 31)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
        }
        if (value & (1 << 28)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
        } else if (value & (1 << 27)) {
            s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
            gic_update(s->gic);
        }
        if (value & (1 << 26)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
        } else if (value & (1 << 25)) {
            s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
            gic_update(s->gic);
        }
        break;
    case 0xd08: /* Vector Table Offset.  */
        cpu_single_env->v7m.vecbase = value & 0xffffff80;
        break;
    case 0xd0c: /* Application Interrupt/Reset Control.  */
        if ((value >> 16) == 0x05fa) {
            if (value & 2) {
                cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
            }
            if (value & 5) {
                cpu_abort(cpu_single_env, "System reset");
            }
        }
        break;
    case 0xd10: /* System Control.  */
    case 0xd14: /* Configuration Control.  */
        /* TODO: Implement control registers.  */
        goto bad_reg;
    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
        {
            int irq;
            irq = offset - 0xd14;
            s->gic->priority1[irq++][0] = value & 0xff;
            s->gic->priority1[irq++][0] = (value >> 8) & 0xff;
            s->gic->priority1[irq++][0] = (value >> 16) & 0xff;
            s->gic->priority1[irq][0] = (value >> 24) & 0xff;
            gic_update(s->gic);
        }
        break;
    case 0xd24: /* System Handler Control.  */
        /* TODO: Real hardware allows you to set/clear the active bits
           under some circumstances.  We don't implement this.  */
        s->gic->irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
        s->gic->irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
        s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
        break;
    case 0xd28: /* Configurable Fault Status.  */
    case 0xd2c: /* Hard Fault Status.  */
    case 0xd30: /* Debug Fault Status.  */
    case 0xd34: /* Mem Manage Address.  */
    case 0xd38: /* Bus Fault Address.  */
    case 0xd3c: /* Aux Fault Status.  */
        goto bad_reg;
    default:
    bad_reg:
        cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
    }
}

qemu_irq *armv7m_nvic_init(CPUState *env)
{
    nvic_state *s;
    qemu_irq *parent;

    parent = arm_pic_init_cpu(env);
    s = (nvic_state *)qemu_mallocz(sizeof(nvic_state));
    s->gic = gic_init(0xe000e000, &parent[ARM_PIC_CPU_IRQ]);
    s->gic->nvic = s;
    s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
    if (env->v7m.nvic)
        cpu_abort(env, "CPU can only have one NVIC\n");
    env->v7m.nvic = s;
    return s->gic->in;
}
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* ARM Nested Vectored Interrupt Controller
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*
	9	* The ARMv7M System controller is fairly tightly tied in with the
	10	* NVIC. Much of that is also implemented here.
	11	*/
	12
87ecb68b PB	13	#include "hw.h"
	14	#include "qemu-timer.h"
	15	#include "arm-misc.h"
9ee6e8bb PB	16
	17	#define GIC_NIRQ 64
	18	#define NCPU 1
	19	#define NVIC 1
	20
	21	/* Only a single "CPU" interface is present. */
	22	static inline int
	23	gic_get_current_cpu(void)
	24	{
	25	return 0;
	26	}
	27
	28	static uint32_t nvic_readl(void *opaque, uint32_t offset);
	29	static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
	30
	31	#include "arm_gic.c"
	32
	33	typedef struct {
	34	struct {
	35	uint32_t control;
	36	uint32_t reload;
	37	int64_t tick;
	38	QEMUTimer *timer;
	39	} systick;
	40	gic_state *gic;
	41	} nvic_state;
	42
	43	/* qemu timers run at 1GHz. We want something closer to 1MHz. */
	44	#define SYSTICK_SCALE 1000ULL
	45
	46	#define SYSTICK_ENABLE (1 << 0)
	47	#define SYSTICK_TICKINT (1 << 1)
	48	#define SYSTICK_CLKSOURCE (1 << 2)
	49	#define SYSTICK_COUNTFLAG (1 << 16)
	50
	51	/* Conversion factor from qemu timer to SysTick frequencies.
	52	QEMU uses a base of 1GHz, so these give 20MHz and 1MHz for core and
	53	reference frequencies. */
	54
	55	static inline int64_t systick_scale(nvic_state *s)
	56	{
	57	if (s->systick.control & SYSTICK_CLKSOURCE)
	58	return 50;
	59	else
	60	return 1000;
	61	}
	62
	63	static void systick_reload(nvic_state *s, int reset)
	64	{
	65	if (reset)
	66	s->systick.tick = qemu_get_clock(vm_clock);
	67	s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
	68	qemu_mod_timer(s->systick.timer, s->systick.tick);
	69	}
	70
	71	static void systick_timer_tick(void * opaque)
	72	{
	73	nvic_state s = (nvic_state )opaque;
	74	s->systick.control \|= SYSTICK_COUNTFLAG;
	75	if (s->systick.control & SYSTICK_TICKINT) {
	76	/* Trigger the interrupt. */
	77	armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
	78	}
	79	if (s->systick.reload == 0) {
80	s->systick.control &= ~SYSTICK_ENABLE;
81	} else {
82	systick_reload(s, 0);
83	}
84	}
85
86	/* The external routines use the hardware vector numbering, ie. the first
87	IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
88	void armv7m_nvic_set_pending(void *opaque, int irq)
89	{
90	nvic_state s = (nvic_state )opaque;
91	if (irq >= 16)
92	irq += 16;
93	gic_set_pending_private(s->gic, 0, irq);
94	}
95
96	/* Make pending IRQ active. */
97	int armv7m_nvic_acknowledge_irq(void *opaque)
98	{
99	nvic_state s = (nvic_state )opaque;
100	uint32_t irq;
101
102	irq = gic_acknowledge_irq(s->gic, 0);
103	if (irq == 1023)
104	cpu_abort(cpu_single_env, "Interrupt but no vector\n");
105	if (irq >= 32)
106	irq -= 16;
107	return irq;
108	}
109
110	void armv7m_nvic_complete_irq(void *opaque, int irq)
111	{
112	nvic_state s = (nvic_state )opaque;
113	if (irq >= 16)
114	irq += 16;
115	gic_complete_irq(s->gic, 0, irq);
116	}
117
118	static uint32_t nvic_readl(void *opaque, uint32_t offset)
119	{
120	nvic_state s = (nvic_state )opaque;
121	uint32_t val;
122	int irq;
123
124	switch (offset) {
125	case 4: /* Interrupt Control Type. */
126	return (GIC_NIRQ / 32) - 1;
127	case 0x10: /* SysTick Control and Status. */
128	val = s->systick.control;
129	s->systick.control &= ~SYSTICK_COUNTFLAG;
130	return val;
131	case 0x14: /* SysTick Reload Value. */
132	return s->systick.reload;
133	case 0x18: /* SysTick Current Value. */
134	{
135	int64_t t;
136	if ((s->systick.control & SYSTICK_ENABLE) == 0)
137	return 0;
138	t = qemu_get_clock(vm_clock);
139	if (t >= s->systick.tick)
140	return 0;
141	val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
142	/* The interrupt in triggered when the timer reaches zero.
143	However the counter is not reloaded until the next clock
144	tick. This is a hack to return zero during the first tick. */
145	if (val > s->systick.reload)
146	val = 0;
147	return val;
148	}
149	case 0x1c: /* SysTick Calibration Value. */
150	return 10000;
151	case 0xd00: /* CPUID Base. */
152	return cpu_single_env->cp15.c0_cpuid;
153	case 0xd04: /* Interrypt Control State. */
154	/* VECTACTIVE */
155	val = s->gic->running_irq[0];
156	if (val == 1023) {
157	val = 0;
158	} else if (val >= 32) {
159	val -= 16;
160	}
161	/* RETTOBASE */
162	if (s->gic->running_irq[0] == 1023
163	\|\| s->gic->last_active[s->gic->running_irq[0]][0] == 1023) {
164	val \|= (1 << 11);
165	}
166	/* VECTPENDING */
167	if (s->gic->current_pending[0] != 1023)
168	val \|= (s->gic->current_pending[0] << 12);
169	/* ISRPENDING */
170	for (irq = 32; irq < GIC_NIRQ; irq++) {
171	if (s->gic->irq_state[irq].pending) {
172	val \|= (1 << 22);
173	break;
174	}
175	}
176	/* PENDSTSET */
177	if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending)
178	val \|= (1 << 26);
179	/* PENDSVSET */
180	if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending)
181	val \|= (1 << 28);
182	/* NMIPENDSET */
183	if (s->gic->irq_state[ARMV7M_EXCP_NMI].pending)
184	val \|= (1 << 31);
185	return val;
186	case 0xd08: /* Vector Table Offset. */
187	return cpu_single_env->v7m.vecbase;
188	case 0xd0c: /* Application Interrupt/Reset Control. */
189	return 0xfa05000;
190	case 0xd10: /* System Control. */
191	/* TODO: Implement SLEEPONEXIT. */
192	return 0;
193	case 0xd14: /* Configuration Control. */
194	/* TODO: Implement Configuration Control bits. */
195	return 0;
196	case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
197	irq = offset - 0xd14;
198	val = 0;
199	val = s->gic->priority1[irq++][0];
200	val = s->gic->priority1[irq++][0] << 8;
201	val = s->gic->priority1[irq++][0] << 16;
202	val = s->gic->priority1[irq][0] << 24;
203	return val;
204	case 0xd24: /* System Handler Status. */
205	val = 0;
206	if (s->gic->irq_state[ARMV7M_EXCP_MEM].active) val \|= (1 << 0);
207	if (s->gic->irq_state[ARMV7M_EXCP_BUS].active) val \|= (1 << 1);
208	if (s->gic->irq_state[ARMV7M_EXCP_USAGE].active) val \|= (1 << 3);
209	if (s->gic->irq_state[ARMV7M_EXCP_SVC].active) val \|= (1 << 7);
210	if (s->gic->irq_state[ARMV7M_EXCP_DEBUG].active) val \|= (1 << 8);
211	if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].active) val \|= (1 << 10);
212	if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].active) val \|= (1 << 11);
213	if (s->gic->irq_state[ARMV7M_EXCP_USAGE].pending) val \|= (1 << 12);
214	if (s->gic->irq_state[ARMV7M_EXCP_MEM].pending) val \|= (1 << 13);
215	if (s->gic->irq_state[ARMV7M_EXCP_BUS].pending) val \|= (1 << 14);
216	if (s->gic->irq_state[ARMV7M_EXCP_SVC].pending) val \|= (1 << 15);
217	if (s->gic->irq_state[ARMV7M_EXCP_MEM].enabled) val \|= (1 << 16);
218	if (s->gic->irq_state[ARMV7M_EXCP_BUS].enabled) val \|= (1 << 17);
219	if (s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled) val \|= (1 << 18);
220	return val;
221	case 0xd28: /* Configurable Fault Status. */
222	/* TODO: Implement Fault Status. */
223	cpu_abort(cpu_single_env,
224	"Not implemented: Configurable Fault Status.");
225	return 0;
226	case 0xd2c: /* Hard Fault Status. */
227	case 0xd30: /* Debug Fault Status. */
228	case 0xd34: /* Mem Manage Address. */
229	case 0xd38: /* Bus Fault Address. */
230	case 0xd3c: /* Aux Fault Status. */
231	/* TODO: Implement fault status registers. */
232	goto bad_reg;
233	case 0xd40: /* PFR0. */
234	return 0x00000030;
235	case 0xd44: /* PRF1. */
236	return 0x00000200;
237	case 0xd48: /* DFR0. */
238	return 0x00100000;
239	case 0xd4c: /* AFR0. */
240	return 0x00000000;
241	case 0xd50: /* MMFR0. */
242	return 0x00000030;
243	case 0xd54: /* MMFR1. */
244	return 0x00000000;
245	case 0xd58: /* MMFR2. */
246	return 0x00000000;
247	case 0xd5c: /* MMFR3. */
248	return 0x00000000;
249	case 0xd60: /* ISAR0. */
250	return 0x01141110;
251	case 0xd64: /* ISAR1. */
252	return 0x02111000;
253	case 0xd68: /* ISAR2. */
254	return 0x21112231;
255	case 0xd6c: /* ISAR3. */
256	return 0x01111110;
257	case 0xd70: /* ISAR4. */
258	return 0x01310102;
259	/* TODO: Implement debug registers. */
260	default:
261	bad_reg:
262	cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
263	}
264	}
265
266	static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
267	{
268	nvic_state s = (nvic_state )opaque;
269	uint32_t oldval;
270	switch (offset) {
271	case 0x10: /* SysTick Control and Status. */
272	oldval = s->systick.control;
273	s->systick.control &= 0xfffffff8;
274	s->systick.control \|= value & 7;
275	if ((oldval ^ value) & SYSTICK_ENABLE) {
276	int64_t now = qemu_get_clock(vm_clock);
277	if (value & SYSTICK_ENABLE) {
278	if (s->systick.tick) {
279	s->systick.tick += now;
280	qemu_mod_timer(s->systick.timer, s->systick.tick);
281	} else {
282	systick_reload(s, 1);
283	}
284	} else {
285	qemu_del_timer(s->systick.timer);
286	s->systick.tick -= now;
287	if (s->systick.tick < 0)
288	s->systick.tick = 0;
289	}
290	} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
291	/* This is a hack. Force the timer to be reloaded
292	when the reference clock is changed. */
293	systick_reload(s, 1);
294	}
295	break;
296	case 0x14: /* SysTick Reload Value. */
297	s->systick.reload = value;
298	break;
299	case 0x18: /* SysTick Current Value. Writes reload the timer. */
300	systick_reload(s, 1);
301	s->systick.control &= ~SYSTICK_COUNTFLAG;
302	break;
303	case 0xd04: /* Interrupt Control State. */
304	if (value & (1 << 31)) {
305	armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
306	}
307	if (value & (1 << 28)) {
308	armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
309	} else if (value & (1 << 27)) {
310	s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
311	gic_update(s->gic);
312	}
313	if (value & (1 << 26)) {
314	armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
315	} else if (value & (1 << 25)) {
316	s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
317	gic_update(s->gic);
318	}
319	break;
320	case 0xd08: /* Vector Table Offset. */
321	cpu_single_env->v7m.vecbase = value & 0xffffff80;
322	break;
323	case 0xd0c: /* Application Interrupt/Reset Control. */
324	if ((value >> 16) == 0x05fa) {
325	if (value & 2) {
326	cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
327	}
328	if (value & 5) {
329	cpu_abort(cpu_single_env, "System reset");
330	}
331	}
332	break;
333	case 0xd10: /* System Control. */
334	case 0xd14: /* Configuration Control. */
335	/* TODO: Implement control registers. */
336	goto bad_reg;
337	case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
338	{
339	int irq;
340	irq = offset - 0xd14;
341	s->gic->priority1[irq++][0] = value & 0xff;
342	s->gic->priority1[irq++][0] = (value >> 8) & 0xff;
343	s->gic->priority1[irq++][0] = (value >> 16) & 0xff;
344	s->gic->priority1[irq][0] = (value >> 24) & 0xff;
345	gic_update(s->gic);
346	}
347	break;
348	case 0xd24: /* System Handler Control. */
349	/* TODO: Real hardware allows you to set/clear the active bits
350	under some circumstances. We don't implement this. */
351	s->gic->irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
352	s->gic->irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
353	s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
354	break;
355	case 0xd28: /* Configurable Fault Status. */
356	case 0xd2c: /* Hard Fault Status. */
357	case 0xd30: /* Debug Fault Status. */
358	case 0xd34: /* Mem Manage Address. */
359	case 0xd38: /* Bus Fault Address. */
360	case 0xd3c: /* Aux Fault Status. */
361	goto bad_reg;
362	default:
363	bad_reg:
364	cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
365	}
366	}
367
368	qemu_irq armv7m_nvic_init(CPUState env)
369	{
370	nvic_state *s;
371	qemu_irq *parent;
372
373	parent = arm_pic_init_cpu(env);
374	s = (nvic_state *)qemu_mallocz(sizeof(nvic_state));
375	s->gic = gic_init(0xe000e000, &parent[ARM_PIC_CPU_IRQ]);
376	s->gic->nvic = s;
377	s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
378	if (env->v7m.nvic)
379	cpu_abort(env, "CPU can only have one NVIC\n");
380	env->v7m.nvic = s;
381	return s->gic->in;
382	}