[qemu.git] / hw / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "net.h"
#include "flash.h"
#include "boards.h"
#include "etraxfs.h"
#include "loader.h"
#include "elf.h"
#include "cris-boot.h"
#include "blockdev.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static CPUReadMemoryFunc * const nand_read[] = {
    &nand_readl,
    &nand_readl,
    &nand_readl,
};

static CPUWriteMemoryFunc * const nand_write[] = {
    &nand_writel,
    &nand_writel,
    &nand_writel,
};


struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celcius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static CPUReadMemoryFunc * const gpio_read[] = {
    NULL, NULL,
    &gpio_readl,
};

static CPUWriteMemoryFunc * const gpio_write[] = {
    NULL, NULL,
    &gpio_writel,
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init (ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2], *cpu_irq;
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    int nand_regs;
    int gpio_regs;
    ram_addr_t phys_ram;
    ram_addr_t phys_intmem;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    env = cpu_init(cpu_model);

    /* allocate RAM */
    phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
    cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
    cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
                                 phys_intmem | IO_MEM_RAM);


      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
                                NAND_MFR_STMICRO, 0x39);
    nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);

    gpio_state.nand = &nand_state;
    gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);


    cpu_irq = cris_pic_init_cpu(env);
    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, cpu_irq[0]);
    sysbus_connect_irq(s, 1, cpu_irq[1]);
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
                             irq[0x14 + i]);
    }

    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    li.image_filename = kernel_filename;
    li.cmdline = kernel_cmdline;
    cris_load_image(env, &li);
}

static QEMUMachine axisdev88_machine = {
    .name = "axis-dev88",
    .desc = "AXIS devboard 88",
    .init = axisdev88_init,
    .is_default = 1,
};

static void axisdev88_machine_init(void)
{
    qemu_register_machine(&axisdev88_machine);
}

machine_init(axisdev88_machine_init);
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985 EI	24
4b816985 EI	25	#include "sysbus.h"
10c144e2 EI	26	#include "net.h"
10c144e2 EI	27	#include "flash.h"
10c144e2	28	#include "boards.h"
10c144e2	29	#include "etraxfs.h"
ca20cf32 BS	30	#include "loader.h"
ca20cf32 BS	31	#include "elf.h"
77d4f95e	32	#include "cris-boot.h"
522f253c	33	#include "blockdev.h"
10c144e2 EI	34
	35	#define D(x)
	36	#define DNAND(x)
	37
	38	struct nand_state_t
	39	{
d4220389	40	DeviceState *nand;
10c144e2 EI	41	unsigned int rdy:1;
	42	unsigned int ale:1;
	43	unsigned int cle:1;
	44	unsigned int ce:1;
	45	};
	46
	47	static struct nand_state_t nand_state;
c227f099	48	static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
10c144e2 EI	49	{
	50	struct nand_state_t *s = opaque;
	51	uint32_t r;
	52	int rdy;
	53
	54	r = nand_getio(s->nand);
	55	nand_getpins(s->nand, &rdy);
	56	s->rdy = rdy;
	57
	58	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	59	return r;
	60	}
	61
	62	static void
c227f099	63	nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
10c144e2 EI	64	{
	65	struct nand_state_t *s = opaque;
	66	int rdy;
	67
	68	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
	69	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	70	nand_setio(s->nand, value);
	71	nand_getpins(s->nand, &rdy);
	72	s->rdy = rdy;
	73	}
	74
d60efc6b	75	static CPUReadMemoryFunc * const nand_read[] = {
10c144e2 EI	76	&nand_readl,
	77	&nand_readl,
	78	&nand_readl,
	79	};
	80
d60efc6b	81	static CPUWriteMemoryFunc * const nand_write[] = {
10c144e2 EI	82	&nand_writel,
	83	&nand_writel,
	84	&nand_writel,
	85	};
	86
4a1e6bea EI	87
	88	struct tempsensor_t
	89	{
	90	unsigned int shiftreg;
	91	unsigned int count;
	92	enum {
	93	ST_OUT, ST_IN, ST_Z
	94	} state;
	95
	96	uint16_t regs[3];
	97	};
	98
	99	static void tempsensor_clkedge(struct tempsensor_t *s,
	100	unsigned int clk, unsigned int data_in)
	101	{
	102	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	103	clk, s->state, s->shiftreg));
	104	if (s->count == 0) {
	105	s->count = 16;
	106	s->state = ST_OUT;
	107	}
	108	switch (s->state) {
	109	case ST_OUT:
	110	/* Output reg is clocked at negedge. */
	111	if (!clk) {
	112	s->count--;
	113	s->shiftreg <<= 1;
	114	if (s->count == 0) {
	115	s->shiftreg = 0;
	116	s->state = ST_IN;
	117	s->count = 16;
	118	}
	119	}
	120	break;
	121	case ST_Z:
	122	if (clk) {
	123	s->count--;
	124	if (s->count == 0) {
	125	s->shiftreg = 0;
	126	s->state = ST_OUT;
	127	s->count = 16;
	128	}
	129	}
	130	break;
	131	case ST_IN:
	132	/* Indata is sampled at posedge. */
	133	if (clk) {
	134	s->count--;
	135	s->shiftreg <<= 1;
	136	s->shiftreg \|= data_in & 1;
	137	if (s->count == 0) {
	138	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	139	s->regs[0] = s->shiftreg;
	140	s->state = ST_OUT;
	141	s->count = 16;
	142
	143	if ((s->regs[0] & 0xff) == 0) {
	144	/* 25 degrees celcius. */
	145	s->shiftreg = 0x0b9f;
	146	} else if ((s->regs[0] & 0xff) == 0xff) {
	147	/* Sensor ID, 0x8100 LM70. */
	148	s->shiftreg = 0x8100;
	149	} else
	150	printf("Invalid tempsens state %x\n", s->regs[0]);
151	}
152	}
153	break;
154	}
155	}
156
157
158	#define RW_PA_DOUT 0x00
159	#define R_PA_DIN 0x01
160	#define RW_PA_OE 0x02
161	#define RW_PD_DOUT 0x10
162	#define R_PD_DIN 0x11
163	#define RW_PD_OE 0x12
164
165	static struct gpio_state_t
10c144e2 EI	166	{
10c144e2 EI	167	struct nand_state_t *nand;
4a1e6bea	168	struct tempsensor_t tempsensor;
10c144e2 EI	169	uint32_t regs[0x5c / 4];
	170	} gpio_state;
	171
c227f099	172	static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
10c144e2 EI	173	{
	174	struct gpio_state_t *s = opaque;
	175	uint32_t r = 0;
	176
	177	addr >>= 2;
	178	switch (addr)
	179	{
	180	case R_PA_DIN:
	181	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	182
	183	/* Encode pins from the nand. */
	184	r \|= s->nand->rdy << 7;
	185	break;
4a1e6bea EI	186	case R_PD_DIN:
	187	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	188
	189	/* Encode temp sensor pins. */
	190	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	191	break;
	192
10c144e2 EI	193	default:
	194	r = s->regs[addr];
	195	break;
	196	}
	197	return r;
	198	D(printf("%s %x=%x\n", __func__, addr, r));
	199	}
	200
c227f099	201	static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
10c144e2 EI	202	{
	203	struct gpio_state_t *s = opaque;
	204	D(printf("%s %x=%x\n", __func__, addr, value));
	205
	206	addr >>= 2;
	207	switch (addr)
	208	{
	209	case RW_PA_DOUT:
	210	/* Decode nand pins. */
	211	s->nand->ale = !!(value & (1 << 6));
	212	s->nand->cle = !!(value & (1 << 5));
	213	s->nand->ce = !!(value & (1 << 4));
	214
	215	s->regs[addr] = value;
	216	break;
4a1e6bea EI	217
	218	case RW_PD_DOUT:
	219	/* Temp sensor clk. */
	220	if ((s->regs[addr] ^ value) & 2)
	221	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	222	!!(value & 16));
	223	s->regs[addr] = value;
	224	break;
	225
10c144e2 EI	226	default:
	227	s->regs[addr] = value;
	228	break;
	229	}
	230	}
	231
d60efc6b	232	static CPUReadMemoryFunc * const gpio_read[] = {
10c144e2 EI	233	NULL, NULL,
	234	&gpio_readl,
	235	};
	236
d60efc6b	237	static CPUWriteMemoryFunc * const gpio_write[] = {
10c144e2 EI	238	NULL, NULL,
	239	&gpio_writel,
	240	};
	241
	242	#define INTMEM_SIZE (128 * 1024)
	243
77d4f95e	244	static struct cris_load_info li;
409dbce5	245
10c144e2	246	static
c227f099	247	void axisdev88_init (ram_addr_t ram_size,
ef998233	248	const char *boot_device,
10c144e2 EI	249	const char kernel_filename, const char kernel_cmdline,
	250	const char initrd_filename, const char cpu_model)
	251	{
	252	CPUState *env;
fd6dc90b EI	253	DeviceState *dev;
fd6dc90b EI	254	SysBusDevice *s;
522f253c	255	DriveInfo *nand;
fd6dc90b	256	qemu_irq irq[30], nmi[2], *cpu_irq;
10c144e2	257	void *etraxfs_dmac;
1da005b3	258	struct etraxfs_dma_client *dma_eth;
10c144e2 EI	259	int i;
	260	int nand_regs;
	261	int gpio_regs;
01e0451a AL	262	ram_addr_t phys_ram;
01e0451a AL	263	ram_addr_t phys_intmem;
10c144e2 EI	264
	265	/* init CPUs */
	266	if (cpu_model == NULL) {
	267	cpu_model = "crisv32";
	268	}
	269	env = cpu_init(cpu_model);
10c144e2 EI	270
10c144e2 EI	271	/* allocate RAM */
01e0451a AL	272	phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
01e0451a AL	273	cpu_register_physical_memory(0x40000000, ram_size, phys_ram \| IO_MEM_RAM);
10c144e2 EI	274
	275	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	276	internal memory. */
01e0451a AL	277	phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
	278	cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
	279	phys_intmem \| IO_MEM_RAM);
	280
10c144e2 EI	281
10c144e2 EI	282	/* Attach a NAND flash to CS1. */
522f253c PM	283	nand = drive_get(IF_MTD, 0, 0);
	284	nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
	285	NAND_MFR_STMICRO, 0x39);
2507c12a AG	286	nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
2507c12a AG	287	DEVICE_NATIVE_ENDIAN);
10c144e2 EI	288	cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
	289
	290	gpio_state.nand = &nand_state;
2507c12a AG	291	gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
2507c12a AG	292	DEVICE_NATIVE_ENDIAN);
4a1e6bea	293	cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
10c144e2 EI	294
10c144e2 EI	295
fd6dc90b EI	296	cpu_irq = cris_pic_init_cpu(env);
	297	dev = qdev_create(NULL, "etraxfs,pic");
	298	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	299	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	300	qdev_init_nofail(dev);
fd6dc90b EI	301	s = sysbus_from_qdev(dev);
	302	sysbus_mmio_map(s, 0, 0x3001c000);
	303	sysbus_connect_irq(s, 0, cpu_irq[0]);
	304	sysbus_connect_irq(s, 1, cpu_irq[1]);
	305	for (i = 0; i < 30; i++) {
067a3ddc	306	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	307	}
067a3ddc PB	308	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	309	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	310
ba494313	311	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	312	for (i = 0; i < 10; i++) {
10c144e2 EI	313	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	314	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	315	}
	316
	317	/* Add the two ethernet blocks. */
7267c094	318	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	319	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	320	if (nb_nics > 1) {
	321	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	322	}
10c144e2 EI	323
10c144e2 EI	324	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	325	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	326	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	327	if (nb_nics > 1) {
	328	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	329	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	330	}
	331
	332	/* 2 timers. */
3b1fd90e EI	333	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	334	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	335
10c144e2 EI	336	for (i = 0; i < 4; i++) {
4b816985	337	sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
3b1fd90e	338	irq[0x14 + i]);
10c144e2 EI	339	}
10c144e2 EI	340
77d4f95e EI	341	if (!kernel_filename) {
	342	fprintf(stderr, "Kernel image must be specified\n");
	343	exit(1);
10c144e2	344	}
77d4f95e EI	345
	346	li.image_filename = kernel_filename;
	347	li.cmdline = kernel_cmdline;
	348	cris_load_image(env, &li);
10c144e2 EI	349	}
10c144e2 EI	350
f80f9ec9	351	static QEMUMachine axisdev88_machine = {
10c144e2 EI	352	.name = "axis-dev88",
	353	.desc = "AXIS devboard 88",
	354	.init = axisdev88_init,
bbea04df	355	.is_default = 1,
10c144e2	356	};
f80f9ec9 AL	357
	358	static void axisdev88_machine_init(void)
	359	{
	360	qemu_register_machine(&axisdev88_machine);
	361	}
	362
	363	machine_init(axisdev88_machine_init);