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d0f7453d HC |
1 | /* |
2 | * bonito north bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | */ | |
9 | ||
10 | /* | |
11 | * fulong 2e mini pc has a bonito north bridge. | |
12 | */ | |
13 | ||
14 | /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? | |
15 | * | |
16 | * devfn pci_slot<<3 + funno | |
17 | * one pci bus can have 32 devices and each device can have 8 functions. | |
18 | * | |
19 | * In bonito north bridge, pci slot = IDSEL bit - 12. | |
20 | * For example, PCI_IDSEL_VIA686B = 17, | |
21 | * pci slot = 17-12=5 | |
22 | * | |
23 | * so | |
24 | * VT686B_FUN0's devfn = (5<<3)+0 | |
25 | * VT686B_FUN1's devfn = (5<<3)+1 | |
26 | * | |
27 | * qemu also uses pci address for north bridge to access pci config register. | |
28 | * bus_no [23:16] | |
29 | * dev_no [15:11] | |
30 | * fun_no [10:8] | |
31 | * reg_no [7:2] | |
32 | * | |
33 | * so function bonito_sbridge_pciaddr for the translation from | |
34 | * north bridge address to pci address. | |
35 | */ | |
36 | ||
37 | #include <assert.h> | |
38 | ||
39 | #include "hw.h" | |
40 | #include "pci.h" | |
41 | #include "pc.h" | |
42 | #include "mips.h" | |
43 | #include "pci_host.h" | |
44 | #include "sysemu.h" | |
1e39101c | 45 | #include "exec-memory.h" |
d0f7453d HC |
46 | |
47 | //#define DEBUG_BONITO | |
48 | ||
49 | #ifdef DEBUG_BONITO | |
50 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
51 | #else | |
52 | #define DPRINTF(fmt, ...) | |
53 | #endif | |
54 | ||
55 | /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ | |
56 | #define BONITO_BOOT_BASE 0x1fc00000 | |
57 | #define BONITO_BOOT_SIZE 0x00100000 | |
58 | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) | |
59 | #define BONITO_FLASH_BASE 0x1c000000 | |
60 | #define BONITO_FLASH_SIZE 0x03000000 | |
61 | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) | |
62 | #define BONITO_SOCKET_BASE 0x1f800000 | |
63 | #define BONITO_SOCKET_SIZE 0x00400000 | |
64 | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) | |
65 | #define BONITO_REG_BASE 0x1fe00000 | |
66 | #define BONITO_REG_SIZE 0x00040000 | |
67 | #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) | |
68 | #define BONITO_DEV_BASE 0x1ff00000 | |
69 | #define BONITO_DEV_SIZE 0x00100000 | |
70 | #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) | |
71 | #define BONITO_PCILO_BASE 0x10000000 | |
72 | #define BONITO_PCILO_BASE_VA 0xb0000000 | |
73 | #define BONITO_PCILO_SIZE 0x0c000000 | |
74 | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) | |
75 | #define BONITO_PCILO0_BASE 0x10000000 | |
76 | #define BONITO_PCILO1_BASE 0x14000000 | |
77 | #define BONITO_PCILO2_BASE 0x18000000 | |
78 | #define BONITO_PCIHI_BASE 0x20000000 | |
79 | #define BONITO_PCIHI_SIZE 0x20000000 | |
80 | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) | |
81 | #define BONITO_PCIIO_BASE 0x1fd00000 | |
82 | #define BONITO_PCIIO_BASE_VA 0xbfd00000 | |
83 | #define BONITO_PCIIO_SIZE 0x00010000 | |
84 | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) | |
85 | #define BONITO_PCICFG_BASE 0x1fe80000 | |
86 | #define BONITO_PCICFG_SIZE 0x00080000 | |
87 | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) | |
88 | ||
89 | ||
90 | #define BONITO_PCICONFIGBASE 0x00 | |
91 | #define BONITO_REGBASE 0x100 | |
92 | ||
93 | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) | |
94 | #define BONITO_PCICONFIG_SIZE (0x100) | |
95 | ||
96 | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) | |
97 | #define BONITO_INTERNAL_REG_SIZE (0x70) | |
98 | ||
99 | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) | |
100 | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) | |
101 | ||
102 | ||
103 | ||
104 | /* 1. Bonito h/w Configuration */ | |
105 | /* Power on register */ | |
106 | ||
107 | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ | |
108 | #define BONITO_BONGENCFG_OFFSET 0x4 | |
109 | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ | |
110 | ||
111 | /* 2. IO & IDE configuration */ | |
112 | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ | |
113 | ||
114 | /* 3. IO & IDE configuration */ | |
115 | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ | |
116 | ||
117 | /* 4. PCI address map control */ | |
118 | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ | |
119 | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ | |
120 | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ | |
121 | ||
122 | /* 5. ICU & GPIO regs */ | |
123 | /* GPIO Regs - r/w */ | |
124 | #define BONITO_GPIODATA_OFFSET 0x1c | |
125 | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ | |
126 | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ | |
127 | ||
128 | /* ICU Configuration Regs - r/w */ | |
129 | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ | |
130 | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ | |
131 | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ | |
132 | ||
133 | /* ICU Enable Regs - IntEn & IntISR are r/o. */ | |
134 | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ | |
135 | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ | |
136 | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ | |
137 | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ | |
138 | ||
139 | /* PCI mail boxes */ | |
140 | #define BONITO_PCIMAIL0_OFFSET 0x40 | |
141 | #define BONITO_PCIMAIL1_OFFSET 0x44 | |
142 | #define BONITO_PCIMAIL2_OFFSET 0x48 | |
143 | #define BONITO_PCIMAIL3_OFFSET 0x4c | |
144 | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ | |
145 | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ | |
146 | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ | |
147 | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ | |
148 | ||
149 | /* 6. PCI cache */ | |
150 | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ | |
151 | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ | |
152 | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ | |
153 | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ | |
154 | ||
155 | /* 7. other*/ | |
156 | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ | |
157 | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ | |
158 | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ | |
159 | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ | |
160 | ||
161 | #define BONITO_REGS (0x70 >> 2) | |
162 | ||
163 | /* PCI config for south bridge. type 0 */ | |
164 | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ | |
165 | #define BONITO_PCICONF_IDSEL_OFFSET 11 | |
166 | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ | |
167 | #define BONITO_PCICONF_FUN_OFFSET 8 | |
168 | #define BONITO_PCICONF_REG_MASK 0xFC | |
169 | #define BONITO_PCICONF_REG_OFFSET 0 | |
170 | ||
171 | ||
172 | /* idsel BIT = pci slot number +12 */ | |
173 | #define PCI_SLOT_BASE 12 | |
174 | #define PCI_IDSEL_VIA686B_BIT (17) | |
175 | #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) | |
176 | ||
177 | #define PCI_ADDR(busno,devno,funno,regno) \ | |
178 | ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) | |
179 | ||
180 | typedef PCIHostState BonitoState; | |
181 | ||
182 | typedef struct PCIBonitoState | |
183 | { | |
184 | PCIDevice dev; | |
185 | BonitoState *pcihost; | |
186 | uint32_t regs[BONITO_REGS]; | |
187 | ||
188 | struct bonldma { | |
189 | uint32_t ldmactrl; | |
190 | uint32_t ldmastat; | |
191 | uint32_t ldmaaddr; | |
192 | uint32_t ldmago; | |
193 | } bonldma; | |
194 | ||
195 | /* Based at 1fe00300, bonito Copier */ | |
196 | struct boncop { | |
197 | uint32_t copctrl; | |
198 | uint32_t copstat; | |
199 | uint32_t coppaddr; | |
200 | uint32_t copgo; | |
201 | } boncop; | |
202 | ||
203 | /* Bonito registers */ | |
89200979 | 204 | MemoryRegion iomem; |
d0f7453d | 205 | |
d0f7453d HC |
206 | target_phys_addr_t bonito_spciconf_start; |
207 | target_phys_addr_t bonito_spciconf_length; | |
208 | int bonito_spciconf_handle; | |
209 | ||
210 | target_phys_addr_t bonito_pciio_start; | |
211 | target_phys_addr_t bonito_pciio_length; | |
212 | int bonito_pciio_handle; | |
213 | ||
214 | target_phys_addr_t bonito_localio_start; | |
215 | target_phys_addr_t bonito_localio_length; | |
216 | int bonito_localio_handle; | |
217 | ||
218 | target_phys_addr_t bonito_ldma_start; | |
219 | target_phys_addr_t bonito_ldma_length; | |
220 | int bonito_ldma_handle; | |
221 | ||
222 | target_phys_addr_t bonito_cop_start; | |
223 | target_phys_addr_t bonito_cop_length; | |
224 | int bonito_cop_handle; | |
225 | ||
226 | } PCIBonitoState; | |
227 | ||
228 | PCIBonitoState * bonito_state; | |
229 | ||
89200979 BC |
230 | static void bonito_writel(void *opaque, target_phys_addr_t addr, |
231 | uint64_t val, unsigned size) | |
d0f7453d HC |
232 | { |
233 | PCIBonitoState *s = opaque; | |
234 | uint32_t saddr; | |
235 | int reset = 0; | |
236 | ||
237 | saddr = (addr - BONITO_REGBASE) >> 2; | |
238 | ||
b2bedb21 | 239 | DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); |
d0f7453d HC |
240 | switch (saddr) { |
241 | case BONITO_BONPONCFG: | |
242 | case BONITO_IODEVCFG: | |
243 | case BONITO_SDCFG: | |
244 | case BONITO_PCIMAP: | |
245 | case BONITO_PCIMEMBASECFG: | |
246 | case BONITO_PCIMAP_CFG: | |
247 | case BONITO_GPIODATA: | |
248 | case BONITO_GPIOIE: | |
249 | case BONITO_INTEDGE: | |
250 | case BONITO_INTSTEER: | |
251 | case BONITO_INTPOL: | |
252 | case BONITO_PCIMAIL0: | |
253 | case BONITO_PCIMAIL1: | |
254 | case BONITO_PCIMAIL2: | |
255 | case BONITO_PCIMAIL3: | |
256 | case BONITO_PCICACHECTRL: | |
257 | case BONITO_PCICACHETAG: | |
258 | case BONITO_PCIBADADDR: | |
259 | case BONITO_PCIMSTAT: | |
260 | case BONITO_TIMECFG: | |
261 | case BONITO_CPUCFG: | |
262 | case BONITO_DQCFG: | |
263 | case BONITO_MEMSIZE: | |
264 | s->regs[saddr] = val; | |
265 | break; | |
266 | case BONITO_BONGENCFG: | |
267 | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { | |
268 | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ | |
269 | } | |
270 | s->regs[saddr] = val; | |
271 | if (reset) { | |
272 | qemu_system_reset_request(); | |
273 | } | |
274 | break; | |
275 | case BONITO_INTENSET: | |
276 | s->regs[BONITO_INTENSET] = val; | |
277 | s->regs[BONITO_INTEN] |= val; | |
278 | break; | |
279 | case BONITO_INTENCLR: | |
280 | s->regs[BONITO_INTENCLR] = val; | |
281 | s->regs[BONITO_INTEN] &= ~val; | |
282 | break; | |
283 | case BONITO_INTEN: | |
284 | case BONITO_INTISR: | |
b2bedb21 | 285 | DPRINTF("write to readonly bonito register %x\n", saddr); |
d0f7453d HC |
286 | break; |
287 | default: | |
b2bedb21 | 288 | DPRINTF("write to unknown bonito register %x\n", saddr); |
d0f7453d HC |
289 | break; |
290 | } | |
291 | } | |
292 | ||
89200979 BC |
293 | static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr, |
294 | unsigned size) | |
d0f7453d HC |
295 | { |
296 | PCIBonitoState *s = opaque; | |
297 | uint32_t saddr; | |
298 | ||
299 | saddr = (addr - BONITO_REGBASE) >> 2; | |
300 | ||
b2bedb21 | 301 | DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
302 | switch (saddr) { |
303 | case BONITO_INTISR: | |
304 | return s->regs[saddr]; | |
305 | default: | |
306 | return s->regs[saddr]; | |
307 | } | |
308 | } | |
309 | ||
89200979 BC |
310 | static const MemoryRegionOps bonito_ops = { |
311 | .read = bonito_readl, | |
312 | .write = bonito_writel, | |
313 | .endianness = DEVICE_NATIVE_ENDIAN, | |
314 | .valid = { | |
315 | .min_access_size = 4, | |
316 | .max_access_size = 4, | |
317 | }, | |
d0f7453d HC |
318 | }; |
319 | ||
320 | static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, | |
183e1d40 | 321 | uint64_t val, unsigned size) |
d0f7453d HC |
322 | { |
323 | PCIBonitoState *s = opaque; | |
324 | ||
b2bedb21 | 325 | DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
d0f7453d HC |
326 | s->dev.config_write(&s->dev, addr, val, 4); |
327 | } | |
328 | ||
183e1d40 BC |
329 | static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr, |
330 | unsigned size) | |
d0f7453d HC |
331 | { |
332 | ||
333 | PCIBonitoState *s = opaque; | |
334 | ||
335 | DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); | |
336 | return s->dev.config_read(&s->dev, addr, 4); | |
337 | } | |
338 | ||
339 | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ | |
d0f7453d | 340 | |
183e1d40 BC |
341 | static const MemoryRegionOps bonito_pciconf_ops = { |
342 | .read = bonito_pciconf_readl, | |
343 | .write = bonito_pciconf_writel, | |
344 | .endianness = DEVICE_NATIVE_ENDIAN, | |
345 | .valid = { | |
346 | .min_access_size = 4, | |
347 | .max_access_size = 4, | |
348 | }, | |
d0f7453d HC |
349 | }; |
350 | ||
351 | static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr) | |
352 | { | |
353 | uint32_t val; | |
354 | PCIBonitoState *s = opaque; | |
355 | ||
356 | val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; | |
357 | ||
358 | return val; | |
359 | } | |
360 | ||
361 | static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr, | |
362 | uint32_t val) | |
363 | { | |
364 | PCIBonitoState *s = opaque; | |
365 | ||
366 | ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; | |
367 | } | |
368 | ||
369 | static CPUWriteMemoryFunc * const bonito_ldma_write[] = { | |
370 | NULL, | |
371 | NULL, | |
372 | bonito_ldma_writel, | |
373 | }; | |
374 | ||
375 | static CPUReadMemoryFunc * const bonito_ldma_read[] = { | |
376 | NULL, | |
377 | NULL, | |
378 | bonito_ldma_readl, | |
379 | }; | |
380 | ||
381 | static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr) | |
382 | { | |
383 | uint32_t val; | |
384 | PCIBonitoState *s = opaque; | |
385 | ||
386 | val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; | |
387 | ||
388 | return val; | |
389 | } | |
390 | ||
391 | static void bonito_cop_writel(void *opaque, target_phys_addr_t addr, | |
392 | uint32_t val) | |
393 | { | |
394 | PCIBonitoState *s = opaque; | |
395 | ||
396 | ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; | |
397 | } | |
398 | ||
399 | static CPUWriteMemoryFunc * const bonito_cop_write[] = { | |
400 | NULL, | |
401 | NULL, | |
402 | bonito_cop_writel, | |
403 | }; | |
404 | ||
405 | static CPUReadMemoryFunc * const bonito_cop_read[] = { | |
406 | NULL, | |
407 | NULL, | |
408 | bonito_cop_readl, | |
409 | }; | |
410 | ||
411 | static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) | |
412 | { | |
413 | PCIBonitoState *s = opaque; | |
414 | uint32_t cfgaddr; | |
415 | uint32_t idsel; | |
416 | uint32_t devno; | |
417 | uint32_t funno; | |
418 | uint32_t regno; | |
419 | uint32_t pciaddr; | |
420 | ||
421 | /* support type0 pci config */ | |
422 | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { | |
423 | return 0xffffffff; | |
424 | } | |
425 | ||
426 | cfgaddr = addr & 0xffff; | |
427 | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; | |
428 | ||
429 | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; | |
430 | devno = ffs(idsel) - 1; | |
431 | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; | |
432 | regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; | |
433 | ||
434 | if (idsel == 0) { | |
435 | fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx | |
436 | ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); | |
437 | exit(1); | |
438 | } | |
439 | pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno); | |
b2bedb21 | 440 | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", |
d0f7453d HC |
441 | cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno); |
442 | ||
443 | return pciaddr; | |
444 | } | |
445 | ||
446 | static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr, | |
447 | uint32_t val) | |
448 | { | |
449 | PCIBonitoState *s = opaque; | |
450 | uint32_t pciaddr; | |
451 | uint16_t status; | |
452 | ||
b2bedb21 | 453 | DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); |
d0f7453d HC |
454 | pciaddr = bonito_sbridge_pciaddr(s, addr); |
455 | ||
456 | if (pciaddr == 0xffffffff) { | |
457 | return; | |
458 | } | |
459 | ||
460 | /* set the pci address in s->config_reg */ | |
461 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
462 | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1); | |
463 | ||
464 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
465 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
466 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
467 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
468 | } | |
469 | ||
470 | static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr, | |
471 | uint32_t val) | |
472 | { | |
473 | PCIBonitoState *s = opaque; | |
474 | uint32_t pciaddr; | |
475 | uint16_t status; | |
476 | ||
b2bedb21 | 477 | DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); |
d0f7453d HC |
478 | assert((addr&0x1)==0); |
479 | ||
480 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
481 | ||
482 | if (pciaddr == 0xffffffff) { | |
483 | return; | |
484 | } | |
485 | ||
486 | /* set the pci address in s->config_reg */ | |
487 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
488 | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2); | |
489 | ||
490 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
491 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
492 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
493 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
494 | } | |
495 | ||
496 | static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, | |
497 | uint32_t val) | |
498 | { | |
499 | PCIBonitoState *s = opaque; | |
500 | uint32_t pciaddr; | |
501 | uint16_t status; | |
502 | ||
b2bedb21 | 503 | DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
d0f7453d HC |
504 | assert((addr&0x3)==0); |
505 | ||
506 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
507 | ||
508 | if (pciaddr == 0xffffffff) { | |
509 | return; | |
510 | } | |
511 | ||
512 | /* set the pci address in s->config_reg */ | |
513 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
514 | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4); | |
515 | ||
516 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
517 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
518 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
519 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
520 | } | |
521 | ||
522 | static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr) | |
523 | { | |
524 | PCIBonitoState *s = opaque; | |
525 | uint32_t pciaddr; | |
526 | uint16_t status; | |
527 | ||
b2bedb21 | 528 | DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
529 | pciaddr = bonito_sbridge_pciaddr(s, addr); |
530 | ||
531 | if (pciaddr == 0xffffffff) { | |
532 | return 0xff; | |
533 | } | |
534 | ||
535 | /* set the pci address in s->config_reg */ | |
536 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
537 | ||
538 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
539 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
540 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
541 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
542 | ||
543 | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1); | |
544 | } | |
545 | ||
546 | static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr) | |
547 | { | |
548 | PCIBonitoState *s = opaque; | |
549 | uint32_t pciaddr; | |
550 | uint16_t status; | |
551 | ||
b2bedb21 | 552 | DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
553 | assert((addr&0x1)==0); |
554 | ||
555 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
556 | ||
557 | if (pciaddr == 0xffffffff) { | |
558 | return 0xffff; | |
559 | } | |
560 | ||
561 | /* set the pci address in s->config_reg */ | |
562 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
563 | ||
564 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
565 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
566 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
567 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
568 | ||
569 | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2); | |
570 | } | |
571 | ||
572 | static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) | |
573 | { | |
574 | PCIBonitoState *s = opaque; | |
575 | uint32_t pciaddr; | |
576 | uint16_t status; | |
577 | ||
b2bedb21 | 578 | DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
579 | assert((addr&0x3) == 0); |
580 | ||
581 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
582 | ||
583 | if (pciaddr == 0xffffffff) { | |
584 | return 0xffffffff; | |
585 | } | |
586 | ||
587 | /* set the pci address in s->config_reg */ | |
588 | s->pcihost->config_reg = (pciaddr) | (1u << 31); | |
589 | ||
590 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
591 | status = pci_get_word(s->dev.config + PCI_STATUS); | |
592 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); | |
593 | pci_set_word(s->dev.config + PCI_STATUS, status); | |
594 | ||
595 | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4); | |
596 | } | |
597 | ||
598 | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ | |
599 | static CPUWriteMemoryFunc * const bonito_spciconf_write[] = { | |
600 | bonito_spciconf_writeb, | |
601 | bonito_spciconf_writew, | |
602 | bonito_spciconf_writel, | |
603 | }; | |
604 | ||
605 | static CPUReadMemoryFunc * const bonito_spciconf_read[] = { | |
606 | bonito_spciconf_readb, | |
607 | bonito_spciconf_readw, | |
608 | bonito_spciconf_readl, | |
609 | }; | |
610 | ||
611 | #define BONITO_IRQ_BASE 32 | |
612 | ||
613 | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) | |
614 | { | |
615 | qemu_irq *pic = opaque; | |
616 | int internal_irq = irq_num - BONITO_IRQ_BASE; | |
617 | ||
618 | if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) { | |
619 | qemu_irq_pulse(*pic); | |
620 | } else { /* level triggered */ | |
621 | if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) { | |
622 | qemu_irq_raise(*pic); | |
623 | } else { | |
624 | qemu_irq_lower(*pic); | |
625 | } | |
626 | } | |
627 | } | |
628 | ||
629 | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ | |
630 | static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) | |
631 | { | |
632 | int slot; | |
633 | ||
634 | slot = (pci_dev->devfn >> 3); | |
635 | ||
636 | switch (slot) { | |
637 | case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ | |
638 | return irq_num % 4 + BONITO_IRQ_BASE; | |
639 | case 6: /* FULONG2E_ATI_SLOT, VGA */ | |
640 | return 4 + BONITO_IRQ_BASE; | |
641 | case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ | |
642 | return 5 + BONITO_IRQ_BASE; | |
643 | case 8 ... 12: /* PCI slot 1 to 4 */ | |
644 | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; | |
645 | default: /* Unknown device, don't do any translation */ | |
646 | return irq_num; | |
647 | } | |
648 | } | |
649 | ||
650 | static void bonito_reset(void *opaque) | |
651 | { | |
652 | PCIBonitoState *s = opaque; | |
653 | ||
654 | /* set the default value of north bridge registers */ | |
655 | ||
656 | s->regs[BONITO_BONPONCFG] = 0xc40; | |
657 | s->regs[BONITO_BONGENCFG] = 0x1384; | |
658 | s->regs[BONITO_IODEVCFG] = 0x2bff8010; | |
659 | s->regs[BONITO_SDCFG] = 0x255e0091; | |
660 | ||
661 | s->regs[BONITO_GPIODATA] = 0x1ff; | |
662 | s->regs[BONITO_GPIOIE] = 0x1ff; | |
663 | s->regs[BONITO_DQCFG] = 0x8; | |
664 | s->regs[BONITO_MEMSIZE] = 0x10000000; | |
665 | s->regs[BONITO_PCIMAP] = 0x6140; | |
666 | } | |
667 | ||
668 | static const VMStateDescription vmstate_bonito = { | |
669 | .name = "Bonito", | |
670 | .version_id = 1, | |
671 | .minimum_version_id = 1, | |
672 | .minimum_version_id_old = 1, | |
673 | .fields = (VMStateField []) { | |
674 | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), | |
675 | VMSTATE_END_OF_LIST() | |
676 | } | |
677 | }; | |
678 | ||
679 | static int bonito_pcihost_initfn(SysBusDevice *dev) | |
680 | { | |
681 | return 0; | |
682 | } | |
683 | ||
684 | static int bonito_initfn(PCIDevice *dev) | |
685 | { | |
686 | PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); | |
89200979 | 687 | SysBusDevice *sysbus = &s->pcihost->busdev; |
d0f7453d HC |
688 | |
689 | /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ | |
d0f7453d | 690 | pci_config_set_prog_interface(dev->config, 0x00); |
d0f7453d HC |
691 | |
692 | /* set the north bridge register mapping */ | |
89200979 BC |
693 | memory_region_init_io(&s->iomem, &bonito_ops, s, |
694 | "north-bridge-register", BONITO_INTERNAL_REG_SIZE); | |
695 | sysbus_init_mmio_region(sysbus, &s->iomem); | |
696 | sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); | |
d0f7453d HC |
697 | |
698 | /* set the north bridge pci configure mapping */ | |
183e1d40 BC |
699 | memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s, |
700 | "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); | |
701 | sysbus_init_mmio_region(sysbus, &s->pcihost->conf_mem); | |
702 | sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); | |
d0f7453d HC |
703 | |
704 | /* set the south bridge pci configure mapping */ | |
705 | s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read, | |
2507c12a AG |
706 | bonito_spciconf_write, s, |
707 | DEVICE_NATIVE_ENDIAN); | |
d0f7453d HC |
708 | s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE; |
709 | s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE; | |
710 | cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length, | |
711 | s->bonito_spciconf_handle); | |
712 | ||
713 | s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read, | |
2507c12a AG |
714 | bonito_ldma_write, s, |
715 | DEVICE_NATIVE_ENDIAN); | |
d0f7453d HC |
716 | s->bonito_ldma_start = 0xbfe00200; |
717 | s->bonito_ldma_length = 0x100; | |
718 | cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length, | |
719 | s->bonito_ldma_handle); | |
720 | ||
721 | s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read, | |
2507c12a AG |
722 | bonito_cop_write, s, |
723 | DEVICE_NATIVE_ENDIAN); | |
d0f7453d HC |
724 | s->bonito_cop_start = 0xbfe00300; |
725 | s->bonito_cop_length = 0x100; | |
726 | cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length, | |
727 | s->bonito_cop_handle); | |
728 | ||
729 | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ | |
730 | s->bonito_pciio_start = BONITO_PCIIO_BASE; | |
731 | s->bonito_pciio_length = BONITO_PCIIO_SIZE; | |
732 | isa_mem_base = s->bonito_pciio_start; | |
968d683c | 733 | isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); |
d0f7453d HC |
734 | |
735 | /* add pci local io mapping */ | |
736 | s->bonito_localio_start = BONITO_DEV_BASE; | |
737 | s->bonito_localio_length = BONITO_DEV_SIZE; | |
968d683c | 738 | isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); |
d0f7453d HC |
739 | |
740 | /* set the default value of north bridge pci config */ | |
741 | pci_set_word(dev->config + PCI_COMMAND, 0x0000); | |
742 | pci_set_word(dev->config + PCI_STATUS, 0x0000); | |
743 | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); | |
744 | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); | |
745 | ||
746 | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); | |
747 | pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); | |
748 | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); | |
749 | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); | |
750 | ||
751 | qemu_register_reset(bonito_reset, s); | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
756 | PCIBus *bonito_init(qemu_irq *pic) | |
757 | { | |
758 | DeviceState *dev; | |
759 | PCIBus *b; | |
760 | BonitoState *pcihost; | |
761 | PCIBonitoState *s; | |
762 | PCIDevice *d; | |
763 | ||
764 | dev = qdev_create(NULL, "Bonito-pcihost"); | |
765 | pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); | |
766 | b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq, | |
1e39101c | 767 | pci_bonito_map_irq, pic, get_system_memory(), |
aee97b84 | 768 | get_system_io(), |
1e39101c | 769 | 0x28, 32); |
d0f7453d HC |
770 | pcihost->bus = b; |
771 | qdev_init_nofail(dev); | |
d0f7453d | 772 | |
89200979 BC |
773 | /* set the pcihost pointer before bonito_initfn is called */ |
774 | d = pci_create(b, PCI_DEVFN(0, 0), "Bonito"); | |
d0f7453d HC |
775 | s = DO_UPCAST(PCIBonitoState, dev, d); |
776 | s->pcihost = pcihost; | |
777 | bonito_state = s; | |
89200979 | 778 | qdev_init_nofail(&d->qdev); |
d0f7453d HC |
779 | |
780 | return b; | |
781 | } | |
782 | ||
783 | static PCIDeviceInfo bonito_info = { | |
784 | .qdev.name = "Bonito", | |
785 | .qdev.desc = "Host bridge", | |
786 | .qdev.size = sizeof(PCIBonitoState), | |
787 | .qdev.vmsd = &vmstate_bonito, | |
788 | .qdev.no_user = 1, | |
789 | .init = bonito_initfn, | |
51387f86 IY |
790 | /*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/ |
791 | .vendor_id = 0xdf53, | |
792 | .device_id = 0x00d5, | |
793 | .revision = 0x01, | |
794 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
d0f7453d HC |
795 | }; |
796 | ||
797 | static SysBusDeviceInfo bonito_pcihost_info = { | |
798 | .init = bonito_pcihost_initfn, | |
799 | .qdev.name = "Bonito-pcihost", | |
800 | .qdev.size = sizeof(BonitoState), | |
801 | .qdev.no_user = 1, | |
802 | }; | |
803 | ||
804 | static void bonito_register(void) | |
805 | { | |
806 | sysbus_register_withprop(&bonito_pcihost_info); | |
807 | pci_qdev_register(&bonito_info); | |
808 | } | |
809 | device_init(bonito_register); |