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sysbus: remove sysbus_init_mmio()
[qemu.git] / hw / bonito.c
CommitLineData
d0f7453d
HC		 1/*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
10/*
11 * fulong 2e mini pc has a bonito north bridge.
12 */
13
14/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
15 *
16 * devfn pci_slot<<3 + funno
17 * one pci bus can have 32 devices and each device can have 8 functions.
18 *
19 * In bonito north bridge, pci slot = IDSEL bit - 12.
20 * For example, PCI_IDSEL_VIA686B = 17,
21 * pci slot = 17-12=5
22 *
23 * so
24 * VT686B_FUN0's devfn = (5<<3)+0
25 * VT686B_FUN1's devfn = (5<<3)+1
26 *
27 * qemu also uses pci address for north bridge to access pci config register.
28 * bus_no [23:16]
29 * dev_no [15:11]
30 * fun_no [10:8]
31 * reg_no [7:2]
32 *
33 * so function bonito_sbridge_pciaddr for the translation from
34 * north bridge address to pci address.
35 */
36
37#include <assert.h>
38
39#include "hw.h"
40#include "pci.h"
41#include "pc.h"
42#include "mips.h"
43#include "pci_host.h"
44#include "sysemu.h"
1e39101c 45#include "exec-memory.h"
d0f7453d
HC		 46
47//#define DEBUG_BONITO
48
49#ifdef DEBUG_BONITO
50#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
51#else
52#define DPRINTF(fmt, ...)
53#endif
54
55/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
56#define BONITO_BOOT_BASE 0x1fc00000
57#define BONITO_BOOT_SIZE 0x00100000
58#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
59#define BONITO_FLASH_BASE 0x1c000000
60#define BONITO_FLASH_SIZE 0x03000000
61#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
62#define BONITO_SOCKET_BASE 0x1f800000
63#define BONITO_SOCKET_SIZE 0x00400000
64#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
65#define BONITO_REG_BASE 0x1fe00000
66#define BONITO_REG_SIZE 0x00040000
67#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
68#define BONITO_DEV_BASE 0x1ff00000
69#define BONITO_DEV_SIZE 0x00100000
70#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
71#define BONITO_PCILO_BASE 0x10000000
72#define BONITO_PCILO_BASE_VA 0xb0000000
73#define BONITO_PCILO_SIZE 0x0c000000
74#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
75#define BONITO_PCILO0_BASE 0x10000000
76#define BONITO_PCILO1_BASE 0x14000000
77#define BONITO_PCILO2_BASE 0x18000000
78#define BONITO_PCIHI_BASE 0x20000000
79#define BONITO_PCIHI_SIZE 0x20000000
80#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
81#define BONITO_PCIIO_BASE 0x1fd00000
82#define BONITO_PCIIO_BASE_VA 0xbfd00000
83#define BONITO_PCIIO_SIZE 0x00010000
84#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
85#define BONITO_PCICFG_BASE 0x1fe80000
86#define BONITO_PCICFG_SIZE 0x00080000
87#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
88
89
90#define BONITO_PCICONFIGBASE 0x00
91#define BONITO_REGBASE 0x100
92
93#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
94#define BONITO_PCICONFIG_SIZE (0x100)
95
96#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
97#define BONITO_INTERNAL_REG_SIZE (0x70)
98
99#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
100#define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
101
102
103
104/* 1. Bonito h/w Configuration */
105/* Power on register */
106
107#define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
108#define BONITO_BONGENCFG_OFFSET 0x4
109#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */
110
111/* 2. IO & IDE configuration */
112#define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
113
114/* 3. IO & IDE configuration */
115#define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
116
117/* 4. PCI address map control */
118#define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
119#define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
120#define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
121
122/* 5. ICU & GPIO regs */
123/* GPIO Regs - r/w */
124#define BONITO_GPIODATA_OFFSET 0x1c
125#define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
126#define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
127
128/* ICU Configuration Regs - r/w */
129#define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
130#define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
131#define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
132
133/* ICU Enable Regs - IntEn & IntISR are r/o. */
134#define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
135#define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
136#define BONITO_INTEN (0x38 >> 2) /* 0x138 */
137#define BONITO_INTISR (0x3c >> 2) /* 0x13c */
138
139/* PCI mail boxes */
140#define BONITO_PCIMAIL0_OFFSET 0x40
141#define BONITO_PCIMAIL1_OFFSET 0x44
142#define BONITO_PCIMAIL2_OFFSET 0x48
143#define BONITO_PCIMAIL3_OFFSET 0x4c
144#define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
145#define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
146#define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
147#define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
148
149/* 6. PCI cache */
150#define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
151#define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
152#define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
153#define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
154
155/* 7. other*/
156#define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
157#define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
158#define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
159#define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
160
161#define BONITO_REGS (0x70 >> 2)
162
163/* PCI config for south bridge. type 0 */
164#define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
165#define BONITO_PCICONF_IDSEL_OFFSET 11
166#define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
167#define BONITO_PCICONF_FUN_OFFSET 8
168#define BONITO_PCICONF_REG_MASK 0xFC
169#define BONITO_PCICONF_REG_OFFSET 0
170
171
172/* idsel BIT = pci slot number +12 */
173#define PCI_SLOT_BASE 12
174#define PCI_IDSEL_VIA686B_BIT (17)
175#define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT)
176
177#define PCI_ADDR(busno,devno,funno,regno) \
178 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
179
180typedef PCIHostState BonitoState;
181
182typedef struct PCIBonitoState
183{
184 PCIDevice dev;
185 BonitoState *pcihost;
186 uint32_t regs[BONITO_REGS];
187
188 struct bonldma {
189 uint32_t ldmactrl;
190 uint32_t ldmastat;
191 uint32_t ldmaaddr;
192 uint32_t ldmago;
193 } bonldma;
194
195 /* Based at 1fe00300, bonito Copier */
196 struct boncop {
197 uint32_t copctrl;
198 uint32_t copstat;
199 uint32_t coppaddr;
200 uint32_t copgo;
201 } boncop;
202
203 /* Bonito registers */
89200979 204 MemoryRegion iomem;
def344a6 205 MemoryRegion iomem_ldma;
9a542a48 206 MemoryRegion iomem_cop;
d0f7453d 207
d0f7453d
HC		 208 target_phys_addr_t bonito_pciio_start;
209 target_phys_addr_t bonito_pciio_length;
210 int bonito_pciio_handle;
211
212 target_phys_addr_t bonito_localio_start;
213 target_phys_addr_t bonito_localio_length;
214 int bonito_localio_handle;
215
d0f7453d
HC		 216} PCIBonitoState;
217
218PCIBonitoState * bonito_state;
219
89200979
BC		 220static void bonito_writel(void *opaque, target_phys_addr_t addr,
221 uint64_t val, unsigned size)
d0f7453d
HC		 222{
223 PCIBonitoState *s = opaque;
224 uint32_t saddr;
225 int reset = 0;
226
227 saddr = (addr - BONITO_REGBASE) >> 2;
228
b2bedb21 229 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
d0f7453d
HC		 230 switch (saddr) {
231 case BONITO_BONPONCFG:
232 case BONITO_IODEVCFG:
233 case BONITO_SDCFG:
234 case BONITO_PCIMAP:
235 case BONITO_PCIMEMBASECFG:
236 case BONITO_PCIMAP_CFG:
237 case BONITO_GPIODATA:
238 case BONITO_GPIOIE:
239 case BONITO_INTEDGE:
240 case BONITO_INTSTEER:
241 case BONITO_INTPOL:
242 case BONITO_PCIMAIL0:
243 case BONITO_PCIMAIL1:
244 case BONITO_PCIMAIL2:
245 case BONITO_PCIMAIL3:
246 case BONITO_PCICACHECTRL:
247 case BONITO_PCICACHETAG:
248 case BONITO_PCIBADADDR:
249 case BONITO_PCIMSTAT:
250 case BONITO_TIMECFG:
251 case BONITO_CPUCFG:
252 case BONITO_DQCFG:
253 case BONITO_MEMSIZE:
254 s->regs[saddr] = val;
255 break;
256 case BONITO_BONGENCFG:
257 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
258 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
259 }
260 s->regs[saddr] = val;
261 if (reset) {
262 qemu_system_reset_request();
263 }
264 break;
265 case BONITO_INTENSET:
266 s->regs[BONITO_INTENSET] = val;
267 s->regs[BONITO_INTEN] |= val;
268 break;
269 case BONITO_INTENCLR:
270 s->regs[BONITO_INTENCLR] = val;
271 s->regs[BONITO_INTEN] &= ~val;
272 break;
273 case BONITO_INTEN:
274 case BONITO_INTISR:
b2bedb21 275 DPRINTF("write to readonly bonito register %x\n", saddr);
d0f7453d
HC		 276 break;
277 default:
b2bedb21 278 DPRINTF("write to unknown bonito register %x\n", saddr);
d0f7453d
HC		 279 break;
280 }
281}
282
89200979
BC		 283static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
284 unsigned size)
d0f7453d
HC		 285{
286 PCIBonitoState *s = opaque;
287 uint32_t saddr;
288
289 saddr = (addr - BONITO_REGBASE) >> 2;
290
b2bedb21 291 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
d0f7453d
HC		 292 switch (saddr) {
293 case BONITO_INTISR:
294 return s->regs[saddr];
295 default:
296 return s->regs[saddr];
297 }
298}
299
89200979
BC		 300static const MemoryRegionOps bonito_ops = {
301 .read = bonito_readl,
302 .write = bonito_writel,
303 .endianness = DEVICE_NATIVE_ENDIAN,
304 .valid = {
305 .min_access_size = 4,
306 .max_access_size = 4,
307 },
d0f7453d
HC		 308};
309
310static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
183e1d40 311 uint64_t val, unsigned size)
d0f7453d
HC		 312{
313 PCIBonitoState *s = opaque;
314
b2bedb21 315 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
d0f7453d
HC		 316 s->dev.config_write(&s->dev, addr, val, 4);
317}
318
183e1d40
BC		 319static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
320 unsigned size)
d0f7453d
HC		 321{
322
323 PCIBonitoState *s = opaque;
324
325 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
326 return s->dev.config_read(&s->dev, addr, 4);
327}
328
329/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
d0f7453d 330
183e1d40
BC		 331static const MemoryRegionOps bonito_pciconf_ops = {
332 .read = bonito_pciconf_readl,
333 .write = bonito_pciconf_writel,
334 .endianness = DEVICE_NATIVE_ENDIAN,
335 .valid = {
336 .min_access_size = 4,
337 .max_access_size = 4,
338 },
d0f7453d
HC		 339};
340
def344a6
BC		 341static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
342 unsigned size)
d0f7453d
HC		 343{
344 uint32_t val;
345 PCIBonitoState *s = opaque;
346
347 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
348
349 return val;
350}
351
352static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
def344a6 353 uint64_t val, unsigned size)
d0f7453d
HC		 354{
355 PCIBonitoState *s = opaque;
356
357 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
358}
359
def344a6
BC		 360static const MemoryRegionOps bonito_ldma_ops = {
361 .read = bonito_ldma_readl,
362 .write = bonito_ldma_writel,
363 .endianness = DEVICE_NATIVE_ENDIAN,
364 .valid = {
365 .min_access_size = 4,
366 .max_access_size = 4,
367 },
d0f7453d
HC		 368};
369
9a542a48
BC		 370static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
371 unsigned size)
d0f7453d
HC		 372{
373 uint32_t val;
374 PCIBonitoState *s = opaque;
375
376 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
377
378 return val;
379}
380
381static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
9a542a48 382 uint64_t val, unsigned size)
d0f7453d
HC		 383{
384 PCIBonitoState *s = opaque;
385
386 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
387}
388
9a542a48
BC		 389static const MemoryRegionOps bonito_cop_ops = {
390 .read = bonito_cop_readl,
391 .write = bonito_cop_writel,
392 .endianness = DEVICE_NATIVE_ENDIAN,
393 .valid = {
394 .min_access_size = 4,
395 .max_access_size = 4,
396 },
d0f7453d
HC		 397};
398
399static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
400{
401 PCIBonitoState *s = opaque;
402 uint32_t cfgaddr;
403 uint32_t idsel;
404 uint32_t devno;
405 uint32_t funno;
406 uint32_t regno;
407 uint32_t pciaddr;
408
409 /* support type0 pci config */
410 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
411 return 0xffffffff;
412 }
413
414 cfgaddr = addr & 0xffff;
415 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
416
417 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
418 devno = ffs(idsel) - 1;
419 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
420 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
421
422 if (idsel == 0) {
423 fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx
424 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
425 exit(1);
426 }
427 pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
b2bedb21 428 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
d0f7453d
HC		 429 cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
430
431 return pciaddr;
432}
433
434static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
435 uint32_t val)
436{
437 PCIBonitoState *s = opaque;
438 uint32_t pciaddr;
439 uint16_t status;
440
b2bedb21 441 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
d0f7453d
HC		 442 pciaddr = bonito_sbridge_pciaddr(s, addr);
443
444 if (pciaddr == 0xffffffff) {
445 return;
446 }
447
448 /* set the pci address in s->config_reg */
449 s->pcihost->config_reg = (pciaddr) | (1u << 31);
450 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1);
451
452 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
453 status = pci_get_word(s->dev.config + PCI_STATUS);
454 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
455 pci_set_word(s->dev.config + PCI_STATUS, status);
456}
457
458static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
459 uint32_t val)
460{
461 PCIBonitoState *s = opaque;
462 uint32_t pciaddr;
463 uint16_t status;
464
b2bedb21 465 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
d0f7453d
HC		 466 assert((addr&0x1)==0);
467
468 pciaddr = bonito_sbridge_pciaddr(s, addr);
469
470 if (pciaddr == 0xffffffff) {
471 return;
472 }
473
474 /* set the pci address in s->config_reg */
475 s->pcihost->config_reg = (pciaddr) | (1u << 31);
476 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2);
477
478 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
479 status = pci_get_word(s->dev.config + PCI_STATUS);
480 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
481 pci_set_word(s->dev.config + PCI_STATUS, status);
482}
483
484static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
485 uint32_t val)
486{
487 PCIBonitoState *s = opaque;
488 uint32_t pciaddr;
489 uint16_t status;
490
b2bedb21 491 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
d0f7453d
HC		 492 assert((addr&0x3)==0);
493
494 pciaddr = bonito_sbridge_pciaddr(s, addr);
495
496 if (pciaddr == 0xffffffff) {
497 return;
498 }
499
500 /* set the pci address in s->config_reg */
501 s->pcihost->config_reg = (pciaddr) | (1u << 31);
502 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);
503
504 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
505 status = pci_get_word(s->dev.config + PCI_STATUS);
506 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
507 pci_set_word(s->dev.config + PCI_STATUS, status);
508}
509
510static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
511{
512 PCIBonitoState *s = opaque;
513 uint32_t pciaddr;
514 uint16_t status;
515
b2bedb21 516 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
d0f7453d
HC		 517 pciaddr = bonito_sbridge_pciaddr(s, addr);
518
519 if (pciaddr == 0xffffffff) {
520 return 0xff;
521 }
522
523 /* set the pci address in s->config_reg */
524 s->pcihost->config_reg = (pciaddr) | (1u << 31);
525
526 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
527 status = pci_get_word(s->dev.config + PCI_STATUS);
528 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
529 pci_set_word(s->dev.config + PCI_STATUS, status);
530
531 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1);
532}
533
534static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
535{
536 PCIBonitoState *s = opaque;
537 uint32_t pciaddr;
538 uint16_t status;
539
b2bedb21 540 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
d0f7453d
HC		 541 assert((addr&0x1)==0);
542
543 pciaddr = bonito_sbridge_pciaddr(s, addr);
544
545 if (pciaddr == 0xffffffff) {
546 return 0xffff;
547 }
548
549 /* set the pci address in s->config_reg */
550 s->pcihost->config_reg = (pciaddr) | (1u << 31);
551
552 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
553 status = pci_get_word(s->dev.config + PCI_STATUS);
554 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
555 pci_set_word(s->dev.config + PCI_STATUS, status);
556
557 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2);
558}
559
560static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
561{
562 PCIBonitoState *s = opaque;
563 uint32_t pciaddr;
564 uint16_t status;
565
b2bedb21 566 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
d0f7453d
HC		 567 assert((addr&0x3) == 0);
568
569 pciaddr = bonito_sbridge_pciaddr(s, addr);
570
571 if (pciaddr == 0xffffffff) {
572 return 0xffffffff;
573 }
574
575 /* set the pci address in s->config_reg */
576 s->pcihost->config_reg = (pciaddr) | (1u << 31);
577
578 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
579 status = pci_get_word(s->dev.config + PCI_STATUS);
580 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
581 pci_set_word(s->dev.config + PCI_STATUS, status);
582
583 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4);
584}
585
586/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
845cbeb8
BC		 587static const MemoryRegionOps bonito_spciconf_ops = {
588 .old_mmio = {
589 .read = {
590 bonito_spciconf_readb,
591 bonito_spciconf_readw,
592 bonito_spciconf_readl,
593 },
594 .write = {
595 bonito_spciconf_writeb,
596 bonito_spciconf_writew,
597 bonito_spciconf_writel,
598 },
599 },
600 .endianness = DEVICE_NATIVE_ENDIAN,
d0f7453d
HC		 601};
602
603#define BONITO_IRQ_BASE 32
604
605static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
606{
607 qemu_irq *pic = opaque;
608 int internal_irq = irq_num - BONITO_IRQ_BASE;
609
610 if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) {
611 qemu_irq_pulse(*pic);
612 } else { /* level triggered */
613 if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) {
614 qemu_irq_raise(*pic);
615 } else {
616 qemu_irq_lower(*pic);
617 }
618 }
619}
620
621/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
622static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
623{
624 int slot;
625
626 slot = (pci_dev->devfn >> 3);
627
628 switch (slot) {
629 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
630 return irq_num % 4 + BONITO_IRQ_BASE;
631 case 6: /* FULONG2E_ATI_SLOT, VGA */
632 return 4 + BONITO_IRQ_BASE;
633 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */
634 return 5 + BONITO_IRQ_BASE;
635 case 8 ... 12: /* PCI slot 1 to 4 */
636 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
637 default: /* Unknown device, don't do any translation */
638 return irq_num;
639 }
640}
641
642static void bonito_reset(void *opaque)
643{
644 PCIBonitoState *s = opaque;
645
646 /* set the default value of north bridge registers */
647
648 s->regs[BONITO_BONPONCFG] = 0xc40;
649 s->regs[BONITO_BONGENCFG] = 0x1384;
650 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
651 s->regs[BONITO_SDCFG] = 0x255e0091;
652
653 s->regs[BONITO_GPIODATA] = 0x1ff;
654 s->regs[BONITO_GPIOIE] = 0x1ff;
655 s->regs[BONITO_DQCFG] = 0x8;
656 s->regs[BONITO_MEMSIZE] = 0x10000000;
657 s->regs[BONITO_PCIMAP] = 0x6140;
658}
659
660static const VMStateDescription vmstate_bonito = {
661 .name = "Bonito",
662 .version_id = 1,
663 .minimum_version_id = 1,
664 .minimum_version_id_old = 1,
665 .fields = (VMStateField []) {
666 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
667 VMSTATE_END_OF_LIST()
668 }
669};
670
671static int bonito_pcihost_initfn(SysBusDevice *dev)
672{
673 return 0;
674}
675
676static int bonito_initfn(PCIDevice *dev)
677{
678 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
89200979 679 SysBusDevice *sysbus = &s->pcihost->busdev;
d0f7453d
HC		 680
681 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
d0f7453d 682 pci_config_set_prog_interface(dev->config, 0x00);
d0f7453d
HC		 683
684 /* set the north bridge register mapping */
89200979
BC		 685 memory_region_init_io(&s->iomem, &bonito_ops, s,
686 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
687 sysbus_init_mmio_region(sysbus, &s->iomem);
688 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
d0f7453d
HC		 689
690 /* set the north bridge pci configure mapping */
183e1d40
BC		 691 memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s,
692 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
693 sysbus_init_mmio_region(sysbus, &s->pcihost->conf_mem);
694 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
d0f7453d
HC		 695
696 /* set the south bridge pci configure mapping */
845cbeb8
BC		 697 memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s,
698 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
699 sysbus_init_mmio_region(sysbus, &s->pcihost->data_mem);
700 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
d0f7453d 701
def344a6
BC		 702 memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s,
703 "ldma", 0x100);
704 sysbus_init_mmio_region(sysbus, &s->iomem_ldma);
705 sysbus_mmio_map(sysbus, 3, 0xbfe00200);
d0f7453d 706
9a542a48
BC		 707 memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s,
708 "cop", 0x100);
709 sysbus_init_mmio_region(sysbus, &s->iomem_cop);
710 sysbus_mmio_map(sysbus, 4, 0xbfe00300);
d0f7453d
HC		 711
712 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
713 s->bonito_pciio_start = BONITO_PCIIO_BASE;
714 s->bonito_pciio_length = BONITO_PCIIO_SIZE;
715 isa_mem_base = s->bonito_pciio_start;
968d683c 716 isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length);
d0f7453d
HC		 717
718 /* add pci local io mapping */
719 s->bonito_localio_start = BONITO_DEV_BASE;
720 s->bonito_localio_length = BONITO_DEV_SIZE;
968d683c 721 isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length);
d0f7453d
HC		 722
723 /* set the default value of north bridge pci config */
724 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
725 pci_set_word(dev->config + PCI_STATUS, 0x0000);
726 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
727 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
728
729 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
730 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
731 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
732 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
733
734 qemu_register_reset(bonito_reset, s);
735
736 return 0;
737}
738
739PCIBus *bonito_init(qemu_irq *pic)
740{
741 DeviceState *dev;
742 PCIBus *b;
743 BonitoState *pcihost;
744 PCIBonitoState *s;
745 PCIDevice *d;
746
747 dev = qdev_create(NULL, "Bonito-pcihost");
748 pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
749 b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
1e39101c 750 pci_bonito_map_irq, pic, get_system_memory(),
aee97b84 751 get_system_io(),
1e39101c 752 0x28, 32);
d0f7453d
HC		 753 pcihost->bus = b;
754 qdev_init_nofail(dev);
d0f7453d 755
89200979
BC		 756 /* set the pcihost pointer before bonito_initfn is called */
757 d = pci_create(b, PCI_DEVFN(0, 0), "Bonito");
d0f7453d
HC		 758 s = DO_UPCAST(PCIBonitoState, dev, d);
759 s->pcihost = pcihost;
760 bonito_state = s;
89200979 761 qdev_init_nofail(&d->qdev);
d0f7453d
HC		 762
763 return b;
764}
765
766static PCIDeviceInfo bonito_info = {
767 .qdev.name = "Bonito",
768 .qdev.desc = "Host bridge",
769 .qdev.size = sizeof(PCIBonitoState),
770 .qdev.vmsd = &vmstate_bonito,
771 .qdev.no_user = 1,
772 .init = bonito_initfn,
51387f86
IY		 773 /*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/
774 .vendor_id = 0xdf53,
775 .device_id = 0x00d5,
776 .revision = 0x01,
777 .class_id = PCI_CLASS_BRIDGE_HOST,
d0f7453d
HC		 778};
779
780static SysBusDeviceInfo bonito_pcihost_info = {
781 .init = bonito_pcihost_initfn,
782 .qdev.name = "Bonito-pcihost",
783 .qdev.size = sizeof(BonitoState),
784 .qdev.no_user = 1,
785};
786
787static void bonito_register(void)
788{
789 sysbus_register_withprop(&bonito_pcihost_info);
790 pci_qdev_register(&bonito_info);
791}
792device_init(bonito_register);
Qemu copy for testing