[qemu.git] / hw / char / imx_serial.c

/*
 * IMX31 UARTS
 *
 * Copyright (c) 2008 OKL
 * Originally Written by Hans Jiang
 * Copyright (c) 2011 NICTA Pty Ltd.
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * This is a `bare-bones' implementation of the IMX series serial ports.
 * TODO:
 *  -- implement FIFOs.  The real hardware has 32 word transmit
 *                       and receive FIFOs; we currently use a 1-char buffer
 *  -- implement DMA
 *  -- implement BAUD-rate and modem lines, for when the backend
 *     is a real serial device.
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
#include "hw/arm/imx.h"

//#define DEBUG_SERIAL 1
#ifdef DEBUG_SERIAL
#define DPRINTF(fmt, args...) \
do { printf("imx_serial: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif

/*
 * Define to 1 for messages about attempts to
 * access unimplemented registers or similar.
 */
//#define DEBUG_IMPLEMENTATION 1
#ifdef DEBUG_IMPLEMENTATION
#  define IPRINTF(fmt, args...) \
    do  { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0)
#else
#  define IPRINTF(fmt, args...) do {} while (0)
#endif

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    int32_t readbuff;

    uint32_t usr1;
    uint32_t usr2;
    uint32_t ucr1;
    uint32_t ucr2;
    uint32_t uts1;

    /*
     * The registers below are implemented just so that the
     * guest OS sees what it has written
     */
    uint32_t onems;
    uint32_t ufcr;
    uint32_t ubmr;
    uint32_t ubrc;
    uint32_t ucr3;

    qemu_irq irq;
    CharDriverState *chr;
} IMXSerialState;

static const VMStateDescription vmstate_imx_serial = {
    .name = "imx-serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(readbuff, IMXSerialState),
        VMSTATE_UINT32(usr1, IMXSerialState),
        VMSTATE_UINT32(usr2, IMXSerialState),
        VMSTATE_UINT32(ucr1, IMXSerialState),
        VMSTATE_UINT32(uts1, IMXSerialState),
        VMSTATE_UINT32(onems, IMXSerialState),
        VMSTATE_UINT32(ufcr, IMXSerialState),
        VMSTATE_UINT32(ubmr, IMXSerialState),
        VMSTATE_UINT32(ubrc, IMXSerialState),
        VMSTATE_UINT32(ucr3, IMXSerialState),
        VMSTATE_END_OF_LIST()
    },
};


#define URXD_CHARRDY    (1<<15)   /* character read is valid */
#define URXD_ERR        (1<<14)   /* Character has error */
#define URXD_BRK        (1<<11)   /* Break received */

#define USR1_PARTYER    (1<<15)   /* Parity Error */
#define USR1_RTSS       (1<<14)   /* RTS pin status */
#define USR1_TRDY       (1<<13)   /* Tx ready */
#define USR1_RTSD       (1<<12)   /* RTS delta: pin changed state */
#define USR1_ESCF       (1<<11)   /* Escape sequence interrupt */
#define USR1_FRAMERR    (1<<10)   /* Framing error  */
#define USR1_RRDY       (1<<9)    /* receiver ready */
#define USR1_AGTIM      (1<<8)    /* Aging timer interrupt */
#define USR1_DTRD       (1<<7)    /* DTR changed */
#define USR1_RXDS       (1<<6)    /* Receiver is idle */
#define USR1_AIRINT     (1<<5)    /* Aysnch IR interrupt */
#define USR1_AWAKE      (1<<4)    /* Falling edge detected on RXd pin */

#define USR2_ADET       (1<<15)   /* Autobaud complete */
#define USR2_TXFE       (1<<14)   /* Transmit FIFO empty */
#define USR2_DTRF       (1<<13)   /* DTR/DSR transition */
#define USR2_IDLE       (1<<12)   /* UART has been idle for too long */
#define USR2_ACST       (1<<11)   /* Autobaud counter stopped */
#define USR2_RIDELT     (1<<10)   /* Ring Indicator delta */
#define USR2_RIIN       (1<<9)    /* Ring Indicator Input */
#define USR2_IRINT      (1<<8)    /* Serial Infrared Interrupt */
#define USR2_WAKE       (1<<7)    /* Start bit detected */
#define USR2_DCDDELT    (1<<6)    /* Data Carrier Detect delta */
#define USR2_DCDIN      (1<<5)    /* Data Carrier Detect Input */
#define USR2_RTSF       (1<<4)    /* RTS transition */
#define USR2_TXDC       (1<<3)    /* Transmission complete */
#define USR2_BRCD       (1<<2)    /* Break condition detected */
#define USR2_ORE        (1<<1)    /* Overrun error */
#define USR2_RDR        (1<<0)    /* Receive data ready */

#define UCR1_TRDYEN     (1<<13)   /* Tx Ready Interrupt Enable */
#define UCR1_RRDYEN     (1<<9)    /* Rx Ready Interrupt Enable */
#define UCR1_TXMPTYEN   (1<<6)    /* Tx Empty Interrupt Enable */
#define UCR1_UARTEN     (1<<0)    /* UART Enable */

#define UCR2_TXEN       (1<<2)    /* Transmitter enable */
#define UCR2_RXEN       (1<<1)    /* Receiver enable */
#define UCR2_SRST       (1<<0)    /* Reset complete */

#define UTS1_TXEMPTY    (1<<6)
#define UTS1_RXEMPTY    (1<<5)
#define UTS1_TXFULL     (1<<4)
#define UTS1_RXFULL     (1<<3)

static void imx_update(IMXSerialState *s)
{
    uint32_t flags;

    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
    if (!(s->ucr1 & UCR1_TXMPTYEN)) {
        flags &= ~USR1_TRDY;
    }

    qemu_set_irq(s->irq, !!flags);
}

static void imx_serial_reset(IMXSerialState *s)
{

    s->usr1 = USR1_TRDY | USR1_RXDS;
    /*
     * Fake attachment of a terminal: assert RTS.
     */
    s->usr1 |= USR1_RTSS;
    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
    s->ucr1 = 0;
    s->ucr2 = UCR2_SRST;
    s->ucr3 = 0x700;
    s->ubmr = 0;
    s->ubrc = 4;
    s->readbuff = URXD_ERR;
}

static void imx_serial_reset_at_boot(DeviceState *dev)
{
    IMXSerialState *s = container_of(dev, IMXSerialState, busdev.qdev);

    imx_serial_reset(s);

    /*
     * enable the uart on boot, so messages from the linux decompresser
     * are visible.  On real hardware this is done by the boot rom
     * before anything else is loaded.
     */
    s->ucr1 = UCR1_UARTEN;
    s->ucr2 = UCR2_TXEN;

}

static uint64_t imx_serial_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    uint32_t c;

    DPRINTF("read(offset=%x)\n", offset >> 2);
    switch (offset >> 2) {
    case 0x0: /* URXD */
        c = s->readbuff;
        if (!(s->uts1 & UTS1_RXEMPTY)) {
            /* Character is valid */
            c |= URXD_CHARRDY;
            s->usr1 &= ~USR1_RRDY;
            s->usr2 &= ~USR2_RDR;
            s->uts1 |= UTS1_RXEMPTY;
            imx_update(s);
            qemu_chr_accept_input(s->chr);
        }
        return c;

    case 0x20: /* UCR1 */
        return s->ucr1;

    case 0x21: /* UCR2 */
        return s->ucr2;

    case 0x25: /* USR1 */
        return s->usr1;

    case 0x26: /* USR2 */
        return s->usr2;

    case 0x2A: /* BRM Modulator */
        return s->ubmr;

    case 0x2B: /* Baud Rate Count */
        return s->ubrc;

    case 0x2d: /* Test register */
        return s->uts1;

    case 0x24: /* UFCR */
        return s->ufcr;

    case 0x2c:
        return s->onems;

    case 0x22: /* UCR3 */
        return s->ucr3;

    case 0x23: /* UCR4 */
    case 0x29: /* BRM Incremental */
        return 0x0; /* TODO */

    default:
        IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset);
        return 0;
    }
}

static void imx_serial_write(void *opaque, hwaddr offset,
                      uint64_t value, unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    unsigned char ch;

    DPRINTF("write(offset=%x, value = %x) to %s\n",
            offset >> 2,
            (unsigned int)value, s->chr ? s->chr->label : "NODEV");

    switch (offset >> 2) {
    case 0x10: /* UTXD */
        ch = value;
        if (s->ucr2 & UCR2_TXEN) {
            if (s->chr) {
                qemu_chr_fe_write(s->chr, &ch, 1);
            }
            s->usr1 &= ~USR1_TRDY;
            imx_update(s);
            s->usr1 |= USR1_TRDY;
            imx_update(s);
        }
        break;

    case 0x20: /* UCR1 */
        s->ucr1 = value & 0xffff;
        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
        imx_update(s);
        break;

    case 0x21: /* UCR2 */
        /*
         * Only a few bits in control register 2 are implemented as yet.
         * If it's intended to use a real serial device as a back-end, this
         * register will have to be implemented more fully.
         */
        if (!(value & UCR2_SRST)) {
            imx_serial_reset(s);
            imx_update(s);
            value |= UCR2_SRST;
        }
        if (value & UCR2_RXEN) {
            if (!(s->ucr2 & UCR2_RXEN)) {
                qemu_chr_accept_input(s->chr);
            }
        }
        s->ucr2 = value & 0xffff;
        break;

    case 0x25: /* USR1 */
        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
            USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
        s->usr1 &= ~value;
        break;

    case 0x26: /* USR2 */
       /*
        * Writing 1 to some bits clears them; all other
        * values are ignored
        */
        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
            USR2_RIDELT | USR2_IRINT | USR2_WAKE |
            USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
        s->usr2 &= ~value;
        break;

        /*
         * Linux expects to see what it writes to these registers
         * We don't currently alter the baud rate
         */
    case 0x29: /* UBIR */
        s->ubrc = value & 0xffff;
        break;

    case 0x2a: /* UBMR */
        s->ubmr = value & 0xffff;
        break;

    case 0x2c: /* One ms reg */
        s->onems = value & 0xffff;
        break;

    case 0x24: /* FIFO control register */
        s->ufcr = value & 0xffff;
        break;

    case 0x22: /* UCR3 */
        s->ucr3 = value & 0xffff;
        break;

    case 0x2d: /* UTS1 */
    case 0x23: /* UCR4 */
        IPRINTF("Unimplemented Register %x written to\n", offset >> 2);
        /* TODO */
        break;

    default:
        IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset);
    }
}

static int imx_can_receive(void *opaque)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    return !(s->usr1 & USR1_RRDY);
}

static void imx_put_data(void *opaque, uint32_t value)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    DPRINTF("received char\n");
    s->usr1 |= USR1_RRDY;
    s->usr2 |= USR2_RDR;
    s->uts1 &= ~UTS1_RXEMPTY;
    s->readbuff = value;
    imx_update(s);
}

static void imx_receive(void *opaque, const uint8_t *buf, int size)
{
    imx_put_data(opaque, *buf);
}

static void imx_event(void *opaque, int event)
{
    if (event == CHR_EVENT_BREAK) {
        imx_put_data(opaque, URXD_BRK);
    }
}


static const struct MemoryRegionOps imx_serial_ops = {
    .read = imx_serial_read,
    .write = imx_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int imx_serial_init(SysBusDevice *dev)
{
    IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);


    memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
                          "imx-serial", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq);

    if (s->chr) {
        qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
                              imx_event, s);
    } else {
        DPRINTF("No char dev for uart at 0x%lx\n",
                (unsigned long)s->iomem.ram_addr);
    }

    return 0;
}

void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *bus;
    CharDriverState *chr;
    const char chr_name[] = "serial";
    char label[ARRAY_SIZE(chr_name) + 1];

    dev = qdev_create(NULL, "imx-serial");

    if (uart >= MAX_SERIAL_PORTS) {
        hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
                 uart, MAX_SERIAL_PORTS);
    }
    chr = serial_hds[uart];
    if (!chr) {
        snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
        chr = qemu_chr_new(label, "null", NULL);
        if (!(chr)) {
            hw_error("Can't assign serial port to imx-uart%d.\n", uart);
        }
    }

    qdev_prop_set_chr(dev, "chardev", chr);
    bus = SYS_BUS_DEVICE(dev);
    qdev_init_nofail(dev);
    if (addr != (hwaddr)-1) {
        sysbus_mmio_map(bus, 0, addr);
    }
    sysbus_connect_irq(bus, 0, irq);

}


static Property imx32_serial_properties[] = {
    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void imx_serial_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = imx_serial_init;
    dc->vmsd = &vmstate_imx_serial;
    dc->reset = imx_serial_reset_at_boot;
    dc->desc = "i.MX series UART";
    dc->props = imx32_serial_properties;
}

static const TypeInfo imx_serial_info = {
    .name = "imx-serial",
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IMXSerialState),
    .class_init = imx_serial_class_init,
};

static void imx_serial_register_types(void)
{
    type_register_static(&imx_serial_info);
}

type_init(imx_serial_register_types)
Commit	Line	Data
40b6f911 PC	1	/*
	2	* IMX31 UARTS
	3	*
	4	* Copyright (c) 2008 OKL
	5	* Originally Written by Hans Jiang
	6	* Copyright (c) 2011 NICTA Pty Ltd.
	7	*
	8	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	9	* See the COPYING file in the top-level directory.
	10	*
	11	* This is a `bare-bones' implementation of the IMX series serial ports.
	12	* TODO:
	13	* -- implement FIFOs. The real hardware has 32 word transmit
	14	* and receive FIFOs; we currently use a 1-char buffer
	15	* -- implement DMA
	16	* -- implement BAUD-rate and modem lines, for when the backend
	17	* is a real serial device.
	18	*/
	19
83c9f4ca PB	20	#include "hw/hw.h"
83c9f4ca PB	21	#include "hw/sysbus.h"
9c17d615	22	#include "sysemu/sysemu.h"
dccfcd0e	23	#include "sysemu/char.h"
0d09e41a	24	#include "hw/arm/imx.h"
40b6f911 PC	25
	26	//#define DEBUG_SERIAL 1
	27	#ifdef DEBUG_SERIAL
	28	#define DPRINTF(fmt, args...) \
	29	do { printf("imx_serial: " fmt , ##args); } while (0)
	30	#else
	31	#define DPRINTF(fmt, args...) do {} while (0)
	32	#endif
	33
	34	/*
	35	* Define to 1 for messages about attempts to
	36	* access unimplemented registers or similar.
	37	*/
	38	//#define DEBUG_IMPLEMENTATION 1
	39	#ifdef DEBUG_IMPLEMENTATION
	40	# define IPRINTF(fmt, args...) \
	41	do { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0)
	42	#else
	43	# define IPRINTF(fmt, args...) do {} while (0)
	44	#endif
	45
	46	typedef struct {
	47	SysBusDevice busdev;
	48	MemoryRegion iomem;
	49	int32_t readbuff;
	50
	51	uint32_t usr1;
	52	uint32_t usr2;
	53	uint32_t ucr1;
	54	uint32_t ucr2;
	55	uint32_t uts1;
	56
	57	/*
	58	* The registers below are implemented just so that the
	59	* guest OS sees what it has written
	60	*/
	61	uint32_t onems;
	62	uint32_t ufcr;
	63	uint32_t ubmr;
	64	uint32_t ubrc;
	65	uint32_t ucr3;
	66
	67	qemu_irq irq;
	68	CharDriverState *chr;
	69	} IMXSerialState;
	70
	71	static const VMStateDescription vmstate_imx_serial = {
	72	.name = "imx-serial",
	73	.version_id = 1,
	74	.minimum_version_id = 1,
	75	.minimum_version_id_old = 1,
	76	.fields = (VMStateField[]) {
	77	VMSTATE_INT32(readbuff, IMXSerialState),
	78	VMSTATE_UINT32(usr1, IMXSerialState),
	79	VMSTATE_UINT32(usr2, IMXSerialState),
	80	VMSTATE_UINT32(ucr1, IMXSerialState),
	81	VMSTATE_UINT32(uts1, IMXSerialState),
	82	VMSTATE_UINT32(onems, IMXSerialState),
	83	VMSTATE_UINT32(ufcr, IMXSerialState),
	84	VMSTATE_UINT32(ubmr, IMXSerialState),
	85	VMSTATE_UINT32(ubrc, IMXSerialState),
	86	VMSTATE_UINT32(ucr3, IMXSerialState),
	87	VMSTATE_END_OF_LIST()
	88	},
89	};
90
91
92	#define URXD_CHARRDY (1<<15) /* character read is valid */
93	#define URXD_ERR (1<<14) /* Character has error */
94	#define URXD_BRK (1<<11) /* Break received */
95
96	#define USR1_PARTYER (1<<15) /* Parity Error */
97	#define USR1_RTSS (1<<14) /* RTS pin status */
98	#define USR1_TRDY (1<<13) /* Tx ready */
99	#define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
100	#define USR1_ESCF (1<<11) /* Escape sequence interrupt */
101	#define USR1_FRAMERR (1<<10) /* Framing error */
102	#define USR1_RRDY (1<<9) /* receiver ready */
103	#define USR1_AGTIM (1<<8) /* Aging timer interrupt */
104	#define USR1_DTRD (1<<7) /* DTR changed */
105	#define USR1_RXDS (1<<6) /* Receiver is idle */
106	#define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
107	#define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
108
109	#define USR2_ADET (1<<15) /* Autobaud complete */
110	#define USR2_TXFE (1<<14) /* Transmit FIFO empty */
111	#define USR2_DTRF (1<<13) /* DTR/DSR transition */
112	#define USR2_IDLE (1<<12) /* UART has been idle for too long */
113	#define USR2_ACST (1<<11) /* Autobaud counter stopped */
114	#define USR2_RIDELT (1<<10) /* Ring Indicator delta */
115	#define USR2_RIIN (1<<9) /* Ring Indicator Input */
116	#define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
117	#define USR2_WAKE (1<<7) /* Start bit detected */
118	#define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */
119	#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
120	#define USR2_RTSF (1<<4) /* RTS transition */
121	#define USR2_TXDC (1<<3) /* Transmission complete */
122	#define USR2_BRCD (1<<2) /* Break condition detected */
123	#define USR2_ORE (1<<1) /* Overrun error */
124	#define USR2_RDR (1<<0) /* Receive data ready */
125
126	#define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
127	#define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
128	#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
129	#define UCR1_UARTEN (1<<0) /* UART Enable */
130
131	#define UCR2_TXEN (1<<2) /* Transmitter enable */
132	#define UCR2_RXEN (1<<1) /* Receiver enable */
133	#define UCR2_SRST (1<<0) /* Reset complete */
134
135	#define UTS1_TXEMPTY (1<<6)
136	#define UTS1_RXEMPTY (1<<5)
137	#define UTS1_TXFULL (1<<4)
138	#define UTS1_RXFULL (1<<3)
139
140	static void imx_update(IMXSerialState *s)
141	{
142	uint32_t flags;
143
144	flags = (s->usr1 & s->ucr1) & (USR1_TRDY\|USR1_RRDY);
145	if (!(s->ucr1 & UCR1_TXMPTYEN)) {
146	flags &= ~USR1_TRDY;
147	}
148
149	qemu_set_irq(s->irq, !!flags);
150	}
151
152	static void imx_serial_reset(IMXSerialState *s)
153	{
154
155	s->usr1 = USR1_TRDY \| USR1_RXDS;
156	/*
157	* Fake attachment of a terminal: assert RTS.
158	*/
159	s->usr1 \|= USR1_RTSS;
160	s->usr2 = USR2_TXFE \| USR2_TXDC \| USR2_DCDIN;
161	s->uts1 = UTS1_RXEMPTY \| UTS1_TXEMPTY;
162	s->ucr1 = 0;
163	s->ucr2 = UCR2_SRST;
164	s->ucr3 = 0x700;
165	s->ubmr = 0;
166	s->ubrc = 4;
167	s->readbuff = URXD_ERR;
168	}
169
170	static void imx_serial_reset_at_boot(DeviceState *dev)
171	{
172	IMXSerialState *s = container_of(dev, IMXSerialState, busdev.qdev);
173
174	imx_serial_reset(s);
175
176	/*
177	* enable the uart on boot, so messages from the linux decompresser
178	* are visible. On real hardware this is done by the boot rom
179	* before anything else is loaded.
180	*/
181	s->ucr1 = UCR1_UARTEN;
182	s->ucr2 = UCR2_TXEN;
183
184	}
185
a8170e5e	186	static uint64_t imx_serial_read(void *opaque, hwaddr offset,
40b6f911 PC	187	unsigned size)
	188	{
	189	IMXSerialState s = (IMXSerialState )opaque;
	190	uint32_t c;
	191
	192	DPRINTF("read(offset=%x)\n", offset >> 2);
	193	switch (offset >> 2) {
	194	case 0x0: /* URXD */
	195	c = s->readbuff;
	196	if (!(s->uts1 & UTS1_RXEMPTY)) {
	197	/* Character is valid */
	198	c \|= URXD_CHARRDY;
	199	s->usr1 &= ~USR1_RRDY;
	200	s->usr2 &= ~USR2_RDR;
	201	s->uts1 \|= UTS1_RXEMPTY;
	202	imx_update(s);
	203	qemu_chr_accept_input(s->chr);
	204	}
	205	return c;
	206
	207	case 0x20: /* UCR1 */
	208	return s->ucr1;
	209
	210	case 0x21: /* UCR2 */
	211	return s->ucr2;
	212
	213	case 0x25: /* USR1 */
	214	return s->usr1;
	215
	216	case 0x26: /* USR2 */
	217	return s->usr2;
	218
	219	case 0x2A: /* BRM Modulator */
	220	return s->ubmr;
	221
	222	case 0x2B: /* Baud Rate Count */
	223	return s->ubrc;
	224
	225	case 0x2d: /* Test register */
	226	return s->uts1;
	227
	228	case 0x24: /* UFCR */
	229	return s->ufcr;
	230
	231	case 0x2c:
	232	return s->onems;
	233
	234	case 0x22: /* UCR3 */
	235	return s->ucr3;
	236
	237	case 0x23: /* UCR4 */
	238	case 0x29: /* BRM Incremental */
	239	return 0x0; /* TODO */
	240
	241	default:
	242	IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset);
	243	return 0;
	244	}
	245	}
	246
a8170e5e	247	static void imx_serial_write(void *opaque, hwaddr offset,
40b6f911 PC	248	uint64_t value, unsigned size)
	249	{
	250	IMXSerialState s = (IMXSerialState )opaque;
	251	unsigned char ch;
	252
	253	DPRINTF("write(offset=%x, value = %x) to %s\n",
	254	offset >> 2,
	255	(unsigned int)value, s->chr ? s->chr->label : "NODEV");
	256
	257	switch (offset >> 2) {
	258	case 0x10: /* UTXD */
	259	ch = value;
	260	if (s->ucr2 & UCR2_TXEN) {
	261	if (s->chr) {
	262	qemu_chr_fe_write(s->chr, &ch, 1);
	263	}
	264	s->usr1 &= ~USR1_TRDY;
	265	imx_update(s);
	266	s->usr1 \|= USR1_TRDY;
	267	imx_update(s);
	268	}
	269	break;
	270
	271	case 0x20: /* UCR1 */
	272	s->ucr1 = value & 0xffff;
	273	DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
	274	imx_update(s);
	275	break;
	276
	277	case 0x21: /* UCR2 */
	278	/*
	279	* Only a few bits in control register 2 are implemented as yet.
	280	* If it's intended to use a real serial device as a back-end, this
	281	* register will have to be implemented more fully.
	282	*/
	283	if (!(value & UCR2_SRST)) {
	284	imx_serial_reset(s);
	285	imx_update(s);
	286	value \|= UCR2_SRST;
	287	}
	288	if (value & UCR2_RXEN) {
	289	if (!(s->ucr2 & UCR2_RXEN)) {
	290	qemu_chr_accept_input(s->chr);
	291	}
	292	}
	293	s->ucr2 = value & 0xffff;
	294	break;
	295
	296	case 0x25: /* USR1 */
	297	value &= USR1_AWAKE \| USR1_AIRINT \| USR1_DTRD \| USR1_AGTIM \|
	298	USR1_FRAMERR \| USR1_ESCF \| USR1_RTSD \| USR1_PARTYER;
	299	s->usr1 &= ~value;
	300	break;
	301
	302	case 0x26: /* USR2 */
	303	/*
	304	* Writing 1 to some bits clears them; all other
	305	* values are ignored
	306	*/
	307	value &= USR2_ADET \| USR2_DTRF \| USR2_IDLE \| USR2_ACST \|
	308	USR2_RIDELT \| USR2_IRINT \| USR2_WAKE \|
	309	USR2_DCDDELT \| USR2_RTSF \| USR2_BRCD \| USR2_ORE;
	310	s->usr2 &= ~value;
	311	break;
312
313	/*
314	* Linux expects to see what it writes to these registers
315	* We don't currently alter the baud rate
316	*/
317	case 0x29: /* UBIR */
318	s->ubrc = value & 0xffff;
319	break;
320
321	case 0x2a: /* UBMR */
322	s->ubmr = value & 0xffff;
323	break;
324
325	case 0x2c: /* One ms reg */
326	s->onems = value & 0xffff;
327	break;
328
329	case 0x24: /* FIFO control register */
330	s->ufcr = value & 0xffff;
331	break;
332
333	case 0x22: /* UCR3 */
334	s->ucr3 = value & 0xffff;
335	break;
336
337	case 0x2d: /* UTS1 */
338	case 0x23: /* UCR4 */
339	IPRINTF("Unimplemented Register %x written to\n", offset >> 2);
340	/* TODO */
341	break;
342
343	default:
344	IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset);
345	}
346	}
347
348	static int imx_can_receive(void *opaque)
349	{
350	IMXSerialState s = (IMXSerialState )opaque;
351	return !(s->usr1 & USR1_RRDY);
352	}
353
354	static void imx_put_data(void *opaque, uint32_t value)
355	{
356	IMXSerialState s = (IMXSerialState )opaque;
357	DPRINTF("received char\n");
358	s->usr1 \|= USR1_RRDY;
359	s->usr2 \|= USR2_RDR;
360	s->uts1 &= ~UTS1_RXEMPTY;
361	s->readbuff = value;
362	imx_update(s);
363	}
364
365	static void imx_receive(void opaque, const uint8_t buf, int size)
366	{
367	imx_put_data(opaque, *buf);
368	}
369
370	static void imx_event(void *opaque, int event)
371	{
372	if (event == CHR_EVENT_BREAK) {
373	imx_put_data(opaque, URXD_BRK);
374	}
375	}
376
377
378	static const struct MemoryRegionOps imx_serial_ops = {
379	.read = imx_serial_read,
380	.write = imx_serial_write,
381	.endianness = DEVICE_NATIVE_ENDIAN,
382	};
383
384	static int imx_serial_init(SysBusDevice *dev)
385	{
386	IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
387
388
300b1fc6 PB	389	memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
300b1fc6 PB	390	"imx-serial", 0x1000);
40b6f911 PC	391	sysbus_init_mmio(dev, &s->iomem);
	392	sysbus_init_irq(dev, &s->irq);
	393
	394	if (s->chr) {
	395	qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
	396	imx_event, s);
	397	} else {
	398	DPRINTF("No char dev for uart at 0x%lx\n",
	399	(unsigned long)s->iomem.ram_addr);
	400	}
	401
	402	return 0;
	403	}
	404
a8170e5e	405	void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
40b6f911 PC	406	{
	407	DeviceState *dev;
	408	SysBusDevice *bus;
	409	CharDriverState *chr;
	410	const char chr_name[] = "serial";
	411	char label[ARRAY_SIZE(chr_name) + 1];
	412
	413	dev = qdev_create(NULL, "imx-serial");
	414
	415	if (uart >= MAX_SERIAL_PORTS) {
	416	hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
	417	uart, MAX_SERIAL_PORTS);
	418	}
	419	chr = serial_hds[uart];
	420	if (!chr) {
	421	snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
	422	chr = qemu_chr_new(label, "null", NULL);
	423	if (!(chr)) {
	424	hw_error("Can't assign serial port to imx-uart%d.\n", uart);
	425	}
	426	}
	427
	428	qdev_prop_set_chr(dev, "chardev", chr);
1356b98d	429	bus = SYS_BUS_DEVICE(dev);
40b6f911	430	qdev_init_nofail(dev);
a8170e5e	431	if (addr != (hwaddr)-1) {
40b6f911 PC	432	sysbus_mmio_map(bus, 0, addr);
	433	}
	434	sysbus_connect_irq(bus, 0, irq);
	435
	436	}
	437
	438
	439	static Property imx32_serial_properties[] = {
	440	DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
	441	DEFINE_PROP_END_OF_LIST(),
	442	};
	443
	444	static void imx_serial_class_init(ObjectClass klass, void data)
	445	{
	446	DeviceClass *dc = DEVICE_CLASS(klass);
	447	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	448
	449	k->init = imx_serial_init;
	450	dc->vmsd = &vmstate_imx_serial;
	451	dc->reset = imx_serial_reset_at_boot;
	452	dc->desc = "i.MX series UART";
	453	dc->props = imx32_serial_properties;
	454	}
	455
8c43a6f0	456	static const TypeInfo imx_serial_info = {
40b6f911 PC	457	.name = "imx-serial",
	458	.parent = TYPE_SYS_BUS_DEVICE,
	459	.instance_size = sizeof(IMXSerialState),
	460	.class_init = imx_serial_class_init,
	461	};
	462
	463	static void imx_serial_register_types(void)
	464	{
	465	type_register_static(&imx_serial_info);
	466	}
	467
	468	type_init(imx_serial_register_types)