[qemu.git] / hw / char / serial-pci.c

/*
 * QEMU 16550A UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2008 Citrix Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* see docs/specs/pci-serial.txt */

#include "hw/char/serial.h"
#include "hw/pci/pci.h"
#include "qapi/qmp/qerror.h"

#define PCI_SERIAL_MAX_PORTS 4

typedef struct PCISerialState {
    PCIDevice dev;
    SerialState state;
} PCISerialState;

typedef struct PCIMultiSerialState {
    PCIDevice    dev;
    MemoryRegion iobar;
    uint32_t     ports;
    char         *name[PCI_SERIAL_MAX_PORTS];
    SerialState  state[PCI_SERIAL_MAX_PORTS];
    uint32_t     level[PCI_SERIAL_MAX_PORTS];
    qemu_irq     *irqs;
} PCIMultiSerialState;

static int serial_pci_init(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;
    Error *err = NULL;

    s->baudbase = 115200;
    serial_realize_core(s, &err);
    if (err != NULL) {
        qerror_report_err(err);
        error_free(err);
        return -1;
    }

    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    s->irq = pci_allocate_irq(&pci->dev);

    memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
    return 0;
}

static void multi_serial_irq_mux(void *opaque, int n, int level)
{
    PCIMultiSerialState *pci = opaque;
    int i, pending = 0;

    pci->level[n] = level;
    for (i = 0; i < pci->ports; i++) {
        if (pci->level[i]) {
            pending = 1;
        }
    }
    pci_set_irq(&pci->dev, pending);
}

static int multi_serial_pci_init(PCIDevice *dev)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    Error *err = NULL;
    int i;

    switch (pc->device_id) {
    case 0x0003:
        pci->ports = 2;
        break;
    case 0x0004:
        pci->ports = 4;
        break;
    }
    assert(pci->ports > 0);
    assert(pci->ports <= PCI_SERIAL_MAX_PORTS);

    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
    pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
                                   pci->ports);

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        s->baudbase = 115200;
        serial_realize_core(s, &err);
        if (err != NULL) {
            qerror_report_err(err);
            error_free(err);
            return -1;
        }
        s->irq = pci->irqs[i];
        pci->name[i] = g_strdup_printf("uart #%d", i+1);
        memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
                              pci->name[i], 8);
        memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
    }
    return 0;
}

static void serial_pci_exit(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;

    serial_exit_core(s);
    memory_region_destroy(&s->io);
    qemu_free_irq(s->irq);
}

static void multi_serial_pci_exit(PCIDevice *dev)
{
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    int i;

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        serial_exit_core(s);
        memory_region_destroy(&s->io);
        g_free(pci->name[i]);
    }
    memory_region_destroy(&pci->iobar);
    qemu_free_irqs(pci->irqs);
}

static const VMStateDescription vmstate_pci_serial = {
    .name = "pci-serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCISerialState),
        VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_multi_serial = {
    .name = "pci-serial-multi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
        VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
                             0, vmstate_serial, SerialState),
        VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
        VMSTATE_END_OF_LIST()
    }
};

static Property serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev",  PCISerialState, state.chr),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_2x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_4x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
    DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = serial_pci_init;
    pc->exit = serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_serial;
    dc->props = serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = multi_serial_pci_init;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_2x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = multi_serial_pci_init;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_4x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo serial_pci_info = {
    .name          = "pci-serial",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCISerialState),
    .class_init    = serial_pci_class_initfn,
};

static const TypeInfo multi_2x_serial_pci_info = {
    .name          = "pci-serial-2x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_2x_serial_pci_class_initfn,
};

static const TypeInfo multi_4x_serial_pci_info = {
    .name          = "pci-serial-4x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_4x_serial_pci_class_initfn,
};

static void serial_pci_register_types(void)
{
    type_register_static(&serial_pci_info);
    type_register_static(&multi_2x_serial_pci_info);
    type_register_static(&multi_4x_serial_pci_info);
}

type_init(serial_pci_register_types)
Commit	Line	Data
419ad672 GH	1	/*
	2	* QEMU 16550A UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2008 Citrix Systems, Inc.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
90734e02 GH	26	/* see docs/specs/pci-serial.txt */
90734e02 GH	27
0d09e41a	28	#include "hw/char/serial.h"
83c9f4ca	29	#include "hw/pci/pci.h"
db895a1e	30	#include "qapi/qmp/qerror.h"
419ad672	31
d66bbea4 GH	32	#define PCI_SERIAL_MAX_PORTS 4
d66bbea4 GH	33
419ad672 GH	34	typedef struct PCISerialState {
	35	PCIDevice dev;
	36	SerialState state;
	37	} PCISerialState;
	38
d66bbea4 GH	39	typedef struct PCIMultiSerialState {
	40	PCIDevice dev;
	41	MemoryRegion iobar;
	42	uint32_t ports;
	43	char *name[PCI_SERIAL_MAX_PORTS];
	44	SerialState state[PCI_SERIAL_MAX_PORTS];
	45	uint32_t level[PCI_SERIAL_MAX_PORTS];
	46	qemu_irq *irqs;
	47	} PCIMultiSerialState;
	48
419ad672 GH	49	static int serial_pci_init(PCIDevice *dev)
	50	{
	51	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	52	SerialState *s = &pci->state;
db895a1e	53	Error *err = NULL;
419ad672 GH	54
419ad672 GH	55	s->baudbase = 115200;
db895a1e AF	56	serial_realize_core(s, &err);
	57	if (err != NULL) {
	58	qerror_report_err(err);
	59	error_free(err);
	60	return -1;
	61	}
419ad672 GH	62
419ad672 GH	63	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
9e64f8a3	64	s->irq = pci_allocate_irq(&pci->dev);
419ad672	65
300b1fc6	66	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
419ad672 GH	67	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
	68	return 0;
	69	}
	70
d66bbea4 GH	71	static void multi_serial_irq_mux(void *opaque, int n, int level)
	72	{
	73	PCIMultiSerialState *pci = opaque;
	74	int i, pending = 0;
	75
	76	pci->level[n] = level;
	77	for (i = 0; i < pci->ports; i++) {
	78	if (pci->level[i]) {
	79	pending = 1;
	80	}
	81	}
9e64f8a3	82	pci_set_irq(&pci->dev, pending);
d66bbea4 GH	83	}
	84
	85	static int multi_serial_pci_init(PCIDevice *dev)
	86	{
	87	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	88	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	89	SerialState *s;
db895a1e	90	Error *err = NULL;
d66bbea4 GH	91	int i;
	92
	93	switch (pc->device_id) {
	94	case 0x0003:
	95	pci->ports = 2;
	96	break;
	97	case 0x0004:
	98	pci->ports = 4;
	99	break;
	100	}
	101	assert(pci->ports > 0);
	102	assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
	103
	104	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
300b1fc6	105	memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
d66bbea4 GH	106	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
	107	pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
	108	pci->ports);
	109
	110	for (i = 0; i < pci->ports; i++) {
	111	s = pci->state + i;
	112	s->baudbase = 115200;
db895a1e AF	113	serial_realize_core(s, &err);
	114	if (err != NULL) {
	115	qerror_report_err(err);
	116	error_free(err);
	117	return -1;
	118	}
d66bbea4 GH	119	s->irq = pci->irqs[i];
d66bbea4 GH	120	pci->name[i] = g_strdup_printf("uart #%d", i+1);
300b1fc6 PB	121	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
300b1fc6 PB	122	pci->name[i], 8);
d66bbea4 GH	123	memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
	124	}
	125	return 0;
	126	}
	127
419ad672 GH	128	static void serial_pci_exit(PCIDevice *dev)
	129	{
	130	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	131	SerialState *s = &pci->state;
	132
	133	serial_exit_core(s);
	134	memory_region_destroy(&s->io);
9e64f8a3	135	qemu_free_irq(s->irq);
419ad672 GH	136	}
419ad672 GH	137
d66bbea4 GH	138	static void multi_serial_pci_exit(PCIDevice *dev)
	139	{
	140	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	141	SerialState *s;
	142	int i;
	143
	144	for (i = 0; i < pci->ports; i++) {
	145	s = pci->state + i;
	146	serial_exit_core(s);
	147	memory_region_destroy(&s->io);
	148	g_free(pci->name[i]);
	149	}
	150	memory_region_destroy(&pci->iobar);
	151	qemu_free_irqs(pci->irqs);
	152	}
	153
419ad672 GH	154	static const VMStateDescription vmstate_pci_serial = {
	155	.name = "pci-serial",
	156	.version_id = 1,
	157	.minimum_version_id = 1,
	158	.fields = (VMStateField[]) {
	159	VMSTATE_PCI_DEVICE(dev, PCISerialState),
	160	VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
	161	VMSTATE_END_OF_LIST()
	162	}
	163	};
	164
d66bbea4 GH	165	static const VMStateDescription vmstate_pci_multi_serial = {
	166	.name = "pci-serial-multi",
	167	.version_id = 1,
	168	.minimum_version_id = 1,
	169	.fields = (VMStateField[]) {
	170	VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
	171	VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
	172	0, vmstate_serial, SerialState),
	173	VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
	174	VMSTATE_END_OF_LIST()
	175	}
	176	};
	177
419ad672 GH	178	static Property serial_pci_properties[] = {
	179	DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
	180	DEFINE_PROP_END_OF_LIST(),
	181	};
	182
d66bbea4 GH	183	static Property multi_2x_serial_pci_properties[] = {
	184	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	185	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	186	DEFINE_PROP_END_OF_LIST(),
	187	};
	188
	189	static Property multi_4x_serial_pci_properties[] = {
	190	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	191	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	192	DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
	193	DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
	194	DEFINE_PROP_END_OF_LIST(),
	195	};
	196
419ad672 GH	197	static void serial_pci_class_initfn(ObjectClass klass, void data)
	198	{
	199	DeviceClass *dc = DEVICE_CLASS(klass);
	200	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	201	pc->init = serial_pci_init;
	202	pc->exit = serial_pci_exit;
5c03a254 PB	203	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	204	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
419ad672 GH	205	pc->revision = 1;
	206	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	207	dc->vmsd = &vmstate_pci_serial;
	208	dc->props = serial_pci_properties;
125ee0ed	209	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
419ad672 GH	210	}
419ad672 GH	211
d66bbea4 GH	212	static void multi_2x_serial_pci_class_initfn(ObjectClass klass, void data)
	213	{
	214	DeviceClass *dc = DEVICE_CLASS(klass);
	215	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	216	pc->init = multi_serial_pci_init;
	217	pc->exit = multi_serial_pci_exit;
5c03a254 PB	218	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	219	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
d66bbea4 GH	220	pc->revision = 1;
	221	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	222	dc->vmsd = &vmstate_pci_multi_serial;
	223	dc->props = multi_2x_serial_pci_properties;
125ee0ed	224	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	225	}
	226
	227	static void multi_4x_serial_pci_class_initfn(ObjectClass klass, void data)
	228	{
	229	DeviceClass *dc = DEVICE_CLASS(klass);
	230	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	231	pc->init = multi_serial_pci_init;
	232	pc->exit = multi_serial_pci_exit;
5c03a254 PB	233	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	234	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
d66bbea4 GH	235	pc->revision = 1;
	236	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	237	dc->vmsd = &vmstate_pci_multi_serial;
	238	dc->props = multi_4x_serial_pci_properties;
125ee0ed	239	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	240	}
d66bbea4 GH	241
8c43a6f0	242	static const TypeInfo serial_pci_info = {
419ad672 GH	243	.name = "pci-serial",
	244	.parent = TYPE_PCI_DEVICE,
	245	.instance_size = sizeof(PCISerialState),
	246	.class_init = serial_pci_class_initfn,
	247	};
	248
8c43a6f0	249	static const TypeInfo multi_2x_serial_pci_info = {
d66bbea4 GH	250	.name = "pci-serial-2x",
	251	.parent = TYPE_PCI_DEVICE,
	252	.instance_size = sizeof(PCIMultiSerialState),
	253	.class_init = multi_2x_serial_pci_class_initfn,
	254	};
	255
8c43a6f0	256	static const TypeInfo multi_4x_serial_pci_info = {
d66bbea4 GH	257	.name = "pci-serial-4x",
	258	.parent = TYPE_PCI_DEVICE,
	259	.instance_size = sizeof(PCIMultiSerialState),
	260	.class_init = multi_4x_serial_pci_class_initfn,
	261	};
	262
419ad672 GH	263	static void serial_pci_register_types(void)
	264	{
	265	type_register_static(&serial_pci_info);
d66bbea4 GH	266	type_register_static(&multi_2x_serial_pci_info);
d66bbea4 GH	267	type_register_static(&multi_4x_serial_pci_info);
419ad672 GH	268	}
	269
	270	type_init(serial_pci_register_types)