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[qemu.git] / hw / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
5245d57a 34#include "loader.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
a21ae81d 174#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 175
b2eb849d
AJ		 176#define BLTUNSAFE(s) \
177 ( \
178 ( /* check dst is within bounds */ \
b2b183c2 179 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 180 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 181 (s)->vga.vram_size \
b2eb849d
AJ		 182 ) || \
183 ( /* check src is within bounds */ \
b2b183c2 184 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 185 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 186 (s)->vga.vram_size \
b2eb849d
AJ		 187 ) \
188 )
189
a5082316
FB		 190struct CirrusVGAState;
191typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
192 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 193 int dstpitch, int srcpitch,
194 int bltwidth, int bltheight);
a5082316
FB		 195typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
196 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 197
198typedef struct CirrusVGAState {
4e12cd94 199 VGACommonState vga;
e6e5ad80 200
b1950430
AK		 201 MemoryRegion cirrus_linear_io;
202 MemoryRegion cirrus_linear_bitblt_io;
203 MemoryRegion cirrus_mmio_io;
204 MemoryRegion pci_bar;
205 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
206 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
207 MemoryRegion low_mem; /* always mapped, overridden by: */
208 MemoryRegion *cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 209 uint32_t cirrus_addr_mask;
78e127ef 210 uint32_t linear_mmio_mask;
e6e5ad80
FB		 211 uint8_t cirrus_shadow_gr0;
212 uint8_t cirrus_shadow_gr1;
213 uint8_t cirrus_hidden_dac_lockindex;
214 uint8_t cirrus_hidden_dac_data;
215 uint32_t cirrus_bank_base[2];
216 uint32_t cirrus_bank_limit[2];
217 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 218 uint32_t hw_cursor_x;
219 uint32_t hw_cursor_y;
e6e5ad80
FB		 220 int cirrus_blt_pixelwidth;
221 int cirrus_blt_width;
222 int cirrus_blt_height;
223 int cirrus_blt_dstpitch;
224 int cirrus_blt_srcpitch;
a5082316
FB		 225 uint32_t cirrus_blt_fgcol;
226 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 227 uint32_t cirrus_blt_dstaddr;
228 uint32_t cirrus_blt_srcaddr;
229 uint8_t cirrus_blt_mode;
a5082316 230 uint8_t cirrus_blt_modeext;
e6e5ad80 231 cirrus_bitblt_rop_t cirrus_rop;
a5082316 232#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 233 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
234 uint8_t *cirrus_srcptr;
235 uint8_t *cirrus_srcptr_end;
236 uint32_t cirrus_srccounter;
a5082316
FB		 237 /* hwcursor display state */
238 int last_hw_cursor_size;
239 int last_hw_cursor_x;
240 int last_hw_cursor_y;
241 int last_hw_cursor_y_start;
242 int last_hw_cursor_y_end;
78e127ef 243 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 244 int device_id;
245 int bustype;
e6e5ad80
FB		 246} CirrusVGAState;
247
248typedef struct PCICirrusVGAState {
249 PCIDevice dev;
250 CirrusVGAState cirrus_vga;
251} PCICirrusVGAState;
252
a5082316 253static uint8_t rop_to_index[256];
3b46e624 254
e6e5ad80
FB		 255/***************************************
256 *
257 * prototypes.
258 *
259 ***************************************/
260
261
8926b517
FB		 262static void cirrus_bitblt_reset(CirrusVGAState *s);
263static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 264
265/***************************************
266 *
267 * raster operations
268 *
269 ***************************************/
270
a5082316
FB		 271static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
272 uint8_t *dst,const uint8_t *src,
273 int dstpitch,int srcpitch,
274 int bltwidth,int bltheight)
275{
e6e5ad80
FB		 276}
277
a5082316
FB		 278static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
279 uint8_t *dst,
280 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 281{
a5082316 282}
e6e5ad80 283
a5082316 284#define ROP_NAME 0
8c78881f 285#define ROP_FN(d, s) 0
a5082316 286#include "cirrus_vga_rop.h"
e6e5ad80 287
a5082316 288#define ROP_NAME src_and_dst
8c78881f 289#define ROP_FN(d, s) (s) & (d)
a5082316 290#include "cirrus_vga_rop.h"
e6e5ad80 291
a5082316 292#define ROP_NAME src_and_notdst
8c78881f 293#define ROP_FN(d, s) (s) & (~(d))
a5082316 294#include "cirrus_vga_rop.h"
e6e5ad80 295
a5082316 296#define ROP_NAME notdst
8c78881f 297#define ROP_FN(d, s) ~(d)
a5082316 298#include "cirrus_vga_rop.h"
e6e5ad80 299
a5082316 300#define ROP_NAME src
8c78881f 301#define ROP_FN(d, s) s
a5082316 302#include "cirrus_vga_rop.h"
e6e5ad80 303
a5082316 304#define ROP_NAME 1
8c78881f 305#define ROP_FN(d, s) ~0
a5082316
FB		 306#include "cirrus_vga_rop.h"
307
308#define ROP_NAME notsrc_and_dst
8c78881f 309#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 310#include "cirrus_vga_rop.h"
311
312#define ROP_NAME src_xor_dst
8c78881f 313#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 314#include "cirrus_vga_rop.h"
315
316#define ROP_NAME src_or_dst
8c78881f 317#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 318#include "cirrus_vga_rop.h"
319
320#define ROP_NAME notsrc_or_notdst
8c78881f 321#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 322#include "cirrus_vga_rop.h"
323
324#define ROP_NAME src_notxor_dst
8c78881f 325#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 326#include "cirrus_vga_rop.h"
e6e5ad80 327
a5082316 328#define ROP_NAME src_or_notdst
8c78881f 329#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 330#include "cirrus_vga_rop.h"
331
332#define ROP_NAME notsrc
8c78881f 333#define ROP_FN(d, s) (~(s))
a5082316
FB		 334#include "cirrus_vga_rop.h"
335
336#define ROP_NAME notsrc_or_dst
8c78881f 337#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 338#include "cirrus_vga_rop.h"
339
340#define ROP_NAME notsrc_and_notdst
8c78881f 341#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 342#include "cirrus_vga_rop.h"
343
344static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
345 cirrus_bitblt_rop_fwd_0,
346 cirrus_bitblt_rop_fwd_src_and_dst,
347 cirrus_bitblt_rop_nop,
348 cirrus_bitblt_rop_fwd_src_and_notdst,
349 cirrus_bitblt_rop_fwd_notdst,
350 cirrus_bitblt_rop_fwd_src,
351 cirrus_bitblt_rop_fwd_1,
352 cirrus_bitblt_rop_fwd_notsrc_and_dst,
353 cirrus_bitblt_rop_fwd_src_xor_dst,
354 cirrus_bitblt_rop_fwd_src_or_dst,
355 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
356 cirrus_bitblt_rop_fwd_src_notxor_dst,
357 cirrus_bitblt_rop_fwd_src_or_notdst,
358 cirrus_bitblt_rop_fwd_notsrc,
359 cirrus_bitblt_rop_fwd_notsrc_or_dst,
360 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
361};
362
363static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
364 cirrus_bitblt_rop_bkwd_0,
365 cirrus_bitblt_rop_bkwd_src_and_dst,
366 cirrus_bitblt_rop_nop,
367 cirrus_bitblt_rop_bkwd_src_and_notdst,
368 cirrus_bitblt_rop_bkwd_notdst,
369 cirrus_bitblt_rop_bkwd_src,
370 cirrus_bitblt_rop_bkwd_1,
371 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
372 cirrus_bitblt_rop_bkwd_src_xor_dst,
373 cirrus_bitblt_rop_bkwd_src_or_dst,
374 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
375 cirrus_bitblt_rop_bkwd_src_notxor_dst,
376 cirrus_bitblt_rop_bkwd_src_or_notdst,
377 cirrus_bitblt_rop_bkwd_notsrc,
378 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
379 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
380};
96cf2df8
TS		 381
382#define TRANSP_ROP(name) {\
383 name ## _8,\
384 name ## _16,\
385 }
386#define TRANSP_NOP(func) {\
387 func,\
388 func,\
389 }
390
391static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
392 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
393 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
394 TRANSP_NOP(cirrus_bitblt_rop_nop),
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
408};
409
410static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
411 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
412 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
413 TRANSP_NOP(cirrus_bitblt_rop_nop),
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
427};
428
a5082316
FB		 429#define ROP2(name) {\
430 name ## _8,\
431 name ## _16,\
432 name ## _24,\
433 name ## _32,\
434 }
435
436#define ROP_NOP2(func) {\
437 func,\
438 func,\
439 func,\
440 func,\
441 }
442
e69390ce
FB		 443static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
444 ROP2(cirrus_patternfill_0),
445 ROP2(cirrus_patternfill_src_and_dst),
446 ROP_NOP2(cirrus_bitblt_rop_nop),
447 ROP2(cirrus_patternfill_src_and_notdst),
448 ROP2(cirrus_patternfill_notdst),
449 ROP2(cirrus_patternfill_src),
450 ROP2(cirrus_patternfill_1),
451 ROP2(cirrus_patternfill_notsrc_and_dst),
452 ROP2(cirrus_patternfill_src_xor_dst),
453 ROP2(cirrus_patternfill_src_or_dst),
454 ROP2(cirrus_patternfill_notsrc_or_notdst),
455 ROP2(cirrus_patternfill_src_notxor_dst),
456 ROP2(cirrus_patternfill_src_or_notdst),
457 ROP2(cirrus_patternfill_notsrc),
458 ROP2(cirrus_patternfill_notsrc_or_dst),
459 ROP2(cirrus_patternfill_notsrc_and_notdst),
460};
461
a5082316
FB		 462static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
463 ROP2(cirrus_colorexpand_transp_0),
464 ROP2(cirrus_colorexpand_transp_src_and_dst),
465 ROP_NOP2(cirrus_bitblt_rop_nop),
466 ROP2(cirrus_colorexpand_transp_src_and_notdst),
467 ROP2(cirrus_colorexpand_transp_notdst),
468 ROP2(cirrus_colorexpand_transp_src),
469 ROP2(cirrus_colorexpand_transp_1),
470 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
471 ROP2(cirrus_colorexpand_transp_src_xor_dst),
472 ROP2(cirrus_colorexpand_transp_src_or_dst),
473 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
474 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
475 ROP2(cirrus_colorexpand_transp_src_or_notdst),
476 ROP2(cirrus_colorexpand_transp_notsrc),
477 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
478 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
479};
480
481static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
482 ROP2(cirrus_colorexpand_0),
483 ROP2(cirrus_colorexpand_src_and_dst),
484 ROP_NOP2(cirrus_bitblt_rop_nop),
485 ROP2(cirrus_colorexpand_src_and_notdst),
486 ROP2(cirrus_colorexpand_notdst),
487 ROP2(cirrus_colorexpand_src),
488 ROP2(cirrus_colorexpand_1),
489 ROP2(cirrus_colorexpand_notsrc_and_dst),
490 ROP2(cirrus_colorexpand_src_xor_dst),
491 ROP2(cirrus_colorexpand_src_or_dst),
492 ROP2(cirrus_colorexpand_notsrc_or_notdst),
493 ROP2(cirrus_colorexpand_src_notxor_dst),
494 ROP2(cirrus_colorexpand_src_or_notdst),
495 ROP2(cirrus_colorexpand_notsrc),
496 ROP2(cirrus_colorexpand_notsrc_or_dst),
497 ROP2(cirrus_colorexpand_notsrc_and_notdst),
498};
499
b30d4608
FB		 500static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
501 ROP2(cirrus_colorexpand_pattern_transp_0),
502 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
503 ROP_NOP2(cirrus_bitblt_rop_nop),
504 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
505 ROP2(cirrus_colorexpand_pattern_transp_notdst),
506 ROP2(cirrus_colorexpand_pattern_transp_src),
507 ROP2(cirrus_colorexpand_pattern_transp_1),
508 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
509 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
510 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
511 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
512 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
514 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
515 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
517};
518
519static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
520 ROP2(cirrus_colorexpand_pattern_0),
521 ROP2(cirrus_colorexpand_pattern_src_and_dst),
522 ROP_NOP2(cirrus_bitblt_rop_nop),
523 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
524 ROP2(cirrus_colorexpand_pattern_notdst),
525 ROP2(cirrus_colorexpand_pattern_src),
526 ROP2(cirrus_colorexpand_pattern_1),
527 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
528 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
529 ROP2(cirrus_colorexpand_pattern_src_or_dst),
530 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
531 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
532 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
533 ROP2(cirrus_colorexpand_pattern_notsrc),
534 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
535 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
536};
537
a5082316
FB		 538static const cirrus_fill_t cirrus_fill[16][4] = {
539 ROP2(cirrus_fill_0),
540 ROP2(cirrus_fill_src_and_dst),
541 ROP_NOP2(cirrus_bitblt_fill_nop),
542 ROP2(cirrus_fill_src_and_notdst),
543 ROP2(cirrus_fill_notdst),
544 ROP2(cirrus_fill_src),
545 ROP2(cirrus_fill_1),
546 ROP2(cirrus_fill_notsrc_and_dst),
547 ROP2(cirrus_fill_src_xor_dst),
548 ROP2(cirrus_fill_src_or_dst),
549 ROP2(cirrus_fill_notsrc_or_notdst),
550 ROP2(cirrus_fill_src_notxor_dst),
551 ROP2(cirrus_fill_src_or_notdst),
552 ROP2(cirrus_fill_notsrc),
553 ROP2(cirrus_fill_notsrc_or_dst),
554 ROP2(cirrus_fill_notsrc_and_notdst),
555};
556
557static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 558{
a5082316
FB		 559 unsigned int color;
560 switch (s->cirrus_blt_pixelwidth) {
561 case 1:
562 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
563 break;
564 case 2:
4e12cd94 565 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 566 s->cirrus_blt_fgcol = le16_to_cpu(color);
567 break;
568 case 3:
5fafdf24 569 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 570 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 571 break;
572 default:
573 case 4:
4e12cd94
AK		 574 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
575 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 576 s->cirrus_blt_fgcol = le32_to_cpu(color);
577 break;
e6e5ad80
FB		 578 }
579}
580
a5082316 581static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 582{
a5082316 583 unsigned int color;
e6e5ad80
FB		 584 switch (s->cirrus_blt_pixelwidth) {
585 case 1:
a5082316
FB		 586 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
587 break;
e6e5ad80 588 case 2:
4e12cd94 589 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 590 s->cirrus_blt_bgcol = le16_to_cpu(color);
591 break;
e6e5ad80 592 case 3:
5fafdf24 593 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 594 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 595 break;
e6e5ad80 596 default:
a5082316 597 case 4:
4e12cd94
AK		 598 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
599 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 600 s->cirrus_blt_bgcol = le32_to_cpu(color);
601 break;
e6e5ad80
FB		 602 }
603}
604
605static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
606 int off_pitch, int bytesperline,
607 int lines)
608{
609 int y;
610 int off_cur;
611 int off_cur_end;
612
613 for (y = 0; y < lines; y++) {
614 off_cur = off_begin;
b2eb849d 615 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 616 off_cur &= TARGET_PAGE_MASK;
617 while (off_cur < off_cur_end) {
b1950430 618 memory_region_set_dirty(&s->vga.vram, off_cur);
e6e5ad80
FB		 619 off_cur += TARGET_PAGE_SIZE;
620 }
621 off_begin += off_pitch;
622 }
623}
624
e6e5ad80
FB		 625static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
626 const uint8_t * src)
627{
e6e5ad80 628 uint8_t *dst;
e6e5ad80 629
4e12cd94 630 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 631
632 if (BLTUNSAFE(s))
633 return 0;
634
e69390ce 635 (*s->cirrus_rop) (s, dst, src,
5fafdf24 636 s->cirrus_blt_dstpitch, 0,
e69390ce 637 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 638 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 639 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
640 s->cirrus_blt_height);
e6e5ad80
FB		 641 return 1;
642}
643
a21ae81d
FB		 644/* fill */
645
a5082316 646static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 647{
a5082316 648 cirrus_fill_t rop_func;
a21ae81d 649
b2eb849d
AJ		 650 if (BLTUNSAFE(s))
651 return 0;
a5082316 652 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 653 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 654 s->cirrus_blt_dstpitch,
655 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 656 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
657 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
658 s->cirrus_blt_height);
659 cirrus_bitblt_reset(s);
660 return 1;
661}
662
e6e5ad80
FB		 663/***************************************
664 *
665 * bitblt (video-to-video)
666 *
667 ***************************************/
668
669static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
670{
671 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 672 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 673 s->cirrus_addr_mask));
e6e5ad80
FB		 674}
675
24236869 676static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 677{
78935c4a
AJ		 678 int sx = 0, sy = 0;
679 int dx = 0, dy = 0;
680 int depth = 0;
24236869
FB		 681 int notify = 0;
682
92d675d1
AJ		 683 /* make sure to only copy if it's a plain copy ROP */
684 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
685 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 686
92d675d1
AJ		 687 int width, height;
688
689 depth = s->vga.get_bpp(&s->vga) / 8;
690 s->vga.get_resolution(&s->vga, &width, &height);
691
692 /* extra x, y */
693 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
694 sy = (src / ABS(s->cirrus_blt_srcpitch));
695 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
696 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 697
92d675d1
AJ		 698 /* normalize width */
699 w /= depth;
24236869 700
92d675d1
AJ		 701 /* if we're doing a backward copy, we have to adjust
702 our x/y to be the upper left corner (instead of the lower
703 right corner) */
704 if (s->cirrus_blt_dstpitch < 0) {
705 sx -= (s->cirrus_blt_width / depth) - 1;
706 dx -= (s->cirrus_blt_width / depth) - 1;
707 sy -= s->cirrus_blt_height - 1;
708 dy -= s->cirrus_blt_height - 1;
709 }
710
711 /* are we in the visible portion of memory? */
712 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
713 (sx + w) <= width && (sy + h) <= height &&
714 (dx + w) <= width && (dy + h) <= height) {
715 notify = 1;
716 }
717 }
24236869
FB		 718
719 /* we have to flush all pending changes so that the copy
720 is generated at the appropriate moment in time */
721 if (notify)
722 vga_hw_update();
723
4e12cd94 724 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 725 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 726 s->vga.vram_ptr +
b2eb849d 727 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 728 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
729 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 730
731 if (notify)
4e12cd94 732 qemu_console_copy(s->vga.ds,
38334f76
AZ		 733 sx, sy, dx, dy,
734 s->cirrus_blt_width / depth,
735 s->cirrus_blt_height);
24236869
FB		 736
737 /* we don't have to notify the display that this portion has
38334f76 738 changed since qemu_console_copy implies this */
24236869 739
31c05501
AL		 740 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
741 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
742 s->cirrus_blt_height);
24236869
FB		 743}
744
745static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
746{
65d35a09
AJ		 747 if (BLTUNSAFE(s))
748 return 0;
749
4e12cd94
AK		 750 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
751 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 752 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 753
e6e5ad80
FB		 754 return 1;
755}
756
757/***************************************
758 *
759 * bitblt (cpu-to-video)
760 *
761 ***************************************/
762
e6e5ad80
FB		 763static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
764{
765 int copy_count;
a5082316 766 uint8_t *end_ptr;
3b46e624 767
e6e5ad80 768 if (s->cirrus_srccounter > 0) {
a5082316
FB		 769 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
770 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
771 the_end:
772 s->cirrus_srccounter = 0;
773 cirrus_bitblt_reset(s);
774 } else {
775 /* at least one scan line */
776 do {
4e12cd94 777 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 778 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
779 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 780 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
781 s->cirrus_blt_width, 1);
782 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
783 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
784 if (s->cirrus_srccounter <= 0)
785 goto the_end;
786 /* more bytes than needed can be transfered because of
787 word alignment, so we keep them for the next line */
788 /* XXX: keep alignment to speed up transfer */
789 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
790 copy_count = s->cirrus_srcptr_end - end_ptr;
791 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
792 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
793 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
794 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
795 }
e6e5ad80
FB		 796 }
797}
798
799/***************************************
800 *
801 * bitblt wrapper
802 *
803 ***************************************/
804
805static void cirrus_bitblt_reset(CirrusVGAState * s)
806{
f8b237af
AL		 807 int need_update;
808
4e12cd94 809 s->vga.gr[0x31] &=
e6e5ad80 810 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 811 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
812 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 813 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
814 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
815 s->cirrus_srccounter = 0;
f8b237af
AL		 816 if (!need_update)
817 return;
8926b517 818 cirrus_update_memory_access(s);
e6e5ad80
FB		 819}
820
821static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
822{
a5082316
FB		 823 int w;
824
e6e5ad80
FB		 825 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
826 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
827 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
828
829 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
830 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 831 s->cirrus_blt_srcpitch = 8;
e6e5ad80 832 } else {
b30d4608 833 /* XXX: check for 24 bpp */
a5082316 834 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 835 }
a5082316 836 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 837 } else {
838 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 839 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 840 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 841 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
842 else
843 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 844 } else {
c9c0eae8
FB		 845 /* always align input size to 32 bits */
846 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 847 }
a5082316 848 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 849 }
a5082316
FB		 850 s->cirrus_srcptr = s->cirrus_bltbuf;
851 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 852 cirrus_update_memory_access(s);
e6e5ad80
FB		 853 return 1;
854}
855
856static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
857{
858 /* XXX */
a5082316 859#ifdef DEBUG_BITBLT
e6e5ad80
FB		 860 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
861#endif
862 return 0;
863}
864
865static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
866{
867 int ret;
868
869 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
870 ret = cirrus_bitblt_videotovideo_patterncopy(s);
871 } else {
872 ret = cirrus_bitblt_videotovideo_copy(s);
873 }
e6e5ad80
FB		 874 if (ret)
875 cirrus_bitblt_reset(s);
876 return ret;
877}
878
879static void cirrus_bitblt_start(CirrusVGAState * s)
880{
881 uint8_t blt_rop;
882
4e12cd94 883 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 884
4e12cd94
AK		 885 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
886 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
887 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
888 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 889 s->cirrus_blt_dstaddr =
4e12cd94 890 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 891 s->cirrus_blt_srcaddr =
4e12cd94
AK		 892 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
893 s->cirrus_blt_mode = s->vga.gr[0x30];
894 s->cirrus_blt_modeext = s->vga.gr[0x33];
895 blt_rop = s->vga.gr[0x32];
e6e5ad80 896
a21ae81d 897#ifdef DEBUG_BITBLT
0b74ed78 898 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 899 blt_rop,
a21ae81d 900 s->cirrus_blt_mode,
a5082316 901 s->cirrus_blt_modeext,
a21ae81d
FB		 902 s->cirrus_blt_width,
903 s->cirrus_blt_height,
904 s->cirrus_blt_dstpitch,
905 s->cirrus_blt_srcpitch,
906 s->cirrus_blt_dstaddr,
a5082316 907 s->cirrus_blt_srcaddr,
4e12cd94 908 s->vga.gr[0x2f]);
a21ae81d
FB		 909#endif
910
e6e5ad80
FB		 911 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
912 case CIRRUS_BLTMODE_PIXELWIDTH8:
913 s->cirrus_blt_pixelwidth = 1;
914 break;
915 case CIRRUS_BLTMODE_PIXELWIDTH16:
916 s->cirrus_blt_pixelwidth = 2;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH24:
919 s->cirrus_blt_pixelwidth = 3;
920 break;
921 case CIRRUS_BLTMODE_PIXELWIDTH32:
922 s->cirrus_blt_pixelwidth = 4;
923 break;
924 default:
a5082316 925#ifdef DEBUG_BITBLT
e6e5ad80
FB		 926 printf("cirrus: bitblt - pixel width is unknown\n");
927#endif
928 goto bitblt_ignore;
929 }
930 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
931
932 if ((s->
933 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
934 CIRRUS_BLTMODE_MEMSYSDEST))
935 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 936#ifdef DEBUG_BITBLT
e6e5ad80
FB		 937 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
938#endif
939 goto bitblt_ignore;
940 }
941
a5082316 942 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 943 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 944 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 945 CIRRUS_BLTMODE_PATTERNCOPY |
946 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 947 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 948 cirrus_bitblt_fgcol(s);
949 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 950 } else {
5fafdf24
TS		 951 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
952 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 953 CIRRUS_BLTMODE_COLOREXPAND) {
954
955 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 956 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 957 cirrus_bitblt_bgcol(s);
b30d4608 958 else
4c8732d7 959 cirrus_bitblt_fgcol(s);
b30d4608 960 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 961 } else {
962 cirrus_bitblt_fgcol(s);
963 cirrus_bitblt_bgcol(s);
964 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
965 }
e69390ce 966 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 967 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
968 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
969 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
970 cirrus_bitblt_bgcol(s);
971 else
972 cirrus_bitblt_fgcol(s);
973 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
974 } else {
975 cirrus_bitblt_fgcol(s);
976 cirrus_bitblt_bgcol(s);
977 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
978 }
979 } else {
980 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
981 }
a21ae81d 982 } else {
96cf2df8
TS		 983 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
984 if (s->cirrus_blt_pixelwidth > 2) {
985 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
986 goto bitblt_ignore;
987 }
988 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
989 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
990 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
991 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
992 } else {
993 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
994 }
995 } else {
996 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
997 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
998 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
999 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1000 } else {
1001 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1002 }
1003 }
1004 }
a21ae81d
FB		 1005 // setup bitblt engine.
1006 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1007 if (!cirrus_bitblt_cputovideo(s))
1008 goto bitblt_ignore;
1009 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1010 if (!cirrus_bitblt_videotocpu(s))
1011 goto bitblt_ignore;
1012 } else {
1013 if (!cirrus_bitblt_videotovideo(s))
1014 goto bitblt_ignore;
1015 }
e6e5ad80 1016 }
e6e5ad80
FB		 1017 return;
1018 bitblt_ignore:;
1019 cirrus_bitblt_reset(s);
1020}
1021
1022static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1023{
1024 unsigned old_value;
1025
4e12cd94
AK		 1026 old_value = s->vga.gr[0x31];
1027 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1028
1029 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1030 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1031 cirrus_bitblt_reset(s);
1032 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1033 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1034 cirrus_bitblt_start(s);
1035 }
1036}
1037
1038
1039/***************************************
1040 *
1041 * basic parameters
1042 *
1043 ***************************************/
1044
a4a2f59c 1045static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1046 uint32_t *pline_offset,
1047 uint32_t *pstart_addr,
1048 uint32_t *pline_compare)
e6e5ad80 1049{
4e12cd94 1050 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1051 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1052
4e12cd94
AK		 1053 line_offset = s->vga.cr[0x13]
1054 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1055 line_offset <<= 3;
1056 *pline_offset = line_offset;
1057
4e12cd94
AK		 1058 start_addr = (s->vga.cr[0x0c] << 8)
1059 | s->vga.cr[0x0d]
1060 | ((s->vga.cr[0x1b] & 0x01) << 16)
1061 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1062 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1063 *pstart_addr = start_addr;
83acc96b 1064
4e12cd94
AK		 1065 line_compare = s->vga.cr[0x18] |
1066 ((s->vga.cr[0x07] & 0x10) << 4) |
1067 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1068 *pline_compare = line_compare;
e6e5ad80
FB		 1069}
1070
1071static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1072{
1073 uint32_t ret = 16;
1074
1075 switch (s->cirrus_hidden_dac_data & 0xf) {
1076 case 0:
1077 ret = 15;
1078 break; /* Sierra HiColor */
1079 case 1:
1080 ret = 16;
1081 break; /* XGA HiColor */
1082 default:
1083#ifdef DEBUG_CIRRUS
1084 printf("cirrus: invalid DAC value %x in 16bpp\n",
1085 (s->cirrus_hidden_dac_data & 0xf));
1086#endif
1087 ret = 15; /* XXX */
1088 break;
1089 }
1090 return ret;
1091}
1092
a4a2f59c 1093static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1094{
4e12cd94 1095 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1096 uint32_t ret = 8;
1097
4e12cd94 1098 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1099 /* Cirrus SVGA */
4e12cd94 1100 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1101 case CIRRUS_SR7_BPP_8:
1102 ret = 8;
1103 break;
1104 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1105 ret = cirrus_get_bpp16_depth(s);
1106 break;
1107 case CIRRUS_SR7_BPP_24:
1108 ret = 24;
1109 break;
1110 case CIRRUS_SR7_BPP_16:
1111 ret = cirrus_get_bpp16_depth(s);
1112 break;
1113 case CIRRUS_SR7_BPP_32:
1114 ret = 32;
1115 break;
1116 default:
1117#ifdef DEBUG_CIRRUS
4e12cd94 1118 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1119#endif
1120 ret = 8;
1121 break;
1122 }
1123 } else {
1124 /* VGA */
aeb3c85f 1125 ret = 0;
e6e5ad80
FB		 1126 }
1127
1128 return ret;
1129}
1130
a4a2f59c 1131static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1132{
1133 int width, height;
3b46e624 1134
78e127ef 1135 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1136 height = s->cr[0x12] |
1137 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1138 ((s->cr[0x07] & 0x40) << 3);
1139 height = (height + 1);
1140 /* interlace support */
1141 if (s->cr[0x1a] & 0x01)
1142 height = height * 2;
1143 *pwidth = width;
1144 *pheight = height;
1145}
1146
e6e5ad80
FB		 1147/***************************************
1148 *
1149 * bank memory
1150 *
1151 ***************************************/
1152
1153static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1154{
1155 unsigned offset;
1156 unsigned limit;
1157
4e12cd94
AK		 1158 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1159 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1160 else /* single bank */
4e12cd94 1161 offset = s->vga.gr[0x09];
e6e5ad80 1162
4e12cd94 1163 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1164 offset <<= 14;
1165 else
1166 offset <<= 12;
1167
e3a4e4b6 1168 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1169 limit = 0;
1170 else
e3a4e4b6 1171 limit = s->real_vram_size - offset;
e6e5ad80 1172
4e12cd94 1173 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1174 if (limit > 0x8000) {
1175 offset += 0x8000;
1176 limit -= 0x8000;
1177 } else {
1178 limit = 0;
1179 }
1180 }
1181
1182 if (limit > 0) {
1183 s->cirrus_bank_base[bank_index] = offset;
1184 s->cirrus_bank_limit[bank_index] = limit;
1185 } else {
1186 s->cirrus_bank_base[bank_index] = 0;
1187 s->cirrus_bank_limit[bank_index] = 0;
1188 }
1189}
1190
1191/***************************************
1192 *
1193 * I/O access between 0x3c4-0x3c5
1194 *
1195 ***************************************/
1196
8a82c322 1197static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1198{
8a82c322 1199 switch (s->vga.sr_index) {
e6e5ad80
FB		 1200 case 0x00: // Standard VGA
1201 case 0x01: // Standard VGA
1202 case 0x02: // Standard VGA
1203 case 0x03: // Standard VGA
1204 case 0x04: // Standard VGA
8a82c322 1205 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1206 case 0x06: // Unlock Cirrus extensions
8a82c322 1207 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1208 case 0x10:
1209 case 0x30:
1210 case 0x50:
1211 case 0x70: // Graphics Cursor X
1212 case 0x90:
1213 case 0xb0:
1214 case 0xd0:
1215 case 0xf0: // Graphics Cursor X
8a82c322 1216 return s->vga.sr[0x10];
e6e5ad80
FB		 1217 case 0x11:
1218 case 0x31:
1219 case 0x51:
1220 case 0x71: // Graphics Cursor Y
1221 case 0x91:
1222 case 0xb1:
1223 case 0xd1:
a5082316 1224 case 0xf1: // Graphics Cursor Y
8a82c322 1225 return s->vga.sr[0x11];
aeb3c85f
FB		 1226 case 0x05: // ???
1227 case 0x07: // Extended Sequencer Mode
1228 case 0x08: // EEPROM Control
1229 case 0x09: // Scratch Register 0
1230 case 0x0a: // Scratch Register 1
1231 case 0x0b: // VCLK 0
1232 case 0x0c: // VCLK 1
1233 case 0x0d: // VCLK 2
1234 case 0x0e: // VCLK 3
1235 case 0x0f: // DRAM Control
e6e5ad80
FB		 1236 case 0x12: // Graphics Cursor Attribute
1237 case 0x13: // Graphics Cursor Pattern Address
1238 case 0x14: // Scratch Register 2
1239 case 0x15: // Scratch Register 3
1240 case 0x16: // Performance Tuning Register
1241 case 0x17: // Configuration Readback and Extended Control
1242 case 0x18: // Signature Generator Control
1243 case 0x19: // Signal Generator Result
1244 case 0x1a: // Signal Generator Result
1245 case 0x1b: // VCLK 0 Denominator & Post
1246 case 0x1c: // VCLK 1 Denominator & Post
1247 case 0x1d: // VCLK 2 Denominator & Post
1248 case 0x1e: // VCLK 3 Denominator & Post
1249 case 0x1f: // BIOS Write Enable and MCLK select
1250#ifdef DEBUG_CIRRUS
8a82c322 1251 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1252#endif
8a82c322 1253 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1254 default:
1255#ifdef DEBUG_CIRRUS
8a82c322 1256 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1257#endif
8a82c322 1258 return 0xff;
e6e5ad80
FB		 1259 break;
1260 }
e6e5ad80
FB		 1261}
1262
31c63201 1263static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1264{
31c63201 1265 switch (s->vga.sr_index) {
e6e5ad80
FB		 1266 case 0x00: // Standard VGA
1267 case 0x01: // Standard VGA
1268 case 0x02: // Standard VGA
1269 case 0x03: // Standard VGA
1270 case 0x04: // Standard VGA
31c63201
JQ		 1271 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1272 if (s->vga.sr_index == 1)
1273 s->vga.update_retrace_info(&s->vga);
1274 break;
e6e5ad80 1275 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1276 val &= 0x17;
1277 if (val == 0x12) {
1278 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1279 } else {
31c63201 1280 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1281 }
1282 break;
1283 case 0x10:
1284 case 0x30:
1285 case 0x50:
1286 case 0x70: // Graphics Cursor X
1287 case 0x90:
1288 case 0xb0:
1289 case 0xd0:
1290 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1291 s->vga.sr[0x10] = val;
1292 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1293 break;
1294 case 0x11:
1295 case 0x31:
1296 case 0x51:
1297 case 0x71: // Graphics Cursor Y
1298 case 0x91:
1299 case 0xb1:
1300 case 0xd1:
1301 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1302 s->vga.sr[0x11] = val;
1303 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1304 break;
1305 case 0x07: // Extended Sequencer Mode
2bec46dc 1306 cirrus_update_memory_access(s);
e6e5ad80
FB		 1307 case 0x08: // EEPROM Control
1308 case 0x09: // Scratch Register 0
1309 case 0x0a: // Scratch Register 1
1310 case 0x0b: // VCLK 0
1311 case 0x0c: // VCLK 1
1312 case 0x0d: // VCLK 2
1313 case 0x0e: // VCLK 3
1314 case 0x0f: // DRAM Control
1315 case 0x12: // Graphics Cursor Attribute
1316 case 0x13: // Graphics Cursor Pattern Address
1317 case 0x14: // Scratch Register 2
1318 case 0x15: // Scratch Register 3
1319 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1320 case 0x18: // Signature Generator Control
1321 case 0x19: // Signature Generator Result
1322 case 0x1a: // Signature Generator Result
1323 case 0x1b: // VCLK 0 Denominator & Post
1324 case 0x1c: // VCLK 1 Denominator & Post
1325 case 0x1d: // VCLK 2 Denominator & Post
1326 case 0x1e: // VCLK 3 Denominator & Post
1327 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1328 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1329#ifdef DEBUG_CIRRUS
1330 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1331 s->vga.sr_index, val);
e6e5ad80
FB		 1332#endif
1333 break;
8926b517 1334 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1335 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1336 | (val & 0xc7);
8926b517
FB		 1337 cirrus_update_memory_access(s);
1338 break;
e6e5ad80
FB		 1339 default:
1340#ifdef DEBUG_CIRRUS
31c63201
JQ		 1341 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1342 s->vga.sr_index, val);
e6e5ad80
FB		 1343#endif
1344 break;
1345 }
e6e5ad80
FB		 1346}
1347
1348/***************************************
1349 *
1350 * I/O access at 0x3c6
1351 *
1352 ***************************************/
1353
957c9db5 1354static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1355{
a21ae81d 1356 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1357 s->cirrus_hidden_dac_lockindex = 0;
1358 return s->cirrus_hidden_dac_data;
e6e5ad80 1359 }
957c9db5 1360 return 0xff;
e6e5ad80
FB		 1361}
1362
1363static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1364{
1365 if (s->cirrus_hidden_dac_lockindex == 4) {
1366 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1367#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1368 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1369#endif
1370 }
1371 s->cirrus_hidden_dac_lockindex = 0;
1372}
1373
1374/***************************************
1375 *
1376 * I/O access at 0x3c9
1377 *
1378 ***************************************/
1379
5deaeee3 1380static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1381{
5deaeee3
JQ		 1382 int val;
1383
1384 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1385 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1386 s->vga.dac_sub_index];
1387 } else {
1388 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1389 }
4e12cd94
AK		 1390 if (++s->vga.dac_sub_index == 3) {
1391 s->vga.dac_sub_index = 0;
1392 s->vga.dac_read_index++;
e6e5ad80 1393 }
5deaeee3 1394 return val;
e6e5ad80
FB		 1395}
1396
86948bb1 1397static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1398{
4e12cd94
AK		 1399 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1400 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1401 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1402 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1403 s->vga.dac_cache, 3);
1404 } else {
1405 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1406 }
a5082316 1407 /* XXX update cursor */
4e12cd94
AK		 1408 s->vga.dac_sub_index = 0;
1409 s->vga.dac_write_index++;
e6e5ad80 1410 }
e6e5ad80
FB		 1411}
1412
1413/***************************************
1414 *
1415 * I/O access between 0x3ce-0x3cf
1416 *
1417 ***************************************/
1418
f705db9d 1419static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1420{
1421 switch (reg_index) {
aeb3c85f 1422 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1423 return s->cirrus_shadow_gr0;
aeb3c85f 1424 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1425 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1426 case 0x02: // Standard VGA
1427 case 0x03: // Standard VGA
1428 case 0x04: // Standard VGA
1429 case 0x06: // Standard VGA
1430 case 0x07: // Standard VGA
1431 case 0x08: // Standard VGA
f705db9d 1432 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1433 case 0x05: // Standard VGA, Cirrus extended mode
1434 default:
1435 break;
1436 }
1437
1438 if (reg_index < 0x3a) {
f705db9d 1439 return s->vga.gr[reg_index];
e6e5ad80
FB		 1440 } else {
1441#ifdef DEBUG_CIRRUS
1442 printf("cirrus: inport gr_index %02x\n", reg_index);
1443#endif
f705db9d 1444 return 0xff;
e6e5ad80 1445 }
e6e5ad80
FB		 1446}
1447
22286bc6
JQ		 1448static void
1449cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1450{
a5082316
FB		 1451#if defined(DEBUG_BITBLT) && 0
1452 printf("gr%02x: %02x\n", reg_index, reg_value);
1453#endif
e6e5ad80
FB		 1454 switch (reg_index) {
1455 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1456 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1457 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1458 break;
e6e5ad80 1459 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1460 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1461 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1462 break;
e6e5ad80
FB		 1463 case 0x02: // Standard VGA
1464 case 0x03: // Standard VGA
1465 case 0x04: // Standard VGA
1466 case 0x06: // Standard VGA
1467 case 0x07: // Standard VGA
1468 case 0x08: // Standard VGA
22286bc6
JQ		 1469 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1470 break;
e6e5ad80 1471 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1472 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1473 cirrus_update_memory_access(s);
e6e5ad80
FB		 1474 break;
1475 case 0x09: // bank offset #0
1476 case 0x0A: // bank offset #1
4e12cd94 1477 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1478 cirrus_update_bank_ptr(s, 0);
1479 cirrus_update_bank_ptr(s, 1);
2bec46dc 1480 cirrus_update_memory_access(s);
8926b517 1481 break;
e6e5ad80 1482 case 0x0B:
4e12cd94 1483 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1484 cirrus_update_bank_ptr(s, 0);
1485 cirrus_update_bank_ptr(s, 1);
8926b517 1486 cirrus_update_memory_access(s);
e6e5ad80
FB		 1487 break;
1488 case 0x10: // BGCOLOR 0x0000ff00
1489 case 0x11: // FGCOLOR 0x0000ff00
1490 case 0x12: // BGCOLOR 0x00ff0000
1491 case 0x13: // FGCOLOR 0x00ff0000
1492 case 0x14: // BGCOLOR 0xff000000
1493 case 0x15: // FGCOLOR 0xff000000
1494 case 0x20: // BLT WIDTH 0x0000ff
1495 case 0x22: // BLT HEIGHT 0x0000ff
1496 case 0x24: // BLT DEST PITCH 0x0000ff
1497 case 0x26: // BLT SRC PITCH 0x0000ff
1498 case 0x28: // BLT DEST ADDR 0x0000ff
1499 case 0x29: // BLT DEST ADDR 0x00ff00
1500 case 0x2c: // BLT SRC ADDR 0x0000ff
1501 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1502 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1503 case 0x30: // BLT MODE
1504 case 0x32: // RASTER OP
a21ae81d 1505 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1506 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1507 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1508 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1509 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1510 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1511 break;
1512 case 0x21: // BLT WIDTH 0x001f00
1513 case 0x23: // BLT HEIGHT 0x001f00
1514 case 0x25: // BLT DEST PITCH 0x001f00
1515 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1516 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1517 break;
1518 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1520 /* if auto start mode, starts bit blt now */
4e12cd94 1521 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1522 cirrus_bitblt_start(s);
1523 }
1524 break;
e6e5ad80 1525 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1526 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1527 break;
1528 case 0x31: // BLT STATUS/START
1529 cirrus_write_bitblt(s, reg_value);
1530 break;
1531 default:
1532#ifdef DEBUG_CIRRUS
1533 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1534 reg_value);
1535#endif
1536 break;
1537 }
e6e5ad80
FB		 1538}
1539
1540/***************************************
1541 *
1542 * I/O access between 0x3d4-0x3d5
1543 *
1544 ***************************************/
1545
b863d514 1546static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1547{
1548 switch (reg_index) {
1549 case 0x00: // Standard VGA
1550 case 0x01: // Standard VGA
1551 case 0x02: // Standard VGA
1552 case 0x03: // Standard VGA
1553 case 0x04: // Standard VGA
1554 case 0x05: // Standard VGA
1555 case 0x06: // Standard VGA
1556 case 0x07: // Standard VGA
1557 case 0x08: // Standard VGA
1558 case 0x09: // Standard VGA
1559 case 0x0a: // Standard VGA
1560 case 0x0b: // Standard VGA
1561 case 0x0c: // Standard VGA
1562 case 0x0d: // Standard VGA
1563 case 0x0e: // Standard VGA
1564 case 0x0f: // Standard VGA
1565 case 0x10: // Standard VGA
1566 case 0x11: // Standard VGA
1567 case 0x12: // Standard VGA
1568 case 0x13: // Standard VGA
1569 case 0x14: // Standard VGA
1570 case 0x15: // Standard VGA
1571 case 0x16: // Standard VGA
1572 case 0x17: // Standard VGA
1573 case 0x18: // Standard VGA
b863d514 1574 return s->vga.cr[s->vga.cr_index];
ca896ef3 1575 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1576 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1577 case 0x19: // Interlace End
1578 case 0x1a: // Miscellaneous Control
1579 case 0x1b: // Extended Display Control
1580 case 0x1c: // Sync Adjust and Genlock
1581 case 0x1d: // Overlay Extended Control
1582 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1583 case 0x25: // Part Status
1584 case 0x27: // Part ID (R)
b863d514 1585 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1586 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1587 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1588 break;
1589 default:
1590#ifdef DEBUG_CIRRUS
1591 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1592#endif
b863d514 1593 return 0xff;
e6e5ad80 1594 }
e6e5ad80
FB		 1595}
1596
4ec1ce04 1597static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1598{
4ec1ce04 1599 switch (s->vga.cr_index) {
e6e5ad80
FB		 1600 case 0x00: // Standard VGA
1601 case 0x01: // Standard VGA
1602 case 0x02: // Standard VGA
1603 case 0x03: // Standard VGA
1604 case 0x04: // Standard VGA
1605 case 0x05: // Standard VGA
1606 case 0x06: // Standard VGA
1607 case 0x07: // Standard VGA
1608 case 0x08: // Standard VGA
1609 case 0x09: // Standard VGA
1610 case 0x0a: // Standard VGA
1611 case 0x0b: // Standard VGA
1612 case 0x0c: // Standard VGA
1613 case 0x0d: // Standard VGA
1614 case 0x0e: // Standard VGA
1615 case 0x0f: // Standard VGA
1616 case 0x10: // Standard VGA
1617 case 0x11: // Standard VGA
1618 case 0x12: // Standard VGA
1619 case 0x13: // Standard VGA
1620 case 0x14: // Standard VGA
1621 case 0x15: // Standard VGA
1622 case 0x16: // Standard VGA
1623 case 0x17: // Standard VGA
1624 case 0x18: // Standard VGA
4ec1ce04
JQ		 1625 /* handle CR0-7 protection */
1626 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1627 /* can always write bit 4 of CR7 */
1628 if (s->vga.cr_index == 7)
1629 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1630 return;
1631 }
1632 s->vga.cr[s->vga.cr_index] = reg_value;
1633 switch(s->vga.cr_index) {
1634 case 0x00:
1635 case 0x04:
1636 case 0x05:
1637 case 0x06:
1638 case 0x07:
1639 case 0x11:
1640 case 0x17:
1641 s->vga.update_retrace_info(&s->vga);
1642 break;
1643 }
1644 break;
e6e5ad80
FB		 1645 case 0x19: // Interlace End
1646 case 0x1a: // Miscellaneous Control
1647 case 0x1b: // Extended Display Control
1648 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1649 case 0x1d: // Overlay Extended Control
4ec1ce04 1650 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1651#ifdef DEBUG_CIRRUS
1652 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1653 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1654#endif
1655 break;
1656 case 0x22: // Graphics Data Latches Readback (R)
1657 case 0x24: // Attribute Controller Toggle Readback (R)
1658 case 0x26: // Attribute Controller Index Readback (R)
1659 case 0x27: // Part ID (R)
1660 break;
e6e5ad80
FB		 1661 case 0x25: // Part Status
1662 default:
1663#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1664 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1665 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1666#endif
1667 break;
1668 }
e6e5ad80
FB		 1669}
1670
1671/***************************************
1672 *
1673 * memory-mapped I/O (bitblt)
1674 *
1675 ***************************************/
1676
1677static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1678{
1679 int value = 0xff;
1680
1681 switch (address) {
1682 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1683 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1684 break;
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1747 break;
1748 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTMODE:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTROP:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1756 break;
a21ae81d 1757 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1759 break;
e6e5ad80 1760 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1762 break;
1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1771 break;
1772 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1774 break;
1775 default:
1776#ifdef DEBUG_CIRRUS
1777 printf("cirrus: mmio read - address 0x%04x\n", address);
1778#endif
1779 break;
1780 }
1781
1782 return (uint8_t) value;
1783}
1784
1785static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1786 uint8_t value)
1787{
1788 switch (address) {
1789 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1790 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1791 break;
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1793 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1796 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1799 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1802 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1805 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1808 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1811 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1814 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1817 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1820 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1823 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1826 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1829 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1832 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1835 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1838 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1841 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1844 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1847 /* ignored */
1848 break;
1849 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1850 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1857 break;
1858 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1859 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTMODE:
22286bc6 1862 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTROP:
22286bc6 1865 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1866 break;
a21ae81d 1867 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1868 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1869 break;
e6e5ad80 1870 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1871 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1872 break;
1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1874 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1877 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1880 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1881 break;
1882 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1883 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1884 break;
1885 default:
1886#ifdef DEBUG_CIRRUS
1887 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1888 address, value);
1889#endif
1890 break;
1891 }
1892}
1893
e6e5ad80
FB		 1894/***************************************
1895 *
1896 * write mode 4/5
1897 *
1898 * assume TARGET_PAGE_SIZE >= 16
1899 *
1900 ***************************************/
1901
1902static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1903 unsigned mode,
1904 unsigned offset,
1905 uint32_t mem_value)
1906{
1907 int x;
1908 unsigned val = mem_value;
1909 uint8_t *dst;
1910
4e12cd94 1911 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1912 for (x = 0; x < 8; x++) {
1913 if (val & 0x80) {
0b74ed78 1914 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1915 } else if (mode == 5) {
0b74ed78 1916 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1917 }
1918 val <<= 1;
0b74ed78 1919 dst++;
e6e5ad80 1920 }
b1950430
AK		 1921 memory_region_set_dirty(&s->vga.vram, offset);
1922 memory_region_set_dirty(&s->vga.vram, offset + 7);
e6e5ad80
FB		 1923}
1924
1925static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1926 unsigned mode,
1927 unsigned offset,
1928 uint32_t mem_value)
1929{
1930 int x;
1931 unsigned val = mem_value;
1932 uint8_t *dst;
1933
4e12cd94 1934 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1935 for (x = 0; x < 8; x++) {
1936 if (val & 0x80) {
0b74ed78 1937 *dst = s->cirrus_shadow_gr1;
4e12cd94 1938 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1939 } else if (mode == 5) {
0b74ed78 1940 *dst = s->cirrus_shadow_gr0;
4e12cd94 1941 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1942 }
1943 val <<= 1;
0b74ed78 1944 dst += 2;
e6e5ad80 1945 }
b1950430
AK		 1946 memory_region_set_dirty(&s->vga.vram, offset);
1947 memory_region_set_dirty(&s->vga.vram, offset + 15);
e6e5ad80
FB		 1948}
1949
1950/***************************************
1951 *
1952 * memory access between 0xa0000-0xbffff
1953 *
1954 ***************************************/
1955
a815b166
AK		 1956static uint64_t cirrus_vga_mem_read(void *opaque,
1957 target_phys_addr_t addr,
1958 uint32_t size)
e6e5ad80
FB		 1959{
1960 CirrusVGAState *s = opaque;
1961 unsigned bank_index;
1962 unsigned bank_offset;
1963 uint32_t val;
1964
4e12cd94 1965 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1966 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1967 }
1968
1969 if (addr < 0x10000) {
1970 /* XXX handle bitblt */
1971 /* video memory */
1972 bank_index = addr >> 15;
1973 bank_offset = addr & 0x7fff;
1974 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1975 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1976 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1977 bank_offset <<= 4;
4e12cd94 1978 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1979 bank_offset <<= 3;
1980 }
1981 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1982 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1983 } else
1984 val = 0xff;
1985 } else if (addr >= 0x18000 && addr < 0x18100) {
1986 /* memory-mapped I/O */
1987 val = 0xff;
4e12cd94 1988 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1989 val = cirrus_mmio_blt_read(s, addr & 0xff);
1990 }
1991 } else {
1992 val = 0xff;
1993#ifdef DEBUG_CIRRUS
0bf9e31a 1994 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1995#endif
1996 }
1997 return val;
1998}
1999
a815b166
AK		 2000static void cirrus_vga_mem_write(void *opaque,
2001 target_phys_addr_t addr,
2002 uint64_t mem_value,
2003 uint32_t size)
e6e5ad80
FB		 2004{
2005 CirrusVGAState *s = opaque;
2006 unsigned bank_index;
2007 unsigned bank_offset;
2008 unsigned mode;
2009
4e12cd94 2010 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2011 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2012 return;
2013 }
2014
2015 if (addr < 0x10000) {
2016 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2017 /* bitblt */
2018 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2019 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2020 cirrus_bitblt_cputovideo_next(s);
2021 }
2022 } else {
2023 /* video memory */
2024 bank_index = addr >> 15;
2025 bank_offset = addr & 0x7fff;
2026 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2027 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2028 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2029 bank_offset <<= 4;
4e12cd94 2030 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2031 bank_offset <<= 3;
2032 }
2033 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2034 mode = s->vga.gr[0x05] & 0x7;
2035 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2036 *(s->vga.vram_ptr + bank_offset) = mem_value;
b1950430 2037 memory_region_set_dirty(&s->vga.vram, bank_offset);
e6e5ad80 2038 } else {
4e12cd94 2039 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2040 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2041 bank_offset,
2042 mem_value);
2043 } else {
2044 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2045 bank_offset,
2046 mem_value);
2047 }
2048 }
2049 }
2050 }
2051 } else if (addr >= 0x18000 && addr < 0x18100) {
2052 /* memory-mapped I/O */
4e12cd94 2053 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2054 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2055 }
2056 } else {
2057#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2058 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2059 mem_value);
e6e5ad80
FB		 2060#endif
2061 }
2062}
2063
b1950430
AK		 2064static const MemoryRegionOps cirrus_vga_mem_ops = {
2065 .read = cirrus_vga_mem_read,
2066 .write = cirrus_vga_mem_write,
2067 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2068 .impl = {
2069 .min_access_size = 1,
2070 .max_access_size = 1,
2071 },
e6e5ad80
FB		 2072};
2073
a5082316
FB		 2074/***************************************
2075 *
2076 * hardware cursor
2077 *
2078 ***************************************/
2079
2080static inline void invalidate_cursor1(CirrusVGAState *s)
2081{
2082 if (s->last_hw_cursor_size) {
4e12cd94 2083 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2084 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2085 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2086 }
2087}
2088
2089static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2090{
2091 const uint8_t *src;
2092 uint32_t content;
2093 int y, y_min, y_max;
2094
4e12cd94
AK		 2095 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2096 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2097 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2098 y_min = 64;
2099 y_max = -1;
2100 for(y = 0; y < 64; y++) {
2101 content = ((uint32_t *)src)[0] |
2102 ((uint32_t *)src)[1] |
2103 ((uint32_t *)src)[2] |
2104 ((uint32_t *)src)[3];
2105 if (content) {
2106 if (y < y_min)
2107 y_min = y;
2108 if (y > y_max)
2109 y_max = y;
2110 }
2111 src += 16;
2112 }
2113 } else {
4e12cd94 2114 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2115 y_min = 32;
2116 y_max = -1;
2117 for(y = 0; y < 32; y++) {
2118 content = ((uint32_t *)src)[0] |
2119 ((uint32_t *)(src + 128))[0];
2120 if (content) {
2121 if (y < y_min)
2122 y_min = y;
2123 if (y > y_max)
2124 y_max = y;
2125 }
2126 src += 4;
2127 }
2128 }
2129 if (y_min > y_max) {
2130 s->last_hw_cursor_y_start = 0;
2131 s->last_hw_cursor_y_end = 0;
2132 } else {
2133 s->last_hw_cursor_y_start = y_min;
2134 s->last_hw_cursor_y_end = y_max + 1;
2135 }
2136}
2137
2138/* NOTE: we do not currently handle the cursor bitmap change, so we
2139 update the cursor only if it moves. */
a4a2f59c 2140static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2141{
4e12cd94 2142 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2143 int size;
2144
4e12cd94 2145 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2146 size = 0;
2147 } else {
4e12cd94 2148 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2149 size = 64;
2150 else
2151 size = 32;
2152 }
2153 /* invalidate last cursor and new cursor if any change */
2154 if (s->last_hw_cursor_size != size ||
2155 s->last_hw_cursor_x != s->hw_cursor_x ||
2156 s->last_hw_cursor_y != s->hw_cursor_y) {
2157
2158 invalidate_cursor1(s);
3b46e624 2159
a5082316
FB		 2160 s->last_hw_cursor_size = size;
2161 s->last_hw_cursor_x = s->hw_cursor_x;
2162 s->last_hw_cursor_y = s->hw_cursor_y;
2163 /* compute the real cursor min and max y */
2164 cirrus_cursor_compute_yrange(s);
2165 invalidate_cursor1(s);
2166 }
2167}
2168
a4a2f59c 2169static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2170{
4e12cd94 2171 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2172 int w, h, bpp, x1, x2, poffset;
2173 unsigned int color0, color1;
2174 const uint8_t *palette, *src;
2175 uint32_t content;
3b46e624 2176
4e12cd94 2177 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2178 return;
2179 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2180 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2181 h = 64;
2182 } else {
2183 h = 32;
2184 }
2185 if (scr_y < s->hw_cursor_y ||
2186 scr_y >= (s->hw_cursor_y + h))
2187 return;
3b46e624 2188
4e12cd94
AK		 2189 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2190 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2191 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2192 src += (scr_y - s->hw_cursor_y) * 16;
2193 poffset = 8;
2194 content = ((uint32_t *)src)[0] |
2195 ((uint32_t *)src)[1] |
2196 ((uint32_t *)src)[2] |
2197 ((uint32_t *)src)[3];
2198 } else {
4e12cd94 2199 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2200 src += (scr_y - s->hw_cursor_y) * 4;
2201 poffset = 128;
2202 content = ((uint32_t *)src)[0] |
2203 ((uint32_t *)(src + 128))[0];
2204 }
2205 /* if nothing to draw, no need to continue */
2206 if (!content)
2207 return;
2208 w = h;
2209
2210 x1 = s->hw_cursor_x;
4e12cd94 2211 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2212 return;
2213 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2214 if (x2 > s->vga.last_scr_width)
2215 x2 = s->vga.last_scr_width;
a5082316
FB		 2216 w = x2 - x1;
2217 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2218 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2219 c6_to_8(palette[0x0 * 3 + 1]),
2220 c6_to_8(palette[0x0 * 3 + 2]));
2221 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2222 c6_to_8(palette[0xf * 3 + 1]),
2223 c6_to_8(palette[0xf * 3 + 2]));
2224 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2225 d1 += x1 * bpp;
4e12cd94 2226 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2227 default:
2228 break;
2229 case 8:
2230 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2231 break;
2232 case 15:
2233 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2234 break;
2235 case 16:
2236 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2237 break;
2238 case 32:
2239 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2240 break;
2241 }
2242}
2243
e6e5ad80
FB		 2244/***************************************
2245 *
2246 * LFB memory access
2247 *
2248 ***************************************/
2249
899adf81
AK		 2250static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
2251 unsigned size)
e6e5ad80 2252{
e05587e8 2253 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2254 uint32_t ret;
2255
e6e5ad80
FB		 2256 addr &= s->cirrus_addr_mask;
2257
4e12cd94 2258 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2259 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2260 /* memory-mapped I/O */
2261 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2262 } else if (0) {
2263 /* XXX handle bitblt */
2264 ret = 0xff;
2265 } else {
2266 /* video memory */
4e12cd94 2267 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2268 addr <<= 4;
4e12cd94 2269 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2270 addr <<= 3;
2271 }
2272 addr &= s->cirrus_addr_mask;
4e12cd94 2273 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2274 }
2275
2276 return ret;
2277}
2278
899adf81
AK		 2279static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
2280 uint64_t val, unsigned size)
e6e5ad80 2281{
e05587e8 2282 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2283 unsigned mode;
2284
2285 addr &= s->cirrus_addr_mask;
3b46e624 2286
4e12cd94 2287 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2288 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2289 /* memory-mapped I/O */
2290 cirrus_mmio_blt_write(s, addr & 0xff, val);
2291 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2292 /* bitblt */
2293 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2294 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2295 cirrus_bitblt_cputovideo_next(s);
2296 }
2297 } else {
2298 /* video memory */
4e12cd94 2299 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2300 addr <<= 4;
4e12cd94 2301 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2302 addr <<= 3;
2303 }
2304 addr &= s->cirrus_addr_mask;
2305
4e12cd94
AK		 2306 mode = s->vga.gr[0x05] & 0x7;
2307 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2308 *(s->vga.vram_ptr + addr) = (uint8_t) val;
b1950430 2309 memory_region_set_dirty(&s->vga.vram, addr);
e6e5ad80 2310 } else {
4e12cd94 2311 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2312 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2313 } else {
2314 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2315 }
2316 }
2317 }
2318}
2319
a5082316
FB		 2320/***************************************
2321 *
2322 * system to screen memory access
2323 *
2324 ***************************************/
2325
2326
4e56f089
AK		 2327static uint64_t cirrus_linear_bitblt_read(void *opaque,
2328 target_phys_addr_t addr,
2329 unsigned size)
a5082316 2330{
4e56f089 2331 CirrusVGAState *s = opaque;
a5082316
FB		 2332 uint32_t ret;
2333
2334 /* XXX handle bitblt */
4e56f089 2335 (void)s;
a5082316
FB		 2336 ret = 0xff;
2337 return ret;
2338}
2339
4e56f089
AK		 2340static void cirrus_linear_bitblt_write(void *opaque,
2341 target_phys_addr_t addr,
2342 uint64_t val,
2343 unsigned size)
a5082316 2344{
e05587e8 2345 CirrusVGAState *s = opaque;
a5082316
FB		 2346
2347 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2348 /* bitblt */
2349 *s->cirrus_srcptr++ = (uint8_t) val;
2350 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2351 cirrus_bitblt_cputovideo_next(s);
2352 }
2353 }
2354}
2355
b1950430
AK		 2356static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2357 .read = cirrus_linear_bitblt_read,
2358 .write = cirrus_linear_bitblt_write,
2359 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2360 .impl = {
2361 .min_access_size = 1,
2362 .max_access_size = 1,
2363 },
a5082316
FB		 2364};
2365
b1950430 2366static void unmap_bank(CirrusVGAState *s, unsigned bank)
2bec46dc 2367{
b1950430
AK		 2368 if (s->cirrus_bank[bank]) {
2369 memory_region_del_subregion(&s->low_mem_container,
2370 s->cirrus_bank[bank]);
2371 memory_region_destroy(s->cirrus_bank[bank]);
7267c094 2372 g_free(s->cirrus_bank[bank]);
b1950430 2373 s->cirrus_bank[bank] = NULL;
2bec46dc 2374 }
b1950430 2375}
2bec46dc 2376
b1950430
AK		 2377static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2378{
2379 MemoryRegion *mr;
2380 static const char *names[] = { "vga.bank0", "vga.bank1" };
2bec46dc
AL		 2381
2382 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2383 && !((s->vga.sr[0x07] & 0x01) == 0)
2384 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2385 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc 2386
7267c094 2387 mr = g_malloc(sizeof(*mr));
b1950430
AK		 2388 memory_region_init_alias(mr, names[bank], &s->vga.vram,
2389 s->cirrus_bank_base[bank], 0x8000);
2390 memory_region_add_subregion_overlap(
2391 &s->low_mem_container,
2392 0x8000 * bank,
2393 mr,
2394 1);
2395 unmap_bank(s, bank);
2396 s->cirrus_bank[bank] = mr;
2397 } else {
2398 unmap_bank(s, bank);
2bec46dc 2399 }
b1950430 2400}
2bec46dc 2401
b1950430
AK		 2402static void map_linear_vram(CirrusVGAState *s)
2403{
2404 if (!s->linear_vram) {
2405 s->linear_vram = true;
2406 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2407 }
2408 map_linear_vram_bank(s, 0);
2409 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2410}
2411
2412static void unmap_linear_vram(CirrusVGAState *s)
2413{
b1950430
AK		 2414 if (s->linear_vram) {
2415 s->linear_vram = false;
2416 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2417 }
b1950430
AK		 2418 unmap_bank(s, 0);
2419 unmap_bank(s, 1);
2bec46dc
AL		 2420}
2421
8926b517
FB		 2422/* Compute the memory access functions */
2423static void cirrus_update_memory_access(CirrusVGAState *s)
2424{
2425 unsigned mode;
2426
4e12cd94 2427 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2428 goto generic_io;
2429 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2430 goto generic_io;
2431 } else {
4e12cd94 2432 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2433 goto generic_io;
4e12cd94 2434 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2435 goto generic_io;
2436 }
3b46e624 2437
4e12cd94
AK		 2438 mode = s->vga.gr[0x05] & 0x7;
2439 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2440 map_linear_vram(s);
8926b517
FB		 2441 } else {
2442 generic_io:
2bec46dc 2443 unmap_linear_vram(s);
8926b517
FB		 2444 }
2445 }
2446}
2447
2448
e6e5ad80
FB		 2449/* I/O ports */
2450
0ceac75b 2451static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2452{
b6343073
JQ		 2453 CirrusVGAState *c = opaque;
2454 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2455 int val, index;
2456
b6343073 2457 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2458 val = 0xff;
2459 } else {
2460 switch (addr) {
2461 case 0x3c0:
b6343073
JQ		 2462 if (s->ar_flip_flop == 0) {
2463 val = s->ar_index;
e6e5ad80
FB		 2464 } else {
2465 val = 0;
2466 }
2467 break;
2468 case 0x3c1:
b6343073 2469 index = s->ar_index & 0x1f;
e6e5ad80 2470 if (index < 21)
b6343073 2471 val = s->ar[index];
e6e5ad80
FB		 2472 else
2473 val = 0;
2474 break;
2475 case 0x3c2:
b6343073 2476 val = s->st00;
e6e5ad80
FB		 2477 break;
2478 case 0x3c4:
b6343073 2479 val = s->sr_index;
e6e5ad80
FB		 2480 break;
2481 case 0x3c5:
8a82c322
JQ		 2482 val = cirrus_vga_read_sr(c);
2483 break;
e6e5ad80 2484#ifdef DEBUG_VGA_REG
b6343073 2485 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2486#endif
2487 break;
2488 case 0x3c6:
957c9db5 2489 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2490 break;
2491 case 0x3c7:
b6343073 2492 val = s->dac_state;
e6e5ad80 2493 break;
ae184e4a 2494 case 0x3c8:
b6343073
JQ		 2495 val = s->dac_write_index;
2496 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2497 break;
2498 case 0x3c9:
5deaeee3
JQ		 2499 val = cirrus_vga_read_palette(c);
2500 break;
e6e5ad80 2501 case 0x3ca:
b6343073 2502 val = s->fcr;
e6e5ad80
FB		 2503 break;
2504 case 0x3cc:
b6343073 2505 val = s->msr;
e6e5ad80
FB		 2506 break;
2507 case 0x3ce:
b6343073 2508 val = s->gr_index;
e6e5ad80
FB		 2509 break;
2510 case 0x3cf:
f705db9d 2511 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2512#ifdef DEBUG_VGA_REG
b6343073 2513 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2514#endif
2515 break;
2516 case 0x3b4:
2517 case 0x3d4:
b6343073 2518 val = s->cr_index;
e6e5ad80
FB		 2519 break;
2520 case 0x3b5:
2521 case 0x3d5:
b863d514 2522 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2523#ifdef DEBUG_VGA_REG
b6343073 2524 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2525#endif
2526 break;
2527 case 0x3ba:
2528 case 0x3da:
2529 /* just toggle to fool polling */
b6343073
JQ		 2530 val = s->st01 = s->retrace(s);
2531 s->ar_flip_flop = 0;
e6e5ad80
FB		 2532 break;
2533 default:
2534 val = 0x00;
2535 break;
2536 }
2537 }
2538#if defined(DEBUG_VGA)
2539 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2540#endif
2541 return val;
2542}
2543
0ceac75b 2544static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2545{
b6343073
JQ		 2546 CirrusVGAState *c = opaque;
2547 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2548 int index;
2549
2550 /* check port range access depending on color/monochrome mode */
b6343073 2551 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2552 return;
25a18cbd 2553 }
e6e5ad80
FB		 2554#ifdef DEBUG_VGA
2555 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2556#endif
2557
2558 switch (addr) {
2559 case 0x3c0:
b6343073 2560 if (s->ar_flip_flop == 0) {
e6e5ad80 2561 val &= 0x3f;
b6343073 2562 s->ar_index = val;
e6e5ad80 2563 } else {
b6343073 2564 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2565 switch (index) {
2566 case 0x00 ... 0x0f:
b6343073 2567 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2568 break;
2569 case 0x10:
b6343073 2570 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2571 break;
2572 case 0x11:
b6343073 2573 s->ar[index] = val;
e6e5ad80
FB		 2574 break;
2575 case 0x12:
b6343073 2576 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2577 break;
2578 case 0x13:
b6343073 2579 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2580 break;
2581 case 0x14:
b6343073 2582 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2583 break;
2584 default:
2585 break;
2586 }
2587 }
b6343073 2588 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2589 break;
2590 case 0x3c2:
b6343073
JQ		 2591 s->msr = val & ~0x10;
2592 s->update_retrace_info(s);
e6e5ad80
FB		 2593 break;
2594 case 0x3c4:
b6343073 2595 s->sr_index = val;
e6e5ad80
FB		 2596 break;
2597 case 0x3c5:
e6e5ad80 2598#ifdef DEBUG_VGA_REG
b6343073 2599 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2600#endif
31c63201
JQ		 2601 cirrus_vga_write_sr(c, val);
2602 break;
e6e5ad80
FB		 2603 break;
2604 case 0x3c6:
b6343073 2605 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2606 break;
2607 case 0x3c7:
b6343073
JQ		 2608 s->dac_read_index = val;
2609 s->dac_sub_index = 0;
2610 s->dac_state = 3;
e6e5ad80
FB		 2611 break;
2612 case 0x3c8:
b6343073
JQ		 2613 s->dac_write_index = val;
2614 s->dac_sub_index = 0;
2615 s->dac_state = 0;
e6e5ad80
FB		 2616 break;
2617 case 0x3c9:
86948bb1
JQ		 2618 cirrus_vga_write_palette(c, val);
2619 break;
e6e5ad80 2620 case 0x3ce:
b6343073 2621 s->gr_index = val;
e6e5ad80
FB		 2622 break;
2623 case 0x3cf:
e6e5ad80 2624#ifdef DEBUG_VGA_REG
b6343073 2625 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2626#endif
22286bc6 2627 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2628 break;
2629 case 0x3b4:
2630 case 0x3d4:
b6343073 2631 s->cr_index = val;
e6e5ad80
FB		 2632 break;
2633 case 0x3b5:
2634 case 0x3d5:
e6e5ad80 2635#ifdef DEBUG_VGA_REG
b6343073 2636 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2637#endif
4ec1ce04 2638 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2639 break;
2640 case 0x3ba:
2641 case 0x3da:
b6343073 2642 s->fcr = val & 0x10;
e6e5ad80
FB		 2643 break;
2644 }
2645}
2646
e36f36e1
FB		 2647/***************************************
2648 *
2649 * memory-mapped I/O access
2650 *
2651 ***************************************/
2652
1e04d4d6
AK		 2653static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
2654 unsigned size)
e36f36e1 2655{
e05587e8 2656 CirrusVGAState *s = opaque;
e36f36e1 2657
e36f36e1
FB		 2658 if (addr >= 0x100) {
2659 return cirrus_mmio_blt_read(s, addr - 0x100);
2660 } else {
0ceac75b 2661 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2662 }
2663}
2664
1e04d4d6
AK		 2665static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
2666 uint64_t val, unsigned size)
e36f36e1 2667{
e05587e8 2668 CirrusVGAState *s = opaque;
e36f36e1 2669
e36f36e1
FB		 2670 if (addr >= 0x100) {
2671 cirrus_mmio_blt_write(s, addr - 0x100, val);
2672 } else {
0ceac75b 2673 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2674 }
2675}
2676
b1950430
AK		 2677static const MemoryRegionOps cirrus_mmio_io_ops = {
2678 .read = cirrus_mmio_read,
2679 .write = cirrus_mmio_write,
2680 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2681 .impl = {
2682 .min_access_size = 1,
2683 .max_access_size = 1,
2684 },
e36f36e1
FB		 2685};
2686
2c6ab832
FB		 2687/* load/save state */
2688
e59fb374 2689static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2690{
2691 CirrusVGAState *s = opaque;
2692
4e12cd94
AK		 2693 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2694 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2695
2bec46dc 2696 cirrus_update_memory_access(s);
2c6ab832 2697 /* force refresh */
4e12cd94 2698 s->vga.graphic_mode = -1;
2c6ab832
FB		 2699 cirrus_update_bank_ptr(s, 0);
2700 cirrus_update_bank_ptr(s, 1);
2701 return 0;
2702}
2703
7e72abc3
JQ		 2704static const VMStateDescription vmstate_cirrus_vga = {
2705 .name = "cirrus_vga",
2706 .version_id = 2,
2707 .minimum_version_id = 1,
2708 .minimum_version_id_old = 1,
2709 .post_load = cirrus_post_load,
2710 .fields = (VMStateField []) {
2711 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2712 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2713 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2714 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2715 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2716 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2717 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2718 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2719 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2720 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2721 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2722 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2723 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2724 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2725 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2726 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2727 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2728 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2729 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2730 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2731 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2732 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2733 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2734 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2735 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2736 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2737 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2738 /* XXX: we do not save the bitblt state - we assume we do not save
2739 the state when the blitter is active */
2740 VMSTATE_END_OF_LIST()
4f335feb 2741 }
7e72abc3 2742};
4f335feb 2743
7e72abc3
JQ		 2744static const VMStateDescription vmstate_pci_cirrus_vga = {
2745 .name = "cirrus_vga",
2746 .version_id = 2,
2747 .minimum_version_id = 2,
2748 .minimum_version_id_old = 2,
7e72abc3
JQ		 2749 .fields = (VMStateField []) {
2750 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2751 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2752 vmstate_cirrus_vga, CirrusVGAState),
2753 VMSTATE_END_OF_LIST()
2754 }
2755};
4f335feb 2756
e6e5ad80
FB		 2757/***************************************
2758 *
2759 * initialize
2760 *
2761 ***************************************/
2762
4abc796d 2763static void cirrus_reset(void *opaque)
e6e5ad80 2764{
4abc796d 2765 CirrusVGAState *s = opaque;
e6e5ad80 2766
03a3e7ba 2767 vga_common_reset(&s->vga);
ee50c6bc 2768 unmap_linear_vram(s);
4e12cd94 2769 s->vga.sr[0x06] = 0x0f;
4abc796d 2770 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2771 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2772 s->vga.sr[0x1F] = 0x2d; // MemClock
2773 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2774 s->vga.sr[0x0f] = 0x98;
2775 s->vga.sr[0x17] = 0x20;
2776 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2777 } else {
4e12cd94
AK		 2778 s->vga.sr[0x1F] = 0x22; // MemClock
2779 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2780 s->vga.sr[0x17] = s->bustype;
2781 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2782 }
4e12cd94 2783 s->vga.cr[0x27] = s->device_id;
e6e5ad80 2784
78e127ef
FB		 2785 /* Win2K seems to assume that the pattern buffer is at 0xff
2786 initially ! */
4e12cd94 2787 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 2788
e6e5ad80
FB		 2789 s->cirrus_hidden_dac_lockindex = 5;
2790 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2791}
2792
b1950430
AK		 2793static const MemoryRegionOps cirrus_linear_io_ops = {
2794 .read = cirrus_linear_read,
2795 .write = cirrus_linear_write,
2796 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2797 .impl = {
2798 .min_access_size = 1,
2799 .max_access_size = 1,
2800 },
b1950430
AK		 2801};
2802
be20f9e9
AK		 2803static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
2804 MemoryRegion *system_memory)
4abc796d
BS		 2805{
2806 int i;
2807 static int inited;
2808
2809 if (!inited) {
2810 inited = 1;
2811 for(i = 0;i < 256; i++)
2812 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2813 rop_to_index[CIRRUS_ROP_0] = 0;
2814 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2815 rop_to_index[CIRRUS_ROP_NOP] = 2;
2816 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2817 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2818 rop_to_index[CIRRUS_ROP_SRC] = 5;
2819 rop_to_index[CIRRUS_ROP_1] = 6;
2820 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2821 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2822 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2823 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2824 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2825 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2826 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2827 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2828 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2829 s->device_id = device_id;
2830 if (is_pci)
2831 s->bustype = CIRRUS_BUSTYPE_PCI;
2832 else
2833 s->bustype = CIRRUS_BUSTYPE_ISA;
2834 }
2835
0ceac75b 2836 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2837
0ceac75b
JQ		 2838 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2839 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2840 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2841 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2842
0ceac75b 2843 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2844
0ceac75b
JQ		 2845 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2846 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2847 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2848 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2849
b1950430
AK		 2850 memory_region_init(&s->low_mem_container,
2851 "cirrus-lowmem-container",
2852 0x20000);
2853
2854 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2855 "cirrus-low-memory", 0x20000);
2856 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
be20f9e9 2857 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2858 isa_mem_base + 0x000a0000,
2859 &s->low_mem_container,
2860 1);
2861 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2862
fefe54e3 2863 /* I/O handler for LFB */
b1950430
AK		 2864 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2865 "cirrus-linear-io", VGA_RAM_SIZE);
fefe54e3
AL		 2866
2867 /* I/O handler for LFB */
b1950430
AK		 2868 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2869 &cirrus_linear_bitblt_io_ops,
2870 s,
2871 "cirrus-bitblt-mmio",
2872 0x400000);
fefe54e3
AL		 2873
2874 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2875 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2876 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
fefe54e3
AL		 2877
2878 s->real_vram_size =
2879 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2880
4e12cd94 2881 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2882 s->cirrus_addr_mask = s->real_vram_size - 1;
2883 s->linear_mmio_mask = s->real_vram_size - 256;
2884
4e12cd94
AK		 2885 s->vga.get_bpp = cirrus_get_bpp;
2886 s->vga.get_offsets = cirrus_get_offsets;
2887 s->vga.get_resolution = cirrus_get_resolution;
2888 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2889 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2890
a08d4367 2891 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2892}
2893
2894/***************************************
2895 *
2896 * ISA bus support
2897 *
2898 ***************************************/
2899
be20f9e9 2900void isa_cirrus_vga_init(MemoryRegion *system_memory)
e6e5ad80
FB		 2901{
2902 CirrusVGAState *s;
2903
7267c094 2904 s = g_malloc0(sizeof(CirrusVGAState));
3b46e624 2905
fbe1b595 2906 vga_common_init(&s->vga, VGA_RAM_SIZE);
be20f9e9 2907 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0, system_memory);
4e12cd94
AK		 2908 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2909 s->vga.screen_dump, s->vga.text_update,
2910 &s->vga);
0be71e32 2911 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
5245d57a 2912 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80
FB		 2913 /* XXX ISA-LFB support */
2914}
2915
2916/***************************************
2917 *
2918 * PCI bus support
2919 *
2920 ***************************************/
2921
81a322d4 2922static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2923{
2924 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2925 CirrusVGAState *s = &d->cirrus_vga;
5b96d8f9
IY		 2926 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
2927 int16_t device_id = info->device_id;
a414c306
GH		 2928
2929 /* setup VGA */
2930 vga_common_init(&s->vga, VGA_RAM_SIZE);
be20f9e9 2931 cirrus_init_common(s, device_id, 1, pci_address_space(dev));
a414c306
GH		 2932 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2933 s->vga.screen_dump, s->vga.text_update,
2934 &s->vga);
2935
2936 /* setup PCI */
a414c306 2937
b1950430
AK		 2938 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2939
2940 /* XXX: add byte swapping apertures */
2941 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2942 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2943 &s->cirrus_linear_bitblt_io);
2944
a414c306
GH		 2945 /* setup memory space */
2946 /* memory #0 LFB */
2947 /* memory #1 memory-mapped I/O */
2948 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2949 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2950 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2951 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2952 }
81a322d4 2953 return 0;
a414c306
GH		 2954}
2955
fbe1b595 2956void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 2957{
556cd098 2958 pci_create_simple(bus, -1, "cirrus-vga");
a414c306 2959}
d34cab9f 2960
a414c306 2961static PCIDeviceInfo cirrus_vga_info = {
556cd098
MA		 2962 .qdev.name = "cirrus-vga",
2963 .qdev.desc = "Cirrus CLGD 54xx VGA",
a414c306 2964 .qdev.size = sizeof(PCICirrusVGAState),
be73cfe2 2965 .qdev.vmsd = &vmstate_pci_cirrus_vga,
be92bbf7 2966 .no_hotplug = 1,
a414c306 2967 .init = pci_cirrus_vga_initfn,
8c52c8f3 2968 .romfile = VGABIOS_CIRRUS_FILENAME,
5b96d8f9
IY		 2969 .vendor_id = PCI_VENDOR_ID_CIRRUS,
2970 .device_id = CIRRUS_ID_CLGD5446,
2971 .class_id = PCI_CLASS_DISPLAY_VGA,
a414c306 2972};
e6e5ad80 2973
a414c306
GH		 2974static void cirrus_vga_register(void)
2975{
2976 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 2977}
a414c306 2978device_init(cirrus_vga_register);
Qemu copy for testing