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report serial devices created with -device in the PIIX4 config space
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
5245d57a 34#include "loader.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
a21ae81d 174#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 175
b2b183c2
AL		 176#define ABS(a) ((signed)(a) > 0 ? a : -a)
177
b2eb849d
AJ		 178#define BLTUNSAFE(s) \
179 ( \
180 ( /* check dst is within bounds */ \
b2b183c2 181 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 182 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 183 (s)->vga.vram_size \
b2eb849d
AJ		 184 ) || \
185 ( /* check src is within bounds */ \
b2b183c2 186 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 187 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 188 (s)->vga.vram_size \
b2eb849d
AJ		 189 ) \
190 )
191
a5082316
FB		 192struct CirrusVGAState;
193typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
194 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 195 int dstpitch, int srcpitch,
196 int bltwidth, int bltheight);
a5082316
FB		 197typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
198 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 199
200typedef struct CirrusVGAState {
4e12cd94 201 VGACommonState vga;
e6e5ad80
FB		 202
203 int cirrus_linear_io_addr;
a5082316 204 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 205 int cirrus_mmio_io_addr;
206 uint32_t cirrus_addr_mask;
78e127ef 207 uint32_t linear_mmio_mask;
e6e5ad80
FB		 208 uint8_t cirrus_shadow_gr0;
209 uint8_t cirrus_shadow_gr1;
210 uint8_t cirrus_hidden_dac_lockindex;
211 uint8_t cirrus_hidden_dac_data;
212 uint32_t cirrus_bank_base[2];
213 uint32_t cirrus_bank_limit[2];
214 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 215 uint32_t hw_cursor_x;
216 uint32_t hw_cursor_y;
e6e5ad80
FB		 217 int cirrus_blt_pixelwidth;
218 int cirrus_blt_width;
219 int cirrus_blt_height;
220 int cirrus_blt_dstpitch;
221 int cirrus_blt_srcpitch;
a5082316
FB		 222 uint32_t cirrus_blt_fgcol;
223 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 224 uint32_t cirrus_blt_dstaddr;
225 uint32_t cirrus_blt_srcaddr;
226 uint8_t cirrus_blt_mode;
a5082316 227 uint8_t cirrus_blt_modeext;
e6e5ad80 228 cirrus_bitblt_rop_t cirrus_rop;
a5082316 229#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 230 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
231 uint8_t *cirrus_srcptr;
232 uint8_t *cirrus_srcptr_end;
233 uint32_t cirrus_srccounter;
a5082316
FB		 234 /* hwcursor display state */
235 int last_hw_cursor_size;
236 int last_hw_cursor_x;
237 int last_hw_cursor_y;
238 int last_hw_cursor_y_start;
239 int last_hw_cursor_y_end;
78e127ef 240 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 241 int device_id;
242 int bustype;
e6e5ad80
FB		 243} CirrusVGAState;
244
245typedef struct PCICirrusVGAState {
246 PCIDevice dev;
247 CirrusVGAState cirrus_vga;
248} PCICirrusVGAState;
249
a5082316 250static uint8_t rop_to_index[256];
3b46e624 251
e6e5ad80
FB		 252/***************************************
253 *
254 * prototypes.
255 *
256 ***************************************/
257
258
8926b517
FB		 259static void cirrus_bitblt_reset(CirrusVGAState *s);
260static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 261
262/***************************************
263 *
264 * raster operations
265 *
266 ***************************************/
267
a5082316
FB		 268static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
269 uint8_t *dst,const uint8_t *src,
270 int dstpitch,int srcpitch,
271 int bltwidth,int bltheight)
272{
e6e5ad80
FB		 273}
274
a5082316
FB		 275static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
276 uint8_t *dst,
277 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 278{
a5082316 279}
e6e5ad80 280
a5082316 281#define ROP_NAME 0
8c78881f 282#define ROP_FN(d, s) 0
a5082316 283#include "cirrus_vga_rop.h"
e6e5ad80 284
a5082316 285#define ROP_NAME src_and_dst
8c78881f 286#define ROP_FN(d, s) (s) & (d)
a5082316 287#include "cirrus_vga_rop.h"
e6e5ad80 288
a5082316 289#define ROP_NAME src_and_notdst
8c78881f 290#define ROP_FN(d, s) (s) & (~(d))
a5082316 291#include "cirrus_vga_rop.h"
e6e5ad80 292
a5082316 293#define ROP_NAME notdst
8c78881f 294#define ROP_FN(d, s) ~(d)
a5082316 295#include "cirrus_vga_rop.h"
e6e5ad80 296
a5082316 297#define ROP_NAME src
8c78881f 298#define ROP_FN(d, s) s
a5082316 299#include "cirrus_vga_rop.h"
e6e5ad80 300
a5082316 301#define ROP_NAME 1
8c78881f 302#define ROP_FN(d, s) ~0
a5082316
FB		 303#include "cirrus_vga_rop.h"
304
305#define ROP_NAME notsrc_and_dst
8c78881f 306#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 307#include "cirrus_vga_rop.h"
308
309#define ROP_NAME src_xor_dst
8c78881f 310#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 311#include "cirrus_vga_rop.h"
312
313#define ROP_NAME src_or_dst
8c78881f 314#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 315#include "cirrus_vga_rop.h"
316
317#define ROP_NAME notsrc_or_notdst
8c78881f 318#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 319#include "cirrus_vga_rop.h"
320
321#define ROP_NAME src_notxor_dst
8c78881f 322#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316 325#define ROP_NAME src_or_notdst
8c78881f 326#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 327#include "cirrus_vga_rop.h"
328
329#define ROP_NAME notsrc
8c78881f 330#define ROP_FN(d, s) (~(s))
a5082316
FB		 331#include "cirrus_vga_rop.h"
332
333#define ROP_NAME notsrc_or_dst
8c78881f 334#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 335#include "cirrus_vga_rop.h"
336
337#define ROP_NAME notsrc_and_notdst
8c78881f 338#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 339#include "cirrus_vga_rop.h"
340
341static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
342 cirrus_bitblt_rop_fwd_0,
343 cirrus_bitblt_rop_fwd_src_and_dst,
344 cirrus_bitblt_rop_nop,
345 cirrus_bitblt_rop_fwd_src_and_notdst,
346 cirrus_bitblt_rop_fwd_notdst,
347 cirrus_bitblt_rop_fwd_src,
348 cirrus_bitblt_rop_fwd_1,
349 cirrus_bitblt_rop_fwd_notsrc_and_dst,
350 cirrus_bitblt_rop_fwd_src_xor_dst,
351 cirrus_bitblt_rop_fwd_src_or_dst,
352 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
353 cirrus_bitblt_rop_fwd_src_notxor_dst,
354 cirrus_bitblt_rop_fwd_src_or_notdst,
355 cirrus_bitblt_rop_fwd_notsrc,
356 cirrus_bitblt_rop_fwd_notsrc_or_dst,
357 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
358};
359
360static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
361 cirrus_bitblt_rop_bkwd_0,
362 cirrus_bitblt_rop_bkwd_src_and_dst,
363 cirrus_bitblt_rop_nop,
364 cirrus_bitblt_rop_bkwd_src_and_notdst,
365 cirrus_bitblt_rop_bkwd_notdst,
366 cirrus_bitblt_rop_bkwd_src,
367 cirrus_bitblt_rop_bkwd_1,
368 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
369 cirrus_bitblt_rop_bkwd_src_xor_dst,
370 cirrus_bitblt_rop_bkwd_src_or_dst,
371 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
372 cirrus_bitblt_rop_bkwd_src_notxor_dst,
373 cirrus_bitblt_rop_bkwd_src_or_notdst,
374 cirrus_bitblt_rop_bkwd_notsrc,
375 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
376 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
377};
96cf2df8
TS		 378
379#define TRANSP_ROP(name) {\
380 name ## _8,\
381 name ## _16,\
382 }
383#define TRANSP_NOP(func) {\
384 func,\
385 func,\
386 }
387
388static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
389 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
390 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
391 TRANSP_NOP(cirrus_bitblt_rop_nop),
392 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
393 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
394 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
405};
406
407static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
408 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
409 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
410 TRANSP_NOP(cirrus_bitblt_rop_nop),
411 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
412 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
413 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
424};
425
a5082316
FB		 426#define ROP2(name) {\
427 name ## _8,\
428 name ## _16,\
429 name ## _24,\
430 name ## _32,\
431 }
432
433#define ROP_NOP2(func) {\
434 func,\
435 func,\
436 func,\
437 func,\
438 }
439
e69390ce
FB		 440static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
441 ROP2(cirrus_patternfill_0),
442 ROP2(cirrus_patternfill_src_and_dst),
443 ROP_NOP2(cirrus_bitblt_rop_nop),
444 ROP2(cirrus_patternfill_src_and_notdst),
445 ROP2(cirrus_patternfill_notdst),
446 ROP2(cirrus_patternfill_src),
447 ROP2(cirrus_patternfill_1),
448 ROP2(cirrus_patternfill_notsrc_and_dst),
449 ROP2(cirrus_patternfill_src_xor_dst),
450 ROP2(cirrus_patternfill_src_or_dst),
451 ROP2(cirrus_patternfill_notsrc_or_notdst),
452 ROP2(cirrus_patternfill_src_notxor_dst),
453 ROP2(cirrus_patternfill_src_or_notdst),
454 ROP2(cirrus_patternfill_notsrc),
455 ROP2(cirrus_patternfill_notsrc_or_dst),
456 ROP2(cirrus_patternfill_notsrc_and_notdst),
457};
458
a5082316
FB		 459static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
460 ROP2(cirrus_colorexpand_transp_0),
461 ROP2(cirrus_colorexpand_transp_src_and_dst),
462 ROP_NOP2(cirrus_bitblt_rop_nop),
463 ROP2(cirrus_colorexpand_transp_src_and_notdst),
464 ROP2(cirrus_colorexpand_transp_notdst),
465 ROP2(cirrus_colorexpand_transp_src),
466 ROP2(cirrus_colorexpand_transp_1),
467 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
468 ROP2(cirrus_colorexpand_transp_src_xor_dst),
469 ROP2(cirrus_colorexpand_transp_src_or_dst),
470 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
471 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
472 ROP2(cirrus_colorexpand_transp_src_or_notdst),
473 ROP2(cirrus_colorexpand_transp_notsrc),
474 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
475 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
476};
477
478static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
479 ROP2(cirrus_colorexpand_0),
480 ROP2(cirrus_colorexpand_src_and_dst),
481 ROP_NOP2(cirrus_bitblt_rop_nop),
482 ROP2(cirrus_colorexpand_src_and_notdst),
483 ROP2(cirrus_colorexpand_notdst),
484 ROP2(cirrus_colorexpand_src),
485 ROP2(cirrus_colorexpand_1),
486 ROP2(cirrus_colorexpand_notsrc_and_dst),
487 ROP2(cirrus_colorexpand_src_xor_dst),
488 ROP2(cirrus_colorexpand_src_or_dst),
489 ROP2(cirrus_colorexpand_notsrc_or_notdst),
490 ROP2(cirrus_colorexpand_src_notxor_dst),
491 ROP2(cirrus_colorexpand_src_or_notdst),
492 ROP2(cirrus_colorexpand_notsrc),
493 ROP2(cirrus_colorexpand_notsrc_or_dst),
494 ROP2(cirrus_colorexpand_notsrc_and_notdst),
495};
496
b30d4608
FB		 497static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
498 ROP2(cirrus_colorexpand_pattern_transp_0),
499 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
500 ROP_NOP2(cirrus_bitblt_rop_nop),
501 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
502 ROP2(cirrus_colorexpand_pattern_transp_notdst),
503 ROP2(cirrus_colorexpand_pattern_transp_src),
504 ROP2(cirrus_colorexpand_pattern_transp_1),
505 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
506 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
507 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
508 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
509 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
510 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
511 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
512 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
514};
515
516static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
517 ROP2(cirrus_colorexpand_pattern_0),
518 ROP2(cirrus_colorexpand_pattern_src_and_dst),
519 ROP_NOP2(cirrus_bitblt_rop_nop),
520 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
521 ROP2(cirrus_colorexpand_pattern_notdst),
522 ROP2(cirrus_colorexpand_pattern_src),
523 ROP2(cirrus_colorexpand_pattern_1),
524 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
525 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
526 ROP2(cirrus_colorexpand_pattern_src_or_dst),
527 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
528 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
529 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
530 ROP2(cirrus_colorexpand_pattern_notsrc),
531 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
532 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
533};
534
a5082316
FB		 535static const cirrus_fill_t cirrus_fill[16][4] = {
536 ROP2(cirrus_fill_0),
537 ROP2(cirrus_fill_src_and_dst),
538 ROP_NOP2(cirrus_bitblt_fill_nop),
539 ROP2(cirrus_fill_src_and_notdst),
540 ROP2(cirrus_fill_notdst),
541 ROP2(cirrus_fill_src),
542 ROP2(cirrus_fill_1),
543 ROP2(cirrus_fill_notsrc_and_dst),
544 ROP2(cirrus_fill_src_xor_dst),
545 ROP2(cirrus_fill_src_or_dst),
546 ROP2(cirrus_fill_notsrc_or_notdst),
547 ROP2(cirrus_fill_src_notxor_dst),
548 ROP2(cirrus_fill_src_or_notdst),
549 ROP2(cirrus_fill_notsrc),
550 ROP2(cirrus_fill_notsrc_or_dst),
551 ROP2(cirrus_fill_notsrc_and_notdst),
552};
553
554static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 555{
a5082316
FB		 556 unsigned int color;
557 switch (s->cirrus_blt_pixelwidth) {
558 case 1:
559 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
560 break;
561 case 2:
4e12cd94 562 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 563 s->cirrus_blt_fgcol = le16_to_cpu(color);
564 break;
565 case 3:
5fafdf24 566 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 567 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 568 break;
569 default:
570 case 4:
4e12cd94
AK		 571 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
572 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 573 s->cirrus_blt_fgcol = le32_to_cpu(color);
574 break;
e6e5ad80
FB		 575 }
576}
577
a5082316 578static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 579{
a5082316 580 unsigned int color;
e6e5ad80
FB		 581 switch (s->cirrus_blt_pixelwidth) {
582 case 1:
a5082316
FB		 583 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
584 break;
e6e5ad80 585 case 2:
4e12cd94 586 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 587 s->cirrus_blt_bgcol = le16_to_cpu(color);
588 break;
e6e5ad80 589 case 3:
5fafdf24 590 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 591 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 592 break;
e6e5ad80 593 default:
a5082316 594 case 4:
4e12cd94
AK		 595 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
596 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 597 s->cirrus_blt_bgcol = le32_to_cpu(color);
598 break;
e6e5ad80
FB		 599 }
600}
601
602static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
603 int off_pitch, int bytesperline,
604 int lines)
605{
606 int y;
607 int off_cur;
608 int off_cur_end;
609
610 for (y = 0; y < lines; y++) {
611 off_cur = off_begin;
b2eb849d 612 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 613 off_cur &= TARGET_PAGE_MASK;
614 while (off_cur < off_cur_end) {
4e12cd94 615 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
e6e5ad80
FB		 616 off_cur += TARGET_PAGE_SIZE;
617 }
618 off_begin += off_pitch;
619 }
620}
621
e6e5ad80
FB		 622static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
623 const uint8_t * src)
624{
e6e5ad80 625 uint8_t *dst;
e6e5ad80 626
4e12cd94 627 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 628
629 if (BLTUNSAFE(s))
630 return 0;
631
e69390ce 632 (*s->cirrus_rop) (s, dst, src,
5fafdf24 633 s->cirrus_blt_dstpitch, 0,
e69390ce 634 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 635 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 636 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
637 s->cirrus_blt_height);
e6e5ad80
FB		 638 return 1;
639}
640
a21ae81d
FB		 641/* fill */
642
a5082316 643static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 644{
a5082316 645 cirrus_fill_t rop_func;
a21ae81d 646
b2eb849d
AJ		 647 if (BLTUNSAFE(s))
648 return 0;
a5082316 649 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 650 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 651 s->cirrus_blt_dstpitch,
652 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 653 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
654 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
655 s->cirrus_blt_height);
656 cirrus_bitblt_reset(s);
657 return 1;
658}
659
e6e5ad80
FB		 660/***************************************
661 *
662 * bitblt (video-to-video)
663 *
664 ***************************************/
665
666static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
667{
668 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 669 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 670 s->cirrus_addr_mask));
e6e5ad80
FB		 671}
672
24236869 673static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 674{
78935c4a
AJ		 675 int sx = 0, sy = 0;
676 int dx = 0, dy = 0;
677 int depth = 0;
24236869
FB		 678 int notify = 0;
679
92d675d1
AJ		 680 /* make sure to only copy if it's a plain copy ROP */
681 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
682 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 683
92d675d1
AJ		 684 int width, height;
685
686 depth = s->vga.get_bpp(&s->vga) / 8;
687 s->vga.get_resolution(&s->vga, &width, &height);
688
689 /* extra x, y */
690 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
691 sy = (src / ABS(s->cirrus_blt_srcpitch));
692 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
693 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 694
92d675d1
AJ		 695 /* normalize width */
696 w /= depth;
24236869 697
92d675d1
AJ		 698 /* if we're doing a backward copy, we have to adjust
699 our x/y to be the upper left corner (instead of the lower
700 right corner) */
701 if (s->cirrus_blt_dstpitch < 0) {
702 sx -= (s->cirrus_blt_width / depth) - 1;
703 dx -= (s->cirrus_blt_width / depth) - 1;
704 sy -= s->cirrus_blt_height - 1;
705 dy -= s->cirrus_blt_height - 1;
706 }
707
708 /* are we in the visible portion of memory? */
709 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
710 (sx + w) <= width && (sy + h) <= height &&
711 (dx + w) <= width && (dy + h) <= height) {
712 notify = 1;
713 }
714 }
24236869
FB		 715
716 /* we have to flush all pending changes so that the copy
717 is generated at the appropriate moment in time */
718 if (notify)
719 vga_hw_update();
720
4e12cd94 721 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 722 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 723 s->vga.vram_ptr +
b2eb849d 724 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 725 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
726 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 727
728 if (notify)
4e12cd94 729 qemu_console_copy(s->vga.ds,
38334f76
AZ		 730 sx, sy, dx, dy,
731 s->cirrus_blt_width / depth,
732 s->cirrus_blt_height);
24236869
FB		 733
734 /* we don't have to notify the display that this portion has
38334f76 735 changed since qemu_console_copy implies this */
24236869 736
31c05501
AL		 737 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
738 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
739 s->cirrus_blt_height);
24236869
FB		 740}
741
742static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
743{
65d35a09
AJ		 744 if (BLTUNSAFE(s))
745 return 0;
746
4e12cd94
AK		 747 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
748 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 749 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 750
e6e5ad80
FB		 751 return 1;
752}
753
754/***************************************
755 *
756 * bitblt (cpu-to-video)
757 *
758 ***************************************/
759
e6e5ad80
FB		 760static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
761{
762 int copy_count;
a5082316 763 uint8_t *end_ptr;
3b46e624 764
e6e5ad80 765 if (s->cirrus_srccounter > 0) {
a5082316
FB		 766 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
767 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
768 the_end:
769 s->cirrus_srccounter = 0;
770 cirrus_bitblt_reset(s);
771 } else {
772 /* at least one scan line */
773 do {
4e12cd94 774 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 775 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
776 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 777 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
778 s->cirrus_blt_width, 1);
779 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
780 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
781 if (s->cirrus_srccounter <= 0)
782 goto the_end;
783 /* more bytes than needed can be transfered because of
784 word alignment, so we keep them for the next line */
785 /* XXX: keep alignment to speed up transfer */
786 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
787 copy_count = s->cirrus_srcptr_end - end_ptr;
788 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
789 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
790 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
791 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
792 }
e6e5ad80
FB		 793 }
794}
795
796/***************************************
797 *
798 * bitblt wrapper
799 *
800 ***************************************/
801
802static void cirrus_bitblt_reset(CirrusVGAState * s)
803{
f8b237af
AL		 804 int need_update;
805
4e12cd94 806 s->vga.gr[0x31] &=
e6e5ad80 807 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 808 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
809 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 810 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
811 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
812 s->cirrus_srccounter = 0;
f8b237af
AL		 813 if (!need_update)
814 return;
8926b517 815 cirrus_update_memory_access(s);
e6e5ad80
FB		 816}
817
818static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
819{
a5082316
FB		 820 int w;
821
e6e5ad80
FB		 822 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
823 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
824 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
825
826 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
827 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 828 s->cirrus_blt_srcpitch = 8;
e6e5ad80 829 } else {
b30d4608 830 /* XXX: check for 24 bpp */
a5082316 831 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 832 }
a5082316 833 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 834 } else {
835 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 836 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 837 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 838 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
839 else
840 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 841 } else {
c9c0eae8
FB		 842 /* always align input size to 32 bits */
843 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 844 }
a5082316 845 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 846 }
a5082316
FB		 847 s->cirrus_srcptr = s->cirrus_bltbuf;
848 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 849 cirrus_update_memory_access(s);
e6e5ad80
FB		 850 return 1;
851}
852
853static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
854{
855 /* XXX */
a5082316 856#ifdef DEBUG_BITBLT
e6e5ad80
FB		 857 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
858#endif
859 return 0;
860}
861
862static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
863{
864 int ret;
865
866 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
867 ret = cirrus_bitblt_videotovideo_patterncopy(s);
868 } else {
869 ret = cirrus_bitblt_videotovideo_copy(s);
870 }
e6e5ad80
FB		 871 if (ret)
872 cirrus_bitblt_reset(s);
873 return ret;
874}
875
876static void cirrus_bitblt_start(CirrusVGAState * s)
877{
878 uint8_t blt_rop;
879
4e12cd94 880 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 881
4e12cd94
AK		 882 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
883 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
884 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
885 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 886 s->cirrus_blt_dstaddr =
4e12cd94 887 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 888 s->cirrus_blt_srcaddr =
4e12cd94
AK		 889 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
890 s->cirrus_blt_mode = s->vga.gr[0x30];
891 s->cirrus_blt_modeext = s->vga.gr[0x33];
892 blt_rop = s->vga.gr[0x32];
e6e5ad80 893
a21ae81d 894#ifdef DEBUG_BITBLT
0b74ed78 895 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 896 blt_rop,
a21ae81d 897 s->cirrus_blt_mode,
a5082316 898 s->cirrus_blt_modeext,
a21ae81d
FB		 899 s->cirrus_blt_width,
900 s->cirrus_blt_height,
901 s->cirrus_blt_dstpitch,
902 s->cirrus_blt_srcpitch,
903 s->cirrus_blt_dstaddr,
a5082316 904 s->cirrus_blt_srcaddr,
4e12cd94 905 s->vga.gr[0x2f]);
a21ae81d
FB		 906#endif
907
e6e5ad80
FB		 908 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
909 case CIRRUS_BLTMODE_PIXELWIDTH8:
910 s->cirrus_blt_pixelwidth = 1;
911 break;
912 case CIRRUS_BLTMODE_PIXELWIDTH16:
913 s->cirrus_blt_pixelwidth = 2;
914 break;
915 case CIRRUS_BLTMODE_PIXELWIDTH24:
916 s->cirrus_blt_pixelwidth = 3;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH32:
919 s->cirrus_blt_pixelwidth = 4;
920 break;
921 default:
a5082316 922#ifdef DEBUG_BITBLT
e6e5ad80
FB		 923 printf("cirrus: bitblt - pixel width is unknown\n");
924#endif
925 goto bitblt_ignore;
926 }
927 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
928
929 if ((s->
930 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
931 CIRRUS_BLTMODE_MEMSYSDEST))
932 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 933#ifdef DEBUG_BITBLT
e6e5ad80
FB		 934 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
935#endif
936 goto bitblt_ignore;
937 }
938
a5082316 939 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 940 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 941 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 942 CIRRUS_BLTMODE_PATTERNCOPY |
943 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 944 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 945 cirrus_bitblt_fgcol(s);
946 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 947 } else {
5fafdf24
TS		 948 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
949 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 950 CIRRUS_BLTMODE_COLOREXPAND) {
951
952 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 953 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 954 cirrus_bitblt_bgcol(s);
b30d4608 955 else
4c8732d7 956 cirrus_bitblt_fgcol(s);
b30d4608 957 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 958 } else {
959 cirrus_bitblt_fgcol(s);
960 cirrus_bitblt_bgcol(s);
961 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
962 }
e69390ce 963 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 964 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
965 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
966 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
967 cirrus_bitblt_bgcol(s);
968 else
969 cirrus_bitblt_fgcol(s);
970 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
971 } else {
972 cirrus_bitblt_fgcol(s);
973 cirrus_bitblt_bgcol(s);
974 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
975 }
976 } else {
977 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
978 }
a21ae81d 979 } else {
96cf2df8
TS		 980 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
981 if (s->cirrus_blt_pixelwidth > 2) {
982 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
983 goto bitblt_ignore;
984 }
985 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
986 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
987 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
988 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
989 } else {
990 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
991 }
992 } else {
993 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
994 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
995 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
996 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
997 } else {
998 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
999 }
1000 }
1001 }
a21ae81d
FB		 1002 // setup bitblt engine.
1003 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1004 if (!cirrus_bitblt_cputovideo(s))
1005 goto bitblt_ignore;
1006 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1007 if (!cirrus_bitblt_videotocpu(s))
1008 goto bitblt_ignore;
1009 } else {
1010 if (!cirrus_bitblt_videotovideo(s))
1011 goto bitblt_ignore;
1012 }
e6e5ad80 1013 }
e6e5ad80
FB		 1014 return;
1015 bitblt_ignore:;
1016 cirrus_bitblt_reset(s);
1017}
1018
1019static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1020{
1021 unsigned old_value;
1022
4e12cd94
AK		 1023 old_value = s->vga.gr[0x31];
1024 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1025
1026 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1027 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1028 cirrus_bitblt_reset(s);
1029 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1030 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1031 cirrus_bitblt_start(s);
1032 }
1033}
1034
1035
1036/***************************************
1037 *
1038 * basic parameters
1039 *
1040 ***************************************/
1041
a4a2f59c 1042static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1043 uint32_t *pline_offset,
1044 uint32_t *pstart_addr,
1045 uint32_t *pline_compare)
e6e5ad80 1046{
4e12cd94 1047 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1048 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1049
4e12cd94
AK		 1050 line_offset = s->vga.cr[0x13]
1051 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1052 line_offset <<= 3;
1053 *pline_offset = line_offset;
1054
4e12cd94
AK		 1055 start_addr = (s->vga.cr[0x0c] << 8)
1056 | s->vga.cr[0x0d]
1057 | ((s->vga.cr[0x1b] & 0x01) << 16)
1058 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1059 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1060 *pstart_addr = start_addr;
83acc96b 1061
4e12cd94
AK		 1062 line_compare = s->vga.cr[0x18] |
1063 ((s->vga.cr[0x07] & 0x10) << 4) |
1064 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1065 *pline_compare = line_compare;
e6e5ad80
FB		 1066}
1067
1068static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1069{
1070 uint32_t ret = 16;
1071
1072 switch (s->cirrus_hidden_dac_data & 0xf) {
1073 case 0:
1074 ret = 15;
1075 break; /* Sierra HiColor */
1076 case 1:
1077 ret = 16;
1078 break; /* XGA HiColor */
1079 default:
1080#ifdef DEBUG_CIRRUS
1081 printf("cirrus: invalid DAC value %x in 16bpp\n",
1082 (s->cirrus_hidden_dac_data & 0xf));
1083#endif
1084 ret = 15; /* XXX */
1085 break;
1086 }
1087 return ret;
1088}
1089
a4a2f59c 1090static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1091{
4e12cd94 1092 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1093 uint32_t ret = 8;
1094
4e12cd94 1095 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1096 /* Cirrus SVGA */
4e12cd94 1097 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1098 case CIRRUS_SR7_BPP_8:
1099 ret = 8;
1100 break;
1101 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1102 ret = cirrus_get_bpp16_depth(s);
1103 break;
1104 case CIRRUS_SR7_BPP_24:
1105 ret = 24;
1106 break;
1107 case CIRRUS_SR7_BPP_16:
1108 ret = cirrus_get_bpp16_depth(s);
1109 break;
1110 case CIRRUS_SR7_BPP_32:
1111 ret = 32;
1112 break;
1113 default:
1114#ifdef DEBUG_CIRRUS
4e12cd94 1115 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1116#endif
1117 ret = 8;
1118 break;
1119 }
1120 } else {
1121 /* VGA */
aeb3c85f 1122 ret = 0;
e6e5ad80
FB		 1123 }
1124
1125 return ret;
1126}
1127
a4a2f59c 1128static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1129{
1130 int width, height;
3b46e624 1131
78e127ef 1132 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1133 height = s->cr[0x12] |
1134 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1135 ((s->cr[0x07] & 0x40) << 3);
1136 height = (height + 1);
1137 /* interlace support */
1138 if (s->cr[0x1a] & 0x01)
1139 height = height * 2;
1140 *pwidth = width;
1141 *pheight = height;
1142}
1143
e6e5ad80
FB		 1144/***************************************
1145 *
1146 * bank memory
1147 *
1148 ***************************************/
1149
1150static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1151{
1152 unsigned offset;
1153 unsigned limit;
1154
4e12cd94
AK		 1155 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1156 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1157 else /* single bank */
4e12cd94 1158 offset = s->vga.gr[0x09];
e6e5ad80 1159
4e12cd94 1160 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1161 offset <<= 14;
1162 else
1163 offset <<= 12;
1164
e3a4e4b6 1165 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1166 limit = 0;
1167 else
e3a4e4b6 1168 limit = s->real_vram_size - offset;
e6e5ad80 1169
4e12cd94 1170 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1171 if (limit > 0x8000) {
1172 offset += 0x8000;
1173 limit -= 0x8000;
1174 } else {
1175 limit = 0;
1176 }
1177 }
1178
1179 if (limit > 0) {
2bec46dc
AL		 1180 /* Thinking about changing bank base? First, drop the dirty bitmap information
1181 * on the current location, otherwise we lose this pointer forever */
4e12cd94 1182 if (s->vga.lfb_vram_mapped) {
c227f099 1183 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
2bec46dc
AL		 1184 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1185 }
e6e5ad80
FB		 1186 s->cirrus_bank_base[bank_index] = offset;
1187 s->cirrus_bank_limit[bank_index] = limit;
1188 } else {
1189 s->cirrus_bank_base[bank_index] = 0;
1190 s->cirrus_bank_limit[bank_index] = 0;
1191 }
1192}
1193
1194/***************************************
1195 *
1196 * I/O access between 0x3c4-0x3c5
1197 *
1198 ***************************************/
1199
8a82c322 1200static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1201{
8a82c322 1202 switch (s->vga.sr_index) {
e6e5ad80
FB		 1203 case 0x00: // Standard VGA
1204 case 0x01: // Standard VGA
1205 case 0x02: // Standard VGA
1206 case 0x03: // Standard VGA
1207 case 0x04: // Standard VGA
8a82c322 1208 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1209 case 0x06: // Unlock Cirrus extensions
8a82c322 1210 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1211 case 0x10:
1212 case 0x30:
1213 case 0x50:
1214 case 0x70: // Graphics Cursor X
1215 case 0x90:
1216 case 0xb0:
1217 case 0xd0:
1218 case 0xf0: // Graphics Cursor X
8a82c322 1219 return s->vga.sr[0x10];
e6e5ad80
FB		 1220 case 0x11:
1221 case 0x31:
1222 case 0x51:
1223 case 0x71: // Graphics Cursor Y
1224 case 0x91:
1225 case 0xb1:
1226 case 0xd1:
a5082316 1227 case 0xf1: // Graphics Cursor Y
8a82c322 1228 return s->vga.sr[0x11];
aeb3c85f
FB		 1229 case 0x05: // ???
1230 case 0x07: // Extended Sequencer Mode
1231 case 0x08: // EEPROM Control
1232 case 0x09: // Scratch Register 0
1233 case 0x0a: // Scratch Register 1
1234 case 0x0b: // VCLK 0
1235 case 0x0c: // VCLK 1
1236 case 0x0d: // VCLK 2
1237 case 0x0e: // VCLK 3
1238 case 0x0f: // DRAM Control
e6e5ad80
FB		 1239 case 0x12: // Graphics Cursor Attribute
1240 case 0x13: // Graphics Cursor Pattern Address
1241 case 0x14: // Scratch Register 2
1242 case 0x15: // Scratch Register 3
1243 case 0x16: // Performance Tuning Register
1244 case 0x17: // Configuration Readback and Extended Control
1245 case 0x18: // Signature Generator Control
1246 case 0x19: // Signal Generator Result
1247 case 0x1a: // Signal Generator Result
1248 case 0x1b: // VCLK 0 Denominator & Post
1249 case 0x1c: // VCLK 1 Denominator & Post
1250 case 0x1d: // VCLK 2 Denominator & Post
1251 case 0x1e: // VCLK 3 Denominator & Post
1252 case 0x1f: // BIOS Write Enable and MCLK select
1253#ifdef DEBUG_CIRRUS
8a82c322 1254 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1255#endif
8a82c322 1256 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1257 default:
1258#ifdef DEBUG_CIRRUS
8a82c322 1259 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1260#endif
8a82c322 1261 return 0xff;
e6e5ad80
FB		 1262 break;
1263 }
e6e5ad80
FB		 1264}
1265
31c63201 1266static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1267{
31c63201 1268 switch (s->vga.sr_index) {
e6e5ad80
FB		 1269 case 0x00: // Standard VGA
1270 case 0x01: // Standard VGA
1271 case 0x02: // Standard VGA
1272 case 0x03: // Standard VGA
1273 case 0x04: // Standard VGA
31c63201
JQ		 1274 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1275 if (s->vga.sr_index == 1)
1276 s->vga.update_retrace_info(&s->vga);
1277 break;
e6e5ad80 1278 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1279 val &= 0x17;
1280 if (val == 0x12) {
1281 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1282 } else {
31c63201 1283 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1284 }
1285 break;
1286 case 0x10:
1287 case 0x30:
1288 case 0x50:
1289 case 0x70: // Graphics Cursor X
1290 case 0x90:
1291 case 0xb0:
1292 case 0xd0:
1293 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1294 s->vga.sr[0x10] = val;
1295 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1296 break;
1297 case 0x11:
1298 case 0x31:
1299 case 0x51:
1300 case 0x71: // Graphics Cursor Y
1301 case 0x91:
1302 case 0xb1:
1303 case 0xd1:
1304 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1305 s->vga.sr[0x11] = val;
1306 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1307 break;
1308 case 0x07: // Extended Sequencer Mode
2bec46dc 1309 cirrus_update_memory_access(s);
e6e5ad80
FB		 1310 case 0x08: // EEPROM Control
1311 case 0x09: // Scratch Register 0
1312 case 0x0a: // Scratch Register 1
1313 case 0x0b: // VCLK 0
1314 case 0x0c: // VCLK 1
1315 case 0x0d: // VCLK 2
1316 case 0x0e: // VCLK 3
1317 case 0x0f: // DRAM Control
1318 case 0x12: // Graphics Cursor Attribute
1319 case 0x13: // Graphics Cursor Pattern Address
1320 case 0x14: // Scratch Register 2
1321 case 0x15: // Scratch Register 3
1322 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1323 case 0x18: // Signature Generator Control
1324 case 0x19: // Signature Generator Result
1325 case 0x1a: // Signature Generator Result
1326 case 0x1b: // VCLK 0 Denominator & Post
1327 case 0x1c: // VCLK 1 Denominator & Post
1328 case 0x1d: // VCLK 2 Denominator & Post
1329 case 0x1e: // VCLK 3 Denominator & Post
1330 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1331 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1332#ifdef DEBUG_CIRRUS
1333 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1334 s->vga.sr_index, val);
e6e5ad80
FB		 1335#endif
1336 break;
8926b517 1337 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1338 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1339 | (val & 0xc7);
8926b517
FB		 1340 cirrus_update_memory_access(s);
1341 break;
e6e5ad80
FB		 1342 default:
1343#ifdef DEBUG_CIRRUS
31c63201
JQ		 1344 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1345 s->vga.sr_index, val);
e6e5ad80
FB		 1346#endif
1347 break;
1348 }
e6e5ad80
FB		 1349}
1350
1351/***************************************
1352 *
1353 * I/O access at 0x3c6
1354 *
1355 ***************************************/
1356
957c9db5 1357static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1358{
a21ae81d 1359 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1360 s->cirrus_hidden_dac_lockindex = 0;
1361 return s->cirrus_hidden_dac_data;
e6e5ad80 1362 }
957c9db5 1363 return 0xff;
e6e5ad80
FB		 1364}
1365
1366static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1367{
1368 if (s->cirrus_hidden_dac_lockindex == 4) {
1369 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1370#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1371 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1372#endif
1373 }
1374 s->cirrus_hidden_dac_lockindex = 0;
1375}
1376
1377/***************************************
1378 *
1379 * I/O access at 0x3c9
1380 *
1381 ***************************************/
1382
5deaeee3 1383static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1384{
5deaeee3
JQ		 1385 int val;
1386
1387 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1388 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1389 s->vga.dac_sub_index];
1390 } else {
1391 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1392 }
4e12cd94
AK		 1393 if (++s->vga.dac_sub_index == 3) {
1394 s->vga.dac_sub_index = 0;
1395 s->vga.dac_read_index++;
e6e5ad80 1396 }
5deaeee3 1397 return val;
e6e5ad80
FB		 1398}
1399
86948bb1 1400static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1401{
4e12cd94
AK		 1402 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1403 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1404 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1405 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1406 s->vga.dac_cache, 3);
1407 } else {
1408 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1409 }
a5082316 1410 /* XXX update cursor */
4e12cd94
AK		 1411 s->vga.dac_sub_index = 0;
1412 s->vga.dac_write_index++;
e6e5ad80 1413 }
e6e5ad80
FB		 1414}
1415
1416/***************************************
1417 *
1418 * I/O access between 0x3ce-0x3cf
1419 *
1420 ***************************************/
1421
f705db9d 1422static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1423{
1424 switch (reg_index) {
aeb3c85f 1425 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1426 return s->cirrus_shadow_gr0;
aeb3c85f 1427 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1428 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1429 case 0x02: // Standard VGA
1430 case 0x03: // Standard VGA
1431 case 0x04: // Standard VGA
1432 case 0x06: // Standard VGA
1433 case 0x07: // Standard VGA
1434 case 0x08: // Standard VGA
f705db9d 1435 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1436 case 0x05: // Standard VGA, Cirrus extended mode
1437 default:
1438 break;
1439 }
1440
1441 if (reg_index < 0x3a) {
f705db9d 1442 return s->vga.gr[reg_index];
e6e5ad80
FB		 1443 } else {
1444#ifdef DEBUG_CIRRUS
1445 printf("cirrus: inport gr_index %02x\n", reg_index);
1446#endif
f705db9d 1447 return 0xff;
e6e5ad80 1448 }
e6e5ad80
FB		 1449}
1450
22286bc6
JQ		 1451static void
1452cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1453{
a5082316
FB		 1454#if defined(DEBUG_BITBLT) && 0
1455 printf("gr%02x: %02x\n", reg_index, reg_value);
1456#endif
e6e5ad80
FB		 1457 switch (reg_index) {
1458 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1459 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1460 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1461 break;
e6e5ad80 1462 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1463 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1464 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1465 break;
e6e5ad80
FB		 1466 case 0x02: // Standard VGA
1467 case 0x03: // Standard VGA
1468 case 0x04: // Standard VGA
1469 case 0x06: // Standard VGA
1470 case 0x07: // Standard VGA
1471 case 0x08: // Standard VGA
22286bc6
JQ		 1472 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1473 break;
e6e5ad80 1474 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1475 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1476 cirrus_update_memory_access(s);
e6e5ad80
FB		 1477 break;
1478 case 0x09: // bank offset #0
1479 case 0x0A: // bank offset #1
4e12cd94 1480 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1481 cirrus_update_bank_ptr(s, 0);
1482 cirrus_update_bank_ptr(s, 1);
2bec46dc 1483 cirrus_update_memory_access(s);
8926b517 1484 break;
e6e5ad80 1485 case 0x0B:
4e12cd94 1486 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1487 cirrus_update_bank_ptr(s, 0);
1488 cirrus_update_bank_ptr(s, 1);
8926b517 1489 cirrus_update_memory_access(s);
e6e5ad80
FB		 1490 break;
1491 case 0x10: // BGCOLOR 0x0000ff00
1492 case 0x11: // FGCOLOR 0x0000ff00
1493 case 0x12: // BGCOLOR 0x00ff0000
1494 case 0x13: // FGCOLOR 0x00ff0000
1495 case 0x14: // BGCOLOR 0xff000000
1496 case 0x15: // FGCOLOR 0xff000000
1497 case 0x20: // BLT WIDTH 0x0000ff
1498 case 0x22: // BLT HEIGHT 0x0000ff
1499 case 0x24: // BLT DEST PITCH 0x0000ff
1500 case 0x26: // BLT SRC PITCH 0x0000ff
1501 case 0x28: // BLT DEST ADDR 0x0000ff
1502 case 0x29: // BLT DEST ADDR 0x00ff00
1503 case 0x2c: // BLT SRC ADDR 0x0000ff
1504 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1505 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1506 case 0x30: // BLT MODE
1507 case 0x32: // RASTER OP
a21ae81d 1508 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1509 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1510 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1511 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1512 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1513 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1514 break;
1515 case 0x21: // BLT WIDTH 0x001f00
1516 case 0x23: // BLT HEIGHT 0x001f00
1517 case 0x25: // BLT DEST PITCH 0x001f00
1518 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1520 break;
1521 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1522 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1523 /* if auto start mode, starts bit blt now */
4e12cd94 1524 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1525 cirrus_bitblt_start(s);
1526 }
1527 break;
e6e5ad80 1528 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1529 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1530 break;
1531 case 0x31: // BLT STATUS/START
1532 cirrus_write_bitblt(s, reg_value);
1533 break;
1534 default:
1535#ifdef DEBUG_CIRRUS
1536 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1537 reg_value);
1538#endif
1539 break;
1540 }
e6e5ad80
FB		 1541}
1542
1543/***************************************
1544 *
1545 * I/O access between 0x3d4-0x3d5
1546 *
1547 ***************************************/
1548
b863d514 1549static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1550{
1551 switch (reg_index) {
1552 case 0x00: // Standard VGA
1553 case 0x01: // Standard VGA
1554 case 0x02: // Standard VGA
1555 case 0x03: // Standard VGA
1556 case 0x04: // Standard VGA
1557 case 0x05: // Standard VGA
1558 case 0x06: // Standard VGA
1559 case 0x07: // Standard VGA
1560 case 0x08: // Standard VGA
1561 case 0x09: // Standard VGA
1562 case 0x0a: // Standard VGA
1563 case 0x0b: // Standard VGA
1564 case 0x0c: // Standard VGA
1565 case 0x0d: // Standard VGA
1566 case 0x0e: // Standard VGA
1567 case 0x0f: // Standard VGA
1568 case 0x10: // Standard VGA
1569 case 0x11: // Standard VGA
1570 case 0x12: // Standard VGA
1571 case 0x13: // Standard VGA
1572 case 0x14: // Standard VGA
1573 case 0x15: // Standard VGA
1574 case 0x16: // Standard VGA
1575 case 0x17: // Standard VGA
1576 case 0x18: // Standard VGA
b863d514 1577 return s->vga.cr[s->vga.cr_index];
ca896ef3 1578 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1579 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1580 case 0x19: // Interlace End
1581 case 0x1a: // Miscellaneous Control
1582 case 0x1b: // Extended Display Control
1583 case 0x1c: // Sync Adjust and Genlock
1584 case 0x1d: // Overlay Extended Control
1585 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1586 case 0x25: // Part Status
1587 case 0x27: // Part ID (R)
b863d514 1588 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1589 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1590 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1591 break;
1592 default:
1593#ifdef DEBUG_CIRRUS
1594 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1595#endif
b863d514 1596 return 0xff;
e6e5ad80 1597 }
e6e5ad80
FB		 1598}
1599
4ec1ce04 1600static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1601{
4ec1ce04 1602 switch (s->vga.cr_index) {
e6e5ad80
FB		 1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
4ec1ce04
JQ		 1628 /* handle CR0-7 protection */
1629 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1630 /* can always write bit 4 of CR7 */
1631 if (s->vga.cr_index == 7)
1632 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1633 return;
1634 }
1635 s->vga.cr[s->vga.cr_index] = reg_value;
1636 switch(s->vga.cr_index) {
1637 case 0x00:
1638 case 0x04:
1639 case 0x05:
1640 case 0x06:
1641 case 0x07:
1642 case 0x11:
1643 case 0x17:
1644 s->vga.update_retrace_info(&s->vga);
1645 break;
1646 }
1647 break;
e6e5ad80
FB		 1648 case 0x19: // Interlace End
1649 case 0x1a: // Miscellaneous Control
1650 case 0x1b: // Extended Display Control
1651 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1652 case 0x1d: // Overlay Extended Control
4ec1ce04 1653 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1654#ifdef DEBUG_CIRRUS
1655 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1656 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1657#endif
1658 break;
1659 case 0x22: // Graphics Data Latches Readback (R)
1660 case 0x24: // Attribute Controller Toggle Readback (R)
1661 case 0x26: // Attribute Controller Index Readback (R)
1662 case 0x27: // Part ID (R)
1663 break;
e6e5ad80
FB		 1664 case 0x25: // Part Status
1665 default:
1666#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1667 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1668 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1669#endif
1670 break;
1671 }
e6e5ad80
FB		 1672}
1673
1674/***************************************
1675 *
1676 * memory-mapped I/O (bitblt)
1677 *
1678 ***************************************/
1679
1680static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1681{
1682 int value = 0xff;
1683
1684 switch (address) {
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1747 break;
1748 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTMODE:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1756 break;
1757 case CIRRUS_MMIO_BLTROP:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1759 break;
a21ae81d 1760 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1762 break;
e6e5ad80 1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1771 break;
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1774 break;
1775 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1776 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1777 break;
1778 default:
1779#ifdef DEBUG_CIRRUS
1780 printf("cirrus: mmio read - address 0x%04x\n", address);
1781#endif
1782 break;
1783 }
1784
1785 return (uint8_t) value;
1786}
1787
1788static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1789 uint8_t value)
1790{
1791 switch (address) {
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1793 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1796 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1799 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1802 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1805 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1808 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1811 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1814 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1817 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1820 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1823 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1826 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1829 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1832 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1835 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1838 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1841 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1844 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1847 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1848 break;
1849 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1850 /* ignored */
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1857 break;
1858 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1859 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1862 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTMODE:
22286bc6 1865 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1866 break;
1867 case CIRRUS_MMIO_BLTROP:
22286bc6 1868 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1869 break;
a21ae81d 1870 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1871 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1872 break;
e6e5ad80 1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1874 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1877 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1880 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1881 break;
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1883 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1884 break;
1885 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1886 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1887 break;
1888 default:
1889#ifdef DEBUG_CIRRUS
1890 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1891 address, value);
1892#endif
1893 break;
1894 }
1895}
1896
e6e5ad80
FB		 1897/***************************************
1898 *
1899 * write mode 4/5
1900 *
1901 * assume TARGET_PAGE_SIZE >= 16
1902 *
1903 ***************************************/
1904
1905static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1906 unsigned mode,
1907 unsigned offset,
1908 uint32_t mem_value)
1909{
1910 int x;
1911 unsigned val = mem_value;
1912 uint8_t *dst;
1913
4e12cd94 1914 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1915 for (x = 0; x < 8; x++) {
1916 if (val & 0x80) {
0b74ed78 1917 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1918 } else if (mode == 5) {
0b74ed78 1919 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1920 }
1921 val <<= 1;
0b74ed78 1922 dst++;
e6e5ad80 1923 }
4e12cd94
AK		 1924 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1925 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
e6e5ad80
FB		 1926}
1927
1928static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1929 unsigned mode,
1930 unsigned offset,
1931 uint32_t mem_value)
1932{
1933 int x;
1934 unsigned val = mem_value;
1935 uint8_t *dst;
1936
4e12cd94 1937 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1938 for (x = 0; x < 8; x++) {
1939 if (val & 0x80) {
0b74ed78 1940 *dst = s->cirrus_shadow_gr1;
4e12cd94 1941 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1942 } else if (mode == 5) {
0b74ed78 1943 *dst = s->cirrus_shadow_gr0;
4e12cd94 1944 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1945 }
1946 val <<= 1;
0b74ed78 1947 dst += 2;
e6e5ad80 1948 }
4e12cd94
AK		 1949 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1950 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
e6e5ad80
FB		 1951}
1952
1953/***************************************
1954 *
1955 * memory access between 0xa0000-0xbffff
1956 *
1957 ***************************************/
1958
c227f099 1959static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 1960{
1961 CirrusVGAState *s = opaque;
1962 unsigned bank_index;
1963 unsigned bank_offset;
1964 uint32_t val;
1965
4e12cd94 1966 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 1967 return vga_mem_readb(s, addr);
1968 }
1969
aeb3c85f
FB		 1970 addr &= 0x1ffff;
1971
e6e5ad80
FB		 1972 if (addr < 0x10000) {
1973 /* XXX handle bitblt */
1974 /* video memory */
1975 bank_index = addr >> 15;
1976 bank_offset = addr & 0x7fff;
1977 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1978 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1979 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1980 bank_offset <<= 4;
4e12cd94 1981 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1982 bank_offset <<= 3;
1983 }
1984 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1985 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1986 } else
1987 val = 0xff;
1988 } else if (addr >= 0x18000 && addr < 0x18100) {
1989 /* memory-mapped I/O */
1990 val = 0xff;
4e12cd94 1991 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1992 val = cirrus_mmio_blt_read(s, addr & 0xff);
1993 }
1994 } else {
1995 val = 0xff;
1996#ifdef DEBUG_CIRRUS
0bf9e31a 1997 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1998#endif
1999 }
2000 return val;
2001}
2002
c227f099 2003static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2004{
2005 uint32_t v;
3fbb33d0 2006
e6e5ad80
FB		 2007 v = cirrus_vga_mem_readb(opaque, addr);
2008 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
e6e5ad80
FB		 2009 return v;
2010}
2011
c227f099 2012static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2013{
2014 uint32_t v;
3fbb33d0 2015
e6e5ad80
FB		 2016 v = cirrus_vga_mem_readb(opaque, addr);
2017 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2018 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2019 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
e6e5ad80
FB		 2020 return v;
2021}
2022
c227f099 2023static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2024 uint32_t mem_value)
2025{
2026 CirrusVGAState *s = opaque;
2027 unsigned bank_index;
2028 unsigned bank_offset;
2029 unsigned mode;
2030
4e12cd94 2031 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2032 vga_mem_writeb(s, addr, mem_value);
2033 return;
2034 }
2035
aeb3c85f
FB		 2036 addr &= 0x1ffff;
2037
e6e5ad80
FB		 2038 if (addr < 0x10000) {
2039 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2040 /* bitblt */
2041 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2042 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2043 cirrus_bitblt_cputovideo_next(s);
2044 }
2045 } else {
2046 /* video memory */
2047 bank_index = addr >> 15;
2048 bank_offset = addr & 0x7fff;
2049 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2050 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2051 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2052 bank_offset <<= 4;
4e12cd94 2053 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2054 bank_offset <<= 3;
2055 }
2056 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2057 mode = s->vga.gr[0x05] & 0x7;
2058 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2059 *(s->vga.vram_ptr + bank_offset) = mem_value;
2060 cpu_physical_memory_set_dirty(s->vga.vram_offset +
e6e5ad80
FB		 2061 bank_offset);
2062 } else {
4e12cd94 2063 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2064 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2065 bank_offset,
2066 mem_value);
2067 } else {
2068 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2069 bank_offset,
2070 mem_value);
2071 }
2072 }
2073 }
2074 }
2075 } else if (addr >= 0x18000 && addr < 0x18100) {
2076 /* memory-mapped I/O */
4e12cd94 2077 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2078 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2079 }
2080 } else {
2081#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2082 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2083 mem_value);
e6e5ad80
FB		 2084#endif
2085 }
2086}
2087
c227f099 2088static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80 2089{
e6e5ad80
FB		 2090 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2091 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
e6e5ad80
FB		 2092}
2093
c227f099 2094static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80 2095{
e6e5ad80
FB		 2096 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2097 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2098 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2099 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
e6e5ad80
FB		 2100}
2101
d60efc6b 2102static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
e6e5ad80
FB		 2103 cirrus_vga_mem_readb,
2104 cirrus_vga_mem_readw,
2105 cirrus_vga_mem_readl,
2106};
2107
d60efc6b 2108static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
e6e5ad80
FB		 2109 cirrus_vga_mem_writeb,
2110 cirrus_vga_mem_writew,
2111 cirrus_vga_mem_writel,
2112};
2113
a5082316
FB		 2114/***************************************
2115 *
2116 * hardware cursor
2117 *
2118 ***************************************/
2119
2120static inline void invalidate_cursor1(CirrusVGAState *s)
2121{
2122 if (s->last_hw_cursor_size) {
4e12cd94 2123 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2124 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2125 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2126 }
2127}
2128
2129static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2130{
2131 const uint8_t *src;
2132 uint32_t content;
2133 int y, y_min, y_max;
2134
4e12cd94
AK		 2135 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2136 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2137 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2138 y_min = 64;
2139 y_max = -1;
2140 for(y = 0; y < 64; y++) {
2141 content = ((uint32_t *)src)[0] |
2142 ((uint32_t *)src)[1] |
2143 ((uint32_t *)src)[2] |
2144 ((uint32_t *)src)[3];
2145 if (content) {
2146 if (y < y_min)
2147 y_min = y;
2148 if (y > y_max)
2149 y_max = y;
2150 }
2151 src += 16;
2152 }
2153 } else {
4e12cd94 2154 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2155 y_min = 32;
2156 y_max = -1;
2157 for(y = 0; y < 32; y++) {
2158 content = ((uint32_t *)src)[0] |
2159 ((uint32_t *)(src + 128))[0];
2160 if (content) {
2161 if (y < y_min)
2162 y_min = y;
2163 if (y > y_max)
2164 y_max = y;
2165 }
2166 src += 4;
2167 }
2168 }
2169 if (y_min > y_max) {
2170 s->last_hw_cursor_y_start = 0;
2171 s->last_hw_cursor_y_end = 0;
2172 } else {
2173 s->last_hw_cursor_y_start = y_min;
2174 s->last_hw_cursor_y_end = y_max + 1;
2175 }
2176}
2177
2178/* NOTE: we do not currently handle the cursor bitmap change, so we
2179 update the cursor only if it moves. */
a4a2f59c 2180static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2181{
4e12cd94 2182 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2183 int size;
2184
4e12cd94 2185 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2186 size = 0;
2187 } else {
4e12cd94 2188 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2189 size = 64;
2190 else
2191 size = 32;
2192 }
2193 /* invalidate last cursor and new cursor if any change */
2194 if (s->last_hw_cursor_size != size ||
2195 s->last_hw_cursor_x != s->hw_cursor_x ||
2196 s->last_hw_cursor_y != s->hw_cursor_y) {
2197
2198 invalidate_cursor1(s);
3b46e624 2199
a5082316
FB		 2200 s->last_hw_cursor_size = size;
2201 s->last_hw_cursor_x = s->hw_cursor_x;
2202 s->last_hw_cursor_y = s->hw_cursor_y;
2203 /* compute the real cursor min and max y */
2204 cirrus_cursor_compute_yrange(s);
2205 invalidate_cursor1(s);
2206 }
2207}
2208
a4a2f59c 2209static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2210{
4e12cd94 2211 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2212 int w, h, bpp, x1, x2, poffset;
2213 unsigned int color0, color1;
2214 const uint8_t *palette, *src;
2215 uint32_t content;
3b46e624 2216
4e12cd94 2217 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2218 return;
2219 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2220 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2221 h = 64;
2222 } else {
2223 h = 32;
2224 }
2225 if (scr_y < s->hw_cursor_y ||
2226 scr_y >= (s->hw_cursor_y + h))
2227 return;
3b46e624 2228
4e12cd94
AK		 2229 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2230 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2231 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2232 src += (scr_y - s->hw_cursor_y) * 16;
2233 poffset = 8;
2234 content = ((uint32_t *)src)[0] |
2235 ((uint32_t *)src)[1] |
2236 ((uint32_t *)src)[2] |
2237 ((uint32_t *)src)[3];
2238 } else {
4e12cd94 2239 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2240 src += (scr_y - s->hw_cursor_y) * 4;
2241 poffset = 128;
2242 content = ((uint32_t *)src)[0] |
2243 ((uint32_t *)(src + 128))[0];
2244 }
2245 /* if nothing to draw, no need to continue */
2246 if (!content)
2247 return;
2248 w = h;
2249
2250 x1 = s->hw_cursor_x;
4e12cd94 2251 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2252 return;
2253 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2254 if (x2 > s->vga.last_scr_width)
2255 x2 = s->vga.last_scr_width;
a5082316
FB		 2256 w = x2 - x1;
2257 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2258 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2259 c6_to_8(palette[0x0 * 3 + 1]),
2260 c6_to_8(palette[0x0 * 3 + 2]));
2261 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2262 c6_to_8(palette[0xf * 3 + 1]),
2263 c6_to_8(palette[0xf * 3 + 2]));
2264 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2265 d1 += x1 * bpp;
4e12cd94 2266 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2267 default:
2268 break;
2269 case 8:
2270 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2271 break;
2272 case 15:
2273 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2274 break;
2275 case 16:
2276 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2277 break;
2278 case 32:
2279 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2280 break;
2281 }
2282}
2283
e6e5ad80
FB		 2284/***************************************
2285 *
2286 * LFB memory access
2287 *
2288 ***************************************/
2289
c227f099 2290static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80 2291{
e05587e8 2292 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2293 uint32_t ret;
2294
e6e5ad80
FB		 2295 addr &= s->cirrus_addr_mask;
2296
4e12cd94 2297 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2298 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2299 /* memory-mapped I/O */
2300 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2301 } else if (0) {
2302 /* XXX handle bitblt */
2303 ret = 0xff;
2304 } else {
2305 /* video memory */
4e12cd94 2306 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2307 addr <<= 4;
4e12cd94 2308 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2309 addr <<= 3;
2310 }
2311 addr &= s->cirrus_addr_mask;
4e12cd94 2312 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2313 }
2314
2315 return ret;
2316}
2317
c227f099 2318static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2319{
2320 uint32_t v;
3fbb33d0 2321
e6e5ad80
FB		 2322 v = cirrus_linear_readb(opaque, addr);
2323 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
e6e5ad80
FB		 2324 return v;
2325}
2326
c227f099 2327static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2328{
2329 uint32_t v;
3fbb33d0 2330
e6e5ad80
FB		 2331 v = cirrus_linear_readb(opaque, addr);
2332 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2333 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2334 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
e6e5ad80
FB		 2335 return v;
2336}
2337
c227f099 2338static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2339 uint32_t val)
2340{
e05587e8 2341 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2342 unsigned mode;
2343
2344 addr &= s->cirrus_addr_mask;
3b46e624 2345
4e12cd94 2346 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2347 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2348 /* memory-mapped I/O */
2349 cirrus_mmio_blt_write(s, addr & 0xff, val);
2350 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2351 /* bitblt */
2352 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2353 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2354 cirrus_bitblt_cputovideo_next(s);
2355 }
2356 } else {
2357 /* video memory */
4e12cd94 2358 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2359 addr <<= 4;
4e12cd94 2360 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2361 addr <<= 3;
2362 }
2363 addr &= s->cirrus_addr_mask;
2364
4e12cd94
AK		 2365 mode = s->vga.gr[0x05] & 0x7;
2366 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2367 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2368 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
e6e5ad80 2369 } else {
4e12cd94 2370 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2371 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2372 } else {
2373 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2374 }
2375 }
2376 }
2377}
2378
c227f099 2379static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2380 uint32_t val)
2381{
e6e5ad80
FB		 2382 cirrus_linear_writeb(opaque, addr, val & 0xff);
2383 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
e6e5ad80
FB		 2384}
2385
c227f099 2386static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2387 uint32_t val)
2388{
e6e5ad80
FB		 2389 cirrus_linear_writeb(opaque, addr, val & 0xff);
2390 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2391 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2392 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
e6e5ad80
FB		 2393}
2394
2395
d60efc6b 2396static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
e6e5ad80
FB		 2397 cirrus_linear_readb,
2398 cirrus_linear_readw,
2399 cirrus_linear_readl,
2400};
2401
d60efc6b 2402static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
e6e5ad80
FB		 2403 cirrus_linear_writeb,
2404 cirrus_linear_writew,
2405 cirrus_linear_writel,
2406};
2407
a5082316
FB		 2408/***************************************
2409 *
2410 * system to screen memory access
2411 *
2412 ***************************************/
2413
2414
c227f099 2415static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2416{
2417 uint32_t ret;
2418
2419 /* XXX handle bitblt */
2420 ret = 0xff;
2421 return ret;
2422}
2423
c227f099 2424static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2425{
2426 uint32_t v;
3fbb33d0 2427
a5082316
FB		 2428 v = cirrus_linear_bitblt_readb(opaque, addr);
2429 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
a5082316
FB		 2430 return v;
2431}
2432
c227f099 2433static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2434{
2435 uint32_t v;
3fbb33d0 2436
a5082316
FB		 2437 v = cirrus_linear_bitblt_readb(opaque, addr);
2438 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2439 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2440 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
a5082316
FB		 2441 return v;
2442}
2443
c227f099 2444static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2445 uint32_t val)
2446{
e05587e8 2447 CirrusVGAState *s = opaque;
a5082316
FB		 2448
2449 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2450 /* bitblt */
2451 *s->cirrus_srcptr++ = (uint8_t) val;
2452 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2453 cirrus_bitblt_cputovideo_next(s);
2454 }
2455 }
2456}
2457
c227f099 2458static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2459 uint32_t val)
2460{
a5082316
FB		 2461 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2462 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a5082316
FB		 2463}
2464
c227f099 2465static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2466 uint32_t val)
2467{
a5082316
FB		 2468 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2469 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2470 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2471 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a5082316
FB		 2472}
2473
2474
d60efc6b 2475static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
a5082316
FB		 2476 cirrus_linear_bitblt_readb,
2477 cirrus_linear_bitblt_readw,
2478 cirrus_linear_bitblt_readl,
2479};
2480
d60efc6b 2481static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
a5082316
FB		 2482 cirrus_linear_bitblt_writeb,
2483 cirrus_linear_bitblt_writew,
2484 cirrus_linear_bitblt_writel,
2485};
2486
2bec46dc
AL		 2487static void map_linear_vram(CirrusVGAState *s)
2488{
4e12cd94
AK		 2489 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2490 s->vga.map_addr = s->vga.lfb_addr;
2491 s->vga.map_end = s->vga.lfb_end;
af94482b
MT		 2492 cpu_register_physical_memory_log(s->vga.map_addr,
2493 s->vga.map_end - s->vga.map_addr,
2494 s->vga.vram_offset, 0, true);
2bec46dc
AL		 2495 }
2496
4e12cd94 2497 if (!s->vga.map_addr)
2bec46dc
AL		 2498 return;
2499
4e12cd94 2500 s->vga.lfb_vram_mapped = 0;
2bec46dc
AL		 2501
2502 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2503 && !((s->vga.sr[0x07] & 0x01) == 0)
2504 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2505 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc 2506
af94482b
MT		 2507 cpu_register_physical_memory_log(isa_mem_base + 0xa0000, 0x8000,
2508 (s->vga.vram_offset +
2509 s->cirrus_bank_base[0]) |
2510 IO_MEM_RAM, 0, true);
2511 cpu_register_physical_memory_log(isa_mem_base + 0xa8000, 0x8000,
2512 (s->vga.vram_offset +
2513 s->cirrus_bank_base[1]) |
2514 IO_MEM_RAM, 0, true);
2bec46dc 2515
4e12cd94 2516 s->vga.lfb_vram_mapped = 1;
2bec46dc
AL		 2517 }
2518 else {
7cff316e 2519 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2520 s->vga.vga_io_memory);
2bec46dc
AL		 2521 }
2522
4e12cd94 2523 vga_dirty_log_start(&s->vga);
2bec46dc
AL		 2524}
2525
2526static void unmap_linear_vram(CirrusVGAState *s)
2527{
4516e45f 2528 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
4e12cd94 2529 s->vga.map_addr = s->vga.map_end = 0;
4516e45f
JK		 2530 cpu_register_physical_memory(s->vga.lfb_addr, s->vga.vram_size,
2531 s->cirrus_linear_io_addr);
2532 }
2bec46dc 2533 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2534 s->vga.vga_io_memory);
2bec46dc
AL		 2535}
2536
8926b517
FB		 2537/* Compute the memory access functions */
2538static void cirrus_update_memory_access(CirrusVGAState *s)
2539{
2540 unsigned mode;
2541
4e12cd94 2542 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2543 goto generic_io;
2544 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2545 goto generic_io;
2546 } else {
4e12cd94 2547 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2548 goto generic_io;
4e12cd94 2549 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2550 goto generic_io;
2551 }
3b46e624 2552
4e12cd94
AK		 2553 mode = s->vga.gr[0x05] & 0x7;
2554 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2555 map_linear_vram(s);
8926b517
FB		 2556 } else {
2557 generic_io:
2bec46dc 2558 unmap_linear_vram(s);
8926b517
FB		 2559 }
2560 }
2561}
2562
2563
e6e5ad80
FB		 2564/* I/O ports */
2565
0ceac75b 2566static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2567{
b6343073
JQ		 2568 CirrusVGAState *c = opaque;
2569 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2570 int val, index;
2571
b6343073 2572 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2573 val = 0xff;
2574 } else {
2575 switch (addr) {
2576 case 0x3c0:
b6343073
JQ		 2577 if (s->ar_flip_flop == 0) {
2578 val = s->ar_index;
e6e5ad80
FB		 2579 } else {
2580 val = 0;
2581 }
2582 break;
2583 case 0x3c1:
b6343073 2584 index = s->ar_index & 0x1f;
e6e5ad80 2585 if (index < 21)
b6343073 2586 val = s->ar[index];
e6e5ad80
FB		 2587 else
2588 val = 0;
2589 break;
2590 case 0x3c2:
b6343073 2591 val = s->st00;
e6e5ad80
FB		 2592 break;
2593 case 0x3c4:
b6343073 2594 val = s->sr_index;
e6e5ad80
FB		 2595 break;
2596 case 0x3c5:
8a82c322
JQ		 2597 val = cirrus_vga_read_sr(c);
2598 break;
e6e5ad80 2599#ifdef DEBUG_VGA_REG
b6343073 2600 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2601#endif
2602 break;
2603 case 0x3c6:
957c9db5 2604 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2605 break;
2606 case 0x3c7:
b6343073 2607 val = s->dac_state;
e6e5ad80 2608 break;
ae184e4a 2609 case 0x3c8:
b6343073
JQ		 2610 val = s->dac_write_index;
2611 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2612 break;
2613 case 0x3c9:
5deaeee3
JQ		 2614 val = cirrus_vga_read_palette(c);
2615 break;
e6e5ad80 2616 case 0x3ca:
b6343073 2617 val = s->fcr;
e6e5ad80
FB		 2618 break;
2619 case 0x3cc:
b6343073 2620 val = s->msr;
e6e5ad80
FB		 2621 break;
2622 case 0x3ce:
b6343073 2623 val = s->gr_index;
e6e5ad80
FB		 2624 break;
2625 case 0x3cf:
f705db9d 2626 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2627#ifdef DEBUG_VGA_REG
b6343073 2628 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2629#endif
2630 break;
2631 case 0x3b4:
2632 case 0x3d4:
b6343073 2633 val = s->cr_index;
e6e5ad80
FB		 2634 break;
2635 case 0x3b5:
2636 case 0x3d5:
b863d514 2637 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2638#ifdef DEBUG_VGA_REG
b6343073 2639 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2640#endif
2641 break;
2642 case 0x3ba:
2643 case 0x3da:
2644 /* just toggle to fool polling */
b6343073
JQ		 2645 val = s->st01 = s->retrace(s);
2646 s->ar_flip_flop = 0;
e6e5ad80
FB		 2647 break;
2648 default:
2649 val = 0x00;
2650 break;
2651 }
2652 }
2653#if defined(DEBUG_VGA)
2654 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2655#endif
2656 return val;
2657}
2658
0ceac75b 2659static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2660{
b6343073
JQ		 2661 CirrusVGAState *c = opaque;
2662 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2663 int index;
2664
2665 /* check port range access depending on color/monochrome mode */
b6343073 2666 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2667 return;
25a18cbd 2668 }
e6e5ad80
FB		 2669#ifdef DEBUG_VGA
2670 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2671#endif
2672
2673 switch (addr) {
2674 case 0x3c0:
b6343073 2675 if (s->ar_flip_flop == 0) {
e6e5ad80 2676 val &= 0x3f;
b6343073 2677 s->ar_index = val;
e6e5ad80 2678 } else {
b6343073 2679 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2680 switch (index) {
2681 case 0x00 ... 0x0f:
b6343073 2682 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2683 break;
2684 case 0x10:
b6343073 2685 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2686 break;
2687 case 0x11:
b6343073 2688 s->ar[index] = val;
e6e5ad80
FB		 2689 break;
2690 case 0x12:
b6343073 2691 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2692 break;
2693 case 0x13:
b6343073 2694 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2695 break;
2696 case 0x14:
b6343073 2697 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2698 break;
2699 default:
2700 break;
2701 }
2702 }
b6343073 2703 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2704 break;
2705 case 0x3c2:
b6343073
JQ		 2706 s->msr = val & ~0x10;
2707 s->update_retrace_info(s);
e6e5ad80
FB		 2708 break;
2709 case 0x3c4:
b6343073 2710 s->sr_index = val;
e6e5ad80
FB		 2711 break;
2712 case 0x3c5:
e6e5ad80 2713#ifdef DEBUG_VGA_REG
b6343073 2714 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2715#endif
31c63201
JQ		 2716 cirrus_vga_write_sr(c, val);
2717 break;
e6e5ad80
FB		 2718 break;
2719 case 0x3c6:
b6343073 2720 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2721 break;
2722 case 0x3c7:
b6343073
JQ		 2723 s->dac_read_index = val;
2724 s->dac_sub_index = 0;
2725 s->dac_state = 3;
e6e5ad80
FB		 2726 break;
2727 case 0x3c8:
b6343073
JQ		 2728 s->dac_write_index = val;
2729 s->dac_sub_index = 0;
2730 s->dac_state = 0;
e6e5ad80
FB		 2731 break;
2732 case 0x3c9:
86948bb1
JQ		 2733 cirrus_vga_write_palette(c, val);
2734 break;
e6e5ad80 2735 case 0x3ce:
b6343073 2736 s->gr_index = val;
e6e5ad80
FB		 2737 break;
2738 case 0x3cf:
e6e5ad80 2739#ifdef DEBUG_VGA_REG
b6343073 2740 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2741#endif
22286bc6 2742 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2743 break;
2744 case 0x3b4:
2745 case 0x3d4:
b6343073 2746 s->cr_index = val;
e6e5ad80
FB		 2747 break;
2748 case 0x3b5:
2749 case 0x3d5:
e6e5ad80 2750#ifdef DEBUG_VGA_REG
b6343073 2751 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2752#endif
4ec1ce04 2753 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2754 break;
2755 case 0x3ba:
2756 case 0x3da:
b6343073 2757 s->fcr = val & 0x10;
e6e5ad80
FB		 2758 break;
2759 }
2760}
2761
e36f36e1
FB		 2762/***************************************
2763 *
2764 * memory-mapped I/O access
2765 *
2766 ***************************************/
2767
c227f099 2768static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
e36f36e1 2769{
e05587e8 2770 CirrusVGAState *s = opaque;
e36f36e1
FB		 2771
2772 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2773
2774 if (addr >= 0x100) {
2775 return cirrus_mmio_blt_read(s, addr - 0x100);
2776 } else {
0ceac75b 2777 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2778 }
2779}
2780
c227f099 2781static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2782{
2783 uint32_t v;
3fbb33d0 2784
e36f36e1
FB		 2785 v = cirrus_mmio_readb(opaque, addr);
2786 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
e36f36e1
FB		 2787 return v;
2788}
2789
c227f099 2790static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2791{
2792 uint32_t v;
3fbb33d0 2793
e36f36e1
FB		 2794 v = cirrus_mmio_readb(opaque, addr);
2795 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2796 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2797 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
e36f36e1
FB		 2798 return v;
2799}
2800
c227f099 2801static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2802 uint32_t val)
2803{
e05587e8 2804 CirrusVGAState *s = opaque;
e36f36e1
FB		 2805
2806 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2807
2808 if (addr >= 0x100) {
2809 cirrus_mmio_blt_write(s, addr - 0x100, val);
2810 } else {
0ceac75b 2811 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2812 }
2813}
2814
c227f099 2815static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2816 uint32_t val)
2817{
e36f36e1
FB		 2818 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2819 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
e36f36e1
FB		 2820}
2821
c227f099 2822static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2823 uint32_t val)
2824{
e36f36e1
FB		 2825 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2826 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2827 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2828 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
e36f36e1
FB		 2829}
2830
2831
d60efc6b 2832static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
e36f36e1
FB		 2833 cirrus_mmio_readb,
2834 cirrus_mmio_readw,
2835 cirrus_mmio_readl,
2836};
2837
d60efc6b 2838static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
e36f36e1
FB		 2839 cirrus_mmio_writeb,
2840 cirrus_mmio_writew,
2841 cirrus_mmio_writel,
2842};
2843
2c6ab832
FB		 2844/* load/save state */
2845
e59fb374 2846static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2847{
2848 CirrusVGAState *s = opaque;
2849
4e12cd94
AK		 2850 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2851 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2852
2bec46dc 2853 cirrus_update_memory_access(s);
2c6ab832 2854 /* force refresh */
4e12cd94 2855 s->vga.graphic_mode = -1;
2c6ab832
FB		 2856 cirrus_update_bank_ptr(s, 0);
2857 cirrus_update_bank_ptr(s, 1);
2858 return 0;
2859}
2860
7e72abc3
JQ		 2861static const VMStateDescription vmstate_cirrus_vga = {
2862 .name = "cirrus_vga",
2863 .version_id = 2,
2864 .minimum_version_id = 1,
2865 .minimum_version_id_old = 1,
2866 .post_load = cirrus_post_load,
2867 .fields = (VMStateField []) {
2868 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2869 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2870 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2871 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2872 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2873 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2874 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2875 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2876 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2877 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2878 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2879 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2880 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2881 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2882 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2883 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2884 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2885 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2886 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2887 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2888 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2889 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2890 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2891 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2892 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2893 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2894 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2895 /* XXX: we do not save the bitblt state - we assume we do not save
2896 the state when the blitter is active */
2897 VMSTATE_END_OF_LIST()
4f335feb 2898 }
7e72abc3 2899};
4f335feb 2900
7e72abc3
JQ		 2901static const VMStateDescription vmstate_pci_cirrus_vga = {
2902 .name = "cirrus_vga",
2903 .version_id = 2,
2904 .minimum_version_id = 2,
2905 .minimum_version_id_old = 2,
7e72abc3
JQ		 2906 .fields = (VMStateField []) {
2907 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2908 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2909 vmstate_cirrus_vga, CirrusVGAState),
2910 VMSTATE_END_OF_LIST()
2911 }
2912};
4f335feb 2913
e6e5ad80
FB		 2914/***************************************
2915 *
2916 * initialize
2917 *
2918 ***************************************/
2919
4abc796d 2920static void cirrus_reset(void *opaque)
e6e5ad80 2921{
4abc796d 2922 CirrusVGAState *s = opaque;
e6e5ad80 2923
03a3e7ba 2924 vga_common_reset(&s->vga);
ee50c6bc 2925 unmap_linear_vram(s);
4e12cd94 2926 s->vga.sr[0x06] = 0x0f;
4abc796d 2927 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2928 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2929 s->vga.sr[0x1F] = 0x2d; // MemClock
2930 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2931 s->vga.sr[0x0f] = 0x98;
2932 s->vga.sr[0x17] = 0x20;
2933 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2934 } else {
4e12cd94
AK		 2935 s->vga.sr[0x1F] = 0x22; // MemClock
2936 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2937 s->vga.sr[0x17] = s->bustype;
2938 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2939 }
4e12cd94 2940 s->vga.cr[0x27] = s->device_id;
e6e5ad80 2941
78e127ef
FB		 2942 /* Win2K seems to assume that the pattern buffer is at 0xff
2943 initially ! */
4e12cd94 2944 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 2945
e6e5ad80
FB		 2946 s->cirrus_hidden_dac_lockindex = 5;
2947 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2948}
2949
2950static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2951{
2952 int i;
2953 static int inited;
2954
2955 if (!inited) {
2956 inited = 1;
2957 for(i = 0;i < 256; i++)
2958 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2959 rop_to_index[CIRRUS_ROP_0] = 0;
2960 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2961 rop_to_index[CIRRUS_ROP_NOP] = 2;
2962 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2963 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2964 rop_to_index[CIRRUS_ROP_SRC] = 5;
2965 rop_to_index[CIRRUS_ROP_1] = 6;
2966 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2967 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2968 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2969 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2970 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2971 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2972 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2973 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2974 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2975 s->device_id = device_id;
2976 if (is_pci)
2977 s->bustype = CIRRUS_BUSTYPE_PCI;
2978 else
2979 s->bustype = CIRRUS_BUSTYPE_ISA;
2980 }
2981
0ceac75b 2982 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2983
0ceac75b
JQ		 2984 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2985 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2986 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2987 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2988
0ceac75b 2989 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2990
0ceac75b
JQ		 2991 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2992 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2993 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2994 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2995
1eed09cb 2996 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
2507c12a 2997 cirrus_vga_mem_write, s,
3fbb33d0 2998 DEVICE_LITTLE_ENDIAN);
4abc796d 2999 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
4e12cd94 3000 s->vga.vga_io_memory);
4abc796d 3001 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2c6ab832 3002
fefe54e3
AL		 3003 /* I/O handler for LFB */
3004 s->cirrus_linear_io_addr =
2507c12a 3005 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
3fbb33d0 3006 DEVICE_LITTLE_ENDIAN);
fefe54e3
AL		 3007
3008 /* I/O handler for LFB */
3009 s->cirrus_linear_bitblt_io_addr =
1eed09cb 3010 cpu_register_io_memory(cirrus_linear_bitblt_read,
2507c12a 3011 cirrus_linear_bitblt_write, s,
3fbb33d0 3012 DEVICE_LITTLE_ENDIAN);
fefe54e3
AL		 3013
3014 /* I/O handler for memory-mapped I/O */
3015 s->cirrus_mmio_io_addr =
2507c12a 3016 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
3fbb33d0 3017 DEVICE_LITTLE_ENDIAN);
fefe54e3
AL		 3018
3019 s->real_vram_size =
3020 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3021
4e12cd94 3022 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 3023 s->cirrus_addr_mask = s->real_vram_size - 1;
3024 s->linear_mmio_mask = s->real_vram_size - 256;
3025
4e12cd94
AK		 3026 s->vga.get_bpp = cirrus_get_bpp;
3027 s->vga.get_offsets = cirrus_get_offsets;
3028 s->vga.get_resolution = cirrus_get_resolution;
3029 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3030 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 3031
a08d4367 3032 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 3033}
3034
3035/***************************************
3036 *
3037 * ISA bus support
3038 *
3039 ***************************************/
3040
fbe1b595 3041void isa_cirrus_vga_init(void)
e6e5ad80
FB		 3042{
3043 CirrusVGAState *s;
3044
3045 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3046
fbe1b595 3047 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3048 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 3049 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3050 s->vga.screen_dump, s->vga.text_update,
3051 &s->vga);
0be71e32 3052 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
5245d57a 3053 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80
FB		 3054 /* XXX ISA-LFB support */
3055}
3056
3057/***************************************
3058 *
3059 * PCI bus support
3060 *
3061 ***************************************/
3062
3063static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
6e355d90 3064 pcibus_t addr, pcibus_t size, int type)
e6e5ad80 3065{
f3566bf9 3066 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
e6e5ad80 3067
a5082316 3068 /* XXX: add byte swapping apertures */
4e12cd94 3069 cpu_register_physical_memory(addr, s->vga.vram_size,
e6e5ad80 3070 s->cirrus_linear_io_addr);
a5082316
FB		 3071 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3072 s->cirrus_linear_bitblt_io_addr);
2bec46dc 3073
4e12cd94
AK		 3074 s->vga.map_addr = s->vga.map_end = 0;
3075 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3076 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2bec46dc 3077 /* account for overflow */
4e12cd94
AK		 3078 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3079 s->vga.lfb_end = addr + VGA_RAM_SIZE;
ba7349cd 3080
4e12cd94 3081 vga_dirty_log_start(&s->vga);
e6e5ad80
FB		 3082}
3083
ba7349cd
AL		 3084static void pci_cirrus_write_config(PCIDevice *d,
3085 uint32_t address, uint32_t val, int len)
3086{
f3566bf9 3087 PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
ba7349cd
AL		 3088 CirrusVGAState *s = &pvs->cirrus_vga;
3089
ba7349cd 3090 pci_default_write_config(d, address, val, len);
45dcd36e 3091 if (s->vga.map_addr && d->io_regions[0].addr == PCI_BAR_UNMAPPED) {
4e12cd94 3092 s->vga.map_addr = 0;
45dcd36e
SS		 3093 s->vga.lfb_addr = 0;
3094 s->vga.lfb_end = 0;
3095 }
ba7349cd 3096 cirrus_update_memory_access(s);
ba7349cd
AL		 3097}
3098
81a322d4 3099static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 3100{
3101 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3102 CirrusVGAState *s = &d->cirrus_vga;
5b96d8f9
IY		 3103 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
3104 int16_t device_id = info->device_id;
a414c306
GH		 3105
3106 /* setup VGA */
3107 vga_common_init(&s->vga, VGA_RAM_SIZE);
3108 cirrus_init_common(s, device_id, 1);
a414c306
GH		 3109 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3110 s->vga.screen_dump, s->vga.text_update,
3111 &s->vga);
3112
3113 /* setup PCI */
a414c306
GH		 3114
3115 /* setup memory space */
3116 /* memory #0 LFB */
3117 /* memory #1 memory-mapped I/O */
3118 /* XXX: s->vga.vram_size must be a power of two */
b90c73cf 3119 pci_register_bar(&d->dev, 0, 0x2000000,
0392a017 3120 PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map);
a414c306 3121 if (device_id == CIRRUS_ID_CLGD5446) {
e30376da
AK		 3122 pci_register_bar_simple(&d->dev, 1, CIRRUS_PNPMMIO_SIZE, 0,
3123 s->cirrus_mmio_io_addr);
a414c306 3124 }
81a322d4 3125 return 0;
a414c306
GH		 3126}
3127
fbe1b595 3128void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 3129{
556cd098 3130 pci_create_simple(bus, -1, "cirrus-vga");
a414c306 3131}
d34cab9f 3132
a414c306 3133static PCIDeviceInfo cirrus_vga_info = {
556cd098
MA		 3134 .qdev.name = "cirrus-vga",
3135 .qdev.desc = "Cirrus CLGD 54xx VGA",
a414c306 3136 .qdev.size = sizeof(PCICirrusVGAState),
be73cfe2 3137 .qdev.vmsd = &vmstate_pci_cirrus_vga,
be92bbf7 3138 .no_hotplug = 1,
a414c306 3139 .init = pci_cirrus_vga_initfn,
8c52c8f3 3140 .romfile = VGABIOS_CIRRUS_FILENAME,
a414c306 3141 .config_write = pci_cirrus_write_config,
5b96d8f9
IY		 3142 .vendor_id = PCI_VENDOR_ID_CIRRUS,
3143 .device_id = CIRRUS_ID_CLGD5446,
3144 .class_id = PCI_CLASS_DISPLAY_VGA,
a414c306 3145};
e6e5ad80 3146
a414c306
GH		 3147static void cirrus_vga_register(void)
3148{
3149 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 3150}
a414c306 3151device_init(cirrus_vga_register);
Qemu copy for testing