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[qemu.git] / hw / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80
FB		 33#include "vga_int.h"
34
a5082316
FB		 35/*
36 * TODO:
ad81218e 37 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
e36f36e1 42//#define DEBUG_CIRRUS
a21ae81d 43//#define DEBUG_BITBLT
e36f36e1 44
e6e5ad80
FB		 45/***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
51#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
52
53// ID
54#define CIRRUS_ID_CLGD5422 (0x23<<2)
55#define CIRRUS_ID_CLGD5426 (0x24<<2)
56#define CIRRUS_ID_CLGD5424 (0x25<<2)
57#define CIRRUS_ID_CLGD5428 (0x26<<2)
58#define CIRRUS_ID_CLGD5430 (0x28<<2)
59#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 60#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 61#define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
175// PCI 0x00: vendor, 0x02: device
176#define PCI_VENDOR_CIRRUS 0x1013
e6e5ad80
FB		 177#define PCI_DEVICE_CLGD5462 0x00d0
178#define PCI_DEVICE_CLGD5465 0x00d6
a21ae81d 179
e6e5ad80
FB		 180// PCI 0x04: command(word), 0x06(word): status
181#define PCI_COMMAND_IOACCESS 0x0001
182#define PCI_COMMAND_MEMACCESS 0x0002
183#define PCI_COMMAND_BUSMASTER 0x0004
184#define PCI_COMMAND_SPECIALCYCLE 0x0008
185#define PCI_COMMAND_MEMWRITEINVALID 0x0010
186#define PCI_COMMAND_PALETTESNOOPING 0x0020
187#define PCI_COMMAND_PARITYDETECTION 0x0040
188#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189#define PCI_COMMAND_SERR 0x0100
190#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192#define PCI_CLASS_BASE_DISPLAY 0x03
193// PCI 0x08, 0x00ff0000
194#define PCI_CLASS_SUB_VGA 0x00
195// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196#define PCI_CLASS_HEADERTYPE_00h 0x00
197// 0x10-0x3f (headertype 00h)
198// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200#define PCI_MAP_MEM 0x0
201#define PCI_MAP_IO 0x1
202#define PCI_MAP_MEM_ADDR_MASK (~0xf)
203#define PCI_MAP_IO_ADDR_MASK (~0x3)
204#define PCI_MAP_MEMFLAGS_32BIT 0x0
205#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206#define PCI_MAP_MEMFLAGS_64BIT 0x4
207#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208// PCI 0x28: cardbus CIS pointer
209// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210// PCI 0x30: expansion ROM base address
211#define PCI_ROMBIOS_ENABLED 0x1
212// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213// PCI 0x38: reserved
214// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
215
a21ae81d 216#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 217
218
219/* I/O and memory hook */
220#define CIRRUS_HOOK_NOT_HANDLED 0
221#define CIRRUS_HOOK_HANDLED 1
222
b2eb849d
AJ		 223#define BLTUNSAFE(s) \
224 ( \
225 ( /* check dst is within bounds */ \
226 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
227 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
228 (s)->vram_size \
229 ) || \
230 ( /* check src is within bounds */ \
231 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
232 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
233 (s)->vram_size \
234 ) \
235 )
236
a5082316
FB		 237struct CirrusVGAState;
238typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
239 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 240 int dstpitch, int srcpitch,
241 int bltwidth, int bltheight);
a5082316
FB		 242typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
243 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 244
245typedef struct CirrusVGAState {
4e3e9d0b 246 VGA_STATE_COMMON
e6e5ad80
FB		 247
248 int cirrus_linear_io_addr;
a5082316 249 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 250 int cirrus_mmio_io_addr;
251 uint32_t cirrus_addr_mask;
78e127ef 252 uint32_t linear_mmio_mask;
e6e5ad80
FB		 253 uint8_t cirrus_shadow_gr0;
254 uint8_t cirrus_shadow_gr1;
255 uint8_t cirrus_hidden_dac_lockindex;
256 uint8_t cirrus_hidden_dac_data;
257 uint32_t cirrus_bank_base[2];
258 uint32_t cirrus_bank_limit[2];
259 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 260 uint32_t hw_cursor_x;
261 uint32_t hw_cursor_y;
e6e5ad80
FB		 262 int cirrus_blt_pixelwidth;
263 int cirrus_blt_width;
264 int cirrus_blt_height;
265 int cirrus_blt_dstpitch;
266 int cirrus_blt_srcpitch;
a5082316
FB		 267 uint32_t cirrus_blt_fgcol;
268 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 269 uint32_t cirrus_blt_dstaddr;
270 uint32_t cirrus_blt_srcaddr;
271 uint8_t cirrus_blt_mode;
a5082316 272 uint8_t cirrus_blt_modeext;
e6e5ad80 273 cirrus_bitblt_rop_t cirrus_rop;
a5082316 274#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 275 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
276 uint8_t *cirrus_srcptr;
277 uint8_t *cirrus_srcptr_end;
278 uint32_t cirrus_srccounter;
a5082316
FB		 279 /* hwcursor display state */
280 int last_hw_cursor_size;
281 int last_hw_cursor_x;
282 int last_hw_cursor_y;
283 int last_hw_cursor_y_start;
284 int last_hw_cursor_y_end;
78e127ef 285 int real_vram_size; /* XXX: suppress that */
8926b517 286 CPUWriteMemoryFunc **cirrus_linear_write;
e6e5ad80
FB		 287} CirrusVGAState;
288
289typedef struct PCICirrusVGAState {
290 PCIDevice dev;
291 CirrusVGAState cirrus_vga;
292} PCICirrusVGAState;
293
a5082316 294static uint8_t rop_to_index[256];
3b46e624 295
e6e5ad80
FB		 296/***************************************
297 *
298 * prototypes.
299 *
300 ***************************************/
301
302
8926b517
FB		 303static void cirrus_bitblt_reset(CirrusVGAState *s);
304static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 305
306/***************************************
307 *
308 * raster operations
309 *
310 ***************************************/
311
a5082316
FB		 312static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
313 uint8_t *dst,const uint8_t *src,
314 int dstpitch,int srcpitch,
315 int bltwidth,int bltheight)
316{
e6e5ad80
FB		 317}
318
a5082316
FB		 319static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
320 uint8_t *dst,
321 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 322{
a5082316 323}
e6e5ad80 324
a5082316
FB		 325#define ROP_NAME 0
326#define ROP_OP(d, s) d = 0
327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316
FB		 329#define ROP_NAME src_and_dst
330#define ROP_OP(d, s) d = (s) & (d)
331#include "cirrus_vga_rop.h"
e6e5ad80 332
a5082316
FB		 333#define ROP_NAME src_and_notdst
334#define ROP_OP(d, s) d = (s) & (~(d))
335#include "cirrus_vga_rop.h"
e6e5ad80 336
a5082316
FB		 337#define ROP_NAME notdst
338#define ROP_OP(d, s) d = ~(d)
339#include "cirrus_vga_rop.h"
e6e5ad80 340
a5082316
FB		 341#define ROP_NAME src
342#define ROP_OP(d, s) d = s
343#include "cirrus_vga_rop.h"
e6e5ad80 344
a5082316 345#define ROP_NAME 1
4c8732d7 346#define ROP_OP(d, s) d = ~0
a5082316
FB		 347#include "cirrus_vga_rop.h"
348
349#define ROP_NAME notsrc_and_dst
350#define ROP_OP(d, s) d = (~(s)) & (d)
351#include "cirrus_vga_rop.h"
352
353#define ROP_NAME src_xor_dst
354#define ROP_OP(d, s) d = (s) ^ (d)
355#include "cirrus_vga_rop.h"
356
357#define ROP_NAME src_or_dst
358#define ROP_OP(d, s) d = (s) | (d)
359#include "cirrus_vga_rop.h"
360
361#define ROP_NAME notsrc_or_notdst
362#define ROP_OP(d, s) d = (~(s)) | (~(d))
363#include "cirrus_vga_rop.h"
364
365#define ROP_NAME src_notxor_dst
366#define ROP_OP(d, s) d = ~((s) ^ (d))
367#include "cirrus_vga_rop.h"
e6e5ad80 368
a5082316
FB		 369#define ROP_NAME src_or_notdst
370#define ROP_OP(d, s) d = (s) | (~(d))
371#include "cirrus_vga_rop.h"
372
373#define ROP_NAME notsrc
374#define ROP_OP(d, s) d = (~(s))
375#include "cirrus_vga_rop.h"
376
377#define ROP_NAME notsrc_or_dst
378#define ROP_OP(d, s) d = (~(s)) | (d)
379#include "cirrus_vga_rop.h"
380
381#define ROP_NAME notsrc_and_notdst
382#define ROP_OP(d, s) d = (~(s)) & (~(d))
383#include "cirrus_vga_rop.h"
384
385static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
386 cirrus_bitblt_rop_fwd_0,
387 cirrus_bitblt_rop_fwd_src_and_dst,
388 cirrus_bitblt_rop_nop,
389 cirrus_bitblt_rop_fwd_src_and_notdst,
390 cirrus_bitblt_rop_fwd_notdst,
391 cirrus_bitblt_rop_fwd_src,
392 cirrus_bitblt_rop_fwd_1,
393 cirrus_bitblt_rop_fwd_notsrc_and_dst,
394 cirrus_bitblt_rop_fwd_src_xor_dst,
395 cirrus_bitblt_rop_fwd_src_or_dst,
396 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
397 cirrus_bitblt_rop_fwd_src_notxor_dst,
398 cirrus_bitblt_rop_fwd_src_or_notdst,
399 cirrus_bitblt_rop_fwd_notsrc,
400 cirrus_bitblt_rop_fwd_notsrc_or_dst,
401 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
402};
403
404static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
405 cirrus_bitblt_rop_bkwd_0,
406 cirrus_bitblt_rop_bkwd_src_and_dst,
407 cirrus_bitblt_rop_nop,
408 cirrus_bitblt_rop_bkwd_src_and_notdst,
409 cirrus_bitblt_rop_bkwd_notdst,
410 cirrus_bitblt_rop_bkwd_src,
411 cirrus_bitblt_rop_bkwd_1,
412 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
413 cirrus_bitblt_rop_bkwd_src_xor_dst,
414 cirrus_bitblt_rop_bkwd_src_or_dst,
415 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
416 cirrus_bitblt_rop_bkwd_src_notxor_dst,
417 cirrus_bitblt_rop_bkwd_src_or_notdst,
418 cirrus_bitblt_rop_bkwd_notsrc,
419 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
420 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
421};
96cf2df8
TS		 422
423#define TRANSP_ROP(name) {\
424 name ## _8,\
425 name ## _16,\
426 }
427#define TRANSP_NOP(func) {\
428 func,\
429 func,\
430 }
431
432static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
435 TRANSP_NOP(cirrus_bitblt_rop_nop),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
449};
450
451static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
454 TRANSP_NOP(cirrus_bitblt_rop_nop),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
468};
469
a5082316
FB		 470#define ROP2(name) {\
471 name ## _8,\
472 name ## _16,\
473 name ## _24,\
474 name ## _32,\
475 }
476
477#define ROP_NOP2(func) {\
478 func,\
479 func,\
480 func,\
481 func,\
482 }
483
e69390ce
FB		 484static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
485 ROP2(cirrus_patternfill_0),
486 ROP2(cirrus_patternfill_src_and_dst),
487 ROP_NOP2(cirrus_bitblt_rop_nop),
488 ROP2(cirrus_patternfill_src_and_notdst),
489 ROP2(cirrus_patternfill_notdst),
490 ROP2(cirrus_patternfill_src),
491 ROP2(cirrus_patternfill_1),
492 ROP2(cirrus_patternfill_notsrc_and_dst),
493 ROP2(cirrus_patternfill_src_xor_dst),
494 ROP2(cirrus_patternfill_src_or_dst),
495 ROP2(cirrus_patternfill_notsrc_or_notdst),
496 ROP2(cirrus_patternfill_src_notxor_dst),
497 ROP2(cirrus_patternfill_src_or_notdst),
498 ROP2(cirrus_patternfill_notsrc),
499 ROP2(cirrus_patternfill_notsrc_or_dst),
500 ROP2(cirrus_patternfill_notsrc_and_notdst),
501};
502
a5082316
FB		 503static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
504 ROP2(cirrus_colorexpand_transp_0),
505 ROP2(cirrus_colorexpand_transp_src_and_dst),
506 ROP_NOP2(cirrus_bitblt_rop_nop),
507 ROP2(cirrus_colorexpand_transp_src_and_notdst),
508 ROP2(cirrus_colorexpand_transp_notdst),
509 ROP2(cirrus_colorexpand_transp_src),
510 ROP2(cirrus_colorexpand_transp_1),
511 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
512 ROP2(cirrus_colorexpand_transp_src_xor_dst),
513 ROP2(cirrus_colorexpand_transp_src_or_dst),
514 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
515 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
516 ROP2(cirrus_colorexpand_transp_src_or_notdst),
517 ROP2(cirrus_colorexpand_transp_notsrc),
518 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
519 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
520};
521
522static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
523 ROP2(cirrus_colorexpand_0),
524 ROP2(cirrus_colorexpand_src_and_dst),
525 ROP_NOP2(cirrus_bitblt_rop_nop),
526 ROP2(cirrus_colorexpand_src_and_notdst),
527 ROP2(cirrus_colorexpand_notdst),
528 ROP2(cirrus_colorexpand_src),
529 ROP2(cirrus_colorexpand_1),
530 ROP2(cirrus_colorexpand_notsrc_and_dst),
531 ROP2(cirrus_colorexpand_src_xor_dst),
532 ROP2(cirrus_colorexpand_src_or_dst),
533 ROP2(cirrus_colorexpand_notsrc_or_notdst),
534 ROP2(cirrus_colorexpand_src_notxor_dst),
535 ROP2(cirrus_colorexpand_src_or_notdst),
536 ROP2(cirrus_colorexpand_notsrc),
537 ROP2(cirrus_colorexpand_notsrc_or_dst),
538 ROP2(cirrus_colorexpand_notsrc_and_notdst),
539};
540
b30d4608
FB		 541static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
542 ROP2(cirrus_colorexpand_pattern_transp_0),
543 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
544 ROP_NOP2(cirrus_bitblt_rop_nop),
545 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
546 ROP2(cirrus_colorexpand_pattern_transp_notdst),
547 ROP2(cirrus_colorexpand_pattern_transp_src),
548 ROP2(cirrus_colorexpand_pattern_transp_1),
549 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
551 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
552 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
554 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
556 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
558};
559
560static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
561 ROP2(cirrus_colorexpand_pattern_0),
562 ROP2(cirrus_colorexpand_pattern_src_and_dst),
563 ROP_NOP2(cirrus_bitblt_rop_nop),
564 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
565 ROP2(cirrus_colorexpand_pattern_notdst),
566 ROP2(cirrus_colorexpand_pattern_src),
567 ROP2(cirrus_colorexpand_pattern_1),
568 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
569 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
570 ROP2(cirrus_colorexpand_pattern_src_or_dst),
571 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
572 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
573 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
574 ROP2(cirrus_colorexpand_pattern_notsrc),
575 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
576 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
577};
578
a5082316
FB		 579static const cirrus_fill_t cirrus_fill[16][4] = {
580 ROP2(cirrus_fill_0),
581 ROP2(cirrus_fill_src_and_dst),
582 ROP_NOP2(cirrus_bitblt_fill_nop),
583 ROP2(cirrus_fill_src_and_notdst),
584 ROP2(cirrus_fill_notdst),
585 ROP2(cirrus_fill_src),
586 ROP2(cirrus_fill_1),
587 ROP2(cirrus_fill_notsrc_and_dst),
588 ROP2(cirrus_fill_src_xor_dst),
589 ROP2(cirrus_fill_src_or_dst),
590 ROP2(cirrus_fill_notsrc_or_notdst),
591 ROP2(cirrus_fill_src_notxor_dst),
592 ROP2(cirrus_fill_src_or_notdst),
593 ROP2(cirrus_fill_notsrc),
594 ROP2(cirrus_fill_notsrc_or_dst),
595 ROP2(cirrus_fill_notsrc_and_notdst),
596};
597
598static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 599{
a5082316
FB		 600 unsigned int color;
601 switch (s->cirrus_blt_pixelwidth) {
602 case 1:
603 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
604 break;
605 case 2:
606 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
607 s->cirrus_blt_fgcol = le16_to_cpu(color);
608 break;
609 case 3:
5fafdf24 610 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
a5082316
FB		 611 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
612 break;
613 default:
614 case 4:
615 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
616 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
617 s->cirrus_blt_fgcol = le32_to_cpu(color);
618 break;
e6e5ad80
FB		 619 }
620}
621
a5082316 622static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 623{
a5082316 624 unsigned int color;
e6e5ad80
FB		 625 switch (s->cirrus_blt_pixelwidth) {
626 case 1:
a5082316
FB		 627 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
628 break;
e6e5ad80 629 case 2:
a5082316
FB		 630 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
631 s->cirrus_blt_bgcol = le16_to_cpu(color);
632 break;
e6e5ad80 633 case 3:
5fafdf24 634 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
a5082316
FB		 635 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
636 break;
e6e5ad80 637 default:
a5082316
FB		 638 case 4:
639 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
640 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
641 s->cirrus_blt_bgcol = le32_to_cpu(color);
642 break;
e6e5ad80
FB		 643 }
644}
645
646static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
647 int off_pitch, int bytesperline,
648 int lines)
649{
650 int y;
651 int off_cur;
652 int off_cur_end;
653
654 for (y = 0; y < lines; y++) {
655 off_cur = off_begin;
b2eb849d 656 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 657 off_cur &= TARGET_PAGE_MASK;
658 while (off_cur < off_cur_end) {
659 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
660 off_cur += TARGET_PAGE_SIZE;
661 }
662 off_begin += off_pitch;
663 }
664}
665
e6e5ad80
FB		 666static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
667 const uint8_t * src)
668{
e6e5ad80 669 uint8_t *dst;
e6e5ad80 670
b2eb849d
AJ		 671 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
672
673 if (BLTUNSAFE(s))
674 return 0;
675
e69390ce 676 (*s->cirrus_rop) (s, dst, src,
5fafdf24 677 s->cirrus_blt_dstpitch, 0,
e69390ce 678 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 679 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 680 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
681 s->cirrus_blt_height);
e6e5ad80
FB		 682 return 1;
683}
684
a21ae81d
FB		 685/* fill */
686
a5082316 687static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 688{
a5082316 689 cirrus_fill_t rop_func;
a21ae81d 690
b2eb849d
AJ		 691 if (BLTUNSAFE(s))
692 return 0;
a5082316 693 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
b2eb849d 694 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 695 s->cirrus_blt_dstpitch,
696 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 697 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
698 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
699 s->cirrus_blt_height);
700 cirrus_bitblt_reset(s);
701 return 1;
702}
703
e6e5ad80
FB		 704/***************************************
705 *
706 * bitblt (video-to-video)
707 *
708 ***************************************/
709
710static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
711{
712 return cirrus_bitblt_common_patterncopy(s,
b2eb849d
AJ		 713 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
714 s->cirrus_addr_mask));
e6e5ad80
FB		 715}
716
24236869 717static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 718{
24236869
FB		 719 int sx, sy;
720 int dx, dy;
721 int width, height;
722 int depth;
723 int notify = 0;
724
725 depth = s->get_bpp((VGAState *)s) / 8;
726 s->get_resolution((VGAState *)s, &width, &height);
727
728 /* extra x, y */
729 sx = (src % (width * depth)) / depth;
730 sy = (src / (width * depth));
731 dx = (dst % (width *depth)) / depth;
732 dy = (dst / (width * depth));
733
734 /* normalize width */
735 w /= depth;
736
737 /* if we're doing a backward copy, we have to adjust
738 our x/y to be the upper left corner (instead of the lower
739 right corner) */
740 if (s->cirrus_blt_dstpitch < 0) {
741 sx -= (s->cirrus_blt_width / depth) - 1;
742 dx -= (s->cirrus_blt_width / depth) - 1;
743 sy -= s->cirrus_blt_height - 1;
744 dy -= s->cirrus_blt_height - 1;
745 }
746
747 /* are we in the visible portion of memory? */
748 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
749 (sx + w) <= width && (sy + h) <= height &&
750 (dx + w) <= width && (dy + h) <= height) {
751 notify = 1;
752 }
753
754 /* make to sure only copy if it's a plain copy ROP */
755 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
756 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
757 notify = 0;
758
759 /* we have to flush all pending changes so that the copy
760 is generated at the appropriate moment in time */
761 if (notify)
762 vga_hw_update();
763
b2eb849d
AJ		 764 (*s->cirrus_rop) (s, s->vram_ptr +
765 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
766 s->vram_ptr +
767 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 768 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
769 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 770
771 if (notify)
38334f76
AZ		 772 qemu_console_copy(s->console,
773 sx, sy, dx, dy,
774 s->cirrus_blt_width / depth,
775 s->cirrus_blt_height);
24236869
FB		 776
777 /* we don't have to notify the display that this portion has
38334f76 778 changed since qemu_console_copy implies this */
24236869
FB		 779
780 if (!notify)
781 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
782 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
783 s->cirrus_blt_height);
784}
785
786static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
787{
65d35a09
AJ		 788 if (BLTUNSAFE(s))
789 return 0;
790
24236869
FB		 791 if (s->ds->dpy_copy) {
792 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
793 s->cirrus_blt_srcaddr - s->start_addr,
794 s->cirrus_blt_width, s->cirrus_blt_height);
795 } else {
b2eb849d
AJ		 796 (*s->cirrus_rop) (s, s->vram_ptr +
797 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
798 s->vram_ptr +
799 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
24236869
FB		 800 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
801 s->cirrus_blt_width, s->cirrus_blt_height);
802
803 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
804 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
805 s->cirrus_blt_height);
806 }
807
e6e5ad80
FB		 808 return 1;
809}
810
811/***************************************
812 *
813 * bitblt (cpu-to-video)
814 *
815 ***************************************/
816
e6e5ad80
FB		 817static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
818{
819 int copy_count;
a5082316 820 uint8_t *end_ptr;
3b46e624 821
e6e5ad80 822 if (s->cirrus_srccounter > 0) {
a5082316
FB		 823 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
824 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
825 the_end:
826 s->cirrus_srccounter = 0;
827 cirrus_bitblt_reset(s);
828 } else {
829 /* at least one scan line */
830 do {
b2eb849d
AJ		 831 (*s->cirrus_rop)(s, s->vram_ptr +
832 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
833 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 834 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
835 s->cirrus_blt_width, 1);
836 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
837 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
838 if (s->cirrus_srccounter <= 0)
839 goto the_end;
840 /* more bytes than needed can be transfered because of
841 word alignment, so we keep them for the next line */
842 /* XXX: keep alignment to speed up transfer */
843 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
844 copy_count = s->cirrus_srcptr_end - end_ptr;
845 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
846 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
847 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
848 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
849 }
e6e5ad80
FB		 850 }
851}
852
853/***************************************
854 *
855 * bitblt wrapper
856 *
857 ***************************************/
858
859static void cirrus_bitblt_reset(CirrusVGAState * s)
860{
861 s->gr[0x31] &=
862 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
863 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
864 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
865 s->cirrus_srccounter = 0;
8926b517 866 cirrus_update_memory_access(s);
e6e5ad80
FB		 867}
868
869static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
870{
a5082316
FB		 871 int w;
872
e6e5ad80
FB		 873 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
874 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
875 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
876
877 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
878 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 879 s->cirrus_blt_srcpitch = 8;
e6e5ad80 880 } else {
b30d4608 881 /* XXX: check for 24 bpp */
a5082316 882 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 883 }
a5082316 884 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 885 } else {
886 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 887 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 888 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 889 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
890 else
891 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 892 } else {
c9c0eae8
FB		 893 /* always align input size to 32 bits */
894 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 895 }
a5082316 896 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 897 }
a5082316
FB		 898 s->cirrus_srcptr = s->cirrus_bltbuf;
899 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 900 cirrus_update_memory_access(s);
e6e5ad80
FB		 901 return 1;
902}
903
904static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
905{
906 /* XXX */
a5082316 907#ifdef DEBUG_BITBLT
e6e5ad80
FB		 908 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
909#endif
910 return 0;
911}
912
913static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
914{
915 int ret;
916
917 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
918 ret = cirrus_bitblt_videotovideo_patterncopy(s);
919 } else {
920 ret = cirrus_bitblt_videotovideo_copy(s);
921 }
e6e5ad80
FB		 922 if (ret)
923 cirrus_bitblt_reset(s);
924 return ret;
925}
926
927static void cirrus_bitblt_start(CirrusVGAState * s)
928{
929 uint8_t blt_rop;
930
a5082316
FB		 931 s->gr[0x31] |= CIRRUS_BLT_BUSY;
932
e6e5ad80
FB		 933 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
934 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
935 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
936 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
937 s->cirrus_blt_dstaddr =
938 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
939 s->cirrus_blt_srcaddr =
940 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
941 s->cirrus_blt_mode = s->gr[0x30];
a5082316 942 s->cirrus_blt_modeext = s->gr[0x33];
e6e5ad80
FB		 943 blt_rop = s->gr[0x32];
944
a21ae81d 945#ifdef DEBUG_BITBLT
0b74ed78 946 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 947 blt_rop,
a21ae81d 948 s->cirrus_blt_mode,
a5082316 949 s->cirrus_blt_modeext,
a21ae81d
FB		 950 s->cirrus_blt_width,
951 s->cirrus_blt_height,
952 s->cirrus_blt_dstpitch,
953 s->cirrus_blt_srcpitch,
954 s->cirrus_blt_dstaddr,
a5082316 955 s->cirrus_blt_srcaddr,
e3a4e4b6 956 s->gr[0x2f]);
a21ae81d
FB		 957#endif
958
e6e5ad80
FB		 959 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
960 case CIRRUS_BLTMODE_PIXELWIDTH8:
961 s->cirrus_blt_pixelwidth = 1;
962 break;
963 case CIRRUS_BLTMODE_PIXELWIDTH16:
964 s->cirrus_blt_pixelwidth = 2;
965 break;
966 case CIRRUS_BLTMODE_PIXELWIDTH24:
967 s->cirrus_blt_pixelwidth = 3;
968 break;
969 case CIRRUS_BLTMODE_PIXELWIDTH32:
970 s->cirrus_blt_pixelwidth = 4;
971 break;
972 default:
a5082316 973#ifdef DEBUG_BITBLT
e6e5ad80
FB		 974 printf("cirrus: bitblt - pixel width is unknown\n");
975#endif
976 goto bitblt_ignore;
977 }
978 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
979
980 if ((s->
981 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
982 CIRRUS_BLTMODE_MEMSYSDEST))
983 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 984#ifdef DEBUG_BITBLT
e6e5ad80
FB		 985 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
986#endif
987 goto bitblt_ignore;
988 }
989
a5082316 990 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 991 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 992 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 993 CIRRUS_BLTMODE_PATTERNCOPY |
994 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 995 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 996 cirrus_bitblt_fgcol(s);
997 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 998 } else {
5fafdf24
TS		 999 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1000 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 1001 CIRRUS_BLTMODE_COLOREXPAND) {
1002
1003 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 1004 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 1005 cirrus_bitblt_bgcol(s);
b30d4608 1006 else
4c8732d7 1007 cirrus_bitblt_fgcol(s);
b30d4608 1008 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 1009 } else {
1010 cirrus_bitblt_fgcol(s);
1011 cirrus_bitblt_bgcol(s);
1012 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1013 }
e69390ce 1014 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1015 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1016 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1017 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1018 cirrus_bitblt_bgcol(s);
1019 else
1020 cirrus_bitblt_fgcol(s);
1021 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1022 } else {
1023 cirrus_bitblt_fgcol(s);
1024 cirrus_bitblt_bgcol(s);
1025 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1026 }
1027 } else {
1028 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1029 }
a21ae81d 1030 } else {
96cf2df8
TS		 1031 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1032 if (s->cirrus_blt_pixelwidth > 2) {
1033 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1034 goto bitblt_ignore;
1035 }
1036 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1037 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1038 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1039 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1040 } else {
1041 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1042 }
1043 } else {
1044 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1045 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1046 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1047 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1048 } else {
1049 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1050 }
1051 }
1052 }
a21ae81d
FB		 1053 // setup bitblt engine.
1054 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1055 if (!cirrus_bitblt_cputovideo(s))
1056 goto bitblt_ignore;
1057 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1058 if (!cirrus_bitblt_videotocpu(s))
1059 goto bitblt_ignore;
1060 } else {
1061 if (!cirrus_bitblt_videotovideo(s))
1062 goto bitblt_ignore;
1063 }
e6e5ad80 1064 }
e6e5ad80
FB		 1065 return;
1066 bitblt_ignore:;
1067 cirrus_bitblt_reset(s);
1068}
1069
1070static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1071{
1072 unsigned old_value;
1073
1074 old_value = s->gr[0x31];
1075 s->gr[0x31] = reg_value;
1076
1077 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1078 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1079 cirrus_bitblt_reset(s);
1080 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1081 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1082 cirrus_bitblt_start(s);
1083 }
1084}
1085
1086
1087/***************************************
1088 *
1089 * basic parameters
1090 *
1091 ***************************************/
1092
5fafdf24 1093static void cirrus_get_offsets(VGAState *s1,
83acc96b
FB		 1094 uint32_t *pline_offset,
1095 uint32_t *pstart_addr,
1096 uint32_t *pline_compare)
e6e5ad80
FB		 1097{
1098 CirrusVGAState * s = (CirrusVGAState *)s1;
83acc96b 1099 uint32_t start_addr, line_offset, line_compare;
e6e5ad80
FB		 1100
1101 line_offset = s->cr[0x13]
e36f36e1 1102 | ((s->cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1103 line_offset <<= 3;
1104 *pline_offset = line_offset;
1105
1106 start_addr = (s->cr[0x0c] << 8)
1107 | s->cr[0x0d]
1108 | ((s->cr[0x1b] & 0x01) << 16)
1109 | ((s->cr[0x1b] & 0x0c) << 15)
1110 | ((s->cr[0x1d] & 0x80) << 12);
1111 *pstart_addr = start_addr;
83acc96b 1112
5fafdf24 1113 line_compare = s->cr[0x18] |
83acc96b
FB		 1114 ((s->cr[0x07] & 0x10) << 4) |
1115 ((s->cr[0x09] & 0x40) << 3);
1116 *pline_compare = line_compare;
e6e5ad80
FB		 1117}
1118
1119static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1120{
1121 uint32_t ret = 16;
1122
1123 switch (s->cirrus_hidden_dac_data & 0xf) {
1124 case 0:
1125 ret = 15;
1126 break; /* Sierra HiColor */
1127 case 1:
1128 ret = 16;
1129 break; /* XGA HiColor */
1130 default:
1131#ifdef DEBUG_CIRRUS
1132 printf("cirrus: invalid DAC value %x in 16bpp\n",
1133 (s->cirrus_hidden_dac_data & 0xf));
1134#endif
1135 ret = 15; /* XXX */
1136 break;
1137 }
1138 return ret;
1139}
1140
1141static int cirrus_get_bpp(VGAState *s1)
1142{
1143 CirrusVGAState * s = (CirrusVGAState *)s1;
1144 uint32_t ret = 8;
1145
1146 if ((s->sr[0x07] & 0x01) != 0) {
1147 /* Cirrus SVGA */
1148 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1149 case CIRRUS_SR7_BPP_8:
1150 ret = 8;
1151 break;
1152 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1153 ret = cirrus_get_bpp16_depth(s);
1154 break;
1155 case CIRRUS_SR7_BPP_24:
1156 ret = 24;
1157 break;
1158 case CIRRUS_SR7_BPP_16:
1159 ret = cirrus_get_bpp16_depth(s);
1160 break;
1161 case CIRRUS_SR7_BPP_32:
1162 ret = 32;
1163 break;
1164 default:
1165#ifdef DEBUG_CIRRUS
1166 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1167#endif
1168 ret = 8;
1169 break;
1170 }
1171 } else {
1172 /* VGA */
aeb3c85f 1173 ret = 0;
e6e5ad80
FB		 1174 }
1175
1176 return ret;
1177}
1178
78e127ef
FB		 1179static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1180{
1181 int width, height;
3b46e624 1182
78e127ef 1183 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1184 height = s->cr[0x12] |
1185 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1186 ((s->cr[0x07] & 0x40) << 3);
1187 height = (height + 1);
1188 /* interlace support */
1189 if (s->cr[0x1a] & 0x01)
1190 height = height * 2;
1191 *pwidth = width;
1192 *pheight = height;
1193}
1194
e6e5ad80
FB		 1195/***************************************
1196 *
1197 * bank memory
1198 *
1199 ***************************************/
1200
1201static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1202{
1203 unsigned offset;
1204 unsigned limit;
1205
1206 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1207 offset = s->gr[0x09 + bank_index];
1208 else /* single bank */
1209 offset = s->gr[0x09];
1210
1211 if ((s->gr[0x0b] & 0x20) != 0)
1212 offset <<= 14;
1213 else
1214 offset <<= 12;
1215
e3a4e4b6 1216 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1217 limit = 0;
1218 else
e3a4e4b6 1219 limit = s->real_vram_size - offset;
e6e5ad80
FB		 1220
1221 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1222 if (limit > 0x8000) {
1223 offset += 0x8000;
1224 limit -= 0x8000;
1225 } else {
1226 limit = 0;
1227 }
1228 }
1229
1230 if (limit > 0) {
1231 s->cirrus_bank_base[bank_index] = offset;
1232 s->cirrus_bank_limit[bank_index] = limit;
1233 } else {
1234 s->cirrus_bank_base[bank_index] = 0;
1235 s->cirrus_bank_limit[bank_index] = 0;
1236 }
1237}
1238
1239/***************************************
1240 *
1241 * I/O access between 0x3c4-0x3c5
1242 *
1243 ***************************************/
1244
1245static int
1246cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1247{
1248 switch (reg_index) {
1249 case 0x00: // Standard VGA
1250 case 0x01: // Standard VGA
1251 case 0x02: // Standard VGA
1252 case 0x03: // Standard VGA
1253 case 0x04: // Standard VGA
1254 return CIRRUS_HOOK_NOT_HANDLED;
1255 case 0x06: // Unlock Cirrus extensions
1256 *reg_value = s->sr[reg_index];
1257 break;
e6e5ad80
FB		 1258 case 0x10:
1259 case 0x30:
1260 case 0x50:
1261 case 0x70: // Graphics Cursor X
1262 case 0x90:
1263 case 0xb0:
1264 case 0xd0:
1265 case 0xf0: // Graphics Cursor X
aeb3c85f
FB		 1266 *reg_value = s->sr[0x10];
1267 break;
e6e5ad80
FB		 1268 case 0x11:
1269 case 0x31:
1270 case 0x51:
1271 case 0x71: // Graphics Cursor Y
1272 case 0x91:
1273 case 0xb1:
1274 case 0xd1:
a5082316 1275 case 0xf1: // Graphics Cursor Y
aeb3c85f
FB		 1276 *reg_value = s->sr[0x11];
1277 break;
1278 case 0x05: // ???
1279 case 0x07: // Extended Sequencer Mode
1280 case 0x08: // EEPROM Control
1281 case 0x09: // Scratch Register 0
1282 case 0x0a: // Scratch Register 1
1283 case 0x0b: // VCLK 0
1284 case 0x0c: // VCLK 1
1285 case 0x0d: // VCLK 2
1286 case 0x0e: // VCLK 3
1287 case 0x0f: // DRAM Control
e6e5ad80
FB		 1288 case 0x12: // Graphics Cursor Attribute
1289 case 0x13: // Graphics Cursor Pattern Address
1290 case 0x14: // Scratch Register 2
1291 case 0x15: // Scratch Register 3
1292 case 0x16: // Performance Tuning Register
1293 case 0x17: // Configuration Readback and Extended Control
1294 case 0x18: // Signature Generator Control
1295 case 0x19: // Signal Generator Result
1296 case 0x1a: // Signal Generator Result
1297 case 0x1b: // VCLK 0 Denominator & Post
1298 case 0x1c: // VCLK 1 Denominator & Post
1299 case 0x1d: // VCLK 2 Denominator & Post
1300 case 0x1e: // VCLK 3 Denominator & Post
1301 case 0x1f: // BIOS Write Enable and MCLK select
1302#ifdef DEBUG_CIRRUS
1303 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1304#endif
1305 *reg_value = s->sr[reg_index];
1306 break;
1307 default:
1308#ifdef DEBUG_CIRRUS
1309 printf("cirrus: inport sr_index %02x\n", reg_index);
1310#endif
1311 *reg_value = 0xff;
1312 break;
1313 }
1314
1315 return CIRRUS_HOOK_HANDLED;
1316}
1317
1318static int
1319cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1320{
1321 switch (reg_index) {
1322 case 0x00: // Standard VGA
1323 case 0x01: // Standard VGA
1324 case 0x02: // Standard VGA
1325 case 0x03: // Standard VGA
1326 case 0x04: // Standard VGA
1327 return CIRRUS_HOOK_NOT_HANDLED;
1328 case 0x06: // Unlock Cirrus extensions
1329 reg_value &= 0x17;
1330 if (reg_value == 0x12) {
1331 s->sr[reg_index] = 0x12;
1332 } else {
1333 s->sr[reg_index] = 0x0f;
1334 }
1335 break;
1336 case 0x10:
1337 case 0x30:
1338 case 0x50:
1339 case 0x70: // Graphics Cursor X
1340 case 0x90:
1341 case 0xb0:
1342 case 0xd0:
1343 case 0xf0: // Graphics Cursor X
1344 s->sr[0x10] = reg_value;
a5082316 1345 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1346 break;
1347 case 0x11:
1348 case 0x31:
1349 case 0x51:
1350 case 0x71: // Graphics Cursor Y
1351 case 0x91:
1352 case 0xb1:
1353 case 0xd1:
1354 case 0xf1: // Graphics Cursor Y
1355 s->sr[0x11] = reg_value;
a5082316 1356 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1357 break;
1358 case 0x07: // Extended Sequencer Mode
1359 case 0x08: // EEPROM Control
1360 case 0x09: // Scratch Register 0
1361 case 0x0a: // Scratch Register 1
1362 case 0x0b: // VCLK 0
1363 case 0x0c: // VCLK 1
1364 case 0x0d: // VCLK 2
1365 case 0x0e: // VCLK 3
1366 case 0x0f: // DRAM Control
1367 case 0x12: // Graphics Cursor Attribute
1368 case 0x13: // Graphics Cursor Pattern Address
1369 case 0x14: // Scratch Register 2
1370 case 0x15: // Scratch Register 3
1371 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1372 case 0x18: // Signature Generator Control
1373 case 0x19: // Signature Generator Result
1374 case 0x1a: // Signature Generator Result
1375 case 0x1b: // VCLK 0 Denominator & Post
1376 case 0x1c: // VCLK 1 Denominator & Post
1377 case 0x1d: // VCLK 2 Denominator & Post
1378 case 0x1e: // VCLK 3 Denominator & Post
1379 case 0x1f: // BIOS Write Enable and MCLK select
1380 s->sr[reg_index] = reg_value;
1381#ifdef DEBUG_CIRRUS
1382 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1383 reg_index, reg_value);
1384#endif
1385 break;
8926b517 1386 case 0x17: // Configuration Readback and Extended Control
e3a4e4b6 1387 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
8926b517
FB		 1388 cirrus_update_memory_access(s);
1389 break;
e6e5ad80
FB		 1390 default:
1391#ifdef DEBUG_CIRRUS
1392 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1393 reg_value);
1394#endif
1395 break;
1396 }
1397
1398 return CIRRUS_HOOK_HANDLED;
1399}
1400
1401/***************************************
1402 *
1403 * I/O access at 0x3c6
1404 *
1405 ***************************************/
1406
1407static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1408{
1409 *reg_value = 0xff;
a21ae81d
FB		 1410 if (++s->cirrus_hidden_dac_lockindex == 5) {
1411 *reg_value = s->cirrus_hidden_dac_data;
1412 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1413 }
1414}
1415
1416static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1417{
1418 if (s->cirrus_hidden_dac_lockindex == 4) {
1419 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1420#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1421 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1422#endif
1423 }
1424 s->cirrus_hidden_dac_lockindex = 0;
1425}
1426
1427/***************************************
1428 *
1429 * I/O access at 0x3c9
1430 *
1431 ***************************************/
1432
1433static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1434{
1435 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1436 return CIRRUS_HOOK_NOT_HANDLED;
a5082316
FB		 1437 *reg_value =
1438 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1439 s->dac_sub_index];
e6e5ad80
FB		 1440 if (++s->dac_sub_index == 3) {
1441 s->dac_sub_index = 0;
1442 s->dac_read_index++;
1443 }
1444 return CIRRUS_HOOK_HANDLED;
1445}
1446
1447static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1448{
1449 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1450 return CIRRUS_HOOK_NOT_HANDLED;
1451 s->dac_cache[s->dac_sub_index] = reg_value;
1452 if (++s->dac_sub_index == 3) {
a5082316
FB		 1453 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1454 s->dac_cache, 3);
1455 /* XXX update cursor */
e6e5ad80
FB		 1456 s->dac_sub_index = 0;
1457 s->dac_write_index++;
1458 }
1459 return CIRRUS_HOOK_HANDLED;
1460}
1461
1462/***************************************
1463 *
1464 * I/O access between 0x3ce-0x3cf
1465 *
1466 ***************************************/
1467
1468static int
1469cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1470{
1471 switch (reg_index) {
aeb3c85f
FB		 1472 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1473 *reg_value = s->cirrus_shadow_gr0;
1474 return CIRRUS_HOOK_HANDLED;
1475 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1476 *reg_value = s->cirrus_shadow_gr1;
1477 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1478 case 0x02: // Standard VGA
1479 case 0x03: // Standard VGA
1480 case 0x04: // Standard VGA
1481 case 0x06: // Standard VGA
1482 case 0x07: // Standard VGA
1483 case 0x08: // Standard VGA
1484 return CIRRUS_HOOK_NOT_HANDLED;
1485 case 0x05: // Standard VGA, Cirrus extended mode
1486 default:
1487 break;
1488 }
1489
1490 if (reg_index < 0x3a) {
1491 *reg_value = s->gr[reg_index];
1492 } else {
1493#ifdef DEBUG_CIRRUS
1494 printf("cirrus: inport gr_index %02x\n", reg_index);
1495#endif
1496 *reg_value = 0xff;
1497 }
1498
1499 return CIRRUS_HOOK_HANDLED;
1500}
1501
1502static int
1503cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1504{
a5082316
FB		 1505#if defined(DEBUG_BITBLT) && 0
1506 printf("gr%02x: %02x\n", reg_index, reg_value);
1507#endif
e6e5ad80
FB		 1508 switch (reg_index) {
1509 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1510 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1511 return CIRRUS_HOOK_NOT_HANDLED;
1512 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1513 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1514 return CIRRUS_HOOK_NOT_HANDLED;
1515 case 0x02: // Standard VGA
1516 case 0x03: // Standard VGA
1517 case 0x04: // Standard VGA
1518 case 0x06: // Standard VGA
1519 case 0x07: // Standard VGA
1520 case 0x08: // Standard VGA
1521 return CIRRUS_HOOK_NOT_HANDLED;
1522 case 0x05: // Standard VGA, Cirrus extended mode
1523 s->gr[reg_index] = reg_value & 0x7f;
8926b517 1524 cirrus_update_memory_access(s);
e6e5ad80
FB		 1525 break;
1526 case 0x09: // bank offset #0
1527 case 0x0A: // bank offset #1
8926b517
FB		 1528 s->gr[reg_index] = reg_value;
1529 cirrus_update_bank_ptr(s, 0);
1530 cirrus_update_bank_ptr(s, 1);
1531 break;
e6e5ad80
FB		 1532 case 0x0B:
1533 s->gr[reg_index] = reg_value;
1534 cirrus_update_bank_ptr(s, 0);
1535 cirrus_update_bank_ptr(s, 1);
8926b517 1536 cirrus_update_memory_access(s);
e6e5ad80
FB		 1537 break;
1538 case 0x10: // BGCOLOR 0x0000ff00
1539 case 0x11: // FGCOLOR 0x0000ff00
1540 case 0x12: // BGCOLOR 0x00ff0000
1541 case 0x13: // FGCOLOR 0x00ff0000
1542 case 0x14: // BGCOLOR 0xff000000
1543 case 0x15: // FGCOLOR 0xff000000
1544 case 0x20: // BLT WIDTH 0x0000ff
1545 case 0x22: // BLT HEIGHT 0x0000ff
1546 case 0x24: // BLT DEST PITCH 0x0000ff
1547 case 0x26: // BLT SRC PITCH 0x0000ff
1548 case 0x28: // BLT DEST ADDR 0x0000ff
1549 case 0x29: // BLT DEST ADDR 0x00ff00
1550 case 0x2c: // BLT SRC ADDR 0x0000ff
1551 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1552 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1553 case 0x30: // BLT MODE
1554 case 0x32: // RASTER OP
a21ae81d 1555 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1556 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1557 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1558 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1559 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1560 s->gr[reg_index] = reg_value;
1561 break;
1562 case 0x21: // BLT WIDTH 0x001f00
1563 case 0x23: // BLT HEIGHT 0x001f00
1564 case 0x25: // BLT DEST PITCH 0x001f00
1565 case 0x27: // BLT SRC PITCH 0x001f00
1566 s->gr[reg_index] = reg_value & 0x1f;
1567 break;
1568 case 0x2a: // BLT DEST ADDR 0x3f0000
a5082316
FB		 1569 s->gr[reg_index] = reg_value & 0x3f;
1570 /* if auto start mode, starts bit blt now */
1571 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1572 cirrus_bitblt_start(s);
1573 }
1574 break;
e6e5ad80
FB		 1575 case 0x2e: // BLT SRC ADDR 0x3f0000
1576 s->gr[reg_index] = reg_value & 0x3f;
1577 break;
1578 case 0x31: // BLT STATUS/START
1579 cirrus_write_bitblt(s, reg_value);
1580 break;
1581 default:
1582#ifdef DEBUG_CIRRUS
1583 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1584 reg_value);
1585#endif
1586 break;
1587 }
1588
1589 return CIRRUS_HOOK_HANDLED;
1590}
1591
1592/***************************************
1593 *
1594 * I/O access between 0x3d4-0x3d5
1595 *
1596 ***************************************/
1597
1598static int
1599cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1600{
1601 switch (reg_index) {
1602 case 0x00: // Standard VGA
1603 case 0x01: // Standard VGA
1604 case 0x02: // Standard VGA
1605 case 0x03: // Standard VGA
1606 case 0x04: // Standard VGA
1607 case 0x05: // Standard VGA
1608 case 0x06: // Standard VGA
1609 case 0x07: // Standard VGA
1610 case 0x08: // Standard VGA
1611 case 0x09: // Standard VGA
1612 case 0x0a: // Standard VGA
1613 case 0x0b: // Standard VGA
1614 case 0x0c: // Standard VGA
1615 case 0x0d: // Standard VGA
1616 case 0x0e: // Standard VGA
1617 case 0x0f: // Standard VGA
1618 case 0x10: // Standard VGA
1619 case 0x11: // Standard VGA
1620 case 0x12: // Standard VGA
1621 case 0x13: // Standard VGA
1622 case 0x14: // Standard VGA
1623 case 0x15: // Standard VGA
1624 case 0x16: // Standard VGA
1625 case 0x17: // Standard VGA
1626 case 0x18: // Standard VGA
1627 return CIRRUS_HOOK_NOT_HANDLED;
ca896ef3
AJ		 1628 case 0x24: // Attribute Controller Toggle Readback (R)
1629 *reg_value = (s->ar_flip_flop << 7);
1630 break;
e6e5ad80
FB		 1631 case 0x19: // Interlace End
1632 case 0x1a: // Miscellaneous Control
1633 case 0x1b: // Extended Display Control
1634 case 0x1c: // Sync Adjust and Genlock
1635 case 0x1d: // Overlay Extended Control
1636 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1637 case 0x25: // Part Status
1638 case 0x27: // Part ID (R)
1639 *reg_value = s->cr[reg_index];
1640 break;
1641 case 0x26: // Attribute Controller Index Readback (R)
1642 *reg_value = s->ar_index & 0x3f;
1643 break;
1644 default:
1645#ifdef DEBUG_CIRRUS
1646 printf("cirrus: inport cr_index %02x\n", reg_index);
1647 *reg_value = 0xff;
1648#endif
1649 break;
1650 }
1651
1652 return CIRRUS_HOOK_HANDLED;
1653}
1654
1655static int
1656cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1657{
1658 switch (reg_index) {
1659 case 0x00: // Standard VGA
1660 case 0x01: // Standard VGA
1661 case 0x02: // Standard VGA
1662 case 0x03: // Standard VGA
1663 case 0x04: // Standard VGA
1664 case 0x05: // Standard VGA
1665 case 0x06: // Standard VGA
1666 case 0x07: // Standard VGA
1667 case 0x08: // Standard VGA
1668 case 0x09: // Standard VGA
1669 case 0x0a: // Standard VGA
1670 case 0x0b: // Standard VGA
1671 case 0x0c: // Standard VGA
1672 case 0x0d: // Standard VGA
1673 case 0x0e: // Standard VGA
1674 case 0x0f: // Standard VGA
1675 case 0x10: // Standard VGA
1676 case 0x11: // Standard VGA
1677 case 0x12: // Standard VGA
1678 case 0x13: // Standard VGA
1679 case 0x14: // Standard VGA
1680 case 0x15: // Standard VGA
1681 case 0x16: // Standard VGA
1682 case 0x17: // Standard VGA
1683 case 0x18: // Standard VGA
1684 return CIRRUS_HOOK_NOT_HANDLED;
1685 case 0x19: // Interlace End
1686 case 0x1a: // Miscellaneous Control
1687 case 0x1b: // Extended Display Control
1688 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1689 case 0x1d: // Overlay Extended Control
e6e5ad80
FB		 1690 s->cr[reg_index] = reg_value;
1691#ifdef DEBUG_CIRRUS
1692 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1693 reg_index, reg_value);
1694#endif
1695 break;
1696 case 0x22: // Graphics Data Latches Readback (R)
1697 case 0x24: // Attribute Controller Toggle Readback (R)
1698 case 0x26: // Attribute Controller Index Readback (R)
1699 case 0x27: // Part ID (R)
1700 break;
e6e5ad80
FB		 1701 case 0x25: // Part Status
1702 default:
1703#ifdef DEBUG_CIRRUS
1704 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1705 reg_value);
1706#endif
1707 break;
1708 }
1709
1710 return CIRRUS_HOOK_HANDLED;
1711}
1712
1713/***************************************
1714 *
1715 * memory-mapped I/O (bitblt)
1716 *
1717 ***************************************/
1718
1719static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1720{
1721 int value = 0xff;
1722
1723 switch (address) {
1724 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1725 cirrus_hook_read_gr(s, 0x00, &value);
1726 break;
1727 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1728 cirrus_hook_read_gr(s, 0x10, &value);
1729 break;
1730 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1731 cirrus_hook_read_gr(s, 0x12, &value);
1732 break;
1733 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1734 cirrus_hook_read_gr(s, 0x14, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1737 cirrus_hook_read_gr(s, 0x01, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1740 cirrus_hook_read_gr(s, 0x11, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1743 cirrus_hook_read_gr(s, 0x13, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1746 cirrus_hook_read_gr(s, 0x15, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTWIDTH + 0):
1749 cirrus_hook_read_gr(s, 0x20, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTWIDTH + 1):
1752 cirrus_hook_read_gr(s, 0x21, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1755 cirrus_hook_read_gr(s, 0x22, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1758 cirrus_hook_read_gr(s, 0x23, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1761 cirrus_hook_read_gr(s, 0x24, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1764 cirrus_hook_read_gr(s, 0x25, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1767 cirrus_hook_read_gr(s, 0x26, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1770 cirrus_hook_read_gr(s, 0x27, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1773 cirrus_hook_read_gr(s, 0x28, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1776 cirrus_hook_read_gr(s, 0x29, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1779 cirrus_hook_read_gr(s, 0x2a, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1782 cirrus_hook_read_gr(s, 0x2c, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1785 cirrus_hook_read_gr(s, 0x2d, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1788 cirrus_hook_read_gr(s, 0x2e, &value);
1789 break;
1790 case CIRRUS_MMIO_BLTWRITEMASK:
1791 cirrus_hook_read_gr(s, 0x2f, &value);
1792 break;
1793 case CIRRUS_MMIO_BLTMODE:
1794 cirrus_hook_read_gr(s, 0x30, &value);
1795 break;
1796 case CIRRUS_MMIO_BLTROP:
1797 cirrus_hook_read_gr(s, 0x32, &value);
1798 break;
a21ae81d
FB		 1799 case CIRRUS_MMIO_BLTMODEEXT:
1800 cirrus_hook_read_gr(s, 0x33, &value);
1801 break;
e6e5ad80
FB		 1802 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1803 cirrus_hook_read_gr(s, 0x34, &value);
1804 break;
1805 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1806 cirrus_hook_read_gr(s, 0x35, &value);
1807 break;
1808 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1809 cirrus_hook_read_gr(s, 0x38, &value);
1810 break;
1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1812 cirrus_hook_read_gr(s, 0x39, &value);
1813 break;
1814 case CIRRUS_MMIO_BLTSTATUS:
1815 cirrus_hook_read_gr(s, 0x31, &value);
1816 break;
1817 default:
1818#ifdef DEBUG_CIRRUS
1819 printf("cirrus: mmio read - address 0x%04x\n", address);
1820#endif
1821 break;
1822 }
1823
1824 return (uint8_t) value;
1825}
1826
1827static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1828 uint8_t value)
1829{
1830 switch (address) {
1831 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1832 cirrus_hook_write_gr(s, 0x00, value);
1833 break;
1834 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1835 cirrus_hook_write_gr(s, 0x10, value);
1836 break;
1837 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1838 cirrus_hook_write_gr(s, 0x12, value);
1839 break;
1840 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1841 cirrus_hook_write_gr(s, 0x14, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1844 cirrus_hook_write_gr(s, 0x01, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1847 cirrus_hook_write_gr(s, 0x11, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1850 cirrus_hook_write_gr(s, 0x13, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1853 cirrus_hook_write_gr(s, 0x15, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTWIDTH + 0):
1856 cirrus_hook_write_gr(s, 0x20, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTWIDTH + 1):
1859 cirrus_hook_write_gr(s, 0x21, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1862 cirrus_hook_write_gr(s, 0x22, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1865 cirrus_hook_write_gr(s, 0x23, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1868 cirrus_hook_write_gr(s, 0x24, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1871 cirrus_hook_write_gr(s, 0x25, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1874 cirrus_hook_write_gr(s, 0x26, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1877 cirrus_hook_write_gr(s, 0x27, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1880 cirrus_hook_write_gr(s, 0x28, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1883 cirrus_hook_write_gr(s, 0x29, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1886 cirrus_hook_write_gr(s, 0x2a, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1889 /* ignored */
1890 break;
1891 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1892 cirrus_hook_write_gr(s, 0x2c, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1895 cirrus_hook_write_gr(s, 0x2d, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1898 cirrus_hook_write_gr(s, 0x2e, value);
1899 break;
1900 case CIRRUS_MMIO_BLTWRITEMASK:
1901 cirrus_hook_write_gr(s, 0x2f, value);
1902 break;
1903 case CIRRUS_MMIO_BLTMODE:
1904 cirrus_hook_write_gr(s, 0x30, value);
1905 break;
1906 case CIRRUS_MMIO_BLTROP:
1907 cirrus_hook_write_gr(s, 0x32, value);
1908 break;
a21ae81d
FB		 1909 case CIRRUS_MMIO_BLTMODEEXT:
1910 cirrus_hook_write_gr(s, 0x33, value);
1911 break;
e6e5ad80
FB		 1912 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1913 cirrus_hook_write_gr(s, 0x34, value);
1914 break;
1915 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1916 cirrus_hook_write_gr(s, 0x35, value);
1917 break;
1918 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1919 cirrus_hook_write_gr(s, 0x38, value);
1920 break;
1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1922 cirrus_hook_write_gr(s, 0x39, value);
1923 break;
1924 case CIRRUS_MMIO_BLTSTATUS:
1925 cirrus_hook_write_gr(s, 0x31, value);
1926 break;
1927 default:
1928#ifdef DEBUG_CIRRUS
1929 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1930 address, value);
1931#endif
1932 break;
1933 }
1934}
1935
e6e5ad80
FB		 1936/***************************************
1937 *
1938 * write mode 4/5
1939 *
1940 * assume TARGET_PAGE_SIZE >= 16
1941 *
1942 ***************************************/
1943
1944static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1945 unsigned mode,
1946 unsigned offset,
1947 uint32_t mem_value)
1948{
1949 int x;
1950 unsigned val = mem_value;
1951 uint8_t *dst;
1952
b2eb849d 1953 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1954 for (x = 0; x < 8; x++) {
1955 if (val & 0x80) {
0b74ed78 1956 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1957 } else if (mode == 5) {
0b74ed78 1958 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1959 }
1960 val <<= 1;
0b74ed78 1961 dst++;
e6e5ad80
FB		 1962 }
1963 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1964 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1965}
1966
1967static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1968 unsigned mode,
1969 unsigned offset,
1970 uint32_t mem_value)
1971{
1972 int x;
1973 unsigned val = mem_value;
1974 uint8_t *dst;
1975
b2eb849d 1976 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1977 for (x = 0; x < 8; x++) {
1978 if (val & 0x80) {
0b74ed78
FB		 1979 *dst = s->cirrus_shadow_gr1;
1980 *(dst + 1) = s->gr[0x11];
e6e5ad80 1981 } else if (mode == 5) {
0b74ed78
FB		 1982 *dst = s->cirrus_shadow_gr0;
1983 *(dst + 1) = s->gr[0x10];
e6e5ad80
FB		 1984 }
1985 val <<= 1;
0b74ed78 1986 dst += 2;
e6e5ad80
FB		 1987 }
1988 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1989 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1990}
1991
1992/***************************************
1993 *
1994 * memory access between 0xa0000-0xbffff
1995 *
1996 ***************************************/
1997
1998static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1999{
2000 CirrusVGAState *s = opaque;
2001 unsigned bank_index;
2002 unsigned bank_offset;
2003 uint32_t val;
2004
2005 if ((s->sr[0x07] & 0x01) == 0) {
2006 return vga_mem_readb(s, addr);
2007 }
2008
aeb3c85f
FB		 2009 addr &= 0x1ffff;
2010
e6e5ad80
FB		 2011 if (addr < 0x10000) {
2012 /* XXX handle bitblt */
2013 /* video memory */
2014 bank_index = addr >> 15;
2015 bank_offset = addr & 0x7fff;
2016 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2017 bank_offset += s->cirrus_bank_base[bank_index];
2018 if ((s->gr[0x0B] & 0x14) == 0x14) {
2019 bank_offset <<= 4;
2020 } else if (s->gr[0x0B] & 0x02) {
2021 bank_offset <<= 3;
2022 }
2023 bank_offset &= s->cirrus_addr_mask;
2024 val = *(s->vram_ptr + bank_offset);
2025 } else
2026 val = 0xff;
2027 } else if (addr >= 0x18000 && addr < 0x18100) {
2028 /* memory-mapped I/O */
2029 val = 0xff;
2030 if ((s->sr[0x17] & 0x44) == 0x04) {
2031 val = cirrus_mmio_blt_read(s, addr & 0xff);
2032 }
2033 } else {
2034 val = 0xff;
2035#ifdef DEBUG_CIRRUS
2036 printf("cirrus: mem_readb %06x\n", addr);
2037#endif
2038 }
2039 return val;
2040}
2041
2042static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2043{
2044 uint32_t v;
2045#ifdef TARGET_WORDS_BIGENDIAN
2046 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2047 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2048#else
2049 v = cirrus_vga_mem_readb(opaque, addr);
2050 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2051#endif
2052 return v;
2053}
2054
2055static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2056{
2057 uint32_t v;
2058#ifdef TARGET_WORDS_BIGENDIAN
2059 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2061 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2062 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2063#else
2064 v = cirrus_vga_mem_readb(opaque, addr);
2065 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2066 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2067 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2068#endif
2069 return v;
2070}
2071
5fafdf24 2072static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2073 uint32_t mem_value)
2074{
2075 CirrusVGAState *s = opaque;
2076 unsigned bank_index;
2077 unsigned bank_offset;
2078 unsigned mode;
2079
2080 if ((s->sr[0x07] & 0x01) == 0) {
2081 vga_mem_writeb(s, addr, mem_value);
2082 return;
2083 }
2084
aeb3c85f
FB		 2085 addr &= 0x1ffff;
2086
e6e5ad80
FB		 2087 if (addr < 0x10000) {
2088 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2089 /* bitblt */
2090 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2091 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2092 cirrus_bitblt_cputovideo_next(s);
2093 }
2094 } else {
2095 /* video memory */
2096 bank_index = addr >> 15;
2097 bank_offset = addr & 0x7fff;
2098 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2099 bank_offset += s->cirrus_bank_base[bank_index];
2100 if ((s->gr[0x0B] & 0x14) == 0x14) {
2101 bank_offset <<= 4;
2102 } else if (s->gr[0x0B] & 0x02) {
2103 bank_offset <<= 3;
2104 }
2105 bank_offset &= s->cirrus_addr_mask;
2106 mode = s->gr[0x05] & 0x7;
2107 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2108 *(s->vram_ptr + bank_offset) = mem_value;
2109 cpu_physical_memory_set_dirty(s->vram_offset +
2110 bank_offset);
2111 } else {
2112 if ((s->gr[0x0B] & 0x14) != 0x14) {
2113 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2114 bank_offset,
2115 mem_value);
2116 } else {
2117 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2118 bank_offset,
2119 mem_value);
2120 }
2121 }
2122 }
2123 }
2124 } else if (addr >= 0x18000 && addr < 0x18100) {
2125 /* memory-mapped I/O */
2126 if ((s->sr[0x17] & 0x44) == 0x04) {
2127 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2128 }
2129 } else {
2130#ifdef DEBUG_CIRRUS
2131 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2132#endif
2133 }
2134}
2135
2136static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2137{
2138#ifdef TARGET_WORDS_BIGENDIAN
2139 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2140 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2141#else
2142 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2143 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2144#endif
2145}
2146
2147static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2148{
2149#ifdef TARGET_WORDS_BIGENDIAN
2150 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2151 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2153 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2154#else
2155 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2157 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2158 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2159#endif
2160}
2161
2162static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2163 cirrus_vga_mem_readb,
2164 cirrus_vga_mem_readw,
2165 cirrus_vga_mem_readl,
2166};
2167
2168static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2169 cirrus_vga_mem_writeb,
2170 cirrus_vga_mem_writew,
2171 cirrus_vga_mem_writel,
2172};
2173
a5082316
FB		 2174/***************************************
2175 *
2176 * hardware cursor
2177 *
2178 ***************************************/
2179
2180static inline void invalidate_cursor1(CirrusVGAState *s)
2181{
2182 if (s->last_hw_cursor_size) {
5fafdf24 2183 vga_invalidate_scanlines((VGAState *)s,
a5082316
FB		 2184 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2185 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2186 }
2187}
2188
2189static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2190{
2191 const uint8_t *src;
2192 uint32_t content;
2193 int y, y_min, y_max;
2194
78e127ef 2195 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2196 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2197 src += (s->sr[0x13] & 0x3c) * 256;
2198 y_min = 64;
2199 y_max = -1;
2200 for(y = 0; y < 64; y++) {
2201 content = ((uint32_t *)src)[0] |
2202 ((uint32_t *)src)[1] |
2203 ((uint32_t *)src)[2] |
2204 ((uint32_t *)src)[3];
2205 if (content) {
2206 if (y < y_min)
2207 y_min = y;
2208 if (y > y_max)
2209 y_max = y;
2210 }
2211 src += 16;
2212 }
2213 } else {
2214 src += (s->sr[0x13] & 0x3f) * 256;
2215 y_min = 32;
2216 y_max = -1;
2217 for(y = 0; y < 32; y++) {
2218 content = ((uint32_t *)src)[0] |
2219 ((uint32_t *)(src + 128))[0];
2220 if (content) {
2221 if (y < y_min)
2222 y_min = y;
2223 if (y > y_max)
2224 y_max = y;
2225 }
2226 src += 4;
2227 }
2228 }
2229 if (y_min > y_max) {
2230 s->last_hw_cursor_y_start = 0;
2231 s->last_hw_cursor_y_end = 0;
2232 } else {
2233 s->last_hw_cursor_y_start = y_min;
2234 s->last_hw_cursor_y_end = y_max + 1;
2235 }
2236}
2237
2238/* NOTE: we do not currently handle the cursor bitmap change, so we
2239 update the cursor only if it moves. */
2240static void cirrus_cursor_invalidate(VGAState *s1)
2241{
2242 CirrusVGAState *s = (CirrusVGAState *)s1;
2243 int size;
2244
2245 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2246 size = 0;
2247 } else {
2248 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2249 size = 64;
2250 else
2251 size = 32;
2252 }
2253 /* invalidate last cursor and new cursor if any change */
2254 if (s->last_hw_cursor_size != size ||
2255 s->last_hw_cursor_x != s->hw_cursor_x ||
2256 s->last_hw_cursor_y != s->hw_cursor_y) {
2257
2258 invalidate_cursor1(s);
3b46e624 2259
a5082316
FB		 2260 s->last_hw_cursor_size = size;
2261 s->last_hw_cursor_x = s->hw_cursor_x;
2262 s->last_hw_cursor_y = s->hw_cursor_y;
2263 /* compute the real cursor min and max y */
2264 cirrus_cursor_compute_yrange(s);
2265 invalidate_cursor1(s);
2266 }
2267}
2268
2269static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2270{
2271 CirrusVGAState *s = (CirrusVGAState *)s1;
2272 int w, h, bpp, x1, x2, poffset;
2273 unsigned int color0, color1;
2274 const uint8_t *palette, *src;
2275 uint32_t content;
3b46e624 2276
5fafdf24 2277 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2278 return;
2279 /* fast test to see if the cursor intersects with the scan line */
2280 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2281 h = 64;
2282 } else {
2283 h = 32;
2284 }
2285 if (scr_y < s->hw_cursor_y ||
2286 scr_y >= (s->hw_cursor_y + h))
2287 return;
3b46e624 2288
78e127ef 2289 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2290 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2291 src += (s->sr[0x13] & 0x3c) * 256;
2292 src += (scr_y - s->hw_cursor_y) * 16;
2293 poffset = 8;
2294 content = ((uint32_t *)src)[0] |
2295 ((uint32_t *)src)[1] |
2296 ((uint32_t *)src)[2] |
2297 ((uint32_t *)src)[3];
2298 } else {
2299 src += (s->sr[0x13] & 0x3f) * 256;
2300 src += (scr_y - s->hw_cursor_y) * 4;
2301 poffset = 128;
2302 content = ((uint32_t *)src)[0] |
2303 ((uint32_t *)(src + 128))[0];
2304 }
2305 /* if nothing to draw, no need to continue */
2306 if (!content)
2307 return;
2308 w = h;
2309
2310 x1 = s->hw_cursor_x;
2311 if (x1 >= s->last_scr_width)
2312 return;
2313 x2 = s->hw_cursor_x + w;
2314 if (x2 > s->last_scr_width)
2315 x2 = s->last_scr_width;
2316 w = x2 - x1;
2317 palette = s->cirrus_hidden_palette;
5fafdf24
TS		 2318 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2319 c6_to_8(palette[0x0 * 3 + 1]),
a5082316 2320 c6_to_8(palette[0x0 * 3 + 2]));
5fafdf24
TS		 2321 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2322 c6_to_8(palette[0xf * 3 + 1]),
a5082316 2323 c6_to_8(palette[0xf * 3 + 2]));
0e1f5a0c 2324 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
a5082316 2325 d1 += x1 * bpp;
0e1f5a0c 2326 switch(ds_get_bits_per_pixel(s->ds)) {
a5082316
FB		 2327 default:
2328 break;
2329 case 8:
2330 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2331 break;
2332 case 15:
2333 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2334 break;
2335 case 16:
2336 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2337 break;
2338 case 32:
2339 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2340 break;
2341 }
2342}
2343
e6e5ad80
FB		 2344/***************************************
2345 *
2346 * LFB memory access
2347 *
2348 ***************************************/
2349
2350static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2351{
2352 CirrusVGAState *s = (CirrusVGAState *) opaque;
2353 uint32_t ret;
2354
e6e5ad80
FB		 2355 addr &= s->cirrus_addr_mask;
2356
5fafdf24 2357 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2358 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2359 /* memory-mapped I/O */
2360 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2361 } else if (0) {
2362 /* XXX handle bitblt */
2363 ret = 0xff;
2364 } else {
2365 /* video memory */
2366 if ((s->gr[0x0B] & 0x14) == 0x14) {
2367 addr <<= 4;
2368 } else if (s->gr[0x0B] & 0x02) {
2369 addr <<= 3;
2370 }
2371 addr &= s->cirrus_addr_mask;
2372 ret = *(s->vram_ptr + addr);
2373 }
2374
2375 return ret;
2376}
2377
2378static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2379{
2380 uint32_t v;
2381#ifdef TARGET_WORDS_BIGENDIAN
2382 v = cirrus_linear_readb(opaque, addr) << 8;
2383 v |= cirrus_linear_readb(opaque, addr + 1);
2384#else
2385 v = cirrus_linear_readb(opaque, addr);
2386 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2387#endif
2388 return v;
2389}
2390
2391static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2392{
2393 uint32_t v;
2394#ifdef TARGET_WORDS_BIGENDIAN
2395 v = cirrus_linear_readb(opaque, addr) << 24;
2396 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2397 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2398 v |= cirrus_linear_readb(opaque, addr + 3);
2399#else
2400 v = cirrus_linear_readb(opaque, addr);
2401 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2402 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2403 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2404#endif
2405 return v;
2406}
2407
2408static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2409 uint32_t val)
2410{
2411 CirrusVGAState *s = (CirrusVGAState *) opaque;
2412 unsigned mode;
2413
2414 addr &= s->cirrus_addr_mask;
3b46e624 2415
5fafdf24 2416 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2417 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2418 /* memory-mapped I/O */
2419 cirrus_mmio_blt_write(s, addr & 0xff, val);
2420 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2421 /* bitblt */
2422 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2423 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2424 cirrus_bitblt_cputovideo_next(s);
2425 }
2426 } else {
2427 /* video memory */
2428 if ((s->gr[0x0B] & 0x14) == 0x14) {
2429 addr <<= 4;
2430 } else if (s->gr[0x0B] & 0x02) {
2431 addr <<= 3;
2432 }
2433 addr &= s->cirrus_addr_mask;
2434
2435 mode = s->gr[0x05] & 0x7;
2436 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2437 *(s->vram_ptr + addr) = (uint8_t) val;
2438 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2439 } else {
2440 if ((s->gr[0x0B] & 0x14) != 0x14) {
2441 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2442 } else {
2443 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2444 }
2445 }
2446 }
2447}
2448
2449static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2450 uint32_t val)
2451{
2452#ifdef TARGET_WORDS_BIGENDIAN
2453 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2454 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2455#else
2456 cirrus_linear_writeb(opaque, addr, val & 0xff);
2457 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2458#endif
2459}
2460
2461static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2462 uint32_t val)
2463{
2464#ifdef TARGET_WORDS_BIGENDIAN
2465 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2468 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2469#else
2470 cirrus_linear_writeb(opaque, addr, val & 0xff);
2471 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2472 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2473 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2474#endif
2475}
2476
2477
2478static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2479 cirrus_linear_readb,
2480 cirrus_linear_readw,
2481 cirrus_linear_readl,
2482};
2483
2484static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2485 cirrus_linear_writeb,
2486 cirrus_linear_writew,
2487 cirrus_linear_writel,
2488};
2489
8926b517
FB		 2490static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2491 uint32_t val)
2492{
2493 CirrusVGAState *s = (CirrusVGAState *) opaque;
2494
2495 addr &= s->cirrus_addr_mask;
2496 *(s->vram_ptr + addr) = val;
2497 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2498}
2499
2500static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2501 uint32_t val)
2502{
2503 CirrusVGAState *s = (CirrusVGAState *) opaque;
2504
2505 addr &= s->cirrus_addr_mask;
2506 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2507 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2508}
2509
2510static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2511 uint32_t val)
2512{
2513 CirrusVGAState *s = (CirrusVGAState *) opaque;
2514
2515 addr &= s->cirrus_addr_mask;
2516 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2517 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2518}
2519
a5082316
FB		 2520/***************************************
2521 *
2522 * system to screen memory access
2523 *
2524 ***************************************/
2525
2526
2527static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2528{
2529 uint32_t ret;
2530
2531 /* XXX handle bitblt */
2532 ret = 0xff;
2533 return ret;
2534}
2535
2536static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2537{
2538 uint32_t v;
2539#ifdef TARGET_WORDS_BIGENDIAN
2540 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2541 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2542#else
2543 v = cirrus_linear_bitblt_readb(opaque, addr);
2544 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2545#endif
2546 return v;
2547}
2548
2549static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2550{
2551 uint32_t v;
2552#ifdef TARGET_WORDS_BIGENDIAN
2553 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2555 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2556 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2557#else
2558 v = cirrus_linear_bitblt_readb(opaque, addr);
2559 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2560 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2561 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2562#endif
2563 return v;
2564}
2565
2566static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2567 uint32_t val)
2568{
2569 CirrusVGAState *s = (CirrusVGAState *) opaque;
2570
2571 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2572 /* bitblt */
2573 *s->cirrus_srcptr++ = (uint8_t) val;
2574 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2575 cirrus_bitblt_cputovideo_next(s);
2576 }
2577 }
2578}
2579
2580static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2581 uint32_t val)
2582{
2583#ifdef TARGET_WORDS_BIGENDIAN
2584 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2585 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2586#else
2587 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2588 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2589#endif
2590}
2591
2592static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2593 uint32_t val)
2594{
2595#ifdef TARGET_WORDS_BIGENDIAN
2596 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2598 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2599 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2600#else
2601 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2602 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2603 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2604 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2605#endif
2606}
2607
2608
2609static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2610 cirrus_linear_bitblt_readb,
2611 cirrus_linear_bitblt_readw,
2612 cirrus_linear_bitblt_readl,
2613};
2614
2615static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2616 cirrus_linear_bitblt_writeb,
2617 cirrus_linear_bitblt_writew,
2618 cirrus_linear_bitblt_writel,
2619};
2620
8926b517
FB		 2621/* Compute the memory access functions */
2622static void cirrus_update_memory_access(CirrusVGAState *s)
2623{
2624 unsigned mode;
2625
2626 if ((s->sr[0x17] & 0x44) == 0x44) {
2627 goto generic_io;
2628 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2629 goto generic_io;
2630 } else {
2631 if ((s->gr[0x0B] & 0x14) == 0x14) {
2632 goto generic_io;
2633 } else if (s->gr[0x0B] & 0x02) {
2634 goto generic_io;
2635 }
3b46e624 2636
8926b517
FB		 2637 mode = s->gr[0x05] & 0x7;
2638 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2639 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2640 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2641 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2642 } else {
2643 generic_io:
2644 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2645 s->cirrus_linear_write[1] = cirrus_linear_writew;
2646 s->cirrus_linear_write[2] = cirrus_linear_writel;
2647 }
2648 }
2649}
2650
2651
e6e5ad80
FB		 2652/* I/O ports */
2653
2654static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2655{
2656 CirrusVGAState *s = opaque;
2657 int val, index;
2658
2659 /* check port range access depending on color/monochrome mode */
2660 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2661 || (addr >= 0x3d0 && addr <= 0x3df
2662 && !(s->msr & MSR_COLOR_EMULATION))) {
2663 val = 0xff;
2664 } else {
2665 switch (addr) {
2666 case 0x3c0:
2667 if (s->ar_flip_flop == 0) {
2668 val = s->ar_index;
2669 } else {
2670 val = 0;
2671 }
2672 break;
2673 case 0x3c1:
2674 index = s->ar_index & 0x1f;
2675 if (index < 21)
2676 val = s->ar[index];
2677 else
2678 val = 0;
2679 break;
2680 case 0x3c2:
2681 val = s->st00;
2682 break;
2683 case 0x3c4:
2684 val = s->sr_index;
2685 break;
2686 case 0x3c5:
2687 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2688 break;
2689 val = s->sr[s->sr_index];
2690#ifdef DEBUG_VGA_REG
2691 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2692#endif
2693 break;
2694 case 0x3c6:
2695 cirrus_read_hidden_dac(s, &val);
2696 break;
2697 case 0x3c7:
2698 val = s->dac_state;
2699 break;
ae184e4a
FB		 2700 case 0x3c8:
2701 val = s->dac_write_index;
2702 s->cirrus_hidden_dac_lockindex = 0;
2703 break;
2704 case 0x3c9:
e6e5ad80
FB		 2705 if (cirrus_hook_read_palette(s, &val))
2706 break;
2707 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2708 if (++s->dac_sub_index == 3) {
2709 s->dac_sub_index = 0;
2710 s->dac_read_index++;
2711 }
2712 break;
2713 case 0x3ca:
2714 val = s->fcr;
2715 break;
2716 case 0x3cc:
2717 val = s->msr;
2718 break;
2719 case 0x3ce:
2720 val = s->gr_index;
2721 break;
2722 case 0x3cf:
2723 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2724 break;
2725 val = s->gr[s->gr_index];
2726#ifdef DEBUG_VGA_REG
2727 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2728#endif
2729 break;
2730 case 0x3b4:
2731 case 0x3d4:
2732 val = s->cr_index;
2733 break;
2734 case 0x3b5:
2735 case 0x3d5:
2736 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2737 break;
2738 val = s->cr[s->cr_index];
2739#ifdef DEBUG_VGA_REG
2740 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2741#endif
2742 break;
2743 case 0x3ba:
2744 case 0x3da:
2745 /* just toggle to fool polling */
cb5a7aa8 2746 val = s->st01 = s->retrace((VGAState *) s);
e6e5ad80
FB		 2747 s->ar_flip_flop = 0;
2748 break;
2749 default:
2750 val = 0x00;
2751 break;
2752 }
2753 }
2754#if defined(DEBUG_VGA)
2755 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2756#endif
2757 return val;
2758}
2759
2760static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2761{
2762 CirrusVGAState *s = opaque;
2763 int index;
2764
2765 /* check port range access depending on color/monochrome mode */
2766 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2767 || (addr >= 0x3d0 && addr <= 0x3df
2768 && !(s->msr & MSR_COLOR_EMULATION)))
2769 return;
2770
2771#ifdef DEBUG_VGA
2772 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2773#endif
2774
2775 switch (addr) {
2776 case 0x3c0:
2777 if (s->ar_flip_flop == 0) {
2778 val &= 0x3f;
2779 s->ar_index = val;
2780 } else {
2781 index = s->ar_index & 0x1f;
2782 switch (index) {
2783 case 0x00 ... 0x0f:
2784 s->ar[index] = val & 0x3f;
2785 break;
2786 case 0x10:
2787 s->ar[index] = val & ~0x10;
2788 break;
2789 case 0x11:
2790 s->ar[index] = val;
2791 break;
2792 case 0x12:
2793 s->ar[index] = val & ~0xc0;
2794 break;
2795 case 0x13:
2796 s->ar[index] = val & ~0xf0;
2797 break;
2798 case 0x14:
2799 s->ar[index] = val & ~0xf0;
2800 break;
2801 default:
2802 break;
2803 }
2804 }
2805 s->ar_flip_flop ^= 1;
2806 break;
2807 case 0x3c2:
2808 s->msr = val & ~0x10;
cb5a7aa8 2809 s->update_retrace_info((VGAState *) s);
e6e5ad80
FB		 2810 break;
2811 case 0x3c4:
2812 s->sr_index = val;
2813 break;
2814 case 0x3c5:
2815 if (cirrus_hook_write_sr(s, s->sr_index, val))
2816 break;
2817#ifdef DEBUG_VGA_REG
2818 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2819#endif
2820 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
cb5a7aa8 2821 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
e6e5ad80
FB		 2822 break;
2823 case 0x3c6:
2824 cirrus_write_hidden_dac(s, val);
2825 break;
2826 case 0x3c7:
2827 s->dac_read_index = val;
2828 s->dac_sub_index = 0;
2829 s->dac_state = 3;
2830 break;
2831 case 0x3c8:
2832 s->dac_write_index = val;
2833 s->dac_sub_index = 0;
2834 s->dac_state = 0;
2835 break;
2836 case 0x3c9:
2837 if (cirrus_hook_write_palette(s, val))
2838 break;
2839 s->dac_cache[s->dac_sub_index] = val;
2840 if (++s->dac_sub_index == 3) {
2841 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2842 s->dac_sub_index = 0;
2843 s->dac_write_index++;
2844 }
2845 break;
2846 case 0x3ce:
2847 s->gr_index = val;
2848 break;
2849 case 0x3cf:
2850 if (cirrus_hook_write_gr(s, s->gr_index, val))
2851 break;
2852#ifdef DEBUG_VGA_REG
2853 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2854#endif
2855 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2856 break;
2857 case 0x3b4:
2858 case 0x3d4:
2859 s->cr_index = val;
2860 break;
2861 case 0x3b5:
2862 case 0x3d5:
2863 if (cirrus_hook_write_cr(s, s->cr_index, val))
2864 break;
2865#ifdef DEBUG_VGA_REG
2866 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2867#endif
2868 /* handle CR0-7 protection */
9bb34eac 2869 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
e6e5ad80
FB		 2870 /* can always write bit 4 of CR7 */
2871 if (s->cr_index == 7)
2872 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2873 return;
2874 }
2875 switch (s->cr_index) {
2876 case 0x01: /* horizontal display end */
2877 case 0x07:
2878 case 0x09:
2879 case 0x0c:
2880 case 0x0d:
e91c8a77 2881 case 0x12: /* vertical display end */
e6e5ad80
FB		 2882 s->cr[s->cr_index] = val;
2883 break;
2884
2885 default:
2886 s->cr[s->cr_index] = val;
2887 break;
2888 }
cb5a7aa8 2889
2890 switch(s->cr_index) {
2891 case 0x00:
2892 case 0x04:
2893 case 0x05:
2894 case 0x06:
2895 case 0x07:
2896 case 0x11:
2897 case 0x17:
2898 s->update_retrace_info((VGAState *) s);
2899 break;
2900 }
e6e5ad80
FB		 2901 break;
2902 case 0x3ba:
2903 case 0x3da:
2904 s->fcr = val & 0x10;
2905 break;
2906 }
2907}
2908
e36f36e1
FB		 2909/***************************************
2910 *
2911 * memory-mapped I/O access
2912 *
2913 ***************************************/
2914
2915static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2916{
2917 CirrusVGAState *s = (CirrusVGAState *) opaque;
2918
2919 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2920
2921 if (addr >= 0x100) {
2922 return cirrus_mmio_blt_read(s, addr - 0x100);
2923 } else {
2924 return vga_ioport_read(s, addr + 0x3c0);
2925 }
2926}
2927
2928static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2929{
2930 uint32_t v;
2931#ifdef TARGET_WORDS_BIGENDIAN
2932 v = cirrus_mmio_readb(opaque, addr) << 8;
2933 v |= cirrus_mmio_readb(opaque, addr + 1);
2934#else
2935 v = cirrus_mmio_readb(opaque, addr);
2936 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2937#endif
2938 return v;
2939}
2940
2941static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2942{
2943 uint32_t v;
2944#ifdef TARGET_WORDS_BIGENDIAN
2945 v = cirrus_mmio_readb(opaque, addr) << 24;
2946 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2947 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2948 v |= cirrus_mmio_readb(opaque, addr + 3);
2949#else
2950 v = cirrus_mmio_readb(opaque, addr);
2951 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2952 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2953 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2954#endif
2955 return v;
2956}
2957
2958static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2959 uint32_t val)
2960{
2961 CirrusVGAState *s = (CirrusVGAState *) opaque;
2962
2963 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2964
2965 if (addr >= 0x100) {
2966 cirrus_mmio_blt_write(s, addr - 0x100, val);
2967 } else {
2968 vga_ioport_write(s, addr + 0x3c0, val);
2969 }
2970}
2971
2972static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2973 uint32_t val)
2974{
2975#ifdef TARGET_WORDS_BIGENDIAN
2976 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2977 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2978#else
2979 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2980 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2981#endif
2982}
2983
2984static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2985 uint32_t val)
2986{
2987#ifdef TARGET_WORDS_BIGENDIAN
2988 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2989 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2990 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2991 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2992#else
2993 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2994 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2995 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2996 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2997#endif
2998}
2999
3000
3001static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3002 cirrus_mmio_readb,
3003 cirrus_mmio_readw,
3004 cirrus_mmio_readl,
3005};
3006
3007static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3008 cirrus_mmio_writeb,
3009 cirrus_mmio_writew,
3010 cirrus_mmio_writel,
3011};
3012
2c6ab832
FB		 3013/* load/save state */
3014
3015static void cirrus_vga_save(QEMUFile *f, void *opaque)
3016{
3017 CirrusVGAState *s = opaque;
3018
d2269f6f
FB		 3019 if (s->pci_dev)
3020 pci_device_save(s->pci_dev, f);
3021
2c6ab832
FB		 3022 qemu_put_be32s(f, &s->latch);
3023 qemu_put_8s(f, &s->sr_index);
3024 qemu_put_buffer(f, s->sr, 256);
3025 qemu_put_8s(f, &s->gr_index);
3026 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3027 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3028 qemu_put_buffer(f, s->gr + 2, 254);
3029 qemu_put_8s(f, &s->ar_index);
3030 qemu_put_buffer(f, s->ar, 21);
bee8d684 3031 qemu_put_be32(f, s->ar_flip_flop);
2c6ab832
FB		 3032 qemu_put_8s(f, &s->cr_index);
3033 qemu_put_buffer(f, s->cr, 256);
3034 qemu_put_8s(f, &s->msr);
3035 qemu_put_8s(f, &s->fcr);
3036 qemu_put_8s(f, &s->st00);
3037 qemu_put_8s(f, &s->st01);
3038
3039 qemu_put_8s(f, &s->dac_state);
3040 qemu_put_8s(f, &s->dac_sub_index);
3041 qemu_put_8s(f, &s->dac_read_index);
3042 qemu_put_8s(f, &s->dac_write_index);
3043 qemu_put_buffer(f, s->dac_cache, 3);
3044 qemu_put_buffer(f, s->palette, 768);
3045
bee8d684 3046 qemu_put_be32(f, s->bank_offset);
2c6ab832
FB		 3047
3048 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3049 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3050
3051 qemu_put_be32s(f, &s->hw_cursor_x);
3052 qemu_put_be32s(f, &s->hw_cursor_y);
3053 /* XXX: we do not save the bitblt state - we assume we do not save
3054 the state when the blitter is active */
3055}
3056
3057static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3058{
3059 CirrusVGAState *s = opaque;
d2269f6f 3060 int ret;
2c6ab832 3061
d2269f6f 3062 if (version_id > 2)
2c6ab832
FB		 3063 return -EINVAL;
3064
d2269f6f
FB		 3065 if (s->pci_dev && version_id >= 2) {
3066 ret = pci_device_load(s->pci_dev, f);
3067 if (ret < 0)
3068 return ret;
3069 }
3070
2c6ab832
FB		 3071 qemu_get_be32s(f, &s->latch);
3072 qemu_get_8s(f, &s->sr_index);
3073 qemu_get_buffer(f, s->sr, 256);
3074 qemu_get_8s(f, &s->gr_index);
3075 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3076 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3077 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3078 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3079 qemu_get_buffer(f, s->gr + 2, 254);
3080 qemu_get_8s(f, &s->ar_index);
3081 qemu_get_buffer(f, s->ar, 21);
bee8d684 3082 s->ar_flip_flop=qemu_get_be32(f);
2c6ab832
FB		 3083 qemu_get_8s(f, &s->cr_index);
3084 qemu_get_buffer(f, s->cr, 256);
3085 qemu_get_8s(f, &s->msr);
3086 qemu_get_8s(f, &s->fcr);
3087 qemu_get_8s(f, &s->st00);
3088 qemu_get_8s(f, &s->st01);
3089
3090 qemu_get_8s(f, &s->dac_state);
3091 qemu_get_8s(f, &s->dac_sub_index);
3092 qemu_get_8s(f, &s->dac_read_index);
3093 qemu_get_8s(f, &s->dac_write_index);
3094 qemu_get_buffer(f, s->dac_cache, 3);
3095 qemu_get_buffer(f, s->palette, 768);
3096
bee8d684 3097 s->bank_offset=qemu_get_be32(f);
2c6ab832
FB		 3098
3099 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3100 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3101
3102 qemu_get_be32s(f, &s->hw_cursor_x);
3103 qemu_get_be32s(f, &s->hw_cursor_y);
3104
3105 /* force refresh */
3106 s->graphic_mode = -1;
3107 cirrus_update_bank_ptr(s, 0);
3108 cirrus_update_bank_ptr(s, 1);
3109 return 0;
3110}
3111
e6e5ad80
FB		 3112/***************************************
3113 *
3114 * initialize
3115 *
3116 ***************************************/
3117
78e127ef 3118static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
e6e5ad80 3119{
b4fbd879 3120 int i;
a5082316
FB		 3121 static int inited;
3122
3123 if (!inited) {
3124 inited = 1;
3125 for(i = 0;i < 256; i++)
3126 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3127 rop_to_index[CIRRUS_ROP_0] = 0;
3128 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3129 rop_to_index[CIRRUS_ROP_NOP] = 2;
3130 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3131 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3132 rop_to_index[CIRRUS_ROP_SRC] = 5;
3133 rop_to_index[CIRRUS_ROP_1] = 6;
3134 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3135 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3136 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3137 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3138 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3139 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3140 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3141 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3142 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3143 }
e6e5ad80
FB		 3144
3145 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3146
3147 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3148 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3149 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3150 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3151
3152 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3153
3154 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3155 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3156 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3157 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3158
b4fbd879 3159 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
e6e5ad80 3160 cirrus_vga_mem_write, s);
5fafdf24 3161 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
b4fbd879 3162 s->vga_io_memory);
e6e5ad80
FB		 3163
3164 s->sr[0x06] = 0x0f;
78e127ef
FB		 3165 if (device_id == CIRRUS_ID_CLGD5446) {
3166 /* 4MB 64 bit memory config, always PCI */
b30d4608
FB		 3167 s->sr[0x1F] = 0x2d; // MemClock
3168 s->gr[0x18] = 0x0f; // fastest memory configuration
78e127ef
FB		 3169#if 1
3170 s->sr[0x0f] = 0x98;
3171 s->sr[0x17] = 0x20;
3172 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3173 s->real_vram_size = 4096 * 1024;
3174#else
3175 s->sr[0x0f] = 0x18;
3176 s->sr[0x17] = 0x20;
3177 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3178 s->real_vram_size = 2048 * 1024;
3179#endif
3180 } else {
b30d4608 3181 s->sr[0x1F] = 0x22; // MemClock
78e127ef 3182 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
5fafdf24 3183 if (is_pci)
78e127ef
FB		 3184 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3185 else
3186 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3187 s->real_vram_size = 2048 * 1024;
3188 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3189 }
20ba3ae1 3190 s->cr[0x27] = device_id;
e6e5ad80 3191
78e127ef
FB		 3192 /* Win2K seems to assume that the pattern buffer is at 0xff
3193 initially ! */
3194 memset(s->vram_ptr, 0xff, s->real_vram_size);
3195
e6e5ad80
FB		 3196 s->cirrus_hidden_dac_lockindex = 5;
3197 s->cirrus_hidden_dac_data = 0;
3198
3199 /* I/O handler for LFB */
3200 s->cirrus_linear_io_addr =
3201 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3202 s);
8926b517
FB		 3203 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3204
a5082316
FB		 3205 /* I/O handler for LFB */
3206 s->cirrus_linear_bitblt_io_addr =
3207 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3208 s);
3209
e6e5ad80
FB		 3210 /* I/O handler for memory-mapped I/O */
3211 s->cirrus_mmio_io_addr =
3212 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3213
3214 /* XXX: s->vram_size must be a power of two */
78e127ef
FB		 3215 s->cirrus_addr_mask = s->real_vram_size - 1;
3216 s->linear_mmio_mask = s->real_vram_size - 256;
e6e5ad80
FB		 3217
3218 s->get_bpp = cirrus_get_bpp;
3219 s->get_offsets = cirrus_get_offsets;
78e127ef 3220 s->get_resolution = cirrus_get_resolution;
a5082316
FB		 3221 s->cursor_invalidate = cirrus_cursor_invalidate;
3222 s->cursor_draw_line = cirrus_cursor_draw_line;
2c6ab832 3223
d2269f6f 3224 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
e6e5ad80
FB		 3225}
3226
3227/***************************************
3228 *
3229 * ISA bus support
3230 *
3231 ***************************************/
3232
5fafdf24 3233void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
4efe2755 3234 ram_addr_t vga_ram_offset, int vga_ram_size)
e6e5ad80
FB		 3235{
3236 CirrusVGAState *s;
3237
3238 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3239
5fafdf24 3240 vga_common_init((VGAState *)s,
e6e5ad80 3241 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3242 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
d5529471
AJ		 3243 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3244 s->screen_dump, s->text_update, s);
e6e5ad80
FB		 3245 /* XXX ISA-LFB support */
3246}
3247
3248/***************************************
3249 *
3250 * PCI bus support
3251 *
3252 ***************************************/
3253
3254static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3255 uint32_t addr, uint32_t size, int type)
3256{
3257 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3258
a5082316 3259 /* XXX: add byte swapping apertures */
e6e5ad80
FB		 3260 cpu_register_physical_memory(addr, s->vram_size,
3261 s->cirrus_linear_io_addr);
a5082316
FB		 3262 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3263 s->cirrus_linear_bitblt_io_addr);
e6e5ad80
FB		 3264}
3265
3266static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3267 uint32_t addr, uint32_t size, int type)
3268{
3269 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3270
3271 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3272 s->cirrus_mmio_io_addr);
3273}
3274
5fafdf24 3275void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
4efe2755 3276 ram_addr_t vga_ram_offset, int vga_ram_size)
e6e5ad80
FB		 3277{
3278 PCICirrusVGAState *d;
3279 uint8_t *pci_conf;
3280 CirrusVGAState *s;
20ba3ae1 3281 int device_id;
3b46e624 3282
20ba3ae1 3283 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 3284
3285 /* setup PCI configuration registers */
5fafdf24
TS		 3286 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3287 sizeof(PCICirrusVGAState),
46e50e9d 3288 -1, NULL, NULL);
e6e5ad80
FB		 3289 pci_conf = d->dev.config;
3290 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3291 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
20ba3ae1
FB		 3292 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3293 pci_conf[0x03] = (uint8_t) (device_id >> 8);
e6e5ad80
FB		 3294 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3295 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3296 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3297 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3298
3299 /* setup VGA */
3300 s = &d->cirrus_vga;
5fafdf24 3301 vga_common_init((VGAState *)s,
e6e5ad80 3302 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3303 cirrus_init_common(s, device_id, 1);
d34cab9f 3304
c60e08d9
PB		 3305 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3306 s->screen_dump, s->text_update, s);
d34cab9f 3307
d2269f6f 3308 s->pci_dev = (PCIDevice *)d;
e6e5ad80
FB		 3309
3310 /* setup memory space */
3311 /* memory #0 LFB */
3312 /* memory #1 memory-mapped I/O */
3313 /* XXX: s->vram_size must be a power of two */
a5082316 3314 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
a21ae81d 3315 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 3316 if (device_id == CIRRUS_ID_CLGD5446) {
a21ae81d
FB		 3317 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3318 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3319 }
e6e5ad80
FB		 3320 /* XXX: ROM BIOS */
3321}
Qemu copy for testing