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[qemu.git] / hw / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
e6e5ad80
FB		 3 *
4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
e6e5ad80
FB		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
e6e5ad80
FB		 29#include "vl.h"
30#include "vga_int.h"
31
a5082316
FB		 32/*
33 * TODO:
34 * - add support for WRITEMASK (GR2F)
a5082316
FB		 35 * - optimize linear mappings
36 * - optimize bitblt functions
37 */
38
e36f36e1 39//#define DEBUG_CIRRUS
a21ae81d 40//#define DEBUG_BITBLT
e36f36e1 41
e6e5ad80
FB		 42/***************************************
43 *
44 * definitions
45 *
46 ***************************************/
47
48#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
49
50// ID
51#define CIRRUS_ID_CLGD5422 (0x23<<2)
52#define CIRRUS_ID_CLGD5426 (0x24<<2)
53#define CIRRUS_ID_CLGD5424 (0x25<<2)
54#define CIRRUS_ID_CLGD5428 (0x26<<2)
55#define CIRRUS_ID_CLGD5430 (0x28<<2)
56#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 57#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 58#define CIRRUS_ID_CLGD5446 (0x2E<<2)
59
60// sequencer 0x07
61#define CIRRUS_SR7_BPP_VGA 0x00
62#define CIRRUS_SR7_BPP_SVGA 0x01
63#define CIRRUS_SR7_BPP_MASK 0x0e
64#define CIRRUS_SR7_BPP_8 0x00
65#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
66#define CIRRUS_SR7_BPP_24 0x04
67#define CIRRUS_SR7_BPP_16 0x06
68#define CIRRUS_SR7_BPP_32 0x08
69#define CIRRUS_SR7_ISAADDR_MASK 0xe0
70
71// sequencer 0x0f
72#define CIRRUS_MEMSIZE_512k 0x08
73#define CIRRUS_MEMSIZE_1M 0x10
74#define CIRRUS_MEMSIZE_2M 0x18
75#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
76
77// sequencer 0x12
78#define CIRRUS_CURSOR_SHOW 0x01
79#define CIRRUS_CURSOR_HIDDENPEL 0x02
80#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
81
82// sequencer 0x17
83#define CIRRUS_BUSTYPE_VLBFAST 0x10
84#define CIRRUS_BUSTYPE_PCI 0x20
85#define CIRRUS_BUSTYPE_VLBSLOW 0x30
86#define CIRRUS_BUSTYPE_ISA 0x38
87#define CIRRUS_MMIO_ENABLE 0x04
88#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
89#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
90
91// control 0x0b
92#define CIRRUS_BANKING_DUAL 0x01
93#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
94
95// control 0x30
96#define CIRRUS_BLTMODE_BACKWARDS 0x01
97#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
98#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
99#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
100#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
101#define CIRRUS_BLTMODE_COLOREXPAND 0x80
102#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
103#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
104#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
105#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
106#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
107
108// control 0x31
109#define CIRRUS_BLT_BUSY 0x01
110#define CIRRUS_BLT_START 0x02
111#define CIRRUS_BLT_RESET 0x04
112#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 113#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 114
115// control 0x32
116#define CIRRUS_ROP_0 0x00
117#define CIRRUS_ROP_SRC_AND_DST 0x05
118#define CIRRUS_ROP_NOP 0x06
119#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
120#define CIRRUS_ROP_NOTDST 0x0b
121#define CIRRUS_ROP_SRC 0x0d
122#define CIRRUS_ROP_1 0x0e
123#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
124#define CIRRUS_ROP_SRC_XOR_DST 0x59
125#define CIRRUS_ROP_SRC_OR_DST 0x6d
126#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
127#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
128#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
129#define CIRRUS_ROP_NOTSRC 0xd0
130#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
131#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
132
a5082316
FB		 133#define CIRRUS_ROP_NOP_INDEX 2
134#define CIRRUS_ROP_SRC_INDEX 5
135
a21ae81d 136// control 0x33
a5082316 137#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 138#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 139#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 140
e6e5ad80
FB		 141// memory-mapped IO
142#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
143#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
144#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
145#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
146#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
147#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
148#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
149#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
150#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
151#define CIRRUS_MMIO_BLTMODE 0x18 // byte
152#define CIRRUS_MMIO_BLTROP 0x1a // byte
153#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
154#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
155#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
156#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
157#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
158#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
159#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
160#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
161#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
164#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
165#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
166#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
167#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
168#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
169#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
170#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
171
172// PCI 0x00: vendor, 0x02: device
173#define PCI_VENDOR_CIRRUS 0x1013
e6e5ad80
FB		 174#define PCI_DEVICE_CLGD5462 0x00d0
175#define PCI_DEVICE_CLGD5465 0x00d6
a21ae81d 176
e6e5ad80
FB		 177// PCI 0x04: command(word), 0x06(word): status
178#define PCI_COMMAND_IOACCESS 0x0001
179#define PCI_COMMAND_MEMACCESS 0x0002
180#define PCI_COMMAND_BUSMASTER 0x0004
181#define PCI_COMMAND_SPECIALCYCLE 0x0008
182#define PCI_COMMAND_MEMWRITEINVALID 0x0010
183#define PCI_COMMAND_PALETTESNOOPING 0x0020
184#define PCI_COMMAND_PARITYDETECTION 0x0040
185#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
186#define PCI_COMMAND_SERR 0x0100
187#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
188// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
189#define PCI_CLASS_BASE_DISPLAY 0x03
190// PCI 0x08, 0x00ff0000
191#define PCI_CLASS_SUB_VGA 0x00
192// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
193#define PCI_CLASS_HEADERTYPE_00h 0x00
194// 0x10-0x3f (headertype 00h)
195// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
196// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
197#define PCI_MAP_MEM 0x0
198#define PCI_MAP_IO 0x1
199#define PCI_MAP_MEM_ADDR_MASK (~0xf)
200#define PCI_MAP_IO_ADDR_MASK (~0x3)
201#define PCI_MAP_MEMFLAGS_32BIT 0x0
202#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
203#define PCI_MAP_MEMFLAGS_64BIT 0x4
204#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
205// PCI 0x28: cardbus CIS pointer
206// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
207// PCI 0x30: expansion ROM base address
208#define PCI_ROMBIOS_ENABLED 0x1
209// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
210// PCI 0x38: reserved
211// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
212
a21ae81d 213#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 214
215
216/* I/O and memory hook */
217#define CIRRUS_HOOK_NOT_HANDLED 0
218#define CIRRUS_HOOK_HANDLED 1
219
a5082316
FB		 220struct CirrusVGAState;
221typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
222 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 223 int dstpitch, int srcpitch,
224 int bltwidth, int bltheight);
a5082316
FB		 225typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
226 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 227
228typedef struct CirrusVGAState {
4e3e9d0b 229 VGA_STATE_COMMON
e6e5ad80
FB		 230
231 int cirrus_linear_io_addr;
a5082316 232 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 233 int cirrus_mmio_io_addr;
234 uint32_t cirrus_addr_mask;
78e127ef 235 uint32_t linear_mmio_mask;
e6e5ad80
FB		 236 uint8_t cirrus_shadow_gr0;
237 uint8_t cirrus_shadow_gr1;
238 uint8_t cirrus_hidden_dac_lockindex;
239 uint8_t cirrus_hidden_dac_data;
240 uint32_t cirrus_bank_base[2];
241 uint32_t cirrus_bank_limit[2];
242 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 243 uint32_t hw_cursor_x;
244 uint32_t hw_cursor_y;
e6e5ad80
FB		 245 int cirrus_blt_pixelwidth;
246 int cirrus_blt_width;
247 int cirrus_blt_height;
248 int cirrus_blt_dstpitch;
249 int cirrus_blt_srcpitch;
a5082316
FB		 250 uint32_t cirrus_blt_fgcol;
251 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 252 uint32_t cirrus_blt_dstaddr;
253 uint32_t cirrus_blt_srcaddr;
254 uint8_t cirrus_blt_mode;
a5082316 255 uint8_t cirrus_blt_modeext;
e6e5ad80 256 cirrus_bitblt_rop_t cirrus_rop;
a5082316 257#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 258 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
259 uint8_t *cirrus_srcptr;
260 uint8_t *cirrus_srcptr_end;
261 uint32_t cirrus_srccounter;
262 uint8_t *cirrus_dstptr;
263 uint8_t *cirrus_dstptr_end;
264 uint32_t cirrus_dstcounter;
a5082316
FB		 265 /* hwcursor display state */
266 int last_hw_cursor_size;
267 int last_hw_cursor_x;
268 int last_hw_cursor_y;
269 int last_hw_cursor_y_start;
270 int last_hw_cursor_y_end;
78e127ef 271 int real_vram_size; /* XXX: suppress that */
e6e5ad80
FB		 272} CirrusVGAState;
273
274typedef struct PCICirrusVGAState {
275 PCIDevice dev;
276 CirrusVGAState cirrus_vga;
277} PCICirrusVGAState;
278
a5082316
FB		 279static uint8_t rop_to_index[256];
280
e6e5ad80
FB		 281/***************************************
282 *
283 * prototypes.
284 *
285 ***************************************/
286
287
288static void cirrus_bitblt_reset(CirrusVGAState * s);
289
290/***************************************
291 *
292 * raster operations
293 *
294 ***************************************/
295
a5082316
FB		 296static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
297 uint8_t *dst,const uint8_t *src,
298 int dstpitch,int srcpitch,
299 int bltwidth,int bltheight)
300{
e6e5ad80
FB		 301}
302
a5082316
FB		 303static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
304 uint8_t *dst,
305 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 306{
a5082316 307}
e6e5ad80 308
a5082316
FB		 309#define ROP_NAME 0
310#define ROP_OP(d, s) d = 0
311#include "cirrus_vga_rop.h"
e6e5ad80 312
a5082316
FB		 313#define ROP_NAME src_and_dst
314#define ROP_OP(d, s) d = (s) & (d)
315#include "cirrus_vga_rop.h"
e6e5ad80 316
a5082316
FB		 317#define ROP_NAME src_and_notdst
318#define ROP_OP(d, s) d = (s) & (~(d))
319#include "cirrus_vga_rop.h"
e6e5ad80 320
a5082316
FB		 321#define ROP_NAME notdst
322#define ROP_OP(d, s) d = ~(d)
323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316
FB		 325#define ROP_NAME src
326#define ROP_OP(d, s) d = s
327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316 329#define ROP_NAME 1
4c8732d7 330#define ROP_OP(d, s) d = ~0
a5082316
FB		 331#include "cirrus_vga_rop.h"
332
333#define ROP_NAME notsrc_and_dst
334#define ROP_OP(d, s) d = (~(s)) & (d)
335#include "cirrus_vga_rop.h"
336
337#define ROP_NAME src_xor_dst
338#define ROP_OP(d, s) d = (s) ^ (d)
339#include "cirrus_vga_rop.h"
340
341#define ROP_NAME src_or_dst
342#define ROP_OP(d, s) d = (s) | (d)
343#include "cirrus_vga_rop.h"
344
345#define ROP_NAME notsrc_or_notdst
346#define ROP_OP(d, s) d = (~(s)) | (~(d))
347#include "cirrus_vga_rop.h"
348
349#define ROP_NAME src_notxor_dst
350#define ROP_OP(d, s) d = ~((s) ^ (d))
351#include "cirrus_vga_rop.h"
e6e5ad80 352
a5082316
FB		 353#define ROP_NAME src_or_notdst
354#define ROP_OP(d, s) d = (s) | (~(d))
355#include "cirrus_vga_rop.h"
356
357#define ROP_NAME notsrc
358#define ROP_OP(d, s) d = (~(s))
359#include "cirrus_vga_rop.h"
360
361#define ROP_NAME notsrc_or_dst
362#define ROP_OP(d, s) d = (~(s)) | (d)
363#include "cirrus_vga_rop.h"
364
365#define ROP_NAME notsrc_and_notdst
366#define ROP_OP(d, s) d = (~(s)) & (~(d))
367#include "cirrus_vga_rop.h"
368
369static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
370 cirrus_bitblt_rop_fwd_0,
371 cirrus_bitblt_rop_fwd_src_and_dst,
372 cirrus_bitblt_rop_nop,
373 cirrus_bitblt_rop_fwd_src_and_notdst,
374 cirrus_bitblt_rop_fwd_notdst,
375 cirrus_bitblt_rop_fwd_src,
376 cirrus_bitblt_rop_fwd_1,
377 cirrus_bitblt_rop_fwd_notsrc_and_dst,
378 cirrus_bitblt_rop_fwd_src_xor_dst,
379 cirrus_bitblt_rop_fwd_src_or_dst,
380 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
381 cirrus_bitblt_rop_fwd_src_notxor_dst,
382 cirrus_bitblt_rop_fwd_src_or_notdst,
383 cirrus_bitblt_rop_fwd_notsrc,
384 cirrus_bitblt_rop_fwd_notsrc_or_dst,
385 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
386};
387
388static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
389 cirrus_bitblt_rop_bkwd_0,
390 cirrus_bitblt_rop_bkwd_src_and_dst,
391 cirrus_bitblt_rop_nop,
392 cirrus_bitblt_rop_bkwd_src_and_notdst,
393 cirrus_bitblt_rop_bkwd_notdst,
394 cirrus_bitblt_rop_bkwd_src,
395 cirrus_bitblt_rop_bkwd_1,
396 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
397 cirrus_bitblt_rop_bkwd_src_xor_dst,
398 cirrus_bitblt_rop_bkwd_src_or_dst,
399 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
400 cirrus_bitblt_rop_bkwd_src_notxor_dst,
401 cirrus_bitblt_rop_bkwd_src_or_notdst,
402 cirrus_bitblt_rop_bkwd_notsrc,
403 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
404 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
405};
406
407#define ROP2(name) {\
408 name ## _8,\
409 name ## _16,\
410 name ## _24,\
411 name ## _32,\
412 }
413
414#define ROP_NOP2(func) {\
415 func,\
416 func,\
417 func,\
418 func,\
419 }
420
e69390ce
FB		 421static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
422 ROP2(cirrus_patternfill_0),
423 ROP2(cirrus_patternfill_src_and_dst),
424 ROP_NOP2(cirrus_bitblt_rop_nop),
425 ROP2(cirrus_patternfill_src_and_notdst),
426 ROP2(cirrus_patternfill_notdst),
427 ROP2(cirrus_patternfill_src),
428 ROP2(cirrus_patternfill_1),
429 ROP2(cirrus_patternfill_notsrc_and_dst),
430 ROP2(cirrus_patternfill_src_xor_dst),
431 ROP2(cirrus_patternfill_src_or_dst),
432 ROP2(cirrus_patternfill_notsrc_or_notdst),
433 ROP2(cirrus_patternfill_src_notxor_dst),
434 ROP2(cirrus_patternfill_src_or_notdst),
435 ROP2(cirrus_patternfill_notsrc),
436 ROP2(cirrus_patternfill_notsrc_or_dst),
437 ROP2(cirrus_patternfill_notsrc_and_notdst),
438};
439
a5082316
FB		 440static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
441 ROP2(cirrus_colorexpand_transp_0),
442 ROP2(cirrus_colorexpand_transp_src_and_dst),
443 ROP_NOP2(cirrus_bitblt_rop_nop),
444 ROP2(cirrus_colorexpand_transp_src_and_notdst),
445 ROP2(cirrus_colorexpand_transp_notdst),
446 ROP2(cirrus_colorexpand_transp_src),
447 ROP2(cirrus_colorexpand_transp_1),
448 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
449 ROP2(cirrus_colorexpand_transp_src_xor_dst),
450 ROP2(cirrus_colorexpand_transp_src_or_dst),
451 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
452 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
453 ROP2(cirrus_colorexpand_transp_src_or_notdst),
454 ROP2(cirrus_colorexpand_transp_notsrc),
455 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
456 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
457};
458
459static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
460 ROP2(cirrus_colorexpand_0),
461 ROP2(cirrus_colorexpand_src_and_dst),
462 ROP_NOP2(cirrus_bitblt_rop_nop),
463 ROP2(cirrus_colorexpand_src_and_notdst),
464 ROP2(cirrus_colorexpand_notdst),
465 ROP2(cirrus_colorexpand_src),
466 ROP2(cirrus_colorexpand_1),
467 ROP2(cirrus_colorexpand_notsrc_and_dst),
468 ROP2(cirrus_colorexpand_src_xor_dst),
469 ROP2(cirrus_colorexpand_src_or_dst),
470 ROP2(cirrus_colorexpand_notsrc_or_notdst),
471 ROP2(cirrus_colorexpand_src_notxor_dst),
472 ROP2(cirrus_colorexpand_src_or_notdst),
473 ROP2(cirrus_colorexpand_notsrc),
474 ROP2(cirrus_colorexpand_notsrc_or_dst),
475 ROP2(cirrus_colorexpand_notsrc_and_notdst),
476};
477
b30d4608
FB		 478static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
479 ROP2(cirrus_colorexpand_pattern_transp_0),
480 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
481 ROP_NOP2(cirrus_bitblt_rop_nop),
482 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
483 ROP2(cirrus_colorexpand_pattern_transp_notdst),
484 ROP2(cirrus_colorexpand_pattern_transp_src),
485 ROP2(cirrus_colorexpand_pattern_transp_1),
486 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
487 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
488 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
489 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
490 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
491 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
492 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
493 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
494 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
495};
496
497static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
498 ROP2(cirrus_colorexpand_pattern_0),
499 ROP2(cirrus_colorexpand_pattern_src_and_dst),
500 ROP_NOP2(cirrus_bitblt_rop_nop),
501 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
502 ROP2(cirrus_colorexpand_pattern_notdst),
503 ROP2(cirrus_colorexpand_pattern_src),
504 ROP2(cirrus_colorexpand_pattern_1),
505 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
506 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
507 ROP2(cirrus_colorexpand_pattern_src_or_dst),
508 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
509 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
510 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
511 ROP2(cirrus_colorexpand_pattern_notsrc),
512 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
513 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
514};
515
a5082316
FB		 516static const cirrus_fill_t cirrus_fill[16][4] = {
517 ROP2(cirrus_fill_0),
518 ROP2(cirrus_fill_src_and_dst),
519 ROP_NOP2(cirrus_bitblt_fill_nop),
520 ROP2(cirrus_fill_src_and_notdst),
521 ROP2(cirrus_fill_notdst),
522 ROP2(cirrus_fill_src),
523 ROP2(cirrus_fill_1),
524 ROP2(cirrus_fill_notsrc_and_dst),
525 ROP2(cirrus_fill_src_xor_dst),
526 ROP2(cirrus_fill_src_or_dst),
527 ROP2(cirrus_fill_notsrc_or_notdst),
528 ROP2(cirrus_fill_src_notxor_dst),
529 ROP2(cirrus_fill_src_or_notdst),
530 ROP2(cirrus_fill_notsrc),
531 ROP2(cirrus_fill_notsrc_or_dst),
532 ROP2(cirrus_fill_notsrc_and_notdst),
533};
534
535static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 536{
a5082316
FB		 537 unsigned int color;
538 switch (s->cirrus_blt_pixelwidth) {
539 case 1:
540 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
541 break;
542 case 2:
543 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
544 s->cirrus_blt_fgcol = le16_to_cpu(color);
545 break;
546 case 3:
547 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
548 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
549 break;
550 default:
551 case 4:
552 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
553 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
554 s->cirrus_blt_fgcol = le32_to_cpu(color);
555 break;
e6e5ad80
FB		 556 }
557}
558
a5082316 559static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 560{
a5082316 561 unsigned int color;
e6e5ad80
FB		 562 switch (s->cirrus_blt_pixelwidth) {
563 case 1:
a5082316
FB		 564 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
565 break;
e6e5ad80 566 case 2:
a5082316
FB		 567 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
568 s->cirrus_blt_bgcol = le16_to_cpu(color);
569 break;
e6e5ad80 570 case 3:
a5082316
FB		 571 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
572 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
573 break;
e6e5ad80 574 default:
a5082316
FB		 575 case 4:
576 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
577 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
578 s->cirrus_blt_bgcol = le32_to_cpu(color);
579 break;
e6e5ad80
FB		 580 }
581}
582
583static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
584 int off_pitch, int bytesperline,
585 int lines)
586{
587 int y;
588 int off_cur;
589 int off_cur_end;
590
591 for (y = 0; y < lines; y++) {
592 off_cur = off_begin;
593 off_cur_end = off_cur + bytesperline;
594 off_cur &= TARGET_PAGE_MASK;
595 while (off_cur < off_cur_end) {
596 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
597 off_cur += TARGET_PAGE_SIZE;
598 }
599 off_begin += off_pitch;
600 }
601}
602
e6e5ad80
FB		 603static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
604 const uint8_t * src)
605{
e6e5ad80 606 uint8_t *dst;
e6e5ad80 607
e6e5ad80 608 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
e69390ce
FB		 609 (*s->cirrus_rop) (s, dst, src,
610 s->cirrus_blt_dstpitch, 0,
611 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 612 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 613 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
614 s->cirrus_blt_height);
e6e5ad80
FB		 615 return 1;
616}
617
a21ae81d
FB		 618/* fill */
619
a5082316 620static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 621{
a5082316 622 cirrus_fill_t rop_func;
a21ae81d 623
a5082316
FB		 624 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
625 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
626 s->cirrus_blt_dstpitch,
627 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 628 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
629 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
630 s->cirrus_blt_height);
631 cirrus_bitblt_reset(s);
632 return 1;
633}
634
e6e5ad80
FB		 635/***************************************
636 *
637 * bitblt (video-to-video)
638 *
639 ***************************************/
640
641static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
642{
643 return cirrus_bitblt_common_patterncopy(s,
e69390ce
FB		 644 s->vram_ptr +
645 (s->cirrus_blt_srcaddr & ~7));
e6e5ad80
FB		 646}
647
648static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
649{
a5082316 650 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
e6e5ad80
FB		 651 s->vram_ptr + s->cirrus_blt_srcaddr,
652 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
653 s->cirrus_blt_width, s->cirrus_blt_height);
654 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
655 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
656 s->cirrus_blt_height);
657 return 1;
658}
659
660/***************************************
661 *
662 * bitblt (cpu-to-video)
663 *
664 ***************************************/
665
e6e5ad80
FB		 666static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
667{
668 int copy_count;
a5082316
FB		 669 uint8_t *end_ptr;
670
e6e5ad80 671 if (s->cirrus_srccounter > 0) {
a5082316
FB		 672 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
673 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
674 the_end:
675 s->cirrus_srccounter = 0;
676 cirrus_bitblt_reset(s);
677 } else {
678 /* at least one scan line */
679 do {
680 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
681 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
682 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
683 s->cirrus_blt_width, 1);
684 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
685 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
686 if (s->cirrus_srccounter <= 0)
687 goto the_end;
688 /* more bytes than needed can be transfered because of
689 word alignment, so we keep them for the next line */
690 /* XXX: keep alignment to speed up transfer */
691 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
692 copy_count = s->cirrus_srcptr_end - end_ptr;
693 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
694 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
695 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
696 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
697 }
e6e5ad80
FB		 698 }
699}
700
701/***************************************
702 *
703 * bitblt wrapper
704 *
705 ***************************************/
706
707static void cirrus_bitblt_reset(CirrusVGAState * s)
708{
709 s->gr[0x31] &=
710 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
711 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
712 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
713 s->cirrus_srccounter = 0;
714 s->cirrus_dstptr = &s->cirrus_bltbuf[0];
715 s->cirrus_dstptr_end = &s->cirrus_bltbuf[0];
716 s->cirrus_dstcounter = 0;
e6e5ad80
FB		 717}
718
719static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
720{
a5082316
FB		 721 int w;
722
e6e5ad80
FB		 723 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
724 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
725 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
726
727 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
728 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 729 s->cirrus_blt_srcpitch = 8;
e6e5ad80 730 } else {
b30d4608 731 /* XXX: check for 24 bpp */
a5082316 732 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 733 }
a5082316 734 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 735 } else {
736 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316
FB		 737 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
738 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
739 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
740 else
741 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 742 } else {
e6e5ad80
FB		 743 s->cirrus_blt_srcpitch = s->cirrus_blt_width;
744 }
a5082316 745 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 746 }
a5082316
FB		 747 s->cirrus_srcptr = s->cirrus_bltbuf;
748 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
e6e5ad80
FB		 749 return 1;
750}
751
752static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
753{
754 /* XXX */
a5082316 755#ifdef DEBUG_BITBLT
e6e5ad80
FB		 756 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
757#endif
758 return 0;
759}
760
761static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
762{
763 int ret;
764
765 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
766 ret = cirrus_bitblt_videotovideo_patterncopy(s);
767 } else {
768 ret = cirrus_bitblt_videotovideo_copy(s);
769 }
e6e5ad80
FB		 770 if (ret)
771 cirrus_bitblt_reset(s);
772 return ret;
773}
774
775static void cirrus_bitblt_start(CirrusVGAState * s)
776{
777 uint8_t blt_rop;
778
a5082316
FB		 779 s->gr[0x31] |= CIRRUS_BLT_BUSY;
780
e6e5ad80
FB		 781 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
782 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
783 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
784 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
785 s->cirrus_blt_dstaddr =
786 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
787 s->cirrus_blt_srcaddr =
788 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
789 s->cirrus_blt_mode = s->gr[0x30];
a5082316 790 s->cirrus_blt_modeext = s->gr[0x33];
e6e5ad80
FB		 791 blt_rop = s->gr[0x32];
792
a21ae81d 793#ifdef DEBUG_BITBLT
a5082316 794 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spicth=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
a21ae81d
FB		 795 blt_rop,
796 s->cirrus_blt_mode,
a5082316 797 s->cirrus_blt_modeext,
a21ae81d
FB		 798 s->cirrus_blt_width,
799 s->cirrus_blt_height,
800 s->cirrus_blt_dstpitch,
801 s->cirrus_blt_srcpitch,
802 s->cirrus_blt_dstaddr,
a5082316
FB		 803 s->cirrus_blt_srcaddr,
804 s->sr[0x2f]);
a21ae81d
FB		 805#endif
806
e6e5ad80
FB		 807 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
808 case CIRRUS_BLTMODE_PIXELWIDTH8:
809 s->cirrus_blt_pixelwidth = 1;
810 break;
811 case CIRRUS_BLTMODE_PIXELWIDTH16:
812 s->cirrus_blt_pixelwidth = 2;
813 break;
814 case CIRRUS_BLTMODE_PIXELWIDTH24:
815 s->cirrus_blt_pixelwidth = 3;
816 break;
817 case CIRRUS_BLTMODE_PIXELWIDTH32:
818 s->cirrus_blt_pixelwidth = 4;
819 break;
820 default:
a5082316 821#ifdef DEBUG_BITBLT
e6e5ad80
FB		 822 printf("cirrus: bitblt - pixel width is unknown\n");
823#endif
824 goto bitblt_ignore;
825 }
826 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
827
828 if ((s->
829 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
830 CIRRUS_BLTMODE_MEMSYSDEST))
831 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 832#ifdef DEBUG_BITBLT
e6e5ad80
FB		 833 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
834#endif
835 goto bitblt_ignore;
836 }
837
a5082316 838 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
a21ae81d
FB		 839 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
840 CIRRUS_BLTMODE_TRANSPARENTCOMP |
841 CIRRUS_BLTMODE_PATTERNCOPY |
842 CIRRUS_BLTMODE_COLOREXPAND)) ==
843 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 844 cirrus_bitblt_fgcol(s);
845 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 846 } else {
a5082316
FB		 847 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
848 CIRRUS_BLTMODE_PATTERNCOPY)) ==
849 CIRRUS_BLTMODE_COLOREXPAND) {
850
851 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 852 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 853 cirrus_bitblt_bgcol(s);
b30d4608 854 else
4c8732d7 855 cirrus_bitblt_fgcol(s);
b30d4608 856 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 857 } else {
858 cirrus_bitblt_fgcol(s);
859 cirrus_bitblt_bgcol(s);
860 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
861 }
e69390ce 862 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 863 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
864 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
865 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
866 cirrus_bitblt_bgcol(s);
867 else
868 cirrus_bitblt_fgcol(s);
869 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
870 } else {
871 cirrus_bitblt_fgcol(s);
872 cirrus_bitblt_bgcol(s);
873 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
874 }
875 } else {
876 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
877 }
a21ae81d 878 } else {
a5082316
FB		 879 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
880 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
881 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
882 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
883 } else {
884 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
885 }
a21ae81d
FB		 886 }
887
888 // setup bitblt engine.
889 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
890 if (!cirrus_bitblt_cputovideo(s))
891 goto bitblt_ignore;
892 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
893 if (!cirrus_bitblt_videotocpu(s))
894 goto bitblt_ignore;
895 } else {
896 if (!cirrus_bitblt_videotovideo(s))
897 goto bitblt_ignore;
898 }
e6e5ad80 899 }
e6e5ad80
FB		 900 return;
901 bitblt_ignore:;
902 cirrus_bitblt_reset(s);
903}
904
905static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
906{
907 unsigned old_value;
908
909 old_value = s->gr[0x31];
910 s->gr[0x31] = reg_value;
911
912 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
913 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
914 cirrus_bitblt_reset(s);
915 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
916 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 917 cirrus_bitblt_start(s);
918 }
919}
920
921
922/***************************************
923 *
924 * basic parameters
925 *
926 ***************************************/
927
928static void cirrus_get_offsets(VGAState *s1,
929 uint32_t *pline_offset,
930 uint32_t *pstart_addr)
931{
932 CirrusVGAState * s = (CirrusVGAState *)s1;
933 uint32_t start_addr;
934 uint32_t line_offset;
935
936 line_offset = s->cr[0x13]
e36f36e1 937 | ((s->cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 938 line_offset <<= 3;
939 *pline_offset = line_offset;
940
941 start_addr = (s->cr[0x0c] << 8)
942 | s->cr[0x0d]
943 | ((s->cr[0x1b] & 0x01) << 16)
944 | ((s->cr[0x1b] & 0x0c) << 15)
945 | ((s->cr[0x1d] & 0x80) << 12);
946 *pstart_addr = start_addr;
947}
948
949static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
950{
951 uint32_t ret = 16;
952
953 switch (s->cirrus_hidden_dac_data & 0xf) {
954 case 0:
955 ret = 15;
956 break; /* Sierra HiColor */
957 case 1:
958 ret = 16;
959 break; /* XGA HiColor */
960 default:
961#ifdef DEBUG_CIRRUS
962 printf("cirrus: invalid DAC value %x in 16bpp\n",
963 (s->cirrus_hidden_dac_data & 0xf));
964#endif
965 ret = 15; /* XXX */
966 break;
967 }
968 return ret;
969}
970
971static int cirrus_get_bpp(VGAState *s1)
972{
973 CirrusVGAState * s = (CirrusVGAState *)s1;
974 uint32_t ret = 8;
975
976 if ((s->sr[0x07] & 0x01) != 0) {
977 /* Cirrus SVGA */
978 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
979 case CIRRUS_SR7_BPP_8:
980 ret = 8;
981 break;
982 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
983 ret = cirrus_get_bpp16_depth(s);
984 break;
985 case CIRRUS_SR7_BPP_24:
986 ret = 24;
987 break;
988 case CIRRUS_SR7_BPP_16:
989 ret = cirrus_get_bpp16_depth(s);
990 break;
991 case CIRRUS_SR7_BPP_32:
992 ret = 32;
993 break;
994 default:
995#ifdef DEBUG_CIRRUS
996 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
997#endif
998 ret = 8;
999 break;
1000 }
1001 } else {
1002 /* VGA */
aeb3c85f 1003 ret = 0;
e6e5ad80
FB		 1004 }
1005
1006 return ret;
1007}
1008
78e127ef
FB		 1009static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1010{
1011 int width, height;
1012
1013 width = (s->cr[0x01] + 1) * 8;
1014 height = s->cr[0x12] |
1015 ((s->cr[0x07] & 0x02) << 7) |
1016 ((s->cr[0x07] & 0x40) << 3);
1017 height = (height + 1);
1018 /* interlace support */
1019 if (s->cr[0x1a] & 0x01)
1020 height = height * 2;
1021 *pwidth = width;
1022 *pheight = height;
1023}
1024
e6e5ad80
FB		 1025/***************************************
1026 *
1027 * bank memory
1028 *
1029 ***************************************/
1030
1031static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1032{
1033 unsigned offset;
1034 unsigned limit;
1035
1036 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1037 offset = s->gr[0x09 + bank_index];
1038 else /* single bank */
1039 offset = s->gr[0x09];
1040
1041 if ((s->gr[0x0b] & 0x20) != 0)
1042 offset <<= 14;
1043 else
1044 offset <<= 12;
1045
1046 if (s->vram_size <= offset)
1047 limit = 0;
1048 else
1049 limit = s->vram_size - offset;
1050
1051 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1052 if (limit > 0x8000) {
1053 offset += 0x8000;
1054 limit -= 0x8000;
1055 } else {
1056 limit = 0;
1057 }
1058 }
1059
1060 if (limit > 0) {
1061 s->cirrus_bank_base[bank_index] = offset;
1062 s->cirrus_bank_limit[bank_index] = limit;
1063 } else {
1064 s->cirrus_bank_base[bank_index] = 0;
1065 s->cirrus_bank_limit[bank_index] = 0;
1066 }
1067}
1068
1069/***************************************
1070 *
1071 * I/O access between 0x3c4-0x3c5
1072 *
1073 ***************************************/
1074
1075static int
1076cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1077{
1078 switch (reg_index) {
1079 case 0x00: // Standard VGA
1080 case 0x01: // Standard VGA
1081 case 0x02: // Standard VGA
1082 case 0x03: // Standard VGA
1083 case 0x04: // Standard VGA
1084 return CIRRUS_HOOK_NOT_HANDLED;
1085 case 0x06: // Unlock Cirrus extensions
1086 *reg_value = s->sr[reg_index];
1087 break;
e6e5ad80
FB		 1088 case 0x10:
1089 case 0x30:
1090 case 0x50:
1091 case 0x70: // Graphics Cursor X
1092 case 0x90:
1093 case 0xb0:
1094 case 0xd0:
1095 case 0xf0: // Graphics Cursor X
aeb3c85f
FB		 1096 *reg_value = s->sr[0x10];
1097 break;
e6e5ad80
FB		 1098 case 0x11:
1099 case 0x31:
1100 case 0x51:
1101 case 0x71: // Graphics Cursor Y
1102 case 0x91:
1103 case 0xb1:
1104 case 0xd1:
a5082316 1105 case 0xf1: // Graphics Cursor Y
aeb3c85f
FB		 1106 *reg_value = s->sr[0x11];
1107 break;
1108 case 0x05: // ???
1109 case 0x07: // Extended Sequencer Mode
1110 case 0x08: // EEPROM Control
1111 case 0x09: // Scratch Register 0
1112 case 0x0a: // Scratch Register 1
1113 case 0x0b: // VCLK 0
1114 case 0x0c: // VCLK 1
1115 case 0x0d: // VCLK 2
1116 case 0x0e: // VCLK 3
1117 case 0x0f: // DRAM Control
e6e5ad80
FB		 1118 case 0x12: // Graphics Cursor Attribute
1119 case 0x13: // Graphics Cursor Pattern Address
1120 case 0x14: // Scratch Register 2
1121 case 0x15: // Scratch Register 3
1122 case 0x16: // Performance Tuning Register
1123 case 0x17: // Configuration Readback and Extended Control
1124 case 0x18: // Signature Generator Control
1125 case 0x19: // Signal Generator Result
1126 case 0x1a: // Signal Generator Result
1127 case 0x1b: // VCLK 0 Denominator & Post
1128 case 0x1c: // VCLK 1 Denominator & Post
1129 case 0x1d: // VCLK 2 Denominator & Post
1130 case 0x1e: // VCLK 3 Denominator & Post
1131 case 0x1f: // BIOS Write Enable and MCLK select
1132#ifdef DEBUG_CIRRUS
1133 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1134#endif
1135 *reg_value = s->sr[reg_index];
1136 break;
1137 default:
1138#ifdef DEBUG_CIRRUS
1139 printf("cirrus: inport sr_index %02x\n", reg_index);
1140#endif
1141 *reg_value = 0xff;
1142 break;
1143 }
1144
1145 return CIRRUS_HOOK_HANDLED;
1146}
1147
1148static int
1149cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1150{
1151 switch (reg_index) {
1152 case 0x00: // Standard VGA
1153 case 0x01: // Standard VGA
1154 case 0x02: // Standard VGA
1155 case 0x03: // Standard VGA
1156 case 0x04: // Standard VGA
1157 return CIRRUS_HOOK_NOT_HANDLED;
1158 case 0x06: // Unlock Cirrus extensions
1159 reg_value &= 0x17;
1160 if (reg_value == 0x12) {
1161 s->sr[reg_index] = 0x12;
1162 } else {
1163 s->sr[reg_index] = 0x0f;
1164 }
1165 break;
1166 case 0x10:
1167 case 0x30:
1168 case 0x50:
1169 case 0x70: // Graphics Cursor X
1170 case 0x90:
1171 case 0xb0:
1172 case 0xd0:
1173 case 0xf0: // Graphics Cursor X
1174 s->sr[0x10] = reg_value;
a5082316 1175 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1176 break;
1177 case 0x11:
1178 case 0x31:
1179 case 0x51:
1180 case 0x71: // Graphics Cursor Y
1181 case 0x91:
1182 case 0xb1:
1183 case 0xd1:
1184 case 0xf1: // Graphics Cursor Y
1185 s->sr[0x11] = reg_value;
a5082316 1186 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1187 break;
1188 case 0x07: // Extended Sequencer Mode
1189 case 0x08: // EEPROM Control
1190 case 0x09: // Scratch Register 0
1191 case 0x0a: // Scratch Register 1
1192 case 0x0b: // VCLK 0
1193 case 0x0c: // VCLK 1
1194 case 0x0d: // VCLK 2
1195 case 0x0e: // VCLK 3
1196 case 0x0f: // DRAM Control
1197 case 0x12: // Graphics Cursor Attribute
1198 case 0x13: // Graphics Cursor Pattern Address
1199 case 0x14: // Scratch Register 2
1200 case 0x15: // Scratch Register 3
1201 case 0x16: // Performance Tuning Register
1202 case 0x17: // Configuration Readback and Extended Control
1203 case 0x18: // Signature Generator Control
1204 case 0x19: // Signature Generator Result
1205 case 0x1a: // Signature Generator Result
1206 case 0x1b: // VCLK 0 Denominator & Post
1207 case 0x1c: // VCLK 1 Denominator & Post
1208 case 0x1d: // VCLK 2 Denominator & Post
1209 case 0x1e: // VCLK 3 Denominator & Post
1210 case 0x1f: // BIOS Write Enable and MCLK select
1211 s->sr[reg_index] = reg_value;
1212#ifdef DEBUG_CIRRUS
1213 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1214 reg_index, reg_value);
1215#endif
1216 break;
1217 default:
1218#ifdef DEBUG_CIRRUS
1219 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1220 reg_value);
1221#endif
1222 break;
1223 }
1224
1225 return CIRRUS_HOOK_HANDLED;
1226}
1227
1228/***************************************
1229 *
1230 * I/O access at 0x3c6
1231 *
1232 ***************************************/
1233
1234static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1235{
1236 *reg_value = 0xff;
a21ae81d
FB		 1237 if (++s->cirrus_hidden_dac_lockindex == 5) {
1238 *reg_value = s->cirrus_hidden_dac_data;
1239 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1240 }
1241}
1242
1243static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1244{
1245 if (s->cirrus_hidden_dac_lockindex == 4) {
1246 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1247#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1248 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1249#endif
1250 }
1251 s->cirrus_hidden_dac_lockindex = 0;
1252}
1253
1254/***************************************
1255 *
1256 * I/O access at 0x3c9
1257 *
1258 ***************************************/
1259
1260static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1261{
1262 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1263 return CIRRUS_HOOK_NOT_HANDLED;
a5082316
FB		 1264 *reg_value =
1265 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1266 s->dac_sub_index];
e6e5ad80
FB		 1267 if (++s->dac_sub_index == 3) {
1268 s->dac_sub_index = 0;
1269 s->dac_read_index++;
1270 }
1271 return CIRRUS_HOOK_HANDLED;
1272}
1273
1274static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1275{
1276 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1277 return CIRRUS_HOOK_NOT_HANDLED;
1278 s->dac_cache[s->dac_sub_index] = reg_value;
1279 if (++s->dac_sub_index == 3) {
a5082316
FB		 1280 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1281 s->dac_cache, 3);
1282 /* XXX update cursor */
e6e5ad80
FB		 1283 s->dac_sub_index = 0;
1284 s->dac_write_index++;
1285 }
1286 return CIRRUS_HOOK_HANDLED;
1287}
1288
1289/***************************************
1290 *
1291 * I/O access between 0x3ce-0x3cf
1292 *
1293 ***************************************/
1294
1295static int
1296cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1297{
1298 switch (reg_index) {
aeb3c85f
FB		 1299 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1300 *reg_value = s->cirrus_shadow_gr0;
1301 return CIRRUS_HOOK_HANDLED;
1302 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1303 *reg_value = s->cirrus_shadow_gr1;
1304 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1305 case 0x02: // Standard VGA
1306 case 0x03: // Standard VGA
1307 case 0x04: // Standard VGA
1308 case 0x06: // Standard VGA
1309 case 0x07: // Standard VGA
1310 case 0x08: // Standard VGA
1311 return CIRRUS_HOOK_NOT_HANDLED;
1312 case 0x05: // Standard VGA, Cirrus extended mode
1313 default:
1314 break;
1315 }
1316
1317 if (reg_index < 0x3a) {
1318 *reg_value = s->gr[reg_index];
1319 } else {
1320#ifdef DEBUG_CIRRUS
1321 printf("cirrus: inport gr_index %02x\n", reg_index);
1322#endif
1323 *reg_value = 0xff;
1324 }
1325
1326 return CIRRUS_HOOK_HANDLED;
1327}
1328
1329static int
1330cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1331{
a5082316
FB		 1332#if defined(DEBUG_BITBLT) && 0
1333 printf("gr%02x: %02x\n", reg_index, reg_value);
1334#endif
e6e5ad80
FB		 1335 switch (reg_index) {
1336 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1337 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1338 return CIRRUS_HOOK_NOT_HANDLED;
1339 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1340 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1341 return CIRRUS_HOOK_NOT_HANDLED;
1342 case 0x02: // Standard VGA
1343 case 0x03: // Standard VGA
1344 case 0x04: // Standard VGA
1345 case 0x06: // Standard VGA
1346 case 0x07: // Standard VGA
1347 case 0x08: // Standard VGA
1348 return CIRRUS_HOOK_NOT_HANDLED;
1349 case 0x05: // Standard VGA, Cirrus extended mode
1350 s->gr[reg_index] = reg_value & 0x7f;
1351 break;
1352 case 0x09: // bank offset #0
1353 case 0x0A: // bank offset #1
1354 case 0x0B:
1355 s->gr[reg_index] = reg_value;
1356 cirrus_update_bank_ptr(s, 0);
1357 cirrus_update_bank_ptr(s, 1);
1358 break;
1359 case 0x10: // BGCOLOR 0x0000ff00
1360 case 0x11: // FGCOLOR 0x0000ff00
1361 case 0x12: // BGCOLOR 0x00ff0000
1362 case 0x13: // FGCOLOR 0x00ff0000
1363 case 0x14: // BGCOLOR 0xff000000
1364 case 0x15: // FGCOLOR 0xff000000
1365 case 0x20: // BLT WIDTH 0x0000ff
1366 case 0x22: // BLT HEIGHT 0x0000ff
1367 case 0x24: // BLT DEST PITCH 0x0000ff
1368 case 0x26: // BLT SRC PITCH 0x0000ff
1369 case 0x28: // BLT DEST ADDR 0x0000ff
1370 case 0x29: // BLT DEST ADDR 0x00ff00
1371 case 0x2c: // BLT SRC ADDR 0x0000ff
1372 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1373 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1374 case 0x30: // BLT MODE
1375 case 0x32: // RASTER OP
a21ae81d 1376 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1377 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1378 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1379 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1380 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1381 s->gr[reg_index] = reg_value;
1382 break;
1383 case 0x21: // BLT WIDTH 0x001f00
1384 case 0x23: // BLT HEIGHT 0x001f00
1385 case 0x25: // BLT DEST PITCH 0x001f00
1386 case 0x27: // BLT SRC PITCH 0x001f00
1387 s->gr[reg_index] = reg_value & 0x1f;
1388 break;
1389 case 0x2a: // BLT DEST ADDR 0x3f0000
a5082316
FB		 1390 s->gr[reg_index] = reg_value & 0x3f;
1391 /* if auto start mode, starts bit blt now */
1392 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1393 cirrus_bitblt_start(s);
1394 }
1395 break;
e6e5ad80
FB		 1396 case 0x2e: // BLT SRC ADDR 0x3f0000
1397 s->gr[reg_index] = reg_value & 0x3f;
1398 break;
1399 case 0x31: // BLT STATUS/START
1400 cirrus_write_bitblt(s, reg_value);
1401 break;
1402 default:
1403#ifdef DEBUG_CIRRUS
1404 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1405 reg_value);
1406#endif
1407 break;
1408 }
1409
1410 return CIRRUS_HOOK_HANDLED;
1411}
1412
1413/***************************************
1414 *
1415 * I/O access between 0x3d4-0x3d5
1416 *
1417 ***************************************/
1418
1419static int
1420cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1421{
1422 switch (reg_index) {
1423 case 0x00: // Standard VGA
1424 case 0x01: // Standard VGA
1425 case 0x02: // Standard VGA
1426 case 0x03: // Standard VGA
1427 case 0x04: // Standard VGA
1428 case 0x05: // Standard VGA
1429 case 0x06: // Standard VGA
1430 case 0x07: // Standard VGA
1431 case 0x08: // Standard VGA
1432 case 0x09: // Standard VGA
1433 case 0x0a: // Standard VGA
1434 case 0x0b: // Standard VGA
1435 case 0x0c: // Standard VGA
1436 case 0x0d: // Standard VGA
1437 case 0x0e: // Standard VGA
1438 case 0x0f: // Standard VGA
1439 case 0x10: // Standard VGA
1440 case 0x11: // Standard VGA
1441 case 0x12: // Standard VGA
1442 case 0x13: // Standard VGA
1443 case 0x14: // Standard VGA
1444 case 0x15: // Standard VGA
1445 case 0x16: // Standard VGA
1446 case 0x17: // Standard VGA
1447 case 0x18: // Standard VGA
1448 return CIRRUS_HOOK_NOT_HANDLED;
1449 case 0x19: // Interlace End
1450 case 0x1a: // Miscellaneous Control
1451 case 0x1b: // Extended Display Control
1452 case 0x1c: // Sync Adjust and Genlock
1453 case 0x1d: // Overlay Extended Control
1454 case 0x22: // Graphics Data Latches Readback (R)
1455 case 0x24: // Attribute Controller Toggle Readback (R)
1456 case 0x25: // Part Status
1457 case 0x27: // Part ID (R)
1458 *reg_value = s->cr[reg_index];
1459 break;
1460 case 0x26: // Attribute Controller Index Readback (R)
1461 *reg_value = s->ar_index & 0x3f;
1462 break;
1463 default:
1464#ifdef DEBUG_CIRRUS
1465 printf("cirrus: inport cr_index %02x\n", reg_index);
1466 *reg_value = 0xff;
1467#endif
1468 break;
1469 }
1470
1471 return CIRRUS_HOOK_HANDLED;
1472}
1473
1474static int
1475cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1476{
1477 switch (reg_index) {
1478 case 0x00: // Standard VGA
1479 case 0x01: // Standard VGA
1480 case 0x02: // Standard VGA
1481 case 0x03: // Standard VGA
1482 case 0x04: // Standard VGA
1483 case 0x05: // Standard VGA
1484 case 0x06: // Standard VGA
1485 case 0x07: // Standard VGA
1486 case 0x08: // Standard VGA
1487 case 0x09: // Standard VGA
1488 case 0x0a: // Standard VGA
1489 case 0x0b: // Standard VGA
1490 case 0x0c: // Standard VGA
1491 case 0x0d: // Standard VGA
1492 case 0x0e: // Standard VGA
1493 case 0x0f: // Standard VGA
1494 case 0x10: // Standard VGA
1495 case 0x11: // Standard VGA
1496 case 0x12: // Standard VGA
1497 case 0x13: // Standard VGA
1498 case 0x14: // Standard VGA
1499 case 0x15: // Standard VGA
1500 case 0x16: // Standard VGA
1501 case 0x17: // Standard VGA
1502 case 0x18: // Standard VGA
1503 return CIRRUS_HOOK_NOT_HANDLED;
1504 case 0x19: // Interlace End
1505 case 0x1a: // Miscellaneous Control
1506 case 0x1b: // Extended Display Control
1507 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1508 case 0x1d: // Overlay Extended Control
e6e5ad80
FB		 1509 s->cr[reg_index] = reg_value;
1510#ifdef DEBUG_CIRRUS
1511 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1512 reg_index, reg_value);
1513#endif
1514 break;
1515 case 0x22: // Graphics Data Latches Readback (R)
1516 case 0x24: // Attribute Controller Toggle Readback (R)
1517 case 0x26: // Attribute Controller Index Readback (R)
1518 case 0x27: // Part ID (R)
1519 break;
e6e5ad80
FB		 1520 case 0x25: // Part Status
1521 default:
1522#ifdef DEBUG_CIRRUS
1523 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1524 reg_value);
1525#endif
1526 break;
1527 }
1528
1529 return CIRRUS_HOOK_HANDLED;
1530}
1531
1532/***************************************
1533 *
1534 * memory-mapped I/O (bitblt)
1535 *
1536 ***************************************/
1537
1538static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1539{
1540 int value = 0xff;
1541
1542 switch (address) {
1543 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1544 cirrus_hook_read_gr(s, 0x00, &value);
1545 break;
1546 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1547 cirrus_hook_read_gr(s, 0x10, &value);
1548 break;
1549 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1550 cirrus_hook_read_gr(s, 0x12, &value);
1551 break;
1552 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1553 cirrus_hook_read_gr(s, 0x14, &value);
1554 break;
1555 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1556 cirrus_hook_read_gr(s, 0x01, &value);
1557 break;
1558 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1559 cirrus_hook_read_gr(s, 0x11, &value);
1560 break;
1561 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1562 cirrus_hook_read_gr(s, 0x13, &value);
1563 break;
1564 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1565 cirrus_hook_read_gr(s, 0x15, &value);
1566 break;
1567 case (CIRRUS_MMIO_BLTWIDTH + 0):
1568 cirrus_hook_read_gr(s, 0x20, &value);
1569 break;
1570 case (CIRRUS_MMIO_BLTWIDTH + 1):
1571 cirrus_hook_read_gr(s, 0x21, &value);
1572 break;
1573 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1574 cirrus_hook_read_gr(s, 0x22, &value);
1575 break;
1576 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1577 cirrus_hook_read_gr(s, 0x23, &value);
1578 break;
1579 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1580 cirrus_hook_read_gr(s, 0x24, &value);
1581 break;
1582 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1583 cirrus_hook_read_gr(s, 0x25, &value);
1584 break;
1585 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1586 cirrus_hook_read_gr(s, 0x26, &value);
1587 break;
1588 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1589 cirrus_hook_read_gr(s, 0x27, &value);
1590 break;
1591 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1592 cirrus_hook_read_gr(s, 0x28, &value);
1593 break;
1594 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1595 cirrus_hook_read_gr(s, 0x29, &value);
1596 break;
1597 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1598 cirrus_hook_read_gr(s, 0x2a, &value);
1599 break;
1600 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1601 cirrus_hook_read_gr(s, 0x2c, &value);
1602 break;
1603 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1604 cirrus_hook_read_gr(s, 0x2d, &value);
1605 break;
1606 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1607 cirrus_hook_read_gr(s, 0x2e, &value);
1608 break;
1609 case CIRRUS_MMIO_BLTWRITEMASK:
1610 cirrus_hook_read_gr(s, 0x2f, &value);
1611 break;
1612 case CIRRUS_MMIO_BLTMODE:
1613 cirrus_hook_read_gr(s, 0x30, &value);
1614 break;
1615 case CIRRUS_MMIO_BLTROP:
1616 cirrus_hook_read_gr(s, 0x32, &value);
1617 break;
a21ae81d
FB		 1618 case CIRRUS_MMIO_BLTMODEEXT:
1619 cirrus_hook_read_gr(s, 0x33, &value);
1620 break;
e6e5ad80
FB		 1621 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1622 cirrus_hook_read_gr(s, 0x34, &value);
1623 break;
1624 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1625 cirrus_hook_read_gr(s, 0x35, &value);
1626 break;
1627 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1628 cirrus_hook_read_gr(s, 0x38, &value);
1629 break;
1630 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1631 cirrus_hook_read_gr(s, 0x39, &value);
1632 break;
1633 case CIRRUS_MMIO_BLTSTATUS:
1634 cirrus_hook_read_gr(s, 0x31, &value);
1635 break;
1636 default:
1637#ifdef DEBUG_CIRRUS
1638 printf("cirrus: mmio read - address 0x%04x\n", address);
1639#endif
1640 break;
1641 }
1642
1643 return (uint8_t) value;
1644}
1645
1646static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1647 uint8_t value)
1648{
1649 switch (address) {
1650 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1651 cirrus_hook_write_gr(s, 0x00, value);
1652 break;
1653 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1654 cirrus_hook_write_gr(s, 0x10, value);
1655 break;
1656 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1657 cirrus_hook_write_gr(s, 0x12, value);
1658 break;
1659 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1660 cirrus_hook_write_gr(s, 0x14, value);
1661 break;
1662 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1663 cirrus_hook_write_gr(s, 0x01, value);
1664 break;
1665 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1666 cirrus_hook_write_gr(s, 0x11, value);
1667 break;
1668 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1669 cirrus_hook_write_gr(s, 0x13, value);
1670 break;
1671 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1672 cirrus_hook_write_gr(s, 0x15, value);
1673 break;
1674 case (CIRRUS_MMIO_BLTWIDTH + 0):
1675 cirrus_hook_write_gr(s, 0x20, value);
1676 break;
1677 case (CIRRUS_MMIO_BLTWIDTH + 1):
1678 cirrus_hook_write_gr(s, 0x21, value);
1679 break;
1680 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1681 cirrus_hook_write_gr(s, 0x22, value);
1682 break;
1683 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1684 cirrus_hook_write_gr(s, 0x23, value);
1685 break;
1686 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1687 cirrus_hook_write_gr(s, 0x24, value);
1688 break;
1689 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1690 cirrus_hook_write_gr(s, 0x25, value);
1691 break;
1692 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1693 cirrus_hook_write_gr(s, 0x26, value);
1694 break;
1695 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1696 cirrus_hook_write_gr(s, 0x27, value);
1697 break;
1698 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1699 cirrus_hook_write_gr(s, 0x28, value);
1700 break;
1701 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1702 cirrus_hook_write_gr(s, 0x29, value);
1703 break;
1704 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1705 cirrus_hook_write_gr(s, 0x2a, value);
1706 break;
1707 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1708 /* ignored */
1709 break;
1710 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1711 cirrus_hook_write_gr(s, 0x2c, value);
1712 break;
1713 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1714 cirrus_hook_write_gr(s, 0x2d, value);
1715 break;
1716 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1717 cirrus_hook_write_gr(s, 0x2e, value);
1718 break;
1719 case CIRRUS_MMIO_BLTWRITEMASK:
1720 cirrus_hook_write_gr(s, 0x2f, value);
1721 break;
1722 case CIRRUS_MMIO_BLTMODE:
1723 cirrus_hook_write_gr(s, 0x30, value);
1724 break;
1725 case CIRRUS_MMIO_BLTROP:
1726 cirrus_hook_write_gr(s, 0x32, value);
1727 break;
a21ae81d
FB		 1728 case CIRRUS_MMIO_BLTMODEEXT:
1729 cirrus_hook_write_gr(s, 0x33, value);
1730 break;
e6e5ad80
FB		 1731 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1732 cirrus_hook_write_gr(s, 0x34, value);
1733 break;
1734 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1735 cirrus_hook_write_gr(s, 0x35, value);
1736 break;
1737 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1738 cirrus_hook_write_gr(s, 0x38, value);
1739 break;
1740 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1741 cirrus_hook_write_gr(s, 0x39, value);
1742 break;
1743 case CIRRUS_MMIO_BLTSTATUS:
1744 cirrus_hook_write_gr(s, 0x31, value);
1745 break;
1746 default:
1747#ifdef DEBUG_CIRRUS
1748 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1749 address, value);
1750#endif
1751 break;
1752 }
1753}
1754
e6e5ad80
FB		 1755/***************************************
1756 *
1757 * write mode 4/5
1758 *
1759 * assume TARGET_PAGE_SIZE >= 16
1760 *
1761 ***************************************/
1762
1763static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1764 unsigned mode,
1765 unsigned offset,
1766 uint32_t mem_value)
1767{
1768 int x;
1769 unsigned val = mem_value;
1770 uint8_t *dst;
1771
1772 dst = s->vram_ptr + offset;
1773 for (x = 0; x < 8; x++) {
1774 if (val & 0x80) {
aeb3c85f 1775 *dst++ = s->cirrus_shadow_gr1;
e6e5ad80 1776 } else if (mode == 5) {
aeb3c85f 1777 *dst++ = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1778 }
1779 val <<= 1;
1780 }
1781 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1782 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1783}
1784
1785static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1786 unsigned mode,
1787 unsigned offset,
1788 uint32_t mem_value)
1789{
1790 int x;
1791 unsigned val = mem_value;
1792 uint8_t *dst;
1793
1794 dst = s->vram_ptr + offset;
1795 for (x = 0; x < 8; x++) {
1796 if (val & 0x80) {
aeb3c85f 1797 *dst++ = s->cirrus_shadow_gr1;
e6e5ad80
FB		 1798 *dst++ = s->gr[0x11];
1799 } else if (mode == 5) {
aeb3c85f 1800 *dst++ = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1801 *dst++ = s->gr[0x10];
1802 }
1803 val <<= 1;
1804 }
1805 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1806 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1807}
1808
1809/***************************************
1810 *
1811 * memory access between 0xa0000-0xbffff
1812 *
1813 ***************************************/
1814
1815static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1816{
1817 CirrusVGAState *s = opaque;
1818 unsigned bank_index;
1819 unsigned bank_offset;
1820 uint32_t val;
1821
1822 if ((s->sr[0x07] & 0x01) == 0) {
1823 return vga_mem_readb(s, addr);
1824 }
1825
aeb3c85f
FB		 1826 addr &= 0x1ffff;
1827
e6e5ad80
FB		 1828 if (addr < 0x10000) {
1829 /* XXX handle bitblt */
1830 /* video memory */
1831 bank_index = addr >> 15;
1832 bank_offset = addr & 0x7fff;
1833 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1834 bank_offset += s->cirrus_bank_base[bank_index];
1835 if ((s->gr[0x0B] & 0x14) == 0x14) {
1836 bank_offset <<= 4;
1837 } else if (s->gr[0x0B] & 0x02) {
1838 bank_offset <<= 3;
1839 }
1840 bank_offset &= s->cirrus_addr_mask;
1841 val = *(s->vram_ptr + bank_offset);
1842 } else
1843 val = 0xff;
1844 } else if (addr >= 0x18000 && addr < 0x18100) {
1845 /* memory-mapped I/O */
1846 val = 0xff;
1847 if ((s->sr[0x17] & 0x44) == 0x04) {
1848 val = cirrus_mmio_blt_read(s, addr & 0xff);
1849 }
1850 } else {
1851 val = 0xff;
1852#ifdef DEBUG_CIRRUS
1853 printf("cirrus: mem_readb %06x\n", addr);
1854#endif
1855 }
1856 return val;
1857}
1858
1859static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
1860{
1861 uint32_t v;
1862#ifdef TARGET_WORDS_BIGENDIAN
1863 v = cirrus_vga_mem_readb(opaque, addr) << 8;
1864 v |= cirrus_vga_mem_readb(opaque, addr + 1);
1865#else
1866 v = cirrus_vga_mem_readb(opaque, addr);
1867 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1868#endif
1869 return v;
1870}
1871
1872static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
1873{
1874 uint32_t v;
1875#ifdef TARGET_WORDS_BIGENDIAN
1876 v = cirrus_vga_mem_readb(opaque, addr) << 24;
1877 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
1878 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
1879 v |= cirrus_vga_mem_readb(opaque, addr + 3);
1880#else
1881 v = cirrus_vga_mem_readb(opaque, addr);
1882 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1883 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
1884 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
1885#endif
1886 return v;
1887}
1888
1889static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1890 uint32_t mem_value)
1891{
1892 CirrusVGAState *s = opaque;
1893 unsigned bank_index;
1894 unsigned bank_offset;
1895 unsigned mode;
1896
1897 if ((s->sr[0x07] & 0x01) == 0) {
1898 vga_mem_writeb(s, addr, mem_value);
1899 return;
1900 }
1901
aeb3c85f
FB		 1902 addr &= 0x1ffff;
1903
e6e5ad80
FB		 1904 if (addr < 0x10000) {
1905 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
1906 /* bitblt */
1907 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 1908 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 1909 cirrus_bitblt_cputovideo_next(s);
1910 }
1911 } else {
1912 /* video memory */
1913 bank_index = addr >> 15;
1914 bank_offset = addr & 0x7fff;
1915 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1916 bank_offset += s->cirrus_bank_base[bank_index];
1917 if ((s->gr[0x0B] & 0x14) == 0x14) {
1918 bank_offset <<= 4;
1919 } else if (s->gr[0x0B] & 0x02) {
1920 bank_offset <<= 3;
1921 }
1922 bank_offset &= s->cirrus_addr_mask;
1923 mode = s->gr[0x05] & 0x7;
1924 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
1925 *(s->vram_ptr + bank_offset) = mem_value;
1926 cpu_physical_memory_set_dirty(s->vram_offset +
1927 bank_offset);
1928 } else {
1929 if ((s->gr[0x0B] & 0x14) != 0x14) {
1930 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
1931 bank_offset,
1932 mem_value);
1933 } else {
1934 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
1935 bank_offset,
1936 mem_value);
1937 }
1938 }
1939 }
1940 }
1941 } else if (addr >= 0x18000 && addr < 0x18100) {
1942 /* memory-mapped I/O */
1943 if ((s->sr[0x17] & 0x44) == 0x04) {
1944 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
1945 }
1946 } else {
1947#ifdef DEBUG_CIRRUS
1948 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
1949#endif
1950 }
1951}
1952
1953static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1954{
1955#ifdef TARGET_WORDS_BIGENDIAN
1956 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1957 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
1958#else
1959 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1960 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1961#endif
1962}
1963
1964static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1965{
1966#ifdef TARGET_WORDS_BIGENDIAN
1967 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1968 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1969 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1970 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
1971#else
1972 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1973 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1974 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1975 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1976#endif
1977}
1978
1979static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
1980 cirrus_vga_mem_readb,
1981 cirrus_vga_mem_readw,
1982 cirrus_vga_mem_readl,
1983};
1984
1985static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
1986 cirrus_vga_mem_writeb,
1987 cirrus_vga_mem_writew,
1988 cirrus_vga_mem_writel,
1989};
1990
a5082316
FB		 1991/***************************************
1992 *
1993 * hardware cursor
1994 *
1995 ***************************************/
1996
1997static inline void invalidate_cursor1(CirrusVGAState *s)
1998{
1999 if (s->last_hw_cursor_size) {
2000 vga_invalidate_scanlines((VGAState *)s,
2001 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2002 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2003 }
2004}
2005
2006static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2007{
2008 const uint8_t *src;
2009 uint32_t content;
2010 int y, y_min, y_max;
2011
78e127ef 2012 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2013 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2014 src += (s->sr[0x13] & 0x3c) * 256;
2015 y_min = 64;
2016 y_max = -1;
2017 for(y = 0; y < 64; y++) {
2018 content = ((uint32_t *)src)[0] |
2019 ((uint32_t *)src)[1] |
2020 ((uint32_t *)src)[2] |
2021 ((uint32_t *)src)[3];
2022 if (content) {
2023 if (y < y_min)
2024 y_min = y;
2025 if (y > y_max)
2026 y_max = y;
2027 }
2028 src += 16;
2029 }
2030 } else {
2031 src += (s->sr[0x13] & 0x3f) * 256;
2032 y_min = 32;
2033 y_max = -1;
2034 for(y = 0; y < 32; y++) {
2035 content = ((uint32_t *)src)[0] |
2036 ((uint32_t *)(src + 128))[0];
2037 if (content) {
2038 if (y < y_min)
2039 y_min = y;
2040 if (y > y_max)
2041 y_max = y;
2042 }
2043 src += 4;
2044 }
2045 }
2046 if (y_min > y_max) {
2047 s->last_hw_cursor_y_start = 0;
2048 s->last_hw_cursor_y_end = 0;
2049 } else {
2050 s->last_hw_cursor_y_start = y_min;
2051 s->last_hw_cursor_y_end = y_max + 1;
2052 }
2053}
2054
2055/* NOTE: we do not currently handle the cursor bitmap change, so we
2056 update the cursor only if it moves. */
2057static void cirrus_cursor_invalidate(VGAState *s1)
2058{
2059 CirrusVGAState *s = (CirrusVGAState *)s1;
2060 int size;
2061
2062 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2063 size = 0;
2064 } else {
2065 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2066 size = 64;
2067 else
2068 size = 32;
2069 }
2070 /* invalidate last cursor and new cursor if any change */
2071 if (s->last_hw_cursor_size != size ||
2072 s->last_hw_cursor_x != s->hw_cursor_x ||
2073 s->last_hw_cursor_y != s->hw_cursor_y) {
2074
2075 invalidate_cursor1(s);
2076
2077 s->last_hw_cursor_size = size;
2078 s->last_hw_cursor_x = s->hw_cursor_x;
2079 s->last_hw_cursor_y = s->hw_cursor_y;
2080 /* compute the real cursor min and max y */
2081 cirrus_cursor_compute_yrange(s);
2082 invalidate_cursor1(s);
2083 }
2084}
2085
2086static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2087{
2088 CirrusVGAState *s = (CirrusVGAState *)s1;
2089 int w, h, bpp, x1, x2, poffset;
2090 unsigned int color0, color1;
2091 const uint8_t *palette, *src;
2092 uint32_t content;
2093
2094 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2095 return;
2096 /* fast test to see if the cursor intersects with the scan line */
2097 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2098 h = 64;
2099 } else {
2100 h = 32;
2101 }
2102 if (scr_y < s->hw_cursor_y ||
2103 scr_y >= (s->hw_cursor_y + h))
2104 return;
2105
78e127ef 2106 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2107 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2108 src += (s->sr[0x13] & 0x3c) * 256;
2109 src += (scr_y - s->hw_cursor_y) * 16;
2110 poffset = 8;
2111 content = ((uint32_t *)src)[0] |
2112 ((uint32_t *)src)[1] |
2113 ((uint32_t *)src)[2] |
2114 ((uint32_t *)src)[3];
2115 } else {
2116 src += (s->sr[0x13] & 0x3f) * 256;
2117 src += (scr_y - s->hw_cursor_y) * 4;
2118 poffset = 128;
2119 content = ((uint32_t *)src)[0] |
2120 ((uint32_t *)(src + 128))[0];
2121 }
2122 /* if nothing to draw, no need to continue */
2123 if (!content)
2124 return;
2125 w = h;
2126
2127 x1 = s->hw_cursor_x;
2128 if (x1 >= s->last_scr_width)
2129 return;
2130 x2 = s->hw_cursor_x + w;
2131 if (x2 > s->last_scr_width)
2132 x2 = s->last_scr_width;
2133 w = x2 - x1;
2134 palette = s->cirrus_hidden_palette;
2135 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2136 c6_to_8(palette[0x0 * 3 + 1]),
2137 c6_to_8(palette[0x0 * 3 + 2]));
2138 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2139 c6_to_8(palette[0xf * 3 + 1]),
2140 c6_to_8(palette[0xf * 3 + 2]));
2141 bpp = ((s->ds->depth + 7) >> 3);
2142 d1 += x1 * bpp;
2143 switch(s->ds->depth) {
2144 default:
2145 break;
2146 case 8:
2147 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2148 break;
2149 case 15:
2150 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2151 break;
2152 case 16:
2153 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2154 break;
2155 case 32:
2156 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2157 break;
2158 }
2159}
2160
e6e5ad80
FB		 2161/***************************************
2162 *
2163 * LFB memory access
2164 *
2165 ***************************************/
2166
2167static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2168{
2169 CirrusVGAState *s = (CirrusVGAState *) opaque;
2170 uint32_t ret;
2171
e6e5ad80
FB		 2172 addr &= s->cirrus_addr_mask;
2173
78e127ef
FB		 2174 if (((s->sr[0x17] & 0x44) == 0x44) &&
2175 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2176 /* memory-mapped I/O */
2177 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2178 } else if (0) {
2179 /* XXX handle bitblt */
2180 ret = 0xff;
2181 } else {
2182 /* video memory */
2183 if ((s->gr[0x0B] & 0x14) == 0x14) {
2184 addr <<= 4;
2185 } else if (s->gr[0x0B] & 0x02) {
2186 addr <<= 3;
2187 }
2188 addr &= s->cirrus_addr_mask;
2189 ret = *(s->vram_ptr + addr);
2190 }
2191
2192 return ret;
2193}
2194
2195static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2196{
2197 uint32_t v;
2198#ifdef TARGET_WORDS_BIGENDIAN
2199 v = cirrus_linear_readb(opaque, addr) << 8;
2200 v |= cirrus_linear_readb(opaque, addr + 1);
2201#else
2202 v = cirrus_linear_readb(opaque, addr);
2203 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2204#endif
2205 return v;
2206}
2207
2208static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2209{
2210 uint32_t v;
2211#ifdef TARGET_WORDS_BIGENDIAN
2212 v = cirrus_linear_readb(opaque, addr) << 24;
2213 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2214 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2215 v |= cirrus_linear_readb(opaque, addr + 3);
2216#else
2217 v = cirrus_linear_readb(opaque, addr);
2218 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2219 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2220 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2221#endif
2222 return v;
2223}
2224
2225static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2226 uint32_t val)
2227{
2228 CirrusVGAState *s = (CirrusVGAState *) opaque;
2229 unsigned mode;
2230
2231 addr &= s->cirrus_addr_mask;
78e127ef
FB		 2232
2233 if (((s->sr[0x17] & 0x44) == 0x44) &&
2234 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2235 /* memory-mapped I/O */
2236 cirrus_mmio_blt_write(s, addr & 0xff, val);
2237 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2238 /* bitblt */
2239 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2240 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2241 cirrus_bitblt_cputovideo_next(s);
2242 }
2243 } else {
2244 /* video memory */
2245 if ((s->gr[0x0B] & 0x14) == 0x14) {
2246 addr <<= 4;
2247 } else if (s->gr[0x0B] & 0x02) {
2248 addr <<= 3;
2249 }
2250 addr &= s->cirrus_addr_mask;
2251
2252 mode = s->gr[0x05] & 0x7;
2253 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2254 *(s->vram_ptr + addr) = (uint8_t) val;
2255 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2256 } else {
2257 if ((s->gr[0x0B] & 0x14) != 0x14) {
2258 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2259 } else {
2260 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2261 }
2262 }
2263 }
2264}
2265
2266static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2267 uint32_t val)
2268{
2269#ifdef TARGET_WORDS_BIGENDIAN
2270 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2271 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2272#else
2273 cirrus_linear_writeb(opaque, addr, val & 0xff);
2274 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2275#endif
2276}
2277
2278static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2279 uint32_t val)
2280{
2281#ifdef TARGET_WORDS_BIGENDIAN
2282 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2283 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2284 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2285 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2286#else
2287 cirrus_linear_writeb(opaque, addr, val & 0xff);
2288 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2289 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2290 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2291#endif
2292}
2293
2294
2295static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2296 cirrus_linear_readb,
2297 cirrus_linear_readw,
2298 cirrus_linear_readl,
2299};
2300
2301static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2302 cirrus_linear_writeb,
2303 cirrus_linear_writew,
2304 cirrus_linear_writel,
2305};
2306
a5082316
FB		 2307/***************************************
2308 *
2309 * system to screen memory access
2310 *
2311 ***************************************/
2312
2313
2314static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2315{
2316 uint32_t ret;
2317
2318 /* XXX handle bitblt */
2319 ret = 0xff;
2320 return ret;
2321}
2322
2323static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2324{
2325 uint32_t v;
2326#ifdef TARGET_WORDS_BIGENDIAN
2327 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2328 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2329#else
2330 v = cirrus_linear_bitblt_readb(opaque, addr);
2331 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2332#endif
2333 return v;
2334}
2335
2336static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2337{
2338 uint32_t v;
2339#ifdef TARGET_WORDS_BIGENDIAN
2340 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2341 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2342 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2343 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2344#else
2345 v = cirrus_linear_bitblt_readb(opaque, addr);
2346 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2347 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2348 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2349#endif
2350 return v;
2351}
2352
2353static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2354 uint32_t val)
2355{
2356 CirrusVGAState *s = (CirrusVGAState *) opaque;
2357
2358 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2359 /* bitblt */
2360 *s->cirrus_srcptr++ = (uint8_t) val;
2361 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2362 cirrus_bitblt_cputovideo_next(s);
2363 }
2364 }
2365}
2366
2367static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2368 uint32_t val)
2369{
2370#ifdef TARGET_WORDS_BIGENDIAN
2371 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2372 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2373#else
2374 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2375 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2376#endif
2377}
2378
2379static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2380 uint32_t val)
2381{
2382#ifdef TARGET_WORDS_BIGENDIAN
2383 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2384 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2385 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2386 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2387#else
2388 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2389 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2390 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2391 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2392#endif
2393}
2394
2395
2396static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2397 cirrus_linear_bitblt_readb,
2398 cirrus_linear_bitblt_readw,
2399 cirrus_linear_bitblt_readl,
2400};
2401
2402static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2403 cirrus_linear_bitblt_writeb,
2404 cirrus_linear_bitblt_writew,
2405 cirrus_linear_bitblt_writel,
2406};
2407
e6e5ad80
FB		 2408/* I/O ports */
2409
2410static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2411{
2412 CirrusVGAState *s = opaque;
2413 int val, index;
2414
2415 /* check port range access depending on color/monochrome mode */
2416 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2417 || (addr >= 0x3d0 && addr <= 0x3df
2418 && !(s->msr & MSR_COLOR_EMULATION))) {
2419 val = 0xff;
2420 } else {
2421 switch (addr) {
2422 case 0x3c0:
2423 if (s->ar_flip_flop == 0) {
2424 val = s->ar_index;
2425 } else {
2426 val = 0;
2427 }
2428 break;
2429 case 0x3c1:
2430 index = s->ar_index & 0x1f;
2431 if (index < 21)
2432 val = s->ar[index];
2433 else
2434 val = 0;
2435 break;
2436 case 0x3c2:
2437 val = s->st00;
2438 break;
2439 case 0x3c4:
2440 val = s->sr_index;
2441 break;
2442 case 0x3c5:
2443 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2444 break;
2445 val = s->sr[s->sr_index];
2446#ifdef DEBUG_VGA_REG
2447 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2448#endif
2449 break;
2450 case 0x3c6:
2451 cirrus_read_hidden_dac(s, &val);
2452 break;
2453 case 0x3c7:
2454 val = s->dac_state;
2455 break;
ae184e4a
FB		 2456 case 0x3c8:
2457 val = s->dac_write_index;
2458 s->cirrus_hidden_dac_lockindex = 0;
2459 break;
2460 case 0x3c9:
e6e5ad80
FB		 2461 if (cirrus_hook_read_palette(s, &val))
2462 break;
2463 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2464 if (++s->dac_sub_index == 3) {
2465 s->dac_sub_index = 0;
2466 s->dac_read_index++;
2467 }
2468 break;
2469 case 0x3ca:
2470 val = s->fcr;
2471 break;
2472 case 0x3cc:
2473 val = s->msr;
2474 break;
2475 case 0x3ce:
2476 val = s->gr_index;
2477 break;
2478 case 0x3cf:
2479 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2480 break;
2481 val = s->gr[s->gr_index];
2482#ifdef DEBUG_VGA_REG
2483 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2484#endif
2485 break;
2486 case 0x3b4:
2487 case 0x3d4:
2488 val = s->cr_index;
2489 break;
2490 case 0x3b5:
2491 case 0x3d5:
2492 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2493 break;
2494 val = s->cr[s->cr_index];
2495#ifdef DEBUG_VGA_REG
2496 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2497#endif
2498 break;
2499 case 0x3ba:
2500 case 0x3da:
2501 /* just toggle to fool polling */
2502 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2503 val = s->st01;
2504 s->ar_flip_flop = 0;
2505 break;
2506 default:
2507 val = 0x00;
2508 break;
2509 }
2510 }
2511#if defined(DEBUG_VGA)
2512 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2513#endif
2514 return val;
2515}
2516
2517static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2518{
2519 CirrusVGAState *s = opaque;
2520 int index;
2521
2522 /* check port range access depending on color/monochrome mode */
2523 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2524 || (addr >= 0x3d0 && addr <= 0x3df
2525 && !(s->msr & MSR_COLOR_EMULATION)))
2526 return;
2527
2528#ifdef DEBUG_VGA
2529 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2530#endif
2531
2532 switch (addr) {
2533 case 0x3c0:
2534 if (s->ar_flip_flop == 0) {
2535 val &= 0x3f;
2536 s->ar_index = val;
2537 } else {
2538 index = s->ar_index & 0x1f;
2539 switch (index) {
2540 case 0x00 ... 0x0f:
2541 s->ar[index] = val & 0x3f;
2542 break;
2543 case 0x10:
2544 s->ar[index] = val & ~0x10;
2545 break;
2546 case 0x11:
2547 s->ar[index] = val;
2548 break;
2549 case 0x12:
2550 s->ar[index] = val & ~0xc0;
2551 break;
2552 case 0x13:
2553 s->ar[index] = val & ~0xf0;
2554 break;
2555 case 0x14:
2556 s->ar[index] = val & ~0xf0;
2557 break;
2558 default:
2559 break;
2560 }
2561 }
2562 s->ar_flip_flop ^= 1;
2563 break;
2564 case 0x3c2:
2565 s->msr = val & ~0x10;
2566 break;
2567 case 0x3c4:
2568 s->sr_index = val;
2569 break;
2570 case 0x3c5:
2571 if (cirrus_hook_write_sr(s, s->sr_index, val))
2572 break;
2573#ifdef DEBUG_VGA_REG
2574 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2575#endif
2576 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2577 break;
2578 case 0x3c6:
2579 cirrus_write_hidden_dac(s, val);
2580 break;
2581 case 0x3c7:
2582 s->dac_read_index = val;
2583 s->dac_sub_index = 0;
2584 s->dac_state = 3;
2585 break;
2586 case 0x3c8:
2587 s->dac_write_index = val;
2588 s->dac_sub_index = 0;
2589 s->dac_state = 0;
2590 break;
2591 case 0x3c9:
2592 if (cirrus_hook_write_palette(s, val))
2593 break;
2594 s->dac_cache[s->dac_sub_index] = val;
2595 if (++s->dac_sub_index == 3) {
2596 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2597 s->dac_sub_index = 0;
2598 s->dac_write_index++;
2599 }
2600 break;
2601 case 0x3ce:
2602 s->gr_index = val;
2603 break;
2604 case 0x3cf:
2605 if (cirrus_hook_write_gr(s, s->gr_index, val))
2606 break;
2607#ifdef DEBUG_VGA_REG
2608 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2609#endif
2610 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2611 break;
2612 case 0x3b4:
2613 case 0x3d4:
2614 s->cr_index = val;
2615 break;
2616 case 0x3b5:
2617 case 0x3d5:
2618 if (cirrus_hook_write_cr(s, s->cr_index, val))
2619 break;
2620#ifdef DEBUG_VGA_REG
2621 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2622#endif
2623 /* handle CR0-7 protection */
2624 if ((s->cr[11] & 0x80) && s->cr_index <= 7) {
2625 /* can always write bit 4 of CR7 */
2626 if (s->cr_index == 7)
2627 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2628 return;
2629 }
2630 switch (s->cr_index) {
2631 case 0x01: /* horizontal display end */
2632 case 0x07:
2633 case 0x09:
2634 case 0x0c:
2635 case 0x0d:
2636 case 0x12: /* veritcal display end */
2637 s->cr[s->cr_index] = val;
2638 break;
2639
2640 default:
2641 s->cr[s->cr_index] = val;
2642 break;
2643 }
2644 break;
2645 case 0x3ba:
2646 case 0x3da:
2647 s->fcr = val & 0x10;
2648 break;
2649 }
2650}
2651
e36f36e1
FB		 2652/***************************************
2653 *
2654 * memory-mapped I/O access
2655 *
2656 ***************************************/
2657
2658static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2659{
2660 CirrusVGAState *s = (CirrusVGAState *) opaque;
2661
2662 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2663
2664 if (addr >= 0x100) {
2665 return cirrus_mmio_blt_read(s, addr - 0x100);
2666 } else {
2667 return vga_ioport_read(s, addr + 0x3c0);
2668 }
2669}
2670
2671static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2672{
2673 uint32_t v;
2674#ifdef TARGET_WORDS_BIGENDIAN
2675 v = cirrus_mmio_readb(opaque, addr) << 8;
2676 v |= cirrus_mmio_readb(opaque, addr + 1);
2677#else
2678 v = cirrus_mmio_readb(opaque, addr);
2679 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2680#endif
2681 return v;
2682}
2683
2684static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2685{
2686 uint32_t v;
2687#ifdef TARGET_WORDS_BIGENDIAN
2688 v = cirrus_mmio_readb(opaque, addr) << 24;
2689 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2690 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2691 v |= cirrus_mmio_readb(opaque, addr + 3);
2692#else
2693 v = cirrus_mmio_readb(opaque, addr);
2694 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2695 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2696 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2697#endif
2698 return v;
2699}
2700
2701static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2702 uint32_t val)
2703{
2704 CirrusVGAState *s = (CirrusVGAState *) opaque;
2705
2706 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2707
2708 if (addr >= 0x100) {
2709 cirrus_mmio_blt_write(s, addr - 0x100, val);
2710 } else {
2711 vga_ioport_write(s, addr + 0x3c0, val);
2712 }
2713}
2714
2715static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2716 uint32_t val)
2717{
2718#ifdef TARGET_WORDS_BIGENDIAN
2719 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2720 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2721#else
2722 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2723 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2724#endif
2725}
2726
2727static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2728 uint32_t val)
2729{
2730#ifdef TARGET_WORDS_BIGENDIAN
2731 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2732 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2733 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2734 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2735#else
2736 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2737 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2738 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2739 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2740#endif
2741}
2742
2743
2744static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2745 cirrus_mmio_readb,
2746 cirrus_mmio_readw,
2747 cirrus_mmio_readl,
2748};
2749
2750static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2751 cirrus_mmio_writeb,
2752 cirrus_mmio_writew,
2753 cirrus_mmio_writel,
2754};
2755
2c6ab832
FB		 2756/* load/save state */
2757
2758static void cirrus_vga_save(QEMUFile *f, void *opaque)
2759{
2760 CirrusVGAState *s = opaque;
2761
2762 qemu_put_be32s(f, &s->latch);
2763 qemu_put_8s(f, &s->sr_index);
2764 qemu_put_buffer(f, s->sr, 256);
2765 qemu_put_8s(f, &s->gr_index);
2766 qemu_put_8s(f, &s->cirrus_shadow_gr0);
2767 qemu_put_8s(f, &s->cirrus_shadow_gr1);
2768 qemu_put_buffer(f, s->gr + 2, 254);
2769 qemu_put_8s(f, &s->ar_index);
2770 qemu_put_buffer(f, s->ar, 21);
2771 qemu_put_be32s(f, &s->ar_flip_flop);
2772 qemu_put_8s(f, &s->cr_index);
2773 qemu_put_buffer(f, s->cr, 256);
2774 qemu_put_8s(f, &s->msr);
2775 qemu_put_8s(f, &s->fcr);
2776 qemu_put_8s(f, &s->st00);
2777 qemu_put_8s(f, &s->st01);
2778
2779 qemu_put_8s(f, &s->dac_state);
2780 qemu_put_8s(f, &s->dac_sub_index);
2781 qemu_put_8s(f, &s->dac_read_index);
2782 qemu_put_8s(f, &s->dac_write_index);
2783 qemu_put_buffer(f, s->dac_cache, 3);
2784 qemu_put_buffer(f, s->palette, 768);
2785
2786 qemu_put_be32s(f, &s->bank_offset);
2787
2788 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
2789 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
2790
2791 qemu_put_be32s(f, &s->hw_cursor_x);
2792 qemu_put_be32s(f, &s->hw_cursor_y);
2793 /* XXX: we do not save the bitblt state - we assume we do not save
2794 the state when the blitter is active */
2795}
2796
2797static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
2798{
2799 CirrusVGAState *s = opaque;
2800
2801 if (version_id != 1)
2802 return -EINVAL;
2803
2804 qemu_get_be32s(f, &s->latch);
2805 qemu_get_8s(f, &s->sr_index);
2806 qemu_get_buffer(f, s->sr, 256);
2807 qemu_get_8s(f, &s->gr_index);
2808 qemu_get_8s(f, &s->cirrus_shadow_gr0);
2809 qemu_get_8s(f, &s->cirrus_shadow_gr1);
2810 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2811 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2812 qemu_get_buffer(f, s->gr + 2, 254);
2813 qemu_get_8s(f, &s->ar_index);
2814 qemu_get_buffer(f, s->ar, 21);
2815 qemu_get_be32s(f, &s->ar_flip_flop);
2816 qemu_get_8s(f, &s->cr_index);
2817 qemu_get_buffer(f, s->cr, 256);
2818 qemu_get_8s(f, &s->msr);
2819 qemu_get_8s(f, &s->fcr);
2820 qemu_get_8s(f, &s->st00);
2821 qemu_get_8s(f, &s->st01);
2822
2823 qemu_get_8s(f, &s->dac_state);
2824 qemu_get_8s(f, &s->dac_sub_index);
2825 qemu_get_8s(f, &s->dac_read_index);
2826 qemu_get_8s(f, &s->dac_write_index);
2827 qemu_get_buffer(f, s->dac_cache, 3);
2828 qemu_get_buffer(f, s->palette, 768);
2829
2830 qemu_get_be32s(f, &s->bank_offset);
2831
2832 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
2833 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
2834
2835 qemu_get_be32s(f, &s->hw_cursor_x);
2836 qemu_get_be32s(f, &s->hw_cursor_y);
2837
2838 /* force refresh */
2839 s->graphic_mode = -1;
2840 cirrus_update_bank_ptr(s, 0);
2841 cirrus_update_bank_ptr(s, 1);
2842 return 0;
2843}
2844
e6e5ad80
FB		 2845/***************************************
2846 *
2847 * initialize
2848 *
2849 ***************************************/
2850
78e127ef 2851static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
e6e5ad80 2852{
a5082316
FB		 2853 int vga_io_memory, i;
2854 static int inited;
2855
2856 if (!inited) {
2857 inited = 1;
2858 for(i = 0;i < 256; i++)
2859 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2860 rop_to_index[CIRRUS_ROP_0] = 0;
2861 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2862 rop_to_index[CIRRUS_ROP_NOP] = 2;
2863 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2864 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2865 rop_to_index[CIRRUS_ROP_SRC] = 5;
2866 rop_to_index[CIRRUS_ROP_1] = 6;
2867 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2868 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2869 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2870 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2871 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2872 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2873 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2874 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2875 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2876 }
e6e5ad80
FB		 2877
2878 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2879
2880 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2881 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2882 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2883 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2884
2885 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2886
2887 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2888 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2889 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2890 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2891
2892 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
2893 cirrus_vga_mem_write, s);
2894 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2895 vga_io_memory);
2896
2897 s->sr[0x06] = 0x0f;
78e127ef
FB		 2898 if (device_id == CIRRUS_ID_CLGD5446) {
2899 /* 4MB 64 bit memory config, always PCI */
b30d4608
FB		 2900 s->sr[0x1F] = 0x2d; // MemClock
2901 s->gr[0x18] = 0x0f; // fastest memory configuration
78e127ef
FB		 2902#if 1
2903 s->sr[0x0f] = 0x98;
2904 s->sr[0x17] = 0x20;
2905 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2906 s->real_vram_size = 4096 * 1024;
2907#else
2908 s->sr[0x0f] = 0x18;
2909 s->sr[0x17] = 0x20;
2910 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2911 s->real_vram_size = 2048 * 1024;
2912#endif
2913 } else {
b30d4608 2914 s->sr[0x1F] = 0x22; // MemClock
78e127ef
FB		 2915 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
2916 if (is_pci)
2917 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
2918 else
2919 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
2920 s->real_vram_size = 2048 * 1024;
2921 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2922 }
20ba3ae1 2923 s->cr[0x27] = device_id;
e6e5ad80 2924
78e127ef
FB		 2925 /* Win2K seems to assume that the pattern buffer is at 0xff
2926 initially ! */
2927 memset(s->vram_ptr, 0xff, s->real_vram_size);
2928
e6e5ad80
FB		 2929 s->cirrus_hidden_dac_lockindex = 5;
2930 s->cirrus_hidden_dac_data = 0;
2931
2932 /* I/O handler for LFB */
2933 s->cirrus_linear_io_addr =
2934 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
2935 s);
a5082316
FB		 2936 /* I/O handler for LFB */
2937 s->cirrus_linear_bitblt_io_addr =
2938 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
2939 s);
2940
e6e5ad80
FB		 2941 /* I/O handler for memory-mapped I/O */
2942 s->cirrus_mmio_io_addr =
2943 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
2944
2945 /* XXX: s->vram_size must be a power of two */
78e127ef
FB		 2946 s->cirrus_addr_mask = s->real_vram_size - 1;
2947 s->linear_mmio_mask = s->real_vram_size - 256;
e6e5ad80
FB		 2948
2949 s->get_bpp = cirrus_get_bpp;
2950 s->get_offsets = cirrus_get_offsets;
78e127ef 2951 s->get_resolution = cirrus_get_resolution;
a5082316
FB		 2952 s->cursor_invalidate = cirrus_cursor_invalidate;
2953 s->cursor_draw_line = cirrus_cursor_draw_line;
2c6ab832
FB		 2954
2955 register_savevm("cirrus_vga", 0, 1, cirrus_vga_save, cirrus_vga_load, s);
e6e5ad80
FB		 2956}
2957
2958/***************************************
2959 *
2960 * ISA bus support
2961 *
2962 ***************************************/
2963
2964void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2965 unsigned long vga_ram_offset, int vga_ram_size)
2966{
2967 CirrusVGAState *s;
2968
2969 s = qemu_mallocz(sizeof(CirrusVGAState));
2970
2971 vga_common_init((VGAState *)s,
2972 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 2973 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
e6e5ad80
FB		 2974 /* XXX ISA-LFB support */
2975}
2976
2977/***************************************
2978 *
2979 * PCI bus support
2980 *
2981 ***************************************/
2982
2983static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
2984 uint32_t addr, uint32_t size, int type)
2985{
2986 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
2987
a5082316 2988 /* XXX: add byte swapping apertures */
e6e5ad80
FB		 2989 cpu_register_physical_memory(addr, s->vram_size,
2990 s->cirrus_linear_io_addr);
a5082316
FB		 2991 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
2992 s->cirrus_linear_bitblt_io_addr);
e6e5ad80
FB		 2993}
2994
2995static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
2996 uint32_t addr, uint32_t size, int type)
2997{
2998 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
2999
3000 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3001 s->cirrus_mmio_io_addr);
3002}
3003
46e50e9d 3004void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
e6e5ad80
FB		 3005 unsigned long vga_ram_offset, int vga_ram_size)
3006{
3007 PCICirrusVGAState *d;
3008 uint8_t *pci_conf;
3009 CirrusVGAState *s;
20ba3ae1
FB		 3010 int device_id;
3011
3012 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 3013
3014 /* setup PCI configuration registers */
46e50e9d 3015 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
e6e5ad80 3016 sizeof(PCICirrusVGAState),
46e50e9d 3017 -1, NULL, NULL);
e6e5ad80
FB		 3018 pci_conf = d->dev.config;
3019 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3020 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
20ba3ae1
FB		 3021 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3022 pci_conf[0x03] = (uint8_t) (device_id >> 8);
e6e5ad80
FB		 3023 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3024 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3025 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3026 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3027
3028 /* setup VGA */
3029 s = &d->cirrus_vga;
3030 vga_common_init((VGAState *)s,
3031 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3032 cirrus_init_common(s, device_id, 1);
e6e5ad80
FB		 3033
3034 /* setup memory space */
3035 /* memory #0 LFB */
3036 /* memory #1 memory-mapped I/O */
3037 /* XXX: s->vram_size must be a power of two */
a5082316 3038 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
a21ae81d 3039 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 3040 if (device_id == CIRRUS_ID_CLGD5446) {
a21ae81d
FB		 3041 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3042 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3043 }
e6e5ad80
FB		 3044 /* XXX: ROM BIOS */
3045}
Qemu copy for testing