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Revert "vl: fix -hdachs/-hda argument order parsing issues"
[qemu.git] / hw / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b 29#include "hw.h"
87ecb68b 30#include "pci.h"
c1195d16 31#include "vga-pci.h"
87ecb68b 32#include "console.h"
e6e5ad80 33#include "vga_int.h"
5245d57a 34#include "loader.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
4a1e244e
GH		 46#define VGA_RAM_SIZE (8192 * 1024)
47
e6e5ad80
FB		 48/***************************************
49 *
50 * definitions
51 *
52 ***************************************/
53
e6e5ad80
FB		 54// ID
55#define CIRRUS_ID_CLGD5422 (0x23<<2)
56#define CIRRUS_ID_CLGD5426 (0x24<<2)
57#define CIRRUS_ID_CLGD5424 (0x25<<2)
58#define CIRRUS_ID_CLGD5428 (0x26<<2)
59#define CIRRUS_ID_CLGD5430 (0x28<<2)
60#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 61#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 62#define CIRRUS_ID_CLGD5446 (0x2E<<2)
63
64// sequencer 0x07
65#define CIRRUS_SR7_BPP_VGA 0x00
66#define CIRRUS_SR7_BPP_SVGA 0x01
67#define CIRRUS_SR7_BPP_MASK 0x0e
68#define CIRRUS_SR7_BPP_8 0x00
69#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70#define CIRRUS_SR7_BPP_24 0x04
71#define CIRRUS_SR7_BPP_16 0x06
72#define CIRRUS_SR7_BPP_32 0x08
73#define CIRRUS_SR7_ISAADDR_MASK 0xe0
74
75// sequencer 0x0f
76#define CIRRUS_MEMSIZE_512k 0x08
77#define CIRRUS_MEMSIZE_1M 0x10
78#define CIRRUS_MEMSIZE_2M 0x18
79#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
80
81// sequencer 0x12
82#define CIRRUS_CURSOR_SHOW 0x01
83#define CIRRUS_CURSOR_HIDDENPEL 0x02
84#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
85
86// sequencer 0x17
87#define CIRRUS_BUSTYPE_VLBFAST 0x10
88#define CIRRUS_BUSTYPE_PCI 0x20
89#define CIRRUS_BUSTYPE_VLBSLOW 0x30
90#define CIRRUS_BUSTYPE_ISA 0x38
91#define CIRRUS_MMIO_ENABLE 0x04
92#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
94
95// control 0x0b
96#define CIRRUS_BANKING_DUAL 0x01
97#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
98
99// control 0x30
100#define CIRRUS_BLTMODE_BACKWARDS 0x01
101#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105#define CIRRUS_BLTMODE_COLOREXPAND 0x80
106#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
111
112// control 0x31
113#define CIRRUS_BLT_BUSY 0x01
114#define CIRRUS_BLT_START 0x02
115#define CIRRUS_BLT_RESET 0x04
116#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 117#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 118
119// control 0x32
120#define CIRRUS_ROP_0 0x00
121#define CIRRUS_ROP_SRC_AND_DST 0x05
122#define CIRRUS_ROP_NOP 0x06
123#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124#define CIRRUS_ROP_NOTDST 0x0b
125#define CIRRUS_ROP_SRC 0x0d
126#define CIRRUS_ROP_1 0x0e
127#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128#define CIRRUS_ROP_SRC_XOR_DST 0x59
129#define CIRRUS_ROP_SRC_OR_DST 0x6d
130#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133#define CIRRUS_ROP_NOTSRC 0xd0
134#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136
a5082316
FB		 137#define CIRRUS_ROP_NOP_INDEX 2
138#define CIRRUS_ROP_SRC_INDEX 5
139
a21ae81d 140// control 0x33
a5082316 141#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 142#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 143#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 144
e6e5ad80
FB		 145// memory-mapped IO
146#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155#define CIRRUS_MMIO_BLTMODE 0x18 // byte
156#define CIRRUS_MMIO_BLTROP 0x1a // byte
157#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175
a21ae81d 176#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 177
b2eb849d
AJ		 178#define BLTUNSAFE(s) \
179 ( \
180 ( /* check dst is within bounds */ \
b2b183c2 181 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 182 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 183 (s)->vga.vram_size \
b2eb849d
AJ		 184 ) || \
185 ( /* check src is within bounds */ \
b2b183c2 186 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 187 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 188 (s)->vga.vram_size \
b2eb849d
AJ		 189 ) \
190 )
191
a5082316
FB		 192struct CirrusVGAState;
193typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
194 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 195 int dstpitch, int srcpitch,
196 int bltwidth, int bltheight);
a5082316
FB		 197typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
198 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 199
200typedef struct CirrusVGAState {
4e12cd94 201 VGACommonState vga;
e6e5ad80 202
b1950430
AK		 203 MemoryRegion cirrus_linear_io;
204 MemoryRegion cirrus_linear_bitblt_io;
205 MemoryRegion cirrus_mmio_io;
206 MemoryRegion pci_bar;
207 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
208 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
209 MemoryRegion low_mem; /* always mapped, overridden by: */
7969d9ed 210 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 211 uint32_t cirrus_addr_mask;
78e127ef 212 uint32_t linear_mmio_mask;
e6e5ad80
FB		 213 uint8_t cirrus_shadow_gr0;
214 uint8_t cirrus_shadow_gr1;
215 uint8_t cirrus_hidden_dac_lockindex;
216 uint8_t cirrus_hidden_dac_data;
217 uint32_t cirrus_bank_base[2];
218 uint32_t cirrus_bank_limit[2];
219 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 220 uint32_t hw_cursor_x;
221 uint32_t hw_cursor_y;
e6e5ad80
FB		 222 int cirrus_blt_pixelwidth;
223 int cirrus_blt_width;
224 int cirrus_blt_height;
225 int cirrus_blt_dstpitch;
226 int cirrus_blt_srcpitch;
a5082316
FB		 227 uint32_t cirrus_blt_fgcol;
228 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 229 uint32_t cirrus_blt_dstaddr;
230 uint32_t cirrus_blt_srcaddr;
231 uint8_t cirrus_blt_mode;
a5082316 232 uint8_t cirrus_blt_modeext;
e6e5ad80 233 cirrus_bitblt_rop_t cirrus_rop;
a5082316 234#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 235 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
236 uint8_t *cirrus_srcptr;
237 uint8_t *cirrus_srcptr_end;
238 uint32_t cirrus_srccounter;
a5082316
FB		 239 /* hwcursor display state */
240 int last_hw_cursor_size;
241 int last_hw_cursor_x;
242 int last_hw_cursor_y;
243 int last_hw_cursor_y_start;
244 int last_hw_cursor_y_end;
78e127ef 245 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 246 int device_id;
247 int bustype;
e6e5ad80
FB		 248} CirrusVGAState;
249
250typedef struct PCICirrusVGAState {
251 PCIDevice dev;
252 CirrusVGAState cirrus_vga;
253} PCICirrusVGAState;
254
3d402831
BS		 255typedef struct ISACirrusVGAState {
256 ISADevice dev;
257 CirrusVGAState cirrus_vga;
258} ISACirrusVGAState;
259
a5082316 260static uint8_t rop_to_index[256];
3b46e624 261
e6e5ad80
FB		 262/***************************************
263 *
264 * prototypes.
265 *
266 ***************************************/
267
268
8926b517
FB		 269static void cirrus_bitblt_reset(CirrusVGAState *s);
270static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 271
272/***************************************
273 *
274 * raster operations
275 *
276 ***************************************/
277
a5082316
FB		 278static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
279 uint8_t *dst,const uint8_t *src,
280 int dstpitch,int srcpitch,
281 int bltwidth,int bltheight)
282{
e6e5ad80
FB		 283}
284
a5082316
FB		 285static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
286 uint8_t *dst,
287 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 288{
a5082316 289}
e6e5ad80 290
a5082316 291#define ROP_NAME 0
8c78881f 292#define ROP_FN(d, s) 0
a5082316 293#include "cirrus_vga_rop.h"
e6e5ad80 294
a5082316 295#define ROP_NAME src_and_dst
8c78881f 296#define ROP_FN(d, s) (s) & (d)
a5082316 297#include "cirrus_vga_rop.h"
e6e5ad80 298
a5082316 299#define ROP_NAME src_and_notdst
8c78881f 300#define ROP_FN(d, s) (s) & (~(d))
a5082316 301#include "cirrus_vga_rop.h"
e6e5ad80 302
a5082316 303#define ROP_NAME notdst
8c78881f 304#define ROP_FN(d, s) ~(d)
a5082316 305#include "cirrus_vga_rop.h"
e6e5ad80 306
a5082316 307#define ROP_NAME src
8c78881f 308#define ROP_FN(d, s) s
a5082316 309#include "cirrus_vga_rop.h"
e6e5ad80 310
a5082316 311#define ROP_NAME 1
8c78881f 312#define ROP_FN(d, s) ~0
a5082316
FB		 313#include "cirrus_vga_rop.h"
314
315#define ROP_NAME notsrc_and_dst
8c78881f 316#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 317#include "cirrus_vga_rop.h"
318
319#define ROP_NAME src_xor_dst
8c78881f 320#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 321#include "cirrus_vga_rop.h"
322
323#define ROP_NAME src_or_dst
8c78881f 324#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 325#include "cirrus_vga_rop.h"
326
327#define ROP_NAME notsrc_or_notdst
8c78881f 328#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 329#include "cirrus_vga_rop.h"
330
331#define ROP_NAME src_notxor_dst
8c78881f 332#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 333#include "cirrus_vga_rop.h"
e6e5ad80 334
a5082316 335#define ROP_NAME src_or_notdst
8c78881f 336#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 337#include "cirrus_vga_rop.h"
338
339#define ROP_NAME notsrc
8c78881f 340#define ROP_FN(d, s) (~(s))
a5082316
FB		 341#include "cirrus_vga_rop.h"
342
343#define ROP_NAME notsrc_or_dst
8c78881f 344#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 345#include "cirrus_vga_rop.h"
346
347#define ROP_NAME notsrc_and_notdst
8c78881f 348#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 349#include "cirrus_vga_rop.h"
350
351static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
352 cirrus_bitblt_rop_fwd_0,
353 cirrus_bitblt_rop_fwd_src_and_dst,
354 cirrus_bitblt_rop_nop,
355 cirrus_bitblt_rop_fwd_src_and_notdst,
356 cirrus_bitblt_rop_fwd_notdst,
357 cirrus_bitblt_rop_fwd_src,
358 cirrus_bitblt_rop_fwd_1,
359 cirrus_bitblt_rop_fwd_notsrc_and_dst,
360 cirrus_bitblt_rop_fwd_src_xor_dst,
361 cirrus_bitblt_rop_fwd_src_or_dst,
362 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
363 cirrus_bitblt_rop_fwd_src_notxor_dst,
364 cirrus_bitblt_rop_fwd_src_or_notdst,
365 cirrus_bitblt_rop_fwd_notsrc,
366 cirrus_bitblt_rop_fwd_notsrc_or_dst,
367 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
368};
369
370static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
371 cirrus_bitblt_rop_bkwd_0,
372 cirrus_bitblt_rop_bkwd_src_and_dst,
373 cirrus_bitblt_rop_nop,
374 cirrus_bitblt_rop_bkwd_src_and_notdst,
375 cirrus_bitblt_rop_bkwd_notdst,
376 cirrus_bitblt_rop_bkwd_src,
377 cirrus_bitblt_rop_bkwd_1,
378 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
379 cirrus_bitblt_rop_bkwd_src_xor_dst,
380 cirrus_bitblt_rop_bkwd_src_or_dst,
381 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
382 cirrus_bitblt_rop_bkwd_src_notxor_dst,
383 cirrus_bitblt_rop_bkwd_src_or_notdst,
384 cirrus_bitblt_rop_bkwd_notsrc,
385 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
386 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
387};
96cf2df8
TS		 388
389#define TRANSP_ROP(name) {\
390 name ## _8,\
391 name ## _16,\
392 }
393#define TRANSP_NOP(func) {\
394 func,\
395 func,\
396 }
397
398static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
401 TRANSP_NOP(cirrus_bitblt_rop_nop),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
413 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
414 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
415};
416
417static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
420 TRANSP_NOP(cirrus_bitblt_rop_nop),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
432 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
433 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
434};
435
a5082316
FB		 436#define ROP2(name) {\
437 name ## _8,\
438 name ## _16,\
439 name ## _24,\
440 name ## _32,\
441 }
442
443#define ROP_NOP2(func) {\
444 func,\
445 func,\
446 func,\
447 func,\
448 }
449
e69390ce
FB		 450static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
451 ROP2(cirrus_patternfill_0),
452 ROP2(cirrus_patternfill_src_and_dst),
453 ROP_NOP2(cirrus_bitblt_rop_nop),
454 ROP2(cirrus_patternfill_src_and_notdst),
455 ROP2(cirrus_patternfill_notdst),
456 ROP2(cirrus_patternfill_src),
457 ROP2(cirrus_patternfill_1),
458 ROP2(cirrus_patternfill_notsrc_and_dst),
459 ROP2(cirrus_patternfill_src_xor_dst),
460 ROP2(cirrus_patternfill_src_or_dst),
461 ROP2(cirrus_patternfill_notsrc_or_notdst),
462 ROP2(cirrus_patternfill_src_notxor_dst),
463 ROP2(cirrus_patternfill_src_or_notdst),
464 ROP2(cirrus_patternfill_notsrc),
465 ROP2(cirrus_patternfill_notsrc_or_dst),
466 ROP2(cirrus_patternfill_notsrc_and_notdst),
467};
468
a5082316
FB		 469static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
470 ROP2(cirrus_colorexpand_transp_0),
471 ROP2(cirrus_colorexpand_transp_src_and_dst),
472 ROP_NOP2(cirrus_bitblt_rop_nop),
473 ROP2(cirrus_colorexpand_transp_src_and_notdst),
474 ROP2(cirrus_colorexpand_transp_notdst),
475 ROP2(cirrus_colorexpand_transp_src),
476 ROP2(cirrus_colorexpand_transp_1),
477 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
478 ROP2(cirrus_colorexpand_transp_src_xor_dst),
479 ROP2(cirrus_colorexpand_transp_src_or_dst),
480 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
481 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
482 ROP2(cirrus_colorexpand_transp_src_or_notdst),
483 ROP2(cirrus_colorexpand_transp_notsrc),
484 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
485 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
486};
487
488static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
489 ROP2(cirrus_colorexpand_0),
490 ROP2(cirrus_colorexpand_src_and_dst),
491 ROP_NOP2(cirrus_bitblt_rop_nop),
492 ROP2(cirrus_colorexpand_src_and_notdst),
493 ROP2(cirrus_colorexpand_notdst),
494 ROP2(cirrus_colorexpand_src),
495 ROP2(cirrus_colorexpand_1),
496 ROP2(cirrus_colorexpand_notsrc_and_dst),
497 ROP2(cirrus_colorexpand_src_xor_dst),
498 ROP2(cirrus_colorexpand_src_or_dst),
499 ROP2(cirrus_colorexpand_notsrc_or_notdst),
500 ROP2(cirrus_colorexpand_src_notxor_dst),
501 ROP2(cirrus_colorexpand_src_or_notdst),
502 ROP2(cirrus_colorexpand_notsrc),
503 ROP2(cirrus_colorexpand_notsrc_or_dst),
504 ROP2(cirrus_colorexpand_notsrc_and_notdst),
505};
506
b30d4608
FB		 507static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
508 ROP2(cirrus_colorexpand_pattern_transp_0),
509 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
510 ROP_NOP2(cirrus_bitblt_rop_nop),
511 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
512 ROP2(cirrus_colorexpand_pattern_transp_notdst),
513 ROP2(cirrus_colorexpand_pattern_transp_src),
514 ROP2(cirrus_colorexpand_pattern_transp_1),
515 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
517 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
518 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
519 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
520 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
521 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
522 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
523 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
524};
525
526static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
527 ROP2(cirrus_colorexpand_pattern_0),
528 ROP2(cirrus_colorexpand_pattern_src_and_dst),
529 ROP_NOP2(cirrus_bitblt_rop_nop),
530 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
531 ROP2(cirrus_colorexpand_pattern_notdst),
532 ROP2(cirrus_colorexpand_pattern_src),
533 ROP2(cirrus_colorexpand_pattern_1),
534 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
535 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
536 ROP2(cirrus_colorexpand_pattern_src_or_dst),
537 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
538 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
539 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
540 ROP2(cirrus_colorexpand_pattern_notsrc),
541 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
542 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
543};
544
a5082316
FB		 545static const cirrus_fill_t cirrus_fill[16][4] = {
546 ROP2(cirrus_fill_0),
547 ROP2(cirrus_fill_src_and_dst),
548 ROP_NOP2(cirrus_bitblt_fill_nop),
549 ROP2(cirrus_fill_src_and_notdst),
550 ROP2(cirrus_fill_notdst),
551 ROP2(cirrus_fill_src),
552 ROP2(cirrus_fill_1),
553 ROP2(cirrus_fill_notsrc_and_dst),
554 ROP2(cirrus_fill_src_xor_dst),
555 ROP2(cirrus_fill_src_or_dst),
556 ROP2(cirrus_fill_notsrc_or_notdst),
557 ROP2(cirrus_fill_src_notxor_dst),
558 ROP2(cirrus_fill_src_or_notdst),
559 ROP2(cirrus_fill_notsrc),
560 ROP2(cirrus_fill_notsrc_or_dst),
561 ROP2(cirrus_fill_notsrc_and_notdst),
562};
563
564static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 565{
a5082316
FB		 566 unsigned int color;
567 switch (s->cirrus_blt_pixelwidth) {
568 case 1:
569 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
570 break;
571 case 2:
4e12cd94 572 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 573 s->cirrus_blt_fgcol = le16_to_cpu(color);
574 break;
575 case 3:
5fafdf24 576 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 577 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 578 break;
579 default:
580 case 4:
4e12cd94
AK		 581 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
582 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 583 s->cirrus_blt_fgcol = le32_to_cpu(color);
584 break;
e6e5ad80
FB		 585 }
586}
587
a5082316 588static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 589{
a5082316 590 unsigned int color;
e6e5ad80
FB		 591 switch (s->cirrus_blt_pixelwidth) {
592 case 1:
a5082316
FB		 593 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
594 break;
e6e5ad80 595 case 2:
4e12cd94 596 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 597 s->cirrus_blt_bgcol = le16_to_cpu(color);
598 break;
e6e5ad80 599 case 3:
5fafdf24 600 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 601 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 602 break;
e6e5ad80 603 default:
a5082316 604 case 4:
4e12cd94
AK		 605 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
606 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 607 s->cirrus_blt_bgcol = le32_to_cpu(color);
608 break;
e6e5ad80
FB		 609 }
610}
611
612static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
613 int off_pitch, int bytesperline,
614 int lines)
615{
616 int y;
617 int off_cur;
618 int off_cur_end;
619
620 for (y = 0; y < lines; y++) {
621 off_cur = off_begin;
b2eb849d 622 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
fd4aa979 623 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e6e5ad80
FB		 624 off_begin += off_pitch;
625 }
626}
627
e6e5ad80
FB		 628static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
629 const uint8_t * src)
630{
e6e5ad80 631 uint8_t *dst;
e6e5ad80 632
4e12cd94 633 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 634
635 if (BLTUNSAFE(s))
636 return 0;
637
e69390ce 638 (*s->cirrus_rop) (s, dst, src,
5fafdf24 639 s->cirrus_blt_dstpitch, 0,
e69390ce 640 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 641 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 642 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
643 s->cirrus_blt_height);
e6e5ad80
FB		 644 return 1;
645}
646
a21ae81d
FB		 647/* fill */
648
a5082316 649static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 650{
a5082316 651 cirrus_fill_t rop_func;
a21ae81d 652
b2eb849d
AJ		 653 if (BLTUNSAFE(s))
654 return 0;
a5082316 655 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 656 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 657 s->cirrus_blt_dstpitch,
658 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 659 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
660 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
661 s->cirrus_blt_height);
662 cirrus_bitblt_reset(s);
663 return 1;
664}
665
e6e5ad80
FB		 666/***************************************
667 *
668 * bitblt (video-to-video)
669 *
670 ***************************************/
671
672static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
673{
674 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 675 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 676 s->cirrus_addr_mask));
e6e5ad80
FB		 677}
678
24236869 679static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 680{
78935c4a
AJ		 681 int sx = 0, sy = 0;
682 int dx = 0, dy = 0;
683 int depth = 0;
24236869
FB		 684 int notify = 0;
685
92d675d1
AJ		 686 /* make sure to only copy if it's a plain copy ROP */
687 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
688 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 689
92d675d1
AJ		 690 int width, height;
691
692 depth = s->vga.get_bpp(&s->vga) / 8;
693 s->vga.get_resolution(&s->vga, &width, &height);
694
695 /* extra x, y */
696 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
697 sy = (src / ABS(s->cirrus_blt_srcpitch));
698 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
699 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 700
92d675d1
AJ		 701 /* normalize width */
702 w /= depth;
24236869 703
92d675d1
AJ		 704 /* if we're doing a backward copy, we have to adjust
705 our x/y to be the upper left corner (instead of the lower
706 right corner) */
707 if (s->cirrus_blt_dstpitch < 0) {
708 sx -= (s->cirrus_blt_width / depth) - 1;
709 dx -= (s->cirrus_blt_width / depth) - 1;
710 sy -= s->cirrus_blt_height - 1;
711 dy -= s->cirrus_blt_height - 1;
712 }
713
714 /* are we in the visible portion of memory? */
715 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
716 (sx + w) <= width && (sy + h) <= height &&
717 (dx + w) <= width && (dy + h) <= height) {
718 notify = 1;
719 }
720 }
24236869
FB		 721
722 /* we have to flush all pending changes so that the copy
723 is generated at the appropriate moment in time */
724 if (notify)
725 vga_hw_update();
726
4e12cd94 727 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 728 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 729 s->vga.vram_ptr +
b2eb849d 730 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 731 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
732 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 733
734 if (notify)
4e12cd94 735 qemu_console_copy(s->vga.ds,
38334f76
AZ		 736 sx, sy, dx, dy,
737 s->cirrus_blt_width / depth,
738 s->cirrus_blt_height);
24236869
FB		 739
740 /* we don't have to notify the display that this portion has
38334f76 741 changed since qemu_console_copy implies this */
24236869 742
31c05501
AL		 743 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
744 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
745 s->cirrus_blt_height);
24236869
FB		 746}
747
748static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
749{
65d35a09
AJ		 750 if (BLTUNSAFE(s))
751 return 0;
752
4e12cd94
AK		 753 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
754 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 755 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 756
e6e5ad80
FB		 757 return 1;
758}
759
760/***************************************
761 *
762 * bitblt (cpu-to-video)
763 *
764 ***************************************/
765
e6e5ad80
FB		 766static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
767{
768 int copy_count;
a5082316 769 uint8_t *end_ptr;
3b46e624 770
e6e5ad80 771 if (s->cirrus_srccounter > 0) {
a5082316
FB		 772 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
773 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
774 the_end:
775 s->cirrus_srccounter = 0;
776 cirrus_bitblt_reset(s);
777 } else {
778 /* at least one scan line */
779 do {
4e12cd94 780 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 781 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
782 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 783 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
784 s->cirrus_blt_width, 1);
785 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
786 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
787 if (s->cirrus_srccounter <= 0)
788 goto the_end;
66a0a2cb 789 /* more bytes than needed can be transferred because of
a5082316
FB		 790 word alignment, so we keep them for the next line */
791 /* XXX: keep alignment to speed up transfer */
792 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
793 copy_count = s->cirrus_srcptr_end - end_ptr;
794 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
795 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
796 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
797 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
798 }
e6e5ad80
FB		 799 }
800}
801
802/***************************************
803 *
804 * bitblt wrapper
805 *
806 ***************************************/
807
808static void cirrus_bitblt_reset(CirrusVGAState * s)
809{
f8b237af
AL		 810 int need_update;
811
4e12cd94 812 s->vga.gr[0x31] &=
e6e5ad80 813 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 814 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
815 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 816 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
817 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
818 s->cirrus_srccounter = 0;
f8b237af
AL		 819 if (!need_update)
820 return;
8926b517 821 cirrus_update_memory_access(s);
e6e5ad80
FB		 822}
823
824static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
825{
a5082316
FB		 826 int w;
827
e6e5ad80
FB		 828 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
829 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
830 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
831
832 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
833 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 834 s->cirrus_blt_srcpitch = 8;
e6e5ad80 835 } else {
b30d4608 836 /* XXX: check for 24 bpp */
a5082316 837 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 838 }
a5082316 839 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 840 } else {
841 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 842 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 843 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 844 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
845 else
846 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 847 } else {
c9c0eae8
FB		 848 /* always align input size to 32 bits */
849 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 850 }
a5082316 851 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 852 }
a5082316
FB		 853 s->cirrus_srcptr = s->cirrus_bltbuf;
854 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 855 cirrus_update_memory_access(s);
e6e5ad80
FB		 856 return 1;
857}
858
859static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
860{
861 /* XXX */
a5082316 862#ifdef DEBUG_BITBLT
e6e5ad80
FB		 863 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
864#endif
865 return 0;
866}
867
868static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
869{
870 int ret;
871
872 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
873 ret = cirrus_bitblt_videotovideo_patterncopy(s);
874 } else {
875 ret = cirrus_bitblt_videotovideo_copy(s);
876 }
e6e5ad80
FB		 877 if (ret)
878 cirrus_bitblt_reset(s);
879 return ret;
880}
881
882static void cirrus_bitblt_start(CirrusVGAState * s)
883{
884 uint8_t blt_rop;
885
4e12cd94 886 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 887
4e12cd94
AK		 888 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
889 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
890 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
891 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 892 s->cirrus_blt_dstaddr =
4e12cd94 893 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 894 s->cirrus_blt_srcaddr =
4e12cd94
AK		 895 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
896 s->cirrus_blt_mode = s->vga.gr[0x30];
897 s->cirrus_blt_modeext = s->vga.gr[0x33];
898 blt_rop = s->vga.gr[0x32];
e6e5ad80 899
a21ae81d 900#ifdef DEBUG_BITBLT
0b74ed78 901 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 902 blt_rop,
a21ae81d 903 s->cirrus_blt_mode,
a5082316 904 s->cirrus_blt_modeext,
a21ae81d
FB		 905 s->cirrus_blt_width,
906 s->cirrus_blt_height,
907 s->cirrus_blt_dstpitch,
908 s->cirrus_blt_srcpitch,
909 s->cirrus_blt_dstaddr,
a5082316 910 s->cirrus_blt_srcaddr,
4e12cd94 911 s->vga.gr[0x2f]);
a21ae81d
FB		 912#endif
913
e6e5ad80
FB		 914 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
915 case CIRRUS_BLTMODE_PIXELWIDTH8:
916 s->cirrus_blt_pixelwidth = 1;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH16:
919 s->cirrus_blt_pixelwidth = 2;
920 break;
921 case CIRRUS_BLTMODE_PIXELWIDTH24:
922 s->cirrus_blt_pixelwidth = 3;
923 break;
924 case CIRRUS_BLTMODE_PIXELWIDTH32:
925 s->cirrus_blt_pixelwidth = 4;
926 break;
927 default:
a5082316 928#ifdef DEBUG_BITBLT
e6e5ad80
FB		 929 printf("cirrus: bitblt - pixel width is unknown\n");
930#endif
931 goto bitblt_ignore;
932 }
933 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
934
935 if ((s->
936 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
937 CIRRUS_BLTMODE_MEMSYSDEST))
938 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 939#ifdef DEBUG_BITBLT
e6e5ad80
FB		 940 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
941#endif
942 goto bitblt_ignore;
943 }
944
a5082316 945 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 946 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 947 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 948 CIRRUS_BLTMODE_PATTERNCOPY |
949 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 950 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 951 cirrus_bitblt_fgcol(s);
952 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 953 } else {
5fafdf24
TS		 954 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
955 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 956 CIRRUS_BLTMODE_COLOREXPAND) {
957
958 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 959 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 960 cirrus_bitblt_bgcol(s);
b30d4608 961 else
4c8732d7 962 cirrus_bitblt_fgcol(s);
b30d4608 963 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 964 } else {
965 cirrus_bitblt_fgcol(s);
966 cirrus_bitblt_bgcol(s);
967 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
968 }
e69390ce 969 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 970 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
971 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
972 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
973 cirrus_bitblt_bgcol(s);
974 else
975 cirrus_bitblt_fgcol(s);
976 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
977 } else {
978 cirrus_bitblt_fgcol(s);
979 cirrus_bitblt_bgcol(s);
980 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
981 }
982 } else {
983 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
984 }
a21ae81d 985 } else {
96cf2df8
TS		 986 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
987 if (s->cirrus_blt_pixelwidth > 2) {
988 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
989 goto bitblt_ignore;
990 }
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
992 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
993 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
994 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
995 } else {
996 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997 }
998 } else {
999 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1000 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1001 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1002 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1003 } else {
1004 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1005 }
1006 }
1007 }
a21ae81d
FB		 1008 // setup bitblt engine.
1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1010 if (!cirrus_bitblt_cputovideo(s))
1011 goto bitblt_ignore;
1012 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1013 if (!cirrus_bitblt_videotocpu(s))
1014 goto bitblt_ignore;
1015 } else {
1016 if (!cirrus_bitblt_videotovideo(s))
1017 goto bitblt_ignore;
1018 }
e6e5ad80 1019 }
e6e5ad80
FB		 1020 return;
1021 bitblt_ignore:;
1022 cirrus_bitblt_reset(s);
1023}
1024
1025static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1026{
1027 unsigned old_value;
1028
4e12cd94
AK		 1029 old_value = s->vga.gr[0x31];
1030 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1031
1032 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1033 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1034 cirrus_bitblt_reset(s);
1035 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1036 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1037 cirrus_bitblt_start(s);
1038 }
1039}
1040
1041
1042/***************************************
1043 *
1044 * basic parameters
1045 *
1046 ***************************************/
1047
a4a2f59c 1048static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1049 uint32_t *pline_offset,
1050 uint32_t *pstart_addr,
1051 uint32_t *pline_compare)
e6e5ad80 1052{
4e12cd94 1053 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1054 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1055
4e12cd94
AK		 1056 line_offset = s->vga.cr[0x13]
1057 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1058 line_offset <<= 3;
1059 *pline_offset = line_offset;
1060
4e12cd94
AK		 1061 start_addr = (s->vga.cr[0x0c] << 8)
1062 | s->vga.cr[0x0d]
1063 | ((s->vga.cr[0x1b] & 0x01) << 16)
1064 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1065 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1066 *pstart_addr = start_addr;
83acc96b 1067
4e12cd94
AK		 1068 line_compare = s->vga.cr[0x18] |
1069 ((s->vga.cr[0x07] & 0x10) << 4) |
1070 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1071 *pline_compare = line_compare;
e6e5ad80
FB		 1072}
1073
1074static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1075{
1076 uint32_t ret = 16;
1077
1078 switch (s->cirrus_hidden_dac_data & 0xf) {
1079 case 0:
1080 ret = 15;
1081 break; /* Sierra HiColor */
1082 case 1:
1083 ret = 16;
1084 break; /* XGA HiColor */
1085 default:
1086#ifdef DEBUG_CIRRUS
1087 printf("cirrus: invalid DAC value %x in 16bpp\n",
1088 (s->cirrus_hidden_dac_data & 0xf));
1089#endif
1090 ret = 15; /* XXX */
1091 break;
1092 }
1093 return ret;
1094}
1095
a4a2f59c 1096static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1097{
4e12cd94 1098 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1099 uint32_t ret = 8;
1100
4e12cd94 1101 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1102 /* Cirrus SVGA */
4e12cd94 1103 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1104 case CIRRUS_SR7_BPP_8:
1105 ret = 8;
1106 break;
1107 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1108 ret = cirrus_get_bpp16_depth(s);
1109 break;
1110 case CIRRUS_SR7_BPP_24:
1111 ret = 24;
1112 break;
1113 case CIRRUS_SR7_BPP_16:
1114 ret = cirrus_get_bpp16_depth(s);
1115 break;
1116 case CIRRUS_SR7_BPP_32:
1117 ret = 32;
1118 break;
1119 default:
1120#ifdef DEBUG_CIRRUS
4e12cd94 1121 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1122#endif
1123 ret = 8;
1124 break;
1125 }
1126 } else {
1127 /* VGA */
aeb3c85f 1128 ret = 0;
e6e5ad80
FB		 1129 }
1130
1131 return ret;
1132}
1133
a4a2f59c 1134static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1135{
1136 int width, height;
3b46e624 1137
78e127ef 1138 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1139 height = s->cr[0x12] |
1140 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1141 ((s->cr[0x07] & 0x40) << 3);
1142 height = (height + 1);
1143 /* interlace support */
1144 if (s->cr[0x1a] & 0x01)
1145 height = height * 2;
1146 *pwidth = width;
1147 *pheight = height;
1148}
1149
e6e5ad80
FB		 1150/***************************************
1151 *
1152 * bank memory
1153 *
1154 ***************************************/
1155
1156static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1157{
1158 unsigned offset;
1159 unsigned limit;
1160
4e12cd94
AK		 1161 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1162 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1163 else /* single bank */
4e12cd94 1164 offset = s->vga.gr[0x09];
e6e5ad80 1165
4e12cd94 1166 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1167 offset <<= 14;
1168 else
1169 offset <<= 12;
1170
e3a4e4b6 1171 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1172 limit = 0;
1173 else
e3a4e4b6 1174 limit = s->real_vram_size - offset;
e6e5ad80 1175
4e12cd94 1176 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1177 if (limit > 0x8000) {
1178 offset += 0x8000;
1179 limit -= 0x8000;
1180 } else {
1181 limit = 0;
1182 }
1183 }
1184
1185 if (limit > 0) {
1186 s->cirrus_bank_base[bank_index] = offset;
1187 s->cirrus_bank_limit[bank_index] = limit;
1188 } else {
1189 s->cirrus_bank_base[bank_index] = 0;
1190 s->cirrus_bank_limit[bank_index] = 0;
1191 }
1192}
1193
1194/***************************************
1195 *
1196 * I/O access between 0x3c4-0x3c5
1197 *
1198 ***************************************/
1199
8a82c322 1200static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1201{
8a82c322 1202 switch (s->vga.sr_index) {
e6e5ad80
FB		 1203 case 0x00: // Standard VGA
1204 case 0x01: // Standard VGA
1205 case 0x02: // Standard VGA
1206 case 0x03: // Standard VGA
1207 case 0x04: // Standard VGA
8a82c322 1208 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1209 case 0x06: // Unlock Cirrus extensions
8a82c322 1210 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1211 case 0x10:
1212 case 0x30:
1213 case 0x50:
1214 case 0x70: // Graphics Cursor X
1215 case 0x90:
1216 case 0xb0:
1217 case 0xd0:
1218 case 0xf0: // Graphics Cursor X
8a82c322 1219 return s->vga.sr[0x10];
e6e5ad80
FB		 1220 case 0x11:
1221 case 0x31:
1222 case 0x51:
1223 case 0x71: // Graphics Cursor Y
1224 case 0x91:
1225 case 0xb1:
1226 case 0xd1:
a5082316 1227 case 0xf1: // Graphics Cursor Y
8a82c322 1228 return s->vga.sr[0x11];
aeb3c85f
FB		 1229 case 0x05: // ???
1230 case 0x07: // Extended Sequencer Mode
1231 case 0x08: // EEPROM Control
1232 case 0x09: // Scratch Register 0
1233 case 0x0a: // Scratch Register 1
1234 case 0x0b: // VCLK 0
1235 case 0x0c: // VCLK 1
1236 case 0x0d: // VCLK 2
1237 case 0x0e: // VCLK 3
1238 case 0x0f: // DRAM Control
e6e5ad80
FB		 1239 case 0x12: // Graphics Cursor Attribute
1240 case 0x13: // Graphics Cursor Pattern Address
1241 case 0x14: // Scratch Register 2
1242 case 0x15: // Scratch Register 3
1243 case 0x16: // Performance Tuning Register
1244 case 0x17: // Configuration Readback and Extended Control
1245 case 0x18: // Signature Generator Control
1246 case 0x19: // Signal Generator Result
1247 case 0x1a: // Signal Generator Result
1248 case 0x1b: // VCLK 0 Denominator & Post
1249 case 0x1c: // VCLK 1 Denominator & Post
1250 case 0x1d: // VCLK 2 Denominator & Post
1251 case 0x1e: // VCLK 3 Denominator & Post
1252 case 0x1f: // BIOS Write Enable and MCLK select
1253#ifdef DEBUG_CIRRUS
8a82c322 1254 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1255#endif
8a82c322 1256 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1257 default:
1258#ifdef DEBUG_CIRRUS
8a82c322 1259 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1260#endif
8a82c322 1261 return 0xff;
e6e5ad80
FB		 1262 break;
1263 }
e6e5ad80
FB		 1264}
1265
31c63201 1266static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1267{
31c63201 1268 switch (s->vga.sr_index) {
e6e5ad80
FB		 1269 case 0x00: // Standard VGA
1270 case 0x01: // Standard VGA
1271 case 0x02: // Standard VGA
1272 case 0x03: // Standard VGA
1273 case 0x04: // Standard VGA
31c63201
JQ		 1274 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1275 if (s->vga.sr_index == 1)
1276 s->vga.update_retrace_info(&s->vga);
1277 break;
e6e5ad80 1278 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1279 val &= 0x17;
1280 if (val == 0x12) {
1281 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1282 } else {
31c63201 1283 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1284 }
1285 break;
1286 case 0x10:
1287 case 0x30:
1288 case 0x50:
1289 case 0x70: // Graphics Cursor X
1290 case 0x90:
1291 case 0xb0:
1292 case 0xd0:
1293 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1294 s->vga.sr[0x10] = val;
1295 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1296 break;
1297 case 0x11:
1298 case 0x31:
1299 case 0x51:
1300 case 0x71: // Graphics Cursor Y
1301 case 0x91:
1302 case 0xb1:
1303 case 0xd1:
1304 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1305 s->vga.sr[0x11] = val;
1306 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1307 break;
1308 case 0x07: // Extended Sequencer Mode
2bec46dc 1309 cirrus_update_memory_access(s);
e6e5ad80
FB		 1310 case 0x08: // EEPROM Control
1311 case 0x09: // Scratch Register 0
1312 case 0x0a: // Scratch Register 1
1313 case 0x0b: // VCLK 0
1314 case 0x0c: // VCLK 1
1315 case 0x0d: // VCLK 2
1316 case 0x0e: // VCLK 3
1317 case 0x0f: // DRAM Control
1318 case 0x12: // Graphics Cursor Attribute
1319 case 0x13: // Graphics Cursor Pattern Address
1320 case 0x14: // Scratch Register 2
1321 case 0x15: // Scratch Register 3
1322 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1323 case 0x18: // Signature Generator Control
1324 case 0x19: // Signature Generator Result
1325 case 0x1a: // Signature Generator Result
1326 case 0x1b: // VCLK 0 Denominator & Post
1327 case 0x1c: // VCLK 1 Denominator & Post
1328 case 0x1d: // VCLK 2 Denominator & Post
1329 case 0x1e: // VCLK 3 Denominator & Post
1330 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1331 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1332#ifdef DEBUG_CIRRUS
1333 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1334 s->vga.sr_index, val);
e6e5ad80
FB		 1335#endif
1336 break;
8926b517 1337 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1338 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1339 | (val & 0xc7);
8926b517
FB		 1340 cirrus_update_memory_access(s);
1341 break;
e6e5ad80
FB		 1342 default:
1343#ifdef DEBUG_CIRRUS
31c63201
JQ		 1344 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1345 s->vga.sr_index, val);
e6e5ad80
FB		 1346#endif
1347 break;
1348 }
e6e5ad80
FB		 1349}
1350
1351/***************************************
1352 *
1353 * I/O access at 0x3c6
1354 *
1355 ***************************************/
1356
957c9db5 1357static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1358{
a21ae81d 1359 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1360 s->cirrus_hidden_dac_lockindex = 0;
1361 return s->cirrus_hidden_dac_data;
e6e5ad80 1362 }
957c9db5 1363 return 0xff;
e6e5ad80
FB		 1364}
1365
1366static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1367{
1368 if (s->cirrus_hidden_dac_lockindex == 4) {
1369 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1370#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1371 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1372#endif
1373 }
1374 s->cirrus_hidden_dac_lockindex = 0;
1375}
1376
1377/***************************************
1378 *
1379 * I/O access at 0x3c9
1380 *
1381 ***************************************/
1382
5deaeee3 1383static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1384{
5deaeee3
JQ		 1385 int val;
1386
1387 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1388 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1389 s->vga.dac_sub_index];
1390 } else {
1391 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1392 }
4e12cd94
AK		 1393 if (++s->vga.dac_sub_index == 3) {
1394 s->vga.dac_sub_index = 0;
1395 s->vga.dac_read_index++;
e6e5ad80 1396 }
5deaeee3 1397 return val;
e6e5ad80
FB		 1398}
1399
86948bb1 1400static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1401{
4e12cd94
AK		 1402 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1403 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1404 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1405 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1406 s->vga.dac_cache, 3);
1407 } else {
1408 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1409 }
a5082316 1410 /* XXX update cursor */
4e12cd94
AK		 1411 s->vga.dac_sub_index = 0;
1412 s->vga.dac_write_index++;
e6e5ad80 1413 }
e6e5ad80
FB		 1414}
1415
1416/***************************************
1417 *
1418 * I/O access between 0x3ce-0x3cf
1419 *
1420 ***************************************/
1421
f705db9d 1422static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1423{
1424 switch (reg_index) {
aeb3c85f 1425 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1426 return s->cirrus_shadow_gr0;
aeb3c85f 1427 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1428 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1429 case 0x02: // Standard VGA
1430 case 0x03: // Standard VGA
1431 case 0x04: // Standard VGA
1432 case 0x06: // Standard VGA
1433 case 0x07: // Standard VGA
1434 case 0x08: // Standard VGA
f705db9d 1435 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1436 case 0x05: // Standard VGA, Cirrus extended mode
1437 default:
1438 break;
1439 }
1440
1441 if (reg_index < 0x3a) {
f705db9d 1442 return s->vga.gr[reg_index];
e6e5ad80
FB		 1443 } else {
1444#ifdef DEBUG_CIRRUS
1445 printf("cirrus: inport gr_index %02x\n", reg_index);
1446#endif
f705db9d 1447 return 0xff;
e6e5ad80 1448 }
e6e5ad80
FB		 1449}
1450
22286bc6
JQ		 1451static void
1452cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1453{
a5082316
FB		 1454#if defined(DEBUG_BITBLT) && 0
1455 printf("gr%02x: %02x\n", reg_index, reg_value);
1456#endif
e6e5ad80
FB		 1457 switch (reg_index) {
1458 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1459 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1460 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1461 break;
e6e5ad80 1462 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1463 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1464 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1465 break;
e6e5ad80
FB		 1466 case 0x02: // Standard VGA
1467 case 0x03: // Standard VGA
1468 case 0x04: // Standard VGA
1469 case 0x06: // Standard VGA
1470 case 0x07: // Standard VGA
1471 case 0x08: // Standard VGA
22286bc6
JQ		 1472 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1473 break;
e6e5ad80 1474 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1475 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1476 cirrus_update_memory_access(s);
e6e5ad80
FB		 1477 break;
1478 case 0x09: // bank offset #0
1479 case 0x0A: // bank offset #1
4e12cd94 1480 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1481 cirrus_update_bank_ptr(s, 0);
1482 cirrus_update_bank_ptr(s, 1);
2bec46dc 1483 cirrus_update_memory_access(s);
8926b517 1484 break;
e6e5ad80 1485 case 0x0B:
4e12cd94 1486 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1487 cirrus_update_bank_ptr(s, 0);
1488 cirrus_update_bank_ptr(s, 1);
8926b517 1489 cirrus_update_memory_access(s);
e6e5ad80
FB		 1490 break;
1491 case 0x10: // BGCOLOR 0x0000ff00
1492 case 0x11: // FGCOLOR 0x0000ff00
1493 case 0x12: // BGCOLOR 0x00ff0000
1494 case 0x13: // FGCOLOR 0x00ff0000
1495 case 0x14: // BGCOLOR 0xff000000
1496 case 0x15: // FGCOLOR 0xff000000
1497 case 0x20: // BLT WIDTH 0x0000ff
1498 case 0x22: // BLT HEIGHT 0x0000ff
1499 case 0x24: // BLT DEST PITCH 0x0000ff
1500 case 0x26: // BLT SRC PITCH 0x0000ff
1501 case 0x28: // BLT DEST ADDR 0x0000ff
1502 case 0x29: // BLT DEST ADDR 0x00ff00
1503 case 0x2c: // BLT SRC ADDR 0x0000ff
1504 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1505 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1506 case 0x30: // BLT MODE
1507 case 0x32: // RASTER OP
a21ae81d 1508 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1509 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1510 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1511 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1512 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1513 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1514 break;
1515 case 0x21: // BLT WIDTH 0x001f00
1516 case 0x23: // BLT HEIGHT 0x001f00
1517 case 0x25: // BLT DEST PITCH 0x001f00
1518 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1520 break;
1521 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1522 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1523 /* if auto start mode, starts bit blt now */
4e12cd94 1524 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1525 cirrus_bitblt_start(s);
1526 }
1527 break;
e6e5ad80 1528 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1529 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1530 break;
1531 case 0x31: // BLT STATUS/START
1532 cirrus_write_bitblt(s, reg_value);
1533 break;
1534 default:
1535#ifdef DEBUG_CIRRUS
1536 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1537 reg_value);
1538#endif
1539 break;
1540 }
e6e5ad80
FB		 1541}
1542
1543/***************************************
1544 *
1545 * I/O access between 0x3d4-0x3d5
1546 *
1547 ***************************************/
1548
b863d514 1549static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1550{
1551 switch (reg_index) {
1552 case 0x00: // Standard VGA
1553 case 0x01: // Standard VGA
1554 case 0x02: // Standard VGA
1555 case 0x03: // Standard VGA
1556 case 0x04: // Standard VGA
1557 case 0x05: // Standard VGA
1558 case 0x06: // Standard VGA
1559 case 0x07: // Standard VGA
1560 case 0x08: // Standard VGA
1561 case 0x09: // Standard VGA
1562 case 0x0a: // Standard VGA
1563 case 0x0b: // Standard VGA
1564 case 0x0c: // Standard VGA
1565 case 0x0d: // Standard VGA
1566 case 0x0e: // Standard VGA
1567 case 0x0f: // Standard VGA
1568 case 0x10: // Standard VGA
1569 case 0x11: // Standard VGA
1570 case 0x12: // Standard VGA
1571 case 0x13: // Standard VGA
1572 case 0x14: // Standard VGA
1573 case 0x15: // Standard VGA
1574 case 0x16: // Standard VGA
1575 case 0x17: // Standard VGA
1576 case 0x18: // Standard VGA
b863d514 1577 return s->vga.cr[s->vga.cr_index];
ca896ef3 1578 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1579 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1580 case 0x19: // Interlace End
1581 case 0x1a: // Miscellaneous Control
1582 case 0x1b: // Extended Display Control
1583 case 0x1c: // Sync Adjust and Genlock
1584 case 0x1d: // Overlay Extended Control
1585 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1586 case 0x25: // Part Status
1587 case 0x27: // Part ID (R)
b863d514 1588 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1589 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1590 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1591 break;
1592 default:
1593#ifdef DEBUG_CIRRUS
1594 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1595#endif
b863d514 1596 return 0xff;
e6e5ad80 1597 }
e6e5ad80
FB		 1598}
1599
4ec1ce04 1600static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1601{
4ec1ce04 1602 switch (s->vga.cr_index) {
e6e5ad80
FB		 1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
4ec1ce04
JQ		 1628 /* handle CR0-7 protection */
1629 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1630 /* can always write bit 4 of CR7 */
1631 if (s->vga.cr_index == 7)
1632 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1633 return;
1634 }
1635 s->vga.cr[s->vga.cr_index] = reg_value;
1636 switch(s->vga.cr_index) {
1637 case 0x00:
1638 case 0x04:
1639 case 0x05:
1640 case 0x06:
1641 case 0x07:
1642 case 0x11:
1643 case 0x17:
1644 s->vga.update_retrace_info(&s->vga);
1645 break;
1646 }
1647 break;
e6e5ad80
FB		 1648 case 0x19: // Interlace End
1649 case 0x1a: // Miscellaneous Control
1650 case 0x1b: // Extended Display Control
1651 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1652 case 0x1d: // Overlay Extended Control
4ec1ce04 1653 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1654#ifdef DEBUG_CIRRUS
1655 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1656 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1657#endif
1658 break;
1659 case 0x22: // Graphics Data Latches Readback (R)
1660 case 0x24: // Attribute Controller Toggle Readback (R)
1661 case 0x26: // Attribute Controller Index Readback (R)
1662 case 0x27: // Part ID (R)
1663 break;
e6e5ad80
FB		 1664 case 0x25: // Part Status
1665 default:
1666#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1667 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1668 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1669#endif
1670 break;
1671 }
e6e5ad80
FB		 1672}
1673
1674/***************************************
1675 *
1676 * memory-mapped I/O (bitblt)
1677 *
1678 ***************************************/
1679
1680static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1681{
1682 int value = 0xff;
1683
1684 switch (address) {
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1747 break;
1748 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTMODE:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1756 break;
1757 case CIRRUS_MMIO_BLTROP:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1759 break;
a21ae81d 1760 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1762 break;
e6e5ad80 1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1771 break;
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1774 break;
1775 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1776 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1777 break;
1778 default:
1779#ifdef DEBUG_CIRRUS
1780 printf("cirrus: mmio read - address 0x%04x\n", address);
1781#endif
1782 break;
1783 }
1784
1785 return (uint8_t) value;
1786}
1787
1788static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1789 uint8_t value)
1790{
1791 switch (address) {
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1793 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1796 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1799 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1802 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1805 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1808 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1811 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1814 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1817 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1820 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1823 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1826 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1829 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1832 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1835 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1838 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1841 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1844 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1847 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1848 break;
1849 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1850 /* ignored */
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1857 break;
1858 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1859 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1862 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTMODE:
22286bc6 1865 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1866 break;
1867 case CIRRUS_MMIO_BLTROP:
22286bc6 1868 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1869 break;
a21ae81d 1870 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1871 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1872 break;
e6e5ad80 1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1874 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1877 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1880 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1881 break;
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1883 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1884 break;
1885 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1886 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1887 break;
1888 default:
1889#ifdef DEBUG_CIRRUS
1890 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1891 address, value);
1892#endif
1893 break;
1894 }
1895}
1896
e6e5ad80
FB		 1897/***************************************
1898 *
1899 * write mode 4/5
1900 *
e6e5ad80
FB		 1901 ***************************************/
1902
1903static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1904 unsigned mode,
1905 unsigned offset,
1906 uint32_t mem_value)
1907{
1908 int x;
1909 unsigned val = mem_value;
1910 uint8_t *dst;
1911
4e12cd94 1912 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1913 for (x = 0; x < 8; x++) {
1914 if (val & 0x80) {
0b74ed78 1915 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1916 } else if (mode == 5) {
0b74ed78 1917 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1918 }
1919 val <<= 1;
0b74ed78 1920 dst++;
e6e5ad80 1921 }
fd4aa979 1922 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1923}
1924
1925static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1926 unsigned mode,
1927 unsigned offset,
1928 uint32_t mem_value)
1929{
1930 int x;
1931 unsigned val = mem_value;
1932 uint8_t *dst;
1933
4e12cd94 1934 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1935 for (x = 0; x < 8; x++) {
1936 if (val & 0x80) {
0b74ed78 1937 *dst = s->cirrus_shadow_gr1;
4e12cd94 1938 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1939 } else if (mode == 5) {
0b74ed78 1940 *dst = s->cirrus_shadow_gr0;
4e12cd94 1941 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1942 }
1943 val <<= 1;
0b74ed78 1944 dst += 2;
e6e5ad80 1945 }
fd4aa979 1946 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1947}
1948
1949/***************************************
1950 *
1951 * memory access between 0xa0000-0xbffff
1952 *
1953 ***************************************/
1954
a815b166
AK		 1955static uint64_t cirrus_vga_mem_read(void *opaque,
1956 target_phys_addr_t addr,
1957 uint32_t size)
e6e5ad80
FB		 1958{
1959 CirrusVGAState *s = opaque;
1960 unsigned bank_index;
1961 unsigned bank_offset;
1962 uint32_t val;
1963
4e12cd94 1964 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1965 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1966 }
1967
1968 if (addr < 0x10000) {
1969 /* XXX handle bitblt */
1970 /* video memory */
1971 bank_index = addr >> 15;
1972 bank_offset = addr & 0x7fff;
1973 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1974 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1975 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1976 bank_offset <<= 4;
4e12cd94 1977 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1978 bank_offset <<= 3;
1979 }
1980 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1981 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1982 } else
1983 val = 0xff;
1984 } else if (addr >= 0x18000 && addr < 0x18100) {
1985 /* memory-mapped I/O */
1986 val = 0xff;
4e12cd94 1987 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1988 val = cirrus_mmio_blt_read(s, addr & 0xff);
1989 }
1990 } else {
1991 val = 0xff;
1992#ifdef DEBUG_CIRRUS
0bf9e31a 1993 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1994#endif
1995 }
1996 return val;
1997}
1998
a815b166
AK		 1999static void cirrus_vga_mem_write(void *opaque,
2000 target_phys_addr_t addr,
2001 uint64_t mem_value,
2002 uint32_t size)
e6e5ad80
FB		 2003{
2004 CirrusVGAState *s = opaque;
2005 unsigned bank_index;
2006 unsigned bank_offset;
2007 unsigned mode;
2008
4e12cd94 2009 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2010 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2011 return;
2012 }
2013
2014 if (addr < 0x10000) {
2015 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2016 /* bitblt */
2017 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2018 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2019 cirrus_bitblt_cputovideo_next(s);
2020 }
2021 } else {
2022 /* video memory */
2023 bank_index = addr >> 15;
2024 bank_offset = addr & 0x7fff;
2025 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2026 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2027 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2028 bank_offset <<= 4;
4e12cd94 2029 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2030 bank_offset <<= 3;
2031 }
2032 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2033 mode = s->vga.gr[0x05] & 0x7;
2034 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2035 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2036 memory_region_set_dirty(&s->vga.vram, bank_offset,
2037 sizeof(mem_value));
e6e5ad80 2038 } else {
4e12cd94 2039 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2040 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2041 bank_offset,
2042 mem_value);
2043 } else {
2044 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2045 bank_offset,
2046 mem_value);
2047 }
2048 }
2049 }
2050 }
2051 } else if (addr >= 0x18000 && addr < 0x18100) {
2052 /* memory-mapped I/O */
4e12cd94 2053 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2054 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2055 }
2056 } else {
2057#ifdef DEBUG_CIRRUS
145c7c88
MO		 2058 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %" PRIx64 "\n",
2059 addr, mem_value);
e6e5ad80
FB		 2060#endif
2061 }
2062}
2063
b1950430
AK		 2064static const MemoryRegionOps cirrus_vga_mem_ops = {
2065 .read = cirrus_vga_mem_read,
2066 .write = cirrus_vga_mem_write,
2067 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2068 .impl = {
2069 .min_access_size = 1,
2070 .max_access_size = 1,
2071 },
e6e5ad80
FB		 2072};
2073
a5082316
FB		 2074/***************************************
2075 *
2076 * hardware cursor
2077 *
2078 ***************************************/
2079
2080static inline void invalidate_cursor1(CirrusVGAState *s)
2081{
2082 if (s->last_hw_cursor_size) {
4e12cd94 2083 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2084 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2085 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2086 }
2087}
2088
2089static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2090{
2091 const uint8_t *src;
2092 uint32_t content;
2093 int y, y_min, y_max;
2094
4e12cd94
AK		 2095 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2096 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2097 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2098 y_min = 64;
2099 y_max = -1;
2100 for(y = 0; y < 64; y++) {
2101 content = ((uint32_t *)src)[0] |
2102 ((uint32_t *)src)[1] |
2103 ((uint32_t *)src)[2] |
2104 ((uint32_t *)src)[3];
2105 if (content) {
2106 if (y < y_min)
2107 y_min = y;
2108 if (y > y_max)
2109 y_max = y;
2110 }
2111 src += 16;
2112 }
2113 } else {
4e12cd94 2114 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2115 y_min = 32;
2116 y_max = -1;
2117 for(y = 0; y < 32; y++) {
2118 content = ((uint32_t *)src)[0] |
2119 ((uint32_t *)(src + 128))[0];
2120 if (content) {
2121 if (y < y_min)
2122 y_min = y;
2123 if (y > y_max)
2124 y_max = y;
2125 }
2126 src += 4;
2127 }
2128 }
2129 if (y_min > y_max) {
2130 s->last_hw_cursor_y_start = 0;
2131 s->last_hw_cursor_y_end = 0;
2132 } else {
2133 s->last_hw_cursor_y_start = y_min;
2134 s->last_hw_cursor_y_end = y_max + 1;
2135 }
2136}
2137
2138/* NOTE: we do not currently handle the cursor bitmap change, so we
2139 update the cursor only if it moves. */
a4a2f59c 2140static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2141{
4e12cd94 2142 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2143 int size;
2144
4e12cd94 2145 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2146 size = 0;
2147 } else {
4e12cd94 2148 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2149 size = 64;
2150 else
2151 size = 32;
2152 }
2153 /* invalidate last cursor and new cursor if any change */
2154 if (s->last_hw_cursor_size != size ||
2155 s->last_hw_cursor_x != s->hw_cursor_x ||
2156 s->last_hw_cursor_y != s->hw_cursor_y) {
2157
2158 invalidate_cursor1(s);
3b46e624 2159
a5082316
FB		 2160 s->last_hw_cursor_size = size;
2161 s->last_hw_cursor_x = s->hw_cursor_x;
2162 s->last_hw_cursor_y = s->hw_cursor_y;
2163 /* compute the real cursor min and max y */
2164 cirrus_cursor_compute_yrange(s);
2165 invalidate_cursor1(s);
2166 }
2167}
2168
94d7b483
BS		 2169#define DEPTH 8
2170#include "cirrus_vga_template.h"
2171
2172#define DEPTH 16
2173#include "cirrus_vga_template.h"
2174
2175#define DEPTH 32
2176#include "cirrus_vga_template.h"
2177
a4a2f59c 2178static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2179{
4e12cd94 2180 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2181 int w, h, bpp, x1, x2, poffset;
2182 unsigned int color0, color1;
2183 const uint8_t *palette, *src;
2184 uint32_t content;
3b46e624 2185
4e12cd94 2186 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2187 return;
2188 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2189 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2190 h = 64;
2191 } else {
2192 h = 32;
2193 }
2194 if (scr_y < s->hw_cursor_y ||
2195 scr_y >= (s->hw_cursor_y + h))
2196 return;
3b46e624 2197
4e12cd94
AK		 2198 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2199 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2200 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2201 src += (scr_y - s->hw_cursor_y) * 16;
2202 poffset = 8;
2203 content = ((uint32_t *)src)[0] |
2204 ((uint32_t *)src)[1] |
2205 ((uint32_t *)src)[2] |
2206 ((uint32_t *)src)[3];
2207 } else {
4e12cd94 2208 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2209 src += (scr_y - s->hw_cursor_y) * 4;
2210 poffset = 128;
2211 content = ((uint32_t *)src)[0] |
2212 ((uint32_t *)(src + 128))[0];
2213 }
2214 /* if nothing to draw, no need to continue */
2215 if (!content)
2216 return;
2217 w = h;
2218
2219 x1 = s->hw_cursor_x;
4e12cd94 2220 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2221 return;
2222 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2223 if (x2 > s->vga.last_scr_width)
2224 x2 = s->vga.last_scr_width;
a5082316
FB		 2225 w = x2 - x1;
2226 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2227 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2228 c6_to_8(palette[0x0 * 3 + 1]),
2229 c6_to_8(palette[0x0 * 3 + 2]));
2230 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2231 c6_to_8(palette[0xf * 3 + 1]),
2232 c6_to_8(palette[0xf * 3 + 2]));
2233 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2234 d1 += x1 * bpp;
4e12cd94 2235 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2236 default:
2237 break;
2238 case 8:
2239 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2240 break;
2241 case 15:
2242 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2243 break;
2244 case 16:
2245 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2246 break;
2247 case 32:
2248 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2249 break;
2250 }
2251}
2252
e6e5ad80
FB		 2253/***************************************
2254 *
2255 * LFB memory access
2256 *
2257 ***************************************/
2258
899adf81
AK		 2259static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
2260 unsigned size)
e6e5ad80 2261{
e05587e8 2262 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2263 uint32_t ret;
2264
e6e5ad80
FB		 2265 addr &= s->cirrus_addr_mask;
2266
4e12cd94 2267 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2268 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2269 /* memory-mapped I/O */
2270 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2271 } else if (0) {
2272 /* XXX handle bitblt */
2273 ret = 0xff;
2274 } else {
2275 /* video memory */
4e12cd94 2276 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2277 addr <<= 4;
4e12cd94 2278 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2279 addr <<= 3;
2280 }
2281 addr &= s->cirrus_addr_mask;
4e12cd94 2282 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2283 }
2284
2285 return ret;
2286}
2287
899adf81
AK		 2288static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
2289 uint64_t val, unsigned size)
e6e5ad80 2290{
e05587e8 2291 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2292 unsigned mode;
2293
2294 addr &= s->cirrus_addr_mask;
3b46e624 2295
4e12cd94 2296 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2297 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2298 /* memory-mapped I/O */
2299 cirrus_mmio_blt_write(s, addr & 0xff, val);
2300 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2301 /* bitblt */
2302 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2303 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2304 cirrus_bitblt_cputovideo_next(s);
2305 }
2306 } else {
2307 /* video memory */
4e12cd94 2308 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2309 addr <<= 4;
4e12cd94 2310 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2311 addr <<= 3;
2312 }
2313 addr &= s->cirrus_addr_mask;
2314
4e12cd94
AK		 2315 mode = s->vga.gr[0x05] & 0x7;
2316 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2317 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2318 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2319 } else {
4e12cd94 2320 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2321 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2322 } else {
2323 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2324 }
2325 }
2326 }
2327}
2328
a5082316
FB		 2329/***************************************
2330 *
2331 * system to screen memory access
2332 *
2333 ***************************************/
2334
2335
4e56f089
AK		 2336static uint64_t cirrus_linear_bitblt_read(void *opaque,
2337 target_phys_addr_t addr,
2338 unsigned size)
a5082316 2339{
4e56f089 2340 CirrusVGAState *s = opaque;
a5082316
FB		 2341 uint32_t ret;
2342
2343 /* XXX handle bitblt */
4e56f089 2344 (void)s;
a5082316
FB		 2345 ret = 0xff;
2346 return ret;
2347}
2348
4e56f089
AK		 2349static void cirrus_linear_bitblt_write(void *opaque,
2350 target_phys_addr_t addr,
2351 uint64_t val,
2352 unsigned size)
a5082316 2353{
e05587e8 2354 CirrusVGAState *s = opaque;
a5082316
FB		 2355
2356 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2357 /* bitblt */
2358 *s->cirrus_srcptr++ = (uint8_t) val;
2359 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2360 cirrus_bitblt_cputovideo_next(s);
2361 }
2362 }
2363}
2364
b1950430
AK		 2365static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2366 .read = cirrus_linear_bitblt_read,
2367 .write = cirrus_linear_bitblt_write,
2368 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2369 .impl = {
2370 .min_access_size = 1,
2371 .max_access_size = 1,
2372 },
a5082316
FB		 2373};
2374
b1950430
AK		 2375static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2376{
7969d9ed
AK		 2377 MemoryRegion *mr = &s->cirrus_bank[bank];
2378 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2379 && !((s->vga.sr[0x07] & 0x01) == 0)
2380 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2381 && !(s->vga.gr[0x0B] & 0x02);
2382
2383 memory_region_set_enabled(mr, enabled);
2384 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2385}
2bec46dc 2386
b1950430
AK		 2387static void map_linear_vram(CirrusVGAState *s)
2388{
4c08fd1e 2389 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2390 s->linear_vram = true;
2391 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2392 }
2393 map_linear_vram_bank(s, 0);
2394 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2395}
2396
2397static void unmap_linear_vram(CirrusVGAState *s)
2398{
4c08fd1e 2399 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2400 s->linear_vram = false;
2401 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2402 }
7969d9ed
AK		 2403 memory_region_set_enabled(&s->cirrus_bank[0], false);
2404 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2405}
2406
8926b517
FB		 2407/* Compute the memory access functions */
2408static void cirrus_update_memory_access(CirrusVGAState *s)
2409{
2410 unsigned mode;
2411
64c048f4 2412 memory_region_transaction_begin();
4e12cd94 2413 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2414 goto generic_io;
2415 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2416 goto generic_io;
2417 } else {
4e12cd94 2418 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2419 goto generic_io;
4e12cd94 2420 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2421 goto generic_io;
2422 }
3b46e624 2423
4e12cd94
AK		 2424 mode = s->vga.gr[0x05] & 0x7;
2425 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2426 map_linear_vram(s);
8926b517
FB		 2427 } else {
2428 generic_io:
2bec46dc 2429 unmap_linear_vram(s);
8926b517
FB		 2430 }
2431 }
64c048f4 2432 memory_region_transaction_commit();
8926b517
FB		 2433}
2434
2435
e6e5ad80
FB		 2436/* I/O ports */
2437
0ceac75b 2438static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2439{
b6343073
JQ		 2440 CirrusVGAState *c = opaque;
2441 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2442 int val, index;
2443
b6343073 2444 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2445 val = 0xff;
2446 } else {
2447 switch (addr) {
2448 case 0x3c0:
b6343073
JQ		 2449 if (s->ar_flip_flop == 0) {
2450 val = s->ar_index;
e6e5ad80
FB		 2451 } else {
2452 val = 0;
2453 }
2454 break;
2455 case 0x3c1:
b6343073 2456 index = s->ar_index & 0x1f;
e6e5ad80 2457 if (index < 21)
b6343073 2458 val = s->ar[index];
e6e5ad80
FB		 2459 else
2460 val = 0;
2461 break;
2462 case 0x3c2:
b6343073 2463 val = s->st00;
e6e5ad80
FB		 2464 break;
2465 case 0x3c4:
b6343073 2466 val = s->sr_index;
e6e5ad80
FB		 2467 break;
2468 case 0x3c5:
8a82c322
JQ		 2469 val = cirrus_vga_read_sr(c);
2470 break;
e6e5ad80 2471#ifdef DEBUG_VGA_REG
b6343073 2472 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2473#endif
2474 break;
2475 case 0x3c6:
957c9db5 2476 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2477 break;
2478 case 0x3c7:
b6343073 2479 val = s->dac_state;
e6e5ad80 2480 break;
ae184e4a 2481 case 0x3c8:
b6343073
JQ		 2482 val = s->dac_write_index;
2483 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2484 break;
2485 case 0x3c9:
5deaeee3
JQ		 2486 val = cirrus_vga_read_palette(c);
2487 break;
e6e5ad80 2488 case 0x3ca:
b6343073 2489 val = s->fcr;
e6e5ad80
FB		 2490 break;
2491 case 0x3cc:
b6343073 2492 val = s->msr;
e6e5ad80
FB		 2493 break;
2494 case 0x3ce:
b6343073 2495 val = s->gr_index;
e6e5ad80
FB		 2496 break;
2497 case 0x3cf:
f705db9d 2498 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2499#ifdef DEBUG_VGA_REG
b6343073 2500 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2501#endif
2502 break;
2503 case 0x3b4:
2504 case 0x3d4:
b6343073 2505 val = s->cr_index;
e6e5ad80
FB		 2506 break;
2507 case 0x3b5:
2508 case 0x3d5:
b863d514 2509 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2510#ifdef DEBUG_VGA_REG
b6343073 2511 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2512#endif
2513 break;
2514 case 0x3ba:
2515 case 0x3da:
2516 /* just toggle to fool polling */
b6343073
JQ		 2517 val = s->st01 = s->retrace(s);
2518 s->ar_flip_flop = 0;
e6e5ad80
FB		 2519 break;
2520 default:
2521 val = 0x00;
2522 break;
2523 }
2524 }
2525#if defined(DEBUG_VGA)
2526 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2527#endif
2528 return val;
2529}
2530
0ceac75b 2531static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2532{
b6343073
JQ		 2533 CirrusVGAState *c = opaque;
2534 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2535 int index;
2536
2537 /* check port range access depending on color/monochrome mode */
b6343073 2538 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2539 return;
25a18cbd 2540 }
e6e5ad80
FB		 2541#ifdef DEBUG_VGA
2542 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2543#endif
2544
2545 switch (addr) {
2546 case 0x3c0:
b6343073 2547 if (s->ar_flip_flop == 0) {
e6e5ad80 2548 val &= 0x3f;
b6343073 2549 s->ar_index = val;
e6e5ad80 2550 } else {
b6343073 2551 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2552 switch (index) {
2553 case 0x00 ... 0x0f:
b6343073 2554 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2555 break;
2556 case 0x10:
b6343073 2557 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2558 break;
2559 case 0x11:
b6343073 2560 s->ar[index] = val;
e6e5ad80
FB		 2561 break;
2562 case 0x12:
b6343073 2563 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2564 break;
2565 case 0x13:
b6343073 2566 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2567 break;
2568 case 0x14:
b6343073 2569 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2570 break;
2571 default:
2572 break;
2573 }
2574 }
b6343073 2575 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2576 break;
2577 case 0x3c2:
b6343073
JQ		 2578 s->msr = val & ~0x10;
2579 s->update_retrace_info(s);
e6e5ad80
FB		 2580 break;
2581 case 0x3c4:
b6343073 2582 s->sr_index = val;
e6e5ad80
FB		 2583 break;
2584 case 0x3c5:
e6e5ad80 2585#ifdef DEBUG_VGA_REG
b6343073 2586 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2587#endif
31c63201
JQ		 2588 cirrus_vga_write_sr(c, val);
2589 break;
e6e5ad80
FB		 2590 break;
2591 case 0x3c6:
b6343073 2592 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2593 break;
2594 case 0x3c7:
b6343073
JQ		 2595 s->dac_read_index = val;
2596 s->dac_sub_index = 0;
2597 s->dac_state = 3;
e6e5ad80
FB		 2598 break;
2599 case 0x3c8:
b6343073
JQ		 2600 s->dac_write_index = val;
2601 s->dac_sub_index = 0;
2602 s->dac_state = 0;
e6e5ad80
FB		 2603 break;
2604 case 0x3c9:
86948bb1
JQ		 2605 cirrus_vga_write_palette(c, val);
2606 break;
e6e5ad80 2607 case 0x3ce:
b6343073 2608 s->gr_index = val;
e6e5ad80
FB		 2609 break;
2610 case 0x3cf:
e6e5ad80 2611#ifdef DEBUG_VGA_REG
b6343073 2612 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2613#endif
22286bc6 2614 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2615 break;
2616 case 0x3b4:
2617 case 0x3d4:
b6343073 2618 s->cr_index = val;
e6e5ad80
FB		 2619 break;
2620 case 0x3b5:
2621 case 0x3d5:
e6e5ad80 2622#ifdef DEBUG_VGA_REG
b6343073 2623 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2624#endif
4ec1ce04 2625 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2626 break;
2627 case 0x3ba:
2628 case 0x3da:
b6343073 2629 s->fcr = val & 0x10;
e6e5ad80
FB		 2630 break;
2631 }
2632}
2633
e36f36e1
FB		 2634/***************************************
2635 *
2636 * memory-mapped I/O access
2637 *
2638 ***************************************/
2639
1e04d4d6
AK		 2640static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
2641 unsigned size)
e36f36e1 2642{
e05587e8 2643 CirrusVGAState *s = opaque;
e36f36e1 2644
e36f36e1
FB		 2645 if (addr >= 0x100) {
2646 return cirrus_mmio_blt_read(s, addr - 0x100);
2647 } else {
0ceac75b 2648 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2649 }
2650}
2651
1e04d4d6
AK		 2652static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
2653 uint64_t val, unsigned size)
e36f36e1 2654{
e05587e8 2655 CirrusVGAState *s = opaque;
e36f36e1 2656
e36f36e1
FB		 2657 if (addr >= 0x100) {
2658 cirrus_mmio_blt_write(s, addr - 0x100, val);
2659 } else {
0ceac75b 2660 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2661 }
2662}
2663
b1950430
AK		 2664static const MemoryRegionOps cirrus_mmio_io_ops = {
2665 .read = cirrus_mmio_read,
2666 .write = cirrus_mmio_write,
2667 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2668 .impl = {
2669 .min_access_size = 1,
2670 .max_access_size = 1,
2671 },
e36f36e1
FB		 2672};
2673
2c6ab832
FB		 2674/* load/save state */
2675
e59fb374 2676static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2677{
2678 CirrusVGAState *s = opaque;
2679
4e12cd94
AK		 2680 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2681 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2682
2bec46dc 2683 cirrus_update_memory_access(s);
2c6ab832 2684 /* force refresh */
4e12cd94 2685 s->vga.graphic_mode = -1;
2c6ab832
FB		 2686 cirrus_update_bank_ptr(s, 0);
2687 cirrus_update_bank_ptr(s, 1);
2688 return 0;
2689}
2690
7e72abc3
JQ		 2691static const VMStateDescription vmstate_cirrus_vga = {
2692 .name = "cirrus_vga",
2693 .version_id = 2,
2694 .minimum_version_id = 1,
2695 .minimum_version_id_old = 1,
2696 .post_load = cirrus_post_load,
2697 .fields = (VMStateField []) {
2698 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2699 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2700 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2701 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2702 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2703 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2704 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2705 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2706 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2707 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2708 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2709 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2710 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2711 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2712 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2713 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2714 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2715 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2716 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2717 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2718 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2719 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2720 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2721 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2722 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2723 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2724 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2725 /* XXX: we do not save the bitblt state - we assume we do not save
2726 the state when the blitter is active */
2727 VMSTATE_END_OF_LIST()
4f335feb 2728 }
7e72abc3 2729};
4f335feb 2730
7e72abc3
JQ		 2731static const VMStateDescription vmstate_pci_cirrus_vga = {
2732 .name = "cirrus_vga",
2733 .version_id = 2,
2734 .minimum_version_id = 2,
2735 .minimum_version_id_old = 2,
7e72abc3
JQ		 2736 .fields = (VMStateField []) {
2737 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2738 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2739 vmstate_cirrus_vga, CirrusVGAState),
2740 VMSTATE_END_OF_LIST()
2741 }
2742};
4f335feb 2743
e6e5ad80
FB		 2744/***************************************
2745 *
2746 * initialize
2747 *
2748 ***************************************/
2749
4abc796d 2750static void cirrus_reset(void *opaque)
e6e5ad80 2751{
4abc796d 2752 CirrusVGAState *s = opaque;
e6e5ad80 2753
03a3e7ba 2754 vga_common_reset(&s->vga);
ee50c6bc 2755 unmap_linear_vram(s);
4e12cd94 2756 s->vga.sr[0x06] = 0x0f;
4abc796d 2757 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2758 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2759 s->vga.sr[0x1F] = 0x2d; // MemClock
2760 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2761 s->vga.sr[0x0f] = 0x98;
2762 s->vga.sr[0x17] = 0x20;
2763 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2764 } else {
4e12cd94
AK		 2765 s->vga.sr[0x1F] = 0x22; // MemClock
2766 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2767 s->vga.sr[0x17] = s->bustype;
2768 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2769 }
4e12cd94 2770 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2771
2772 s->cirrus_hidden_dac_lockindex = 5;
2773 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2774}
2775
b1950430
AK		 2776static const MemoryRegionOps cirrus_linear_io_ops = {
2777 .read = cirrus_linear_read,
2778 .write = cirrus_linear_write,
2779 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2780 .impl = {
2781 .min_access_size = 1,
2782 .max_access_size = 1,
2783 },
b1950430
AK		 2784};
2785
be20f9e9
AK		 2786static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
2787 MemoryRegion *system_memory)
4abc796d
BS		 2788{
2789 int i;
2790 static int inited;
2791
2792 if (!inited) {
2793 inited = 1;
2794 for(i = 0;i < 256; i++)
2795 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2796 rop_to_index[CIRRUS_ROP_0] = 0;
2797 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2798 rop_to_index[CIRRUS_ROP_NOP] = 2;
2799 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2800 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2801 rop_to_index[CIRRUS_ROP_SRC] = 5;
2802 rop_to_index[CIRRUS_ROP_1] = 6;
2803 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2804 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2805 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2806 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2807 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2808 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2809 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2810 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2811 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2812 s->device_id = device_id;
2813 if (is_pci)
2814 s->bustype = CIRRUS_BUSTYPE_PCI;
2815 else
2816 s->bustype = CIRRUS_BUSTYPE_ISA;
2817 }
2818
0ceac75b 2819 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2820
0ceac75b
JQ		 2821 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2822 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2823 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2824 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2825
0ceac75b 2826 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2827
0ceac75b
JQ		 2828 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2829 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2830 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2831 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2832
b1950430
AK		 2833 memory_region_init(&s->low_mem_container,
2834 "cirrus-lowmem-container",
2835 0x20000);
2836
2837 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2838 "cirrus-low-memory", 0x20000);
2839 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2840 for (i = 0; i < 2; ++i) {
2841 static const char *names[] = { "vga.bank0", "vga.bank1" };
2842 MemoryRegion *bank = &s->cirrus_bank[i];
2843 memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
2844 memory_region_set_enabled(bank, false);
2845 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2846 bank, 1);
2847 }
be20f9e9 2848 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2849 isa_mem_base + 0x000a0000,
2850 &s->low_mem_container,
2851 1);
2852 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2853
fefe54e3 2854 /* I/O handler for LFB */
b1950430
AK		 2855 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2856 "cirrus-linear-io", VGA_RAM_SIZE);
fefe54e3
AL		 2857
2858 /* I/O handler for LFB */
b1950430
AK		 2859 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2860 &cirrus_linear_bitblt_io_ops,
2861 s,
2862 "cirrus-bitblt-mmio",
2863 0x400000);
fefe54e3
AL		 2864
2865 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2866 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2867 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
fefe54e3
AL		 2868
2869 s->real_vram_size =
2870 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2871
4e12cd94 2872 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2873 s->cirrus_addr_mask = s->real_vram_size - 1;
2874 s->linear_mmio_mask = s->real_vram_size - 256;
2875
4e12cd94
AK		 2876 s->vga.get_bpp = cirrus_get_bpp;
2877 s->vga.get_offsets = cirrus_get_offsets;
2878 s->vga.get_resolution = cirrus_get_resolution;
2879 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2880 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2881
a08d4367 2882 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2883}
2884
2885/***************************************
2886 *
2887 * ISA bus support
2888 *
2889 ***************************************/
2890
3d402831 2891static int vga_initfn(ISADevice *dev)
e6e5ad80 2892{
3d402831
BS		 2893 ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
2894 VGACommonState *s = &d->cirrus_vga.vga;
2895
4a1e244e
GH		 2896 s->vram_size_mb = VGA_RAM_SIZE >> 20;
2897 vga_common_init(s);
3d402831
BS		 2898 cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
2899 isa_address_space(dev));
2900 s->ds = graphic_console_init(s->update, s->invalidate,
2901 s->screen_dump, s->text_update,
2902 s);
5245d57a 2903 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80 2904 /* XXX ISA-LFB support */
ad6d45fa 2905 /* FIXME not qdev yet */
3d402831
BS		 2906 return 0;
2907}
2908
8f04ee08
AL		 2909static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2910{
2911 ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
39bffca2 2912 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 2913
39bffca2
AL		 2914 dc->vmsd = &vmstate_cirrus_vga;
2915 k->init = vga_initfn;
8f04ee08
AL		 2916}
2917
39bffca2
AL		 2918static TypeInfo isa_cirrus_vga_info = {
2919 .name = "isa-cirrus-vga",
2920 .parent = TYPE_ISA_DEVICE,
2921 .instance_size = sizeof(ISACirrusVGAState),
8f04ee08 2922 .class_init = isa_cirrus_vga_class_init,
3d402831
BS		 2923};
2924
e6e5ad80
FB		 2925/***************************************
2926 *
2927 * PCI bus support
2928 *
2929 ***************************************/
2930
81a322d4 2931static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2932{
2933 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2934 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2935 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2936 int16_t device_id = pc->device_id;
a414c306
GH		 2937
2938 /* setup VGA */
4a1e244e
GH		 2939 s->vga.vram_size_mb = VGA_RAM_SIZE >> 20;
2940 vga_common_init(&s->vga);
be20f9e9 2941 cirrus_init_common(s, device_id, 1, pci_address_space(dev));
a414c306
GH		 2942 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2943 s->vga.screen_dump, s->vga.text_update,
2944 &s->vga);
2945
2946 /* setup PCI */
a414c306 2947
b1950430
AK		 2948 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2949
2950 /* XXX: add byte swapping apertures */
2951 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2952 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2953 &s->cirrus_linear_bitblt_io);
2954
a414c306
GH		 2955 /* setup memory space */
2956 /* memory #0 LFB */
2957 /* memory #1 memory-mapped I/O */
2958 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2959 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2960 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2961 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2962 }
81a322d4 2963 return 0;
a414c306
GH		 2964}
2965
ad6d45fa 2966DeviceState *pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 2967{
ad6d45fa 2968 return &pci_create_simple(bus, -1, "cirrus-vga")->qdev;
a414c306 2969}
d34cab9f 2970
40021f08
AL		 2971static void cirrus_vga_class_init(ObjectClass *klass, void *data)
2972{
39bffca2 2973 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2974 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2975
2976 k->no_hotplug = 1;
2977 k->init = pci_cirrus_vga_initfn;
2978 k->romfile = VGABIOS_CIRRUS_FILENAME;
2979 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
2980 k->device_id = CIRRUS_ID_CLGD5446;
2981 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 2982 dc->desc = "Cirrus CLGD 54xx VGA";
2983 dc->vmsd = &vmstate_pci_cirrus_vga;
40021f08
AL		 2984}
2985
39bffca2
AL		 2986static TypeInfo cirrus_vga_info = {
2987 .name = "cirrus-vga",
2988 .parent = TYPE_PCI_DEVICE,
2989 .instance_size = sizeof(PCICirrusVGAState),
2990 .class_init = cirrus_vga_class_init,
a414c306 2991};
e6e5ad80 2992
83f7d43a 2993static void cirrus_vga_register_types(void)
a414c306 2994{
83f7d43a 2995 type_register_static(&isa_cirrus_vga_info);
39bffca2 2996 type_register_static(&cirrus_vga_info);
e6e5ad80 2997}
83f7d43a
AF		 2998
2999type_init(cirrus_vga_register_types)
Qemu copy for testing