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Fix build with DEBUG_PCI in pci_host.h enabled
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
2bec46dc 34#include "kvm.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
e6e5ad80
FB		 174// PCI 0x04: command(word), 0x06(word): status
175#define PCI_COMMAND_IOACCESS 0x0001
176#define PCI_COMMAND_MEMACCESS 0x0002
177#define PCI_COMMAND_BUSMASTER 0x0004
178#define PCI_COMMAND_SPECIALCYCLE 0x0008
179#define PCI_COMMAND_MEMWRITEINVALID 0x0010
180#define PCI_COMMAND_PALETTESNOOPING 0x0020
181#define PCI_COMMAND_PARITYDETECTION 0x0040
182#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
183#define PCI_COMMAND_SERR 0x0100
184#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
185// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
186#define PCI_CLASS_BASE_DISPLAY 0x03
187// PCI 0x08, 0x00ff0000
188#define PCI_CLASS_SUB_VGA 0x00
189// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
e6e5ad80
FB		 190// 0x10-0x3f (headertype 00h)
191// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
192// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
193#define PCI_MAP_MEM 0x0
194#define PCI_MAP_IO 0x1
195#define PCI_MAP_MEM_ADDR_MASK (~0xf)
196#define PCI_MAP_IO_ADDR_MASK (~0x3)
197#define PCI_MAP_MEMFLAGS_32BIT 0x0
198#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
199#define PCI_MAP_MEMFLAGS_64BIT 0x4
200#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
201// PCI 0x28: cardbus CIS pointer
202// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
203// PCI 0x30: expansion ROM base address
204#define PCI_ROMBIOS_ENABLED 0x1
205// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
206// PCI 0x38: reserved
207// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
208
a21ae81d 209#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 210
211
212/* I/O and memory hook */
213#define CIRRUS_HOOK_NOT_HANDLED 0
214#define CIRRUS_HOOK_HANDLED 1
215
b2b183c2
AL		 216#define ABS(a) ((signed)(a) > 0 ? a : -a)
217
b2eb849d
AJ		 218#define BLTUNSAFE(s) \
219 ( \
220 ( /* check dst is within bounds */ \
b2b183c2 221 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 222 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 223 (s)->vga.vram_size \
b2eb849d
AJ		 224 ) || \
225 ( /* check src is within bounds */ \
b2b183c2 226 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 227 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 228 (s)->vga.vram_size \
b2eb849d
AJ		 229 ) \
230 )
231
a5082316
FB		 232struct CirrusVGAState;
233typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
234 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 235 int dstpitch, int srcpitch,
236 int bltwidth, int bltheight);
a5082316
FB		 237typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
238 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 239
240typedef struct CirrusVGAState {
4e12cd94 241 VGACommonState vga;
e6e5ad80
FB		 242
243 int cirrus_linear_io_addr;
a5082316 244 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 245 int cirrus_mmio_io_addr;
246 uint32_t cirrus_addr_mask;
78e127ef 247 uint32_t linear_mmio_mask;
e6e5ad80
FB		 248 uint8_t cirrus_shadow_gr0;
249 uint8_t cirrus_shadow_gr1;
250 uint8_t cirrus_hidden_dac_lockindex;
251 uint8_t cirrus_hidden_dac_data;
252 uint32_t cirrus_bank_base[2];
253 uint32_t cirrus_bank_limit[2];
254 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 255 uint32_t hw_cursor_x;
256 uint32_t hw_cursor_y;
e6e5ad80
FB		 257 int cirrus_blt_pixelwidth;
258 int cirrus_blt_width;
259 int cirrus_blt_height;
260 int cirrus_blt_dstpitch;
261 int cirrus_blt_srcpitch;
a5082316
FB		 262 uint32_t cirrus_blt_fgcol;
263 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 264 uint32_t cirrus_blt_dstaddr;
265 uint32_t cirrus_blt_srcaddr;
266 uint8_t cirrus_blt_mode;
a5082316 267 uint8_t cirrus_blt_modeext;
e6e5ad80 268 cirrus_bitblt_rop_t cirrus_rop;
a5082316 269#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 270 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
271 uint8_t *cirrus_srcptr;
272 uint8_t *cirrus_srcptr_end;
273 uint32_t cirrus_srccounter;
a5082316
FB		 274 /* hwcursor display state */
275 int last_hw_cursor_size;
276 int last_hw_cursor_x;
277 int last_hw_cursor_y;
278 int last_hw_cursor_y_start;
279 int last_hw_cursor_y_end;
78e127ef 280 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 281 int device_id;
282 int bustype;
e6e5ad80
FB		 283} CirrusVGAState;
284
285typedef struct PCICirrusVGAState {
286 PCIDevice dev;
287 CirrusVGAState cirrus_vga;
288} PCICirrusVGAState;
289
a5082316 290static uint8_t rop_to_index[256];
3b46e624 291
e6e5ad80
FB		 292/***************************************
293 *
294 * prototypes.
295 *
296 ***************************************/
297
298
8926b517
FB		 299static void cirrus_bitblt_reset(CirrusVGAState *s);
300static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 301
302/***************************************
303 *
304 * raster operations
305 *
306 ***************************************/
307
a5082316
FB		 308static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
309 uint8_t *dst,const uint8_t *src,
310 int dstpitch,int srcpitch,
311 int bltwidth,int bltheight)
312{
e6e5ad80
FB		 313}
314
a5082316
FB		 315static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
316 uint8_t *dst,
317 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 318{
a5082316 319}
e6e5ad80 320
a5082316
FB		 321#define ROP_NAME 0
322#define ROP_OP(d, s) d = 0
323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316
FB		 325#define ROP_NAME src_and_dst
326#define ROP_OP(d, s) d = (s) & (d)
327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316
FB		 329#define ROP_NAME src_and_notdst
330#define ROP_OP(d, s) d = (s) & (~(d))
331#include "cirrus_vga_rop.h"
e6e5ad80 332
a5082316
FB		 333#define ROP_NAME notdst
334#define ROP_OP(d, s) d = ~(d)
335#include "cirrus_vga_rop.h"
e6e5ad80 336
a5082316
FB		 337#define ROP_NAME src
338#define ROP_OP(d, s) d = s
339#include "cirrus_vga_rop.h"
e6e5ad80 340
a5082316 341#define ROP_NAME 1
4c8732d7 342#define ROP_OP(d, s) d = ~0
a5082316
FB		 343#include "cirrus_vga_rop.h"
344
345#define ROP_NAME notsrc_and_dst
346#define ROP_OP(d, s) d = (~(s)) & (d)
347#include "cirrus_vga_rop.h"
348
349#define ROP_NAME src_xor_dst
350#define ROP_OP(d, s) d = (s) ^ (d)
351#include "cirrus_vga_rop.h"
352
353#define ROP_NAME src_or_dst
354#define ROP_OP(d, s) d = (s) | (d)
355#include "cirrus_vga_rop.h"
356
357#define ROP_NAME notsrc_or_notdst
358#define ROP_OP(d, s) d = (~(s)) | (~(d))
359#include "cirrus_vga_rop.h"
360
361#define ROP_NAME src_notxor_dst
362#define ROP_OP(d, s) d = ~((s) ^ (d))
363#include "cirrus_vga_rop.h"
e6e5ad80 364
a5082316
FB		 365#define ROP_NAME src_or_notdst
366#define ROP_OP(d, s) d = (s) | (~(d))
367#include "cirrus_vga_rop.h"
368
369#define ROP_NAME notsrc
370#define ROP_OP(d, s) d = (~(s))
371#include "cirrus_vga_rop.h"
372
373#define ROP_NAME notsrc_or_dst
374#define ROP_OP(d, s) d = (~(s)) | (d)
375#include "cirrus_vga_rop.h"
376
377#define ROP_NAME notsrc_and_notdst
378#define ROP_OP(d, s) d = (~(s)) & (~(d))
379#include "cirrus_vga_rop.h"
380
381static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
382 cirrus_bitblt_rop_fwd_0,
383 cirrus_bitblt_rop_fwd_src_and_dst,
384 cirrus_bitblt_rop_nop,
385 cirrus_bitblt_rop_fwd_src_and_notdst,
386 cirrus_bitblt_rop_fwd_notdst,
387 cirrus_bitblt_rop_fwd_src,
388 cirrus_bitblt_rop_fwd_1,
389 cirrus_bitblt_rop_fwd_notsrc_and_dst,
390 cirrus_bitblt_rop_fwd_src_xor_dst,
391 cirrus_bitblt_rop_fwd_src_or_dst,
392 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
393 cirrus_bitblt_rop_fwd_src_notxor_dst,
394 cirrus_bitblt_rop_fwd_src_or_notdst,
395 cirrus_bitblt_rop_fwd_notsrc,
396 cirrus_bitblt_rop_fwd_notsrc_or_dst,
397 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
398};
399
400static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
401 cirrus_bitblt_rop_bkwd_0,
402 cirrus_bitblt_rop_bkwd_src_and_dst,
403 cirrus_bitblt_rop_nop,
404 cirrus_bitblt_rop_bkwd_src_and_notdst,
405 cirrus_bitblt_rop_bkwd_notdst,
406 cirrus_bitblt_rop_bkwd_src,
407 cirrus_bitblt_rop_bkwd_1,
408 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
409 cirrus_bitblt_rop_bkwd_src_xor_dst,
410 cirrus_bitblt_rop_bkwd_src_or_dst,
411 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
412 cirrus_bitblt_rop_bkwd_src_notxor_dst,
413 cirrus_bitblt_rop_bkwd_src_or_notdst,
414 cirrus_bitblt_rop_bkwd_notsrc,
415 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
416 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
417};
96cf2df8
TS		 418
419#define TRANSP_ROP(name) {\
420 name ## _8,\
421 name ## _16,\
422 }
423#define TRANSP_NOP(func) {\
424 func,\
425 func,\
426 }
427
428static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
431 TRANSP_NOP(cirrus_bitblt_rop_nop),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
445};
446
447static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
450 TRANSP_NOP(cirrus_bitblt_rop_nop),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
464};
465
a5082316
FB		 466#define ROP2(name) {\
467 name ## _8,\
468 name ## _16,\
469 name ## _24,\
470 name ## _32,\
471 }
472
473#define ROP_NOP2(func) {\
474 func,\
475 func,\
476 func,\
477 func,\
478 }
479
e69390ce
FB		 480static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
481 ROP2(cirrus_patternfill_0),
482 ROP2(cirrus_patternfill_src_and_dst),
483 ROP_NOP2(cirrus_bitblt_rop_nop),
484 ROP2(cirrus_patternfill_src_and_notdst),
485 ROP2(cirrus_patternfill_notdst),
486 ROP2(cirrus_patternfill_src),
487 ROP2(cirrus_patternfill_1),
488 ROP2(cirrus_patternfill_notsrc_and_dst),
489 ROP2(cirrus_patternfill_src_xor_dst),
490 ROP2(cirrus_patternfill_src_or_dst),
491 ROP2(cirrus_patternfill_notsrc_or_notdst),
492 ROP2(cirrus_patternfill_src_notxor_dst),
493 ROP2(cirrus_patternfill_src_or_notdst),
494 ROP2(cirrus_patternfill_notsrc),
495 ROP2(cirrus_patternfill_notsrc_or_dst),
496 ROP2(cirrus_patternfill_notsrc_and_notdst),
497};
498
a5082316
FB		 499static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
500 ROP2(cirrus_colorexpand_transp_0),
501 ROP2(cirrus_colorexpand_transp_src_and_dst),
502 ROP_NOP2(cirrus_bitblt_rop_nop),
503 ROP2(cirrus_colorexpand_transp_src_and_notdst),
504 ROP2(cirrus_colorexpand_transp_notdst),
505 ROP2(cirrus_colorexpand_transp_src),
506 ROP2(cirrus_colorexpand_transp_1),
507 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
508 ROP2(cirrus_colorexpand_transp_src_xor_dst),
509 ROP2(cirrus_colorexpand_transp_src_or_dst),
510 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
511 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
512 ROP2(cirrus_colorexpand_transp_src_or_notdst),
513 ROP2(cirrus_colorexpand_transp_notsrc),
514 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
515 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
516};
517
518static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
519 ROP2(cirrus_colorexpand_0),
520 ROP2(cirrus_colorexpand_src_and_dst),
521 ROP_NOP2(cirrus_bitblt_rop_nop),
522 ROP2(cirrus_colorexpand_src_and_notdst),
523 ROP2(cirrus_colorexpand_notdst),
524 ROP2(cirrus_colorexpand_src),
525 ROP2(cirrus_colorexpand_1),
526 ROP2(cirrus_colorexpand_notsrc_and_dst),
527 ROP2(cirrus_colorexpand_src_xor_dst),
528 ROP2(cirrus_colorexpand_src_or_dst),
529 ROP2(cirrus_colorexpand_notsrc_or_notdst),
530 ROP2(cirrus_colorexpand_src_notxor_dst),
531 ROP2(cirrus_colorexpand_src_or_notdst),
532 ROP2(cirrus_colorexpand_notsrc),
533 ROP2(cirrus_colorexpand_notsrc_or_dst),
534 ROP2(cirrus_colorexpand_notsrc_and_notdst),
535};
536
b30d4608
FB		 537static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
538 ROP2(cirrus_colorexpand_pattern_transp_0),
539 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
540 ROP_NOP2(cirrus_bitblt_rop_nop),
541 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
542 ROP2(cirrus_colorexpand_pattern_transp_notdst),
543 ROP2(cirrus_colorexpand_pattern_transp_src),
544 ROP2(cirrus_colorexpand_pattern_transp_1),
545 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
546 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
547 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
549 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
552 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
554};
555
556static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
557 ROP2(cirrus_colorexpand_pattern_0),
558 ROP2(cirrus_colorexpand_pattern_src_and_dst),
559 ROP_NOP2(cirrus_bitblt_rop_nop),
560 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
561 ROP2(cirrus_colorexpand_pattern_notdst),
562 ROP2(cirrus_colorexpand_pattern_src),
563 ROP2(cirrus_colorexpand_pattern_1),
564 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
565 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
566 ROP2(cirrus_colorexpand_pattern_src_or_dst),
567 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
568 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
569 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
570 ROP2(cirrus_colorexpand_pattern_notsrc),
571 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
572 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
573};
574
a5082316
FB		 575static const cirrus_fill_t cirrus_fill[16][4] = {
576 ROP2(cirrus_fill_0),
577 ROP2(cirrus_fill_src_and_dst),
578 ROP_NOP2(cirrus_bitblt_fill_nop),
579 ROP2(cirrus_fill_src_and_notdst),
580 ROP2(cirrus_fill_notdst),
581 ROP2(cirrus_fill_src),
582 ROP2(cirrus_fill_1),
583 ROP2(cirrus_fill_notsrc_and_dst),
584 ROP2(cirrus_fill_src_xor_dst),
585 ROP2(cirrus_fill_src_or_dst),
586 ROP2(cirrus_fill_notsrc_or_notdst),
587 ROP2(cirrus_fill_src_notxor_dst),
588 ROP2(cirrus_fill_src_or_notdst),
589 ROP2(cirrus_fill_notsrc),
590 ROP2(cirrus_fill_notsrc_or_dst),
591 ROP2(cirrus_fill_notsrc_and_notdst),
592};
593
594static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 595{
a5082316
FB		 596 unsigned int color;
597 switch (s->cirrus_blt_pixelwidth) {
598 case 1:
599 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600 break;
601 case 2:
4e12cd94 602 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 603 s->cirrus_blt_fgcol = le16_to_cpu(color);
604 break;
605 case 3:
5fafdf24 606 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 607 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 608 break;
609 default:
610 case 4:
4e12cd94
AK		 611 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
612 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 613 s->cirrus_blt_fgcol = le32_to_cpu(color);
614 break;
e6e5ad80
FB		 615 }
616}
617
a5082316 618static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 619{
a5082316 620 unsigned int color;
e6e5ad80
FB		 621 switch (s->cirrus_blt_pixelwidth) {
622 case 1:
a5082316
FB		 623 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624 break;
e6e5ad80 625 case 2:
4e12cd94 626 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 627 s->cirrus_blt_bgcol = le16_to_cpu(color);
628 break;
e6e5ad80 629 case 3:
5fafdf24 630 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 631 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 632 break;
e6e5ad80 633 default:
a5082316 634 case 4:
4e12cd94
AK		 635 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
636 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 637 s->cirrus_blt_bgcol = le32_to_cpu(color);
638 break;
e6e5ad80
FB		 639 }
640}
641
642static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
643 int off_pitch, int bytesperline,
644 int lines)
645{
646 int y;
647 int off_cur;
648 int off_cur_end;
649
650 for (y = 0; y < lines; y++) {
651 off_cur = off_begin;
b2eb849d 652 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 653 off_cur &= TARGET_PAGE_MASK;
654 while (off_cur < off_cur_end) {
4e12cd94 655 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
e6e5ad80
FB		 656 off_cur += TARGET_PAGE_SIZE;
657 }
658 off_begin += off_pitch;
659 }
660}
661
e6e5ad80
FB		 662static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
663 const uint8_t * src)
664{
e6e5ad80 665 uint8_t *dst;
e6e5ad80 666
4e12cd94 667 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 668
669 if (BLTUNSAFE(s))
670 return 0;
671
e69390ce 672 (*s->cirrus_rop) (s, dst, src,
5fafdf24 673 s->cirrus_blt_dstpitch, 0,
e69390ce 674 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 675 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 676 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
677 s->cirrus_blt_height);
e6e5ad80
FB		 678 return 1;
679}
680
a21ae81d
FB		 681/* fill */
682
a5082316 683static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 684{
a5082316 685 cirrus_fill_t rop_func;
a21ae81d 686
b2eb849d
AJ		 687 if (BLTUNSAFE(s))
688 return 0;
a5082316 689 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 690 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 691 s->cirrus_blt_dstpitch,
692 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 693 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
694 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
695 s->cirrus_blt_height);
696 cirrus_bitblt_reset(s);
697 return 1;
698}
699
e6e5ad80
FB		 700/***************************************
701 *
702 * bitblt (video-to-video)
703 *
704 ***************************************/
705
706static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707{
708 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 709 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 710 s->cirrus_addr_mask));
e6e5ad80
FB		 711}
712
24236869 713static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 714{
24236869
FB		 715 int sx, sy;
716 int dx, dy;
717 int width, height;
718 int depth;
719 int notify = 0;
720
4e12cd94
AK		 721 depth = s->vga.get_bpp(&s->vga) / 8;
722 s->vga.get_resolution(&s->vga, &width, &height);
24236869
FB		 723
724 /* extra x, y */
d85d0d38
AL		 725 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
726 sy = (src / ABS(s->cirrus_blt_srcpitch));
727 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
728 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869
FB		 729
730 /* normalize width */
731 w /= depth;
732
733 /* if we're doing a backward copy, we have to adjust
734 our x/y to be the upper left corner (instead of the lower
735 right corner) */
736 if (s->cirrus_blt_dstpitch < 0) {
737 sx -= (s->cirrus_blt_width / depth) - 1;
738 dx -= (s->cirrus_blt_width / depth) - 1;
739 sy -= s->cirrus_blt_height - 1;
740 dy -= s->cirrus_blt_height - 1;
741 }
742
743 /* are we in the visible portion of memory? */
744 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
745 (sx + w) <= width && (sy + h) <= height &&
746 (dx + w) <= width && (dy + h) <= height) {
747 notify = 1;
748 }
749
750 /* make to sure only copy if it's a plain copy ROP */
751 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
752 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
753 notify = 0;
754
755 /* we have to flush all pending changes so that the copy
756 is generated at the appropriate moment in time */
757 if (notify)
758 vga_hw_update();
759
4e12cd94 760 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 761 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 762 s->vga.vram_ptr +
b2eb849d 763 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 764 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 766
767 if (notify)
4e12cd94 768 qemu_console_copy(s->vga.ds,
38334f76
AZ		 769 sx, sy, dx, dy,
770 s->cirrus_blt_width / depth,
771 s->cirrus_blt_height);
24236869
FB		 772
773 /* we don't have to notify the display that this portion has
38334f76 774 changed since qemu_console_copy implies this */
24236869 775
31c05501
AL		 776 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
777 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
778 s->cirrus_blt_height);
24236869
FB		 779}
780
781static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
782{
65d35a09
AJ		 783 if (BLTUNSAFE(s))
784 return 0;
785
4e12cd94
AK		 786 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
787 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 788 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 789
e6e5ad80
FB		 790 return 1;
791}
792
793/***************************************
794 *
795 * bitblt (cpu-to-video)
796 *
797 ***************************************/
798
e6e5ad80
FB		 799static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
800{
801 int copy_count;
a5082316 802 uint8_t *end_ptr;
3b46e624 803
e6e5ad80 804 if (s->cirrus_srccounter > 0) {
a5082316
FB		 805 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
806 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
807 the_end:
808 s->cirrus_srccounter = 0;
809 cirrus_bitblt_reset(s);
810 } else {
811 /* at least one scan line */
812 do {
4e12cd94 813 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 814 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 816 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
817 s->cirrus_blt_width, 1);
818 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
819 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
820 if (s->cirrus_srccounter <= 0)
821 goto the_end;
822 /* more bytes than needed can be transfered because of
823 word alignment, so we keep them for the next line */
824 /* XXX: keep alignment to speed up transfer */
825 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826 copy_count = s->cirrus_srcptr_end - end_ptr;
827 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
828 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
829 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
830 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
831 }
e6e5ad80
FB		 832 }
833}
834
835/***************************************
836 *
837 * bitblt wrapper
838 *
839 ***************************************/
840
841static void cirrus_bitblt_reset(CirrusVGAState * s)
842{
f8b237af
AL		 843 int need_update;
844
4e12cd94 845 s->vga.gr[0x31] &=
e6e5ad80 846 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 847 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 849 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
850 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
851 s->cirrus_srccounter = 0;
f8b237af
AL		 852 if (!need_update)
853 return;
8926b517 854 cirrus_update_memory_access(s);
e6e5ad80
FB		 855}
856
857static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
858{
a5082316
FB		 859 int w;
860
e6e5ad80
FB		 861 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
862 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
863 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
864
865 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
866 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 867 s->cirrus_blt_srcpitch = 8;
e6e5ad80 868 } else {
b30d4608 869 /* XXX: check for 24 bpp */
a5082316 870 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 871 }
a5082316 872 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 873 } else {
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 875 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 876 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 877 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
878 else
879 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 880 } else {
c9c0eae8
FB		 881 /* always align input size to 32 bits */
882 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 883 }
a5082316 884 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 885 }
a5082316
FB		 886 s->cirrus_srcptr = s->cirrus_bltbuf;
887 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 888 cirrus_update_memory_access(s);
e6e5ad80
FB		 889 return 1;
890}
891
892static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
893{
894 /* XXX */
a5082316 895#ifdef DEBUG_BITBLT
e6e5ad80
FB		 896 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
897#endif
898 return 0;
899}
900
901static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
902{
903 int ret;
904
905 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
906 ret = cirrus_bitblt_videotovideo_patterncopy(s);
907 } else {
908 ret = cirrus_bitblt_videotovideo_copy(s);
909 }
e6e5ad80
FB		 910 if (ret)
911 cirrus_bitblt_reset(s);
912 return ret;
913}
914
915static void cirrus_bitblt_start(CirrusVGAState * s)
916{
917 uint8_t blt_rop;
918
4e12cd94 919 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 920
4e12cd94
AK		 921 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
922 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
923 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
924 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 925 s->cirrus_blt_dstaddr =
4e12cd94 926 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 927 s->cirrus_blt_srcaddr =
4e12cd94
AK		 928 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
929 s->cirrus_blt_mode = s->vga.gr[0x30];
930 s->cirrus_blt_modeext = s->vga.gr[0x33];
931 blt_rop = s->vga.gr[0x32];
e6e5ad80 932
a21ae81d 933#ifdef DEBUG_BITBLT
0b74ed78 934 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 935 blt_rop,
a21ae81d 936 s->cirrus_blt_mode,
a5082316 937 s->cirrus_blt_modeext,
a21ae81d
FB		 938 s->cirrus_blt_width,
939 s->cirrus_blt_height,
940 s->cirrus_blt_dstpitch,
941 s->cirrus_blt_srcpitch,
942 s->cirrus_blt_dstaddr,
a5082316 943 s->cirrus_blt_srcaddr,
4e12cd94 944 s->vga.gr[0x2f]);
a21ae81d
FB		 945#endif
946
e6e5ad80
FB		 947 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
948 case CIRRUS_BLTMODE_PIXELWIDTH8:
949 s->cirrus_blt_pixelwidth = 1;
950 break;
951 case CIRRUS_BLTMODE_PIXELWIDTH16:
952 s->cirrus_blt_pixelwidth = 2;
953 break;
954 case CIRRUS_BLTMODE_PIXELWIDTH24:
955 s->cirrus_blt_pixelwidth = 3;
956 break;
957 case CIRRUS_BLTMODE_PIXELWIDTH32:
958 s->cirrus_blt_pixelwidth = 4;
959 break;
960 default:
a5082316 961#ifdef DEBUG_BITBLT
e6e5ad80
FB		 962 printf("cirrus: bitblt - pixel width is unknown\n");
963#endif
964 goto bitblt_ignore;
965 }
966 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
967
968 if ((s->
969 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
970 CIRRUS_BLTMODE_MEMSYSDEST))
971 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 972#ifdef DEBUG_BITBLT
e6e5ad80
FB		 973 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
974#endif
975 goto bitblt_ignore;
976 }
977
a5082316 978 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 979 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 980 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 981 CIRRUS_BLTMODE_PATTERNCOPY |
982 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 983 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 984 cirrus_bitblt_fgcol(s);
985 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 986 } else {
5fafdf24
TS		 987 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
988 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 989 CIRRUS_BLTMODE_COLOREXPAND) {
990
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 992 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 993 cirrus_bitblt_bgcol(s);
b30d4608 994 else
4c8732d7 995 cirrus_bitblt_fgcol(s);
b30d4608 996 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 997 } else {
998 cirrus_bitblt_fgcol(s);
999 cirrus_bitblt_bgcol(s);
1000 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1001 }
e69390ce 1002 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1003 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1005 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1006 cirrus_bitblt_bgcol(s);
1007 else
1008 cirrus_bitblt_fgcol(s);
1009 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1010 } else {
1011 cirrus_bitblt_fgcol(s);
1012 cirrus_bitblt_bgcol(s);
1013 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 }
1015 } else {
1016 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1017 }
a21ae81d 1018 } else {
96cf2df8
TS		 1019 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1020 if (s->cirrus_blt_pixelwidth > 2) {
1021 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1022 goto bitblt_ignore;
1023 }
1024 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1025 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1026 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1027 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 } else {
1029 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 }
1031 } else {
1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1033 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1034 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1035 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1036 } else {
1037 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1038 }
1039 }
1040 }
a21ae81d
FB		 1041 // setup bitblt engine.
1042 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1043 if (!cirrus_bitblt_cputovideo(s))
1044 goto bitblt_ignore;
1045 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1046 if (!cirrus_bitblt_videotocpu(s))
1047 goto bitblt_ignore;
1048 } else {
1049 if (!cirrus_bitblt_videotovideo(s))
1050 goto bitblt_ignore;
1051 }
e6e5ad80 1052 }
e6e5ad80
FB		 1053 return;
1054 bitblt_ignore:;
1055 cirrus_bitblt_reset(s);
1056}
1057
1058static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1059{
1060 unsigned old_value;
1061
4e12cd94
AK		 1062 old_value = s->vga.gr[0x31];
1063 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1064
1065 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1067 cirrus_bitblt_reset(s);
1068 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1069 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1070 cirrus_bitblt_start(s);
1071 }
1072}
1073
1074
1075/***************************************
1076 *
1077 * basic parameters
1078 *
1079 ***************************************/
1080
5fafdf24 1081static void cirrus_get_offsets(VGAState *s1,
83acc96b
FB		 1082 uint32_t *pline_offset,
1083 uint32_t *pstart_addr,
1084 uint32_t *pline_compare)
e6e5ad80 1085{
4e12cd94 1086 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1087 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1088
4e12cd94
AK		 1089 line_offset = s->vga.cr[0x13]
1090 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1091 line_offset <<= 3;
1092 *pline_offset = line_offset;
1093
4e12cd94
AK		 1094 start_addr = (s->vga.cr[0x0c] << 8)
1095 | s->vga.cr[0x0d]
1096 | ((s->vga.cr[0x1b] & 0x01) << 16)
1097 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1098 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1099 *pstart_addr = start_addr;
83acc96b 1100
4e12cd94
AK		 1101 line_compare = s->vga.cr[0x18] |
1102 ((s->vga.cr[0x07] & 0x10) << 4) |
1103 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1104 *pline_compare = line_compare;
e6e5ad80
FB		 1105}
1106
1107static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1108{
1109 uint32_t ret = 16;
1110
1111 switch (s->cirrus_hidden_dac_data & 0xf) {
1112 case 0:
1113 ret = 15;
1114 break; /* Sierra HiColor */
1115 case 1:
1116 ret = 16;
1117 break; /* XGA HiColor */
1118 default:
1119#ifdef DEBUG_CIRRUS
1120 printf("cirrus: invalid DAC value %x in 16bpp\n",
1121 (s->cirrus_hidden_dac_data & 0xf));
1122#endif
1123 ret = 15; /* XXX */
1124 break;
1125 }
1126 return ret;
1127}
1128
1129static int cirrus_get_bpp(VGAState *s1)
1130{
4e12cd94 1131 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1132 uint32_t ret = 8;
1133
4e12cd94 1134 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1135 /* Cirrus SVGA */
4e12cd94 1136 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1137 case CIRRUS_SR7_BPP_8:
1138 ret = 8;
1139 break;
1140 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1141 ret = cirrus_get_bpp16_depth(s);
1142 break;
1143 case CIRRUS_SR7_BPP_24:
1144 ret = 24;
1145 break;
1146 case CIRRUS_SR7_BPP_16:
1147 ret = cirrus_get_bpp16_depth(s);
1148 break;
1149 case CIRRUS_SR7_BPP_32:
1150 ret = 32;
1151 break;
1152 default:
1153#ifdef DEBUG_CIRRUS
4e12cd94 1154 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1155#endif
1156 ret = 8;
1157 break;
1158 }
1159 } else {
1160 /* VGA */
aeb3c85f 1161 ret = 0;
e6e5ad80
FB		 1162 }
1163
1164 return ret;
1165}
1166
78e127ef
FB		 1167static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1168{
1169 int width, height;
3b46e624 1170
78e127ef 1171 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1172 height = s->cr[0x12] |
1173 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1174 ((s->cr[0x07] & 0x40) << 3);
1175 height = (height + 1);
1176 /* interlace support */
1177 if (s->cr[0x1a] & 0x01)
1178 height = height * 2;
1179 *pwidth = width;
1180 *pheight = height;
1181}
1182
e6e5ad80
FB		 1183/***************************************
1184 *
1185 * bank memory
1186 *
1187 ***************************************/
1188
1189static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1190{
1191 unsigned offset;
1192 unsigned limit;
1193
4e12cd94
AK		 1194 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1195 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1196 else /* single bank */
4e12cd94 1197 offset = s->vga.gr[0x09];
e6e5ad80 1198
4e12cd94 1199 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1200 offset <<= 14;
1201 else
1202 offset <<= 12;
1203
e3a4e4b6 1204 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1205 limit = 0;
1206 else
e3a4e4b6 1207 limit = s->real_vram_size - offset;
e6e5ad80 1208
4e12cd94 1209 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1210 if (limit > 0x8000) {
1211 offset += 0x8000;
1212 limit -= 0x8000;
1213 } else {
1214 limit = 0;
1215 }
1216 }
1217
1218 if (limit > 0) {
2bec46dc
AL		 1219 /* Thinking about changing bank base? First, drop the dirty bitmap information
1220 * on the current location, otherwise we lose this pointer forever */
4e12cd94 1221 if (s->vga.lfb_vram_mapped) {
2bec46dc
AL		 1222 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224 }
e6e5ad80
FB		 1225 s->cirrus_bank_base[bank_index] = offset;
1226 s->cirrus_bank_limit[bank_index] = limit;
1227 } else {
1228 s->cirrus_bank_base[bank_index] = 0;
1229 s->cirrus_bank_limit[bank_index] = 0;
1230 }
1231}
1232
1233/***************************************
1234 *
1235 * I/O access between 0x3c4-0x3c5
1236 *
1237 ***************************************/
1238
1239static int
1240cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1241{
1242 switch (reg_index) {
1243 case 0x00: // Standard VGA
1244 case 0x01: // Standard VGA
1245 case 0x02: // Standard VGA
1246 case 0x03: // Standard VGA
1247 case 0x04: // Standard VGA
1248 return CIRRUS_HOOK_NOT_HANDLED;
1249 case 0x06: // Unlock Cirrus extensions
4e12cd94 1250 *reg_value = s->vga.sr[reg_index];
e6e5ad80 1251 break;
e6e5ad80
FB		 1252 case 0x10:
1253 case 0x30:
1254 case 0x50:
1255 case 0x70: // Graphics Cursor X
1256 case 0x90:
1257 case 0xb0:
1258 case 0xd0:
1259 case 0xf0: // Graphics Cursor X
4e12cd94 1260 *reg_value = s->vga.sr[0x10];
aeb3c85f 1261 break;
e6e5ad80
FB		 1262 case 0x11:
1263 case 0x31:
1264 case 0x51:
1265 case 0x71: // Graphics Cursor Y
1266 case 0x91:
1267 case 0xb1:
1268 case 0xd1:
a5082316 1269 case 0xf1: // Graphics Cursor Y
4e12cd94 1270 *reg_value = s->vga.sr[0x11];
aeb3c85f
FB		 1271 break;
1272 case 0x05: // ???
1273 case 0x07: // Extended Sequencer Mode
1274 case 0x08: // EEPROM Control
1275 case 0x09: // Scratch Register 0
1276 case 0x0a: // Scratch Register 1
1277 case 0x0b: // VCLK 0
1278 case 0x0c: // VCLK 1
1279 case 0x0d: // VCLK 2
1280 case 0x0e: // VCLK 3
1281 case 0x0f: // DRAM Control
e6e5ad80
FB		 1282 case 0x12: // Graphics Cursor Attribute
1283 case 0x13: // Graphics Cursor Pattern Address
1284 case 0x14: // Scratch Register 2
1285 case 0x15: // Scratch Register 3
1286 case 0x16: // Performance Tuning Register
1287 case 0x17: // Configuration Readback and Extended Control
1288 case 0x18: // Signature Generator Control
1289 case 0x19: // Signal Generator Result
1290 case 0x1a: // Signal Generator Result
1291 case 0x1b: // VCLK 0 Denominator & Post
1292 case 0x1c: // VCLK 1 Denominator & Post
1293 case 0x1d: // VCLK 2 Denominator & Post
1294 case 0x1e: // VCLK 3 Denominator & Post
1295 case 0x1f: // BIOS Write Enable and MCLK select
1296#ifdef DEBUG_CIRRUS
1297 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1298#endif
4e12cd94 1299 *reg_value = s->vga.sr[reg_index];
e6e5ad80
FB		 1300 break;
1301 default:
1302#ifdef DEBUG_CIRRUS
1303 printf("cirrus: inport sr_index %02x\n", reg_index);
1304#endif
1305 *reg_value = 0xff;
1306 break;
1307 }
1308
1309 return CIRRUS_HOOK_HANDLED;
1310}
1311
1312static int
1313cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1314{
1315 switch (reg_index) {
1316 case 0x00: // Standard VGA
1317 case 0x01: // Standard VGA
1318 case 0x02: // Standard VGA
1319 case 0x03: // Standard VGA
1320 case 0x04: // Standard VGA
1321 return CIRRUS_HOOK_NOT_HANDLED;
1322 case 0x06: // Unlock Cirrus extensions
1323 reg_value &= 0x17;
1324 if (reg_value == 0x12) {
4e12cd94 1325 s->vga.sr[reg_index] = 0x12;
e6e5ad80 1326 } else {
4e12cd94 1327 s->vga.sr[reg_index] = 0x0f;
e6e5ad80
FB		 1328 }
1329 break;
1330 case 0x10:
1331 case 0x30:
1332 case 0x50:
1333 case 0x70: // Graphics Cursor X
1334 case 0x90:
1335 case 0xb0:
1336 case 0xd0:
1337 case 0xf0: // Graphics Cursor X
4e12cd94 1338 s->vga.sr[0x10] = reg_value;
a5082316 1339 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1340 break;
1341 case 0x11:
1342 case 0x31:
1343 case 0x51:
1344 case 0x71: // Graphics Cursor Y
1345 case 0x91:
1346 case 0xb1:
1347 case 0xd1:
1348 case 0xf1: // Graphics Cursor Y
4e12cd94 1349 s->vga.sr[0x11] = reg_value;
a5082316 1350 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1351 break;
1352 case 0x07: // Extended Sequencer Mode
2bec46dc 1353 cirrus_update_memory_access(s);
e6e5ad80
FB		 1354 case 0x08: // EEPROM Control
1355 case 0x09: // Scratch Register 0
1356 case 0x0a: // Scratch Register 1
1357 case 0x0b: // VCLK 0
1358 case 0x0c: // VCLK 1
1359 case 0x0d: // VCLK 2
1360 case 0x0e: // VCLK 3
1361 case 0x0f: // DRAM Control
1362 case 0x12: // Graphics Cursor Attribute
1363 case 0x13: // Graphics Cursor Pattern Address
1364 case 0x14: // Scratch Register 2
1365 case 0x15: // Scratch Register 3
1366 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1367 case 0x18: // Signature Generator Control
1368 case 0x19: // Signature Generator Result
1369 case 0x1a: // Signature Generator Result
1370 case 0x1b: // VCLK 0 Denominator & Post
1371 case 0x1c: // VCLK 1 Denominator & Post
1372 case 0x1d: // VCLK 2 Denominator & Post
1373 case 0x1e: // VCLK 3 Denominator & Post
1374 case 0x1f: // BIOS Write Enable and MCLK select
4e12cd94 1375 s->vga.sr[reg_index] = reg_value;
e6e5ad80
FB		 1376#ifdef DEBUG_CIRRUS
1377 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1378 reg_index, reg_value);
1379#endif
1380 break;
8926b517 1381 case 0x17: // Configuration Readback and Extended Control
4e12cd94 1382 s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
8926b517
FB		 1383 cirrus_update_memory_access(s);
1384 break;
e6e5ad80
FB		 1385 default:
1386#ifdef DEBUG_CIRRUS
1387 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1388 reg_value);
1389#endif
1390 break;
1391 }
1392
1393 return CIRRUS_HOOK_HANDLED;
1394}
1395
1396/***************************************
1397 *
1398 * I/O access at 0x3c6
1399 *
1400 ***************************************/
1401
1402static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1403{
1404 *reg_value = 0xff;
a21ae81d
FB		 1405 if (++s->cirrus_hidden_dac_lockindex == 5) {
1406 *reg_value = s->cirrus_hidden_dac_data;
1407 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1408 }
1409}
1410
1411static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1412{
1413 if (s->cirrus_hidden_dac_lockindex == 4) {
1414 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1415#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1416 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1417#endif
1418 }
1419 s->cirrus_hidden_dac_lockindex = 0;
1420}
1421
1422/***************************************
1423 *
1424 * I/O access at 0x3c9
1425 *
1426 ***************************************/
1427
1428static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1429{
4e12cd94 1430 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
e6e5ad80 1431 return CIRRUS_HOOK_NOT_HANDLED;
a5082316 1432 *reg_value =
4e12cd94
AK		 1433 s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1434 s->vga.dac_sub_index];
1435 if (++s->vga.dac_sub_index == 3) {
1436 s->vga.dac_sub_index = 0;
1437 s->vga.dac_read_index++;
e6e5ad80
FB		 1438 }
1439 return CIRRUS_HOOK_HANDLED;
1440}
1441
1442static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1443{
4e12cd94 1444 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
e6e5ad80 1445 return CIRRUS_HOOK_NOT_HANDLED;
4e12cd94
AK		 1446 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1447 if (++s->vga.dac_sub_index == 3) {
1448 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1449 s->vga.dac_cache, 3);
a5082316 1450 /* XXX update cursor */
4e12cd94
AK		 1451 s->vga.dac_sub_index = 0;
1452 s->vga.dac_write_index++;
e6e5ad80
FB		 1453 }
1454 return CIRRUS_HOOK_HANDLED;
1455}
1456
1457/***************************************
1458 *
1459 * I/O access between 0x3ce-0x3cf
1460 *
1461 ***************************************/
1462
1463static int
1464cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1465{
1466 switch (reg_index) {
aeb3c85f
FB		 1467 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1468 *reg_value = s->cirrus_shadow_gr0;
1469 return CIRRUS_HOOK_HANDLED;
1470 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1471 *reg_value = s->cirrus_shadow_gr1;
1472 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1473 case 0x02: // Standard VGA
1474 case 0x03: // Standard VGA
1475 case 0x04: // Standard VGA
1476 case 0x06: // Standard VGA
1477 case 0x07: // Standard VGA
1478 case 0x08: // Standard VGA
1479 return CIRRUS_HOOK_NOT_HANDLED;
1480 case 0x05: // Standard VGA, Cirrus extended mode
1481 default:
1482 break;
1483 }
1484
1485 if (reg_index < 0x3a) {
4e12cd94 1486 *reg_value = s->vga.gr[reg_index];
e6e5ad80
FB		 1487 } else {
1488#ifdef DEBUG_CIRRUS
1489 printf("cirrus: inport gr_index %02x\n", reg_index);
1490#endif
1491 *reg_value = 0xff;
1492 }
1493
1494 return CIRRUS_HOOK_HANDLED;
1495}
1496
1497static int
1498cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1499{
a5082316
FB		 1500#if defined(DEBUG_BITBLT) && 0
1501 printf("gr%02x: %02x\n", reg_index, reg_value);
1502#endif
e6e5ad80
FB		 1503 switch (reg_index) {
1504 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1505 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1506 return CIRRUS_HOOK_NOT_HANDLED;
1507 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1508 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1509 return CIRRUS_HOOK_NOT_HANDLED;
1510 case 0x02: // Standard VGA
1511 case 0x03: // Standard VGA
1512 case 0x04: // Standard VGA
1513 case 0x06: // Standard VGA
1514 case 0x07: // Standard VGA
1515 case 0x08: // Standard VGA
1516 return CIRRUS_HOOK_NOT_HANDLED;
1517 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1518 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1519 cirrus_update_memory_access(s);
e6e5ad80
FB		 1520 break;
1521 case 0x09: // bank offset #0
1522 case 0x0A: // bank offset #1
4e12cd94 1523 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1524 cirrus_update_bank_ptr(s, 0);
1525 cirrus_update_bank_ptr(s, 1);
2bec46dc 1526 cirrus_update_memory_access(s);
8926b517 1527 break;
e6e5ad80 1528 case 0x0B:
4e12cd94 1529 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1530 cirrus_update_bank_ptr(s, 0);
1531 cirrus_update_bank_ptr(s, 1);
8926b517 1532 cirrus_update_memory_access(s);
e6e5ad80
FB		 1533 break;
1534 case 0x10: // BGCOLOR 0x0000ff00
1535 case 0x11: // FGCOLOR 0x0000ff00
1536 case 0x12: // BGCOLOR 0x00ff0000
1537 case 0x13: // FGCOLOR 0x00ff0000
1538 case 0x14: // BGCOLOR 0xff000000
1539 case 0x15: // FGCOLOR 0xff000000
1540 case 0x20: // BLT WIDTH 0x0000ff
1541 case 0x22: // BLT HEIGHT 0x0000ff
1542 case 0x24: // BLT DEST PITCH 0x0000ff
1543 case 0x26: // BLT SRC PITCH 0x0000ff
1544 case 0x28: // BLT DEST ADDR 0x0000ff
1545 case 0x29: // BLT DEST ADDR 0x00ff00
1546 case 0x2c: // BLT SRC ADDR 0x0000ff
1547 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1548 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1549 case 0x30: // BLT MODE
1550 case 0x32: // RASTER OP
a21ae81d 1551 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1552 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1553 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1554 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1555 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1556 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1557 break;
1558 case 0x21: // BLT WIDTH 0x001f00
1559 case 0x23: // BLT HEIGHT 0x001f00
1560 case 0x25: // BLT DEST PITCH 0x001f00
1561 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1562 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1563 break;
1564 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1565 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1566 /* if auto start mode, starts bit blt now */
4e12cd94 1567 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1568 cirrus_bitblt_start(s);
1569 }
1570 break;
e6e5ad80 1571 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1572 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1573 break;
1574 case 0x31: // BLT STATUS/START
1575 cirrus_write_bitblt(s, reg_value);
1576 break;
1577 default:
1578#ifdef DEBUG_CIRRUS
1579 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1580 reg_value);
1581#endif
1582 break;
1583 }
1584
1585 return CIRRUS_HOOK_HANDLED;
1586}
1587
1588/***************************************
1589 *
1590 * I/O access between 0x3d4-0x3d5
1591 *
1592 ***************************************/
1593
1594static int
1595cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1596{
1597 switch (reg_index) {
1598 case 0x00: // Standard VGA
1599 case 0x01: // Standard VGA
1600 case 0x02: // Standard VGA
1601 case 0x03: // Standard VGA
1602 case 0x04: // Standard VGA
1603 case 0x05: // Standard VGA
1604 case 0x06: // Standard VGA
1605 case 0x07: // Standard VGA
1606 case 0x08: // Standard VGA
1607 case 0x09: // Standard VGA
1608 case 0x0a: // Standard VGA
1609 case 0x0b: // Standard VGA
1610 case 0x0c: // Standard VGA
1611 case 0x0d: // Standard VGA
1612 case 0x0e: // Standard VGA
1613 case 0x0f: // Standard VGA
1614 case 0x10: // Standard VGA
1615 case 0x11: // Standard VGA
1616 case 0x12: // Standard VGA
1617 case 0x13: // Standard VGA
1618 case 0x14: // Standard VGA
1619 case 0x15: // Standard VGA
1620 case 0x16: // Standard VGA
1621 case 0x17: // Standard VGA
1622 case 0x18: // Standard VGA
1623 return CIRRUS_HOOK_NOT_HANDLED;
ca896ef3 1624 case 0x24: // Attribute Controller Toggle Readback (R)
4e12cd94 1625 *reg_value = (s->vga.ar_flip_flop << 7);
ca896ef3 1626 break;
e6e5ad80
FB		 1627 case 0x19: // Interlace End
1628 case 0x1a: // Miscellaneous Control
1629 case 0x1b: // Extended Display Control
1630 case 0x1c: // Sync Adjust and Genlock
1631 case 0x1d: // Overlay Extended Control
1632 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1633 case 0x25: // Part Status
1634 case 0x27: // Part ID (R)
4e12cd94 1635 *reg_value = s->vga.cr[reg_index];
e6e5ad80
FB		 1636 break;
1637 case 0x26: // Attribute Controller Index Readback (R)
4e12cd94 1638 *reg_value = s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1639 break;
1640 default:
1641#ifdef DEBUG_CIRRUS
1642 printf("cirrus: inport cr_index %02x\n", reg_index);
1643 *reg_value = 0xff;
1644#endif
1645 break;
1646 }
1647
1648 return CIRRUS_HOOK_HANDLED;
1649}
1650
1651static int
1652cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1653{
1654 switch (reg_index) {
1655 case 0x00: // Standard VGA
1656 case 0x01: // Standard VGA
1657 case 0x02: // Standard VGA
1658 case 0x03: // Standard VGA
1659 case 0x04: // Standard VGA
1660 case 0x05: // Standard VGA
1661 case 0x06: // Standard VGA
1662 case 0x07: // Standard VGA
1663 case 0x08: // Standard VGA
1664 case 0x09: // Standard VGA
1665 case 0x0a: // Standard VGA
1666 case 0x0b: // Standard VGA
1667 case 0x0c: // Standard VGA
1668 case 0x0d: // Standard VGA
1669 case 0x0e: // Standard VGA
1670 case 0x0f: // Standard VGA
1671 case 0x10: // Standard VGA
1672 case 0x11: // Standard VGA
1673 case 0x12: // Standard VGA
1674 case 0x13: // Standard VGA
1675 case 0x14: // Standard VGA
1676 case 0x15: // Standard VGA
1677 case 0x16: // Standard VGA
1678 case 0x17: // Standard VGA
1679 case 0x18: // Standard VGA
1680 return CIRRUS_HOOK_NOT_HANDLED;
1681 case 0x19: // Interlace End
1682 case 0x1a: // Miscellaneous Control
1683 case 0x1b: // Extended Display Control
1684 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1685 case 0x1d: // Overlay Extended Control
4e12cd94 1686 s->vga.cr[reg_index] = reg_value;
e6e5ad80
FB		 1687#ifdef DEBUG_CIRRUS
1688 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1689 reg_index, reg_value);
1690#endif
1691 break;
1692 case 0x22: // Graphics Data Latches Readback (R)
1693 case 0x24: // Attribute Controller Toggle Readback (R)
1694 case 0x26: // Attribute Controller Index Readback (R)
1695 case 0x27: // Part ID (R)
1696 break;
e6e5ad80
FB		 1697 case 0x25: // Part Status
1698 default:
1699#ifdef DEBUG_CIRRUS
1700 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1701 reg_value);
1702#endif
1703 break;
1704 }
1705
1706 return CIRRUS_HOOK_HANDLED;
1707}
1708
1709/***************************************
1710 *
1711 * memory-mapped I/O (bitblt)
1712 *
1713 ***************************************/
1714
1715static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1716{
1717 int value = 0xff;
1718
1719 switch (address) {
1720 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1721 cirrus_hook_read_gr(s, 0x00, &value);
1722 break;
1723 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1724 cirrus_hook_read_gr(s, 0x10, &value);
1725 break;
1726 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1727 cirrus_hook_read_gr(s, 0x12, &value);
1728 break;
1729 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1730 cirrus_hook_read_gr(s, 0x14, &value);
1731 break;
1732 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1733 cirrus_hook_read_gr(s, 0x01, &value);
1734 break;
1735 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1736 cirrus_hook_read_gr(s, 0x11, &value);
1737 break;
1738 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1739 cirrus_hook_read_gr(s, 0x13, &value);
1740 break;
1741 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1742 cirrus_hook_read_gr(s, 0x15, &value);
1743 break;
1744 case (CIRRUS_MMIO_BLTWIDTH + 0):
1745 cirrus_hook_read_gr(s, 0x20, &value);
1746 break;
1747 case (CIRRUS_MMIO_BLTWIDTH + 1):
1748 cirrus_hook_read_gr(s, 0x21, &value);
1749 break;
1750 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1751 cirrus_hook_read_gr(s, 0x22, &value);
1752 break;
1753 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1754 cirrus_hook_read_gr(s, 0x23, &value);
1755 break;
1756 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1757 cirrus_hook_read_gr(s, 0x24, &value);
1758 break;
1759 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1760 cirrus_hook_read_gr(s, 0x25, &value);
1761 break;
1762 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1763 cirrus_hook_read_gr(s, 0x26, &value);
1764 break;
1765 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1766 cirrus_hook_read_gr(s, 0x27, &value);
1767 break;
1768 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1769 cirrus_hook_read_gr(s, 0x28, &value);
1770 break;
1771 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1772 cirrus_hook_read_gr(s, 0x29, &value);
1773 break;
1774 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1775 cirrus_hook_read_gr(s, 0x2a, &value);
1776 break;
1777 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1778 cirrus_hook_read_gr(s, 0x2c, &value);
1779 break;
1780 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1781 cirrus_hook_read_gr(s, 0x2d, &value);
1782 break;
1783 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1784 cirrus_hook_read_gr(s, 0x2e, &value);
1785 break;
1786 case CIRRUS_MMIO_BLTWRITEMASK:
1787 cirrus_hook_read_gr(s, 0x2f, &value);
1788 break;
1789 case CIRRUS_MMIO_BLTMODE:
1790 cirrus_hook_read_gr(s, 0x30, &value);
1791 break;
1792 case CIRRUS_MMIO_BLTROP:
1793 cirrus_hook_read_gr(s, 0x32, &value);
1794 break;
a21ae81d
FB		 1795 case CIRRUS_MMIO_BLTMODEEXT:
1796 cirrus_hook_read_gr(s, 0x33, &value);
1797 break;
e6e5ad80
FB		 1798 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1799 cirrus_hook_read_gr(s, 0x34, &value);
1800 break;
1801 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1802 cirrus_hook_read_gr(s, 0x35, &value);
1803 break;
1804 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1805 cirrus_hook_read_gr(s, 0x38, &value);
1806 break;
1807 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1808 cirrus_hook_read_gr(s, 0x39, &value);
1809 break;
1810 case CIRRUS_MMIO_BLTSTATUS:
1811 cirrus_hook_read_gr(s, 0x31, &value);
1812 break;
1813 default:
1814#ifdef DEBUG_CIRRUS
1815 printf("cirrus: mmio read - address 0x%04x\n", address);
1816#endif
1817 break;
1818 }
1819
1820 return (uint8_t) value;
1821}
1822
1823static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1824 uint8_t value)
1825{
1826 switch (address) {
1827 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1828 cirrus_hook_write_gr(s, 0x00, value);
1829 break;
1830 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1831 cirrus_hook_write_gr(s, 0x10, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1834 cirrus_hook_write_gr(s, 0x12, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1837 cirrus_hook_write_gr(s, 0x14, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1840 cirrus_hook_write_gr(s, 0x01, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1843 cirrus_hook_write_gr(s, 0x11, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1846 cirrus_hook_write_gr(s, 0x13, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1849 cirrus_hook_write_gr(s, 0x15, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTWIDTH + 0):
1852 cirrus_hook_write_gr(s, 0x20, value);
1853 break;
1854 case (CIRRUS_MMIO_BLTWIDTH + 1):
1855 cirrus_hook_write_gr(s, 0x21, value);
1856 break;
1857 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1858 cirrus_hook_write_gr(s, 0x22, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1861 cirrus_hook_write_gr(s, 0x23, value);
1862 break;
1863 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1864 cirrus_hook_write_gr(s, 0x24, value);
1865 break;
1866 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1867 cirrus_hook_write_gr(s, 0x25, value);
1868 break;
1869 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1870 cirrus_hook_write_gr(s, 0x26, value);
1871 break;
1872 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1873 cirrus_hook_write_gr(s, 0x27, value);
1874 break;
1875 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1876 cirrus_hook_write_gr(s, 0x28, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1879 cirrus_hook_write_gr(s, 0x29, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1882 cirrus_hook_write_gr(s, 0x2a, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1885 /* ignored */
1886 break;
1887 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1888 cirrus_hook_write_gr(s, 0x2c, value);
1889 break;
1890 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1891 cirrus_hook_write_gr(s, 0x2d, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1894 cirrus_hook_write_gr(s, 0x2e, value);
1895 break;
1896 case CIRRUS_MMIO_BLTWRITEMASK:
1897 cirrus_hook_write_gr(s, 0x2f, value);
1898 break;
1899 case CIRRUS_MMIO_BLTMODE:
1900 cirrus_hook_write_gr(s, 0x30, value);
1901 break;
1902 case CIRRUS_MMIO_BLTROP:
1903 cirrus_hook_write_gr(s, 0x32, value);
1904 break;
a21ae81d
FB		 1905 case CIRRUS_MMIO_BLTMODEEXT:
1906 cirrus_hook_write_gr(s, 0x33, value);
1907 break;
e6e5ad80
FB		 1908 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1909 cirrus_hook_write_gr(s, 0x34, value);
1910 break;
1911 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1912 cirrus_hook_write_gr(s, 0x35, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1915 cirrus_hook_write_gr(s, 0x38, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1918 cirrus_hook_write_gr(s, 0x39, value);
1919 break;
1920 case CIRRUS_MMIO_BLTSTATUS:
1921 cirrus_hook_write_gr(s, 0x31, value);
1922 break;
1923 default:
1924#ifdef DEBUG_CIRRUS
1925 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1926 address, value);
1927#endif
1928 break;
1929 }
1930}
1931
e6e5ad80
FB		 1932/***************************************
1933 *
1934 * write mode 4/5
1935 *
1936 * assume TARGET_PAGE_SIZE >= 16
1937 *
1938 ***************************************/
1939
1940static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1941 unsigned mode,
1942 unsigned offset,
1943 uint32_t mem_value)
1944{
1945 int x;
1946 unsigned val = mem_value;
1947 uint8_t *dst;
1948
4e12cd94 1949 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1950 for (x = 0; x < 8; x++) {
1951 if (val & 0x80) {
0b74ed78 1952 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1953 } else if (mode == 5) {
0b74ed78 1954 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1955 }
1956 val <<= 1;
0b74ed78 1957 dst++;
e6e5ad80 1958 }
4e12cd94
AK		 1959 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1960 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
e6e5ad80
FB		 1961}
1962
1963static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1964 unsigned mode,
1965 unsigned offset,
1966 uint32_t mem_value)
1967{
1968 int x;
1969 unsigned val = mem_value;
1970 uint8_t *dst;
1971
4e12cd94 1972 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1973 for (x = 0; x < 8; x++) {
1974 if (val & 0x80) {
0b74ed78 1975 *dst = s->cirrus_shadow_gr1;
4e12cd94 1976 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1977 } else if (mode == 5) {
0b74ed78 1978 *dst = s->cirrus_shadow_gr0;
4e12cd94 1979 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1980 }
1981 val <<= 1;
0b74ed78 1982 dst += 2;
e6e5ad80 1983 }
4e12cd94
AK		 1984 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1985 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
e6e5ad80
FB		 1986}
1987
1988/***************************************
1989 *
1990 * memory access between 0xa0000-0xbffff
1991 *
1992 ***************************************/
1993
1994static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1995{
1996 CirrusVGAState *s = opaque;
1997 unsigned bank_index;
1998 unsigned bank_offset;
1999 uint32_t val;
2000
4e12cd94 2001 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2002 return vga_mem_readb(s, addr);
2003 }
2004
aeb3c85f
FB		 2005 addr &= 0x1ffff;
2006
e6e5ad80
FB		 2007 if (addr < 0x10000) {
2008 /* XXX handle bitblt */
2009 /* video memory */
2010 bank_index = addr >> 15;
2011 bank_offset = addr & 0x7fff;
2012 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2013 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2014 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2015 bank_offset <<= 4;
4e12cd94 2016 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2017 bank_offset <<= 3;
2018 }
2019 bank_offset &= s->cirrus_addr_mask;
4e12cd94 2020 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 2021 } else
2022 val = 0xff;
2023 } else if (addr >= 0x18000 && addr < 0x18100) {
2024 /* memory-mapped I/O */
2025 val = 0xff;
4e12cd94 2026 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2027 val = cirrus_mmio_blt_read(s, addr & 0xff);
2028 }
2029 } else {
2030 val = 0xff;
2031#ifdef DEBUG_CIRRUS
2032 printf("cirrus: mem_readb %06x\n", addr);
2033#endif
2034 }
2035 return val;
2036}
2037
2038static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2039{
2040 uint32_t v;
2041#ifdef TARGET_WORDS_BIGENDIAN
2042 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2043 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2044#else
2045 v = cirrus_vga_mem_readb(opaque, addr);
2046 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2047#endif
2048 return v;
2049}
2050
2051static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2052{
2053 uint32_t v;
2054#ifdef TARGET_WORDS_BIGENDIAN
2055 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2057 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2058 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2059#else
2060 v = cirrus_vga_mem_readb(opaque, addr);
2061 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2062 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2063 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2064#endif
2065 return v;
2066}
2067
5fafdf24 2068static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2069 uint32_t mem_value)
2070{
2071 CirrusVGAState *s = opaque;
2072 unsigned bank_index;
2073 unsigned bank_offset;
2074 unsigned mode;
2075
4e12cd94 2076 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2077 vga_mem_writeb(s, addr, mem_value);
2078 return;
2079 }
2080
aeb3c85f
FB		 2081 addr &= 0x1ffff;
2082
e6e5ad80
FB		 2083 if (addr < 0x10000) {
2084 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2085 /* bitblt */
2086 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2087 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2088 cirrus_bitblt_cputovideo_next(s);
2089 }
2090 } else {
2091 /* video memory */
2092 bank_index = addr >> 15;
2093 bank_offset = addr & 0x7fff;
2094 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2095 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2096 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2097 bank_offset <<= 4;
4e12cd94 2098 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2099 bank_offset <<= 3;
2100 }
2101 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2102 mode = s->vga.gr[0x05] & 0x7;
2103 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2104 *(s->vga.vram_ptr + bank_offset) = mem_value;
2105 cpu_physical_memory_set_dirty(s->vga.vram_offset +
e6e5ad80
FB		 2106 bank_offset);
2107 } else {
4e12cd94 2108 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2109 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2110 bank_offset,
2111 mem_value);
2112 } else {
2113 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2114 bank_offset,
2115 mem_value);
2116 }
2117 }
2118 }
2119 }
2120 } else if (addr >= 0x18000 && addr < 0x18100) {
2121 /* memory-mapped I/O */
4e12cd94 2122 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2123 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2124 }
2125 } else {
2126#ifdef DEBUG_CIRRUS
2127 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2128#endif
2129 }
2130}
2131
2132static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2133{
2134#ifdef TARGET_WORDS_BIGENDIAN
2135 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2136 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2137#else
2138 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2139 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2140#endif
2141}
2142
2143static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2144{
2145#ifdef TARGET_WORDS_BIGENDIAN
2146 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2147 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2148 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2150#else
2151 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2153 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2154 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2155#endif
2156}
2157
2158static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2159 cirrus_vga_mem_readb,
2160 cirrus_vga_mem_readw,
2161 cirrus_vga_mem_readl,
2162};
2163
2164static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2165 cirrus_vga_mem_writeb,
2166 cirrus_vga_mem_writew,
2167 cirrus_vga_mem_writel,
2168};
2169
a5082316
FB		 2170/***************************************
2171 *
2172 * hardware cursor
2173 *
2174 ***************************************/
2175
2176static inline void invalidate_cursor1(CirrusVGAState *s)
2177{
2178 if (s->last_hw_cursor_size) {
4e12cd94 2179 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2180 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2181 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2182 }
2183}
2184
2185static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2186{
2187 const uint8_t *src;
2188 uint32_t content;
2189 int y, y_min, y_max;
2190
4e12cd94
AK		 2191 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2192 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2193 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2194 y_min = 64;
2195 y_max = -1;
2196 for(y = 0; y < 64; y++) {
2197 content = ((uint32_t *)src)[0] |
2198 ((uint32_t *)src)[1] |
2199 ((uint32_t *)src)[2] |
2200 ((uint32_t *)src)[3];
2201 if (content) {
2202 if (y < y_min)
2203 y_min = y;
2204 if (y > y_max)
2205 y_max = y;
2206 }
2207 src += 16;
2208 }
2209 } else {
4e12cd94 2210 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2211 y_min = 32;
2212 y_max = -1;
2213 for(y = 0; y < 32; y++) {
2214 content = ((uint32_t *)src)[0] |
2215 ((uint32_t *)(src + 128))[0];
2216 if (content) {
2217 if (y < y_min)
2218 y_min = y;
2219 if (y > y_max)
2220 y_max = y;
2221 }
2222 src += 4;
2223 }
2224 }
2225 if (y_min > y_max) {
2226 s->last_hw_cursor_y_start = 0;
2227 s->last_hw_cursor_y_end = 0;
2228 } else {
2229 s->last_hw_cursor_y_start = y_min;
2230 s->last_hw_cursor_y_end = y_max + 1;
2231 }
2232}
2233
2234/* NOTE: we do not currently handle the cursor bitmap change, so we
2235 update the cursor only if it moves. */
2236static void cirrus_cursor_invalidate(VGAState *s1)
2237{
4e12cd94 2238 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2239 int size;
2240
4e12cd94 2241 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2242 size = 0;
2243 } else {
4e12cd94 2244 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2245 size = 64;
2246 else
2247 size = 32;
2248 }
2249 /* invalidate last cursor and new cursor if any change */
2250 if (s->last_hw_cursor_size != size ||
2251 s->last_hw_cursor_x != s->hw_cursor_x ||
2252 s->last_hw_cursor_y != s->hw_cursor_y) {
2253
2254 invalidate_cursor1(s);
3b46e624 2255
a5082316
FB		 2256 s->last_hw_cursor_size = size;
2257 s->last_hw_cursor_x = s->hw_cursor_x;
2258 s->last_hw_cursor_y = s->hw_cursor_y;
2259 /* compute the real cursor min and max y */
2260 cirrus_cursor_compute_yrange(s);
2261 invalidate_cursor1(s);
2262 }
2263}
2264
2265static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2266{
4e12cd94 2267 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2268 int w, h, bpp, x1, x2, poffset;
2269 unsigned int color0, color1;
2270 const uint8_t *palette, *src;
2271 uint32_t content;
3b46e624 2272
4e12cd94 2273 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2274 return;
2275 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2276 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2277 h = 64;
2278 } else {
2279 h = 32;
2280 }
2281 if (scr_y < s->hw_cursor_y ||
2282 scr_y >= (s->hw_cursor_y + h))
2283 return;
3b46e624 2284
4e12cd94
AK		 2285 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2286 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2288 src += (scr_y - s->hw_cursor_y) * 16;
2289 poffset = 8;
2290 content = ((uint32_t *)src)[0] |
2291 ((uint32_t *)src)[1] |
2292 ((uint32_t *)src)[2] |
2293 ((uint32_t *)src)[3];
2294 } else {
4e12cd94 2295 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2296 src += (scr_y - s->hw_cursor_y) * 4;
2297 poffset = 128;
2298 content = ((uint32_t *)src)[0] |
2299 ((uint32_t *)(src + 128))[0];
2300 }
2301 /* if nothing to draw, no need to continue */
2302 if (!content)
2303 return;
2304 w = h;
2305
2306 x1 = s->hw_cursor_x;
4e12cd94 2307 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2308 return;
2309 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2310 if (x2 > s->vga.last_scr_width)
2311 x2 = s->vga.last_scr_width;
a5082316
FB		 2312 w = x2 - x1;
2313 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2314 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2315 c6_to_8(palette[0x0 * 3 + 1]),
2316 c6_to_8(palette[0x0 * 3 + 2]));
2317 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2318 c6_to_8(palette[0xf * 3 + 1]),
2319 c6_to_8(palette[0xf * 3 + 2]));
2320 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2321 d1 += x1 * bpp;
4e12cd94 2322 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2323 default:
2324 break;
2325 case 8:
2326 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2327 break;
2328 case 15:
2329 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2330 break;
2331 case 16:
2332 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2333 break;
2334 case 32:
2335 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2336 break;
2337 }
2338}
2339
e6e5ad80
FB		 2340/***************************************
2341 *
2342 * LFB memory access
2343 *
2344 ***************************************/
2345
2346static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2347{
2348 CirrusVGAState *s = (CirrusVGAState *) opaque;
2349 uint32_t ret;
2350
e6e5ad80
FB		 2351 addr &= s->cirrus_addr_mask;
2352
4e12cd94 2353 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2354 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2355 /* memory-mapped I/O */
2356 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2357 } else if (0) {
2358 /* XXX handle bitblt */
2359 ret = 0xff;
2360 } else {
2361 /* video memory */
4e12cd94 2362 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2363 addr <<= 4;
4e12cd94 2364 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2365 addr <<= 3;
2366 }
2367 addr &= s->cirrus_addr_mask;
4e12cd94 2368 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2369 }
2370
2371 return ret;
2372}
2373
2374static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2375{
2376 uint32_t v;
2377#ifdef TARGET_WORDS_BIGENDIAN
2378 v = cirrus_linear_readb(opaque, addr) << 8;
2379 v |= cirrus_linear_readb(opaque, addr + 1);
2380#else
2381 v = cirrus_linear_readb(opaque, addr);
2382 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2383#endif
2384 return v;
2385}
2386
2387static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2388{
2389 uint32_t v;
2390#ifdef TARGET_WORDS_BIGENDIAN
2391 v = cirrus_linear_readb(opaque, addr) << 24;
2392 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2393 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2394 v |= cirrus_linear_readb(opaque, addr + 3);
2395#else
2396 v = cirrus_linear_readb(opaque, addr);
2397 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2398 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2399 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2400#endif
2401 return v;
2402}
2403
2404static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2405 uint32_t val)
2406{
2407 CirrusVGAState *s = (CirrusVGAState *) opaque;
2408 unsigned mode;
2409
2410 addr &= s->cirrus_addr_mask;
3b46e624 2411
4e12cd94 2412 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2413 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2414 /* memory-mapped I/O */
2415 cirrus_mmio_blt_write(s, addr & 0xff, val);
2416 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2417 /* bitblt */
2418 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2419 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2420 cirrus_bitblt_cputovideo_next(s);
2421 }
2422 } else {
2423 /* video memory */
4e12cd94 2424 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2425 addr <<= 4;
4e12cd94 2426 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2427 addr <<= 3;
2428 }
2429 addr &= s->cirrus_addr_mask;
2430
4e12cd94
AK		 2431 mode = s->vga.gr[0x05] & 0x7;
2432 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2433 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2434 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
e6e5ad80 2435 } else {
4e12cd94 2436 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2437 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2438 } else {
2439 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2440 }
2441 }
2442 }
2443}
2444
2445static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2446 uint32_t val)
2447{
2448#ifdef TARGET_WORDS_BIGENDIAN
2449 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2450 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2451#else
2452 cirrus_linear_writeb(opaque, addr, val & 0xff);
2453 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2454#endif
2455}
2456
2457static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2458 uint32_t val)
2459{
2460#ifdef TARGET_WORDS_BIGENDIAN
2461 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2462 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2464 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2465#else
2466 cirrus_linear_writeb(opaque, addr, val & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2468 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2469 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2470#endif
2471}
2472
2473
2474static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2475 cirrus_linear_readb,
2476 cirrus_linear_readw,
2477 cirrus_linear_readl,
2478};
2479
2480static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2481 cirrus_linear_writeb,
2482 cirrus_linear_writew,
2483 cirrus_linear_writel,
2484};
2485
a5082316
FB		 2486/***************************************
2487 *
2488 * system to screen memory access
2489 *
2490 ***************************************/
2491
2492
2493static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2494{
2495 uint32_t ret;
2496
2497 /* XXX handle bitblt */
2498 ret = 0xff;
2499 return ret;
2500}
2501
2502static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2503{
2504 uint32_t v;
2505#ifdef TARGET_WORDS_BIGENDIAN
2506 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2507 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2508#else
2509 v = cirrus_linear_bitblt_readb(opaque, addr);
2510 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2511#endif
2512 return v;
2513}
2514
2515static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2516{
2517 uint32_t v;
2518#ifdef TARGET_WORDS_BIGENDIAN
2519 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2520 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2521 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2522 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2523#else
2524 v = cirrus_linear_bitblt_readb(opaque, addr);
2525 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2526 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2527 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2528#endif
2529 return v;
2530}
2531
2532static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2533 uint32_t val)
2534{
2535 CirrusVGAState *s = (CirrusVGAState *) opaque;
2536
2537 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2538 /* bitblt */
2539 *s->cirrus_srcptr++ = (uint8_t) val;
2540 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2541 cirrus_bitblt_cputovideo_next(s);
2542 }
2543 }
2544}
2545
2546static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2547 uint32_t val)
2548{
2549#ifdef TARGET_WORDS_BIGENDIAN
2550 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2551 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2552#else
2553 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2554 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2555#endif
2556}
2557
2558static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2559 uint32_t val)
2560{
2561#ifdef TARGET_WORDS_BIGENDIAN
2562 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2563 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2564 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2565 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2566#else
2567 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2568 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2569 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2570 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2571#endif
2572}
2573
2574
2575static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2576 cirrus_linear_bitblt_readb,
2577 cirrus_linear_bitblt_readw,
2578 cirrus_linear_bitblt_readl,
2579};
2580
2581static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2582 cirrus_linear_bitblt_writeb,
2583 cirrus_linear_bitblt_writew,
2584 cirrus_linear_bitblt_writel,
2585};
2586
2bec46dc
AL		 2587static void map_linear_vram(CirrusVGAState *s)
2588{
4e12cd94
AK		 2589 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2590 s->vga.map_addr = s->vga.lfb_addr;
2591 s->vga.map_end = s->vga.lfb_end;
2592 cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2bec46dc
AL		 2593 }
2594
4e12cd94 2595 if (!s->vga.map_addr)
2bec46dc
AL		 2596 return;
2597
4e12cd94 2598 s->vga.lfb_vram_mapped = 0;
2bec46dc
AL		 2599
2600 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2601 && !((s->vga.sr[0x07] & 0x01) == 0)
2602 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2603 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc
AL		 2604
2605 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
4e12cd94 2606 (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2bec46dc 2607 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
4e12cd94 2608 (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2bec46dc 2609
4e12cd94 2610 s->vga.lfb_vram_mapped = 1;
2bec46dc
AL		 2611 }
2612 else {
7cff316e 2613 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2614 s->vga.vga_io_memory);
2bec46dc
AL		 2615 }
2616
4e12cd94 2617 vga_dirty_log_start(&s->vga);
2bec46dc
AL		 2618}
2619
2620static void unmap_linear_vram(CirrusVGAState *s)
2621{
4e12cd94
AK		 2622 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2623 s->vga.map_addr = s->vga.map_end = 0;
2bec46dc
AL		 2624
2625 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2626 s->vga.vga_io_memory);
2bec46dc
AL		 2627}
2628
8926b517
FB		 2629/* Compute the memory access functions */
2630static void cirrus_update_memory_access(CirrusVGAState *s)
2631{
2632 unsigned mode;
2633
4e12cd94 2634 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2635 goto generic_io;
2636 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2637 goto generic_io;
2638 } else {
4e12cd94 2639 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2640 goto generic_io;
4e12cd94 2641 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2642 goto generic_io;
2643 }
3b46e624 2644
4e12cd94
AK		 2645 mode = s->vga.gr[0x05] & 0x7;
2646 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2647 map_linear_vram(s);
8926b517
FB		 2648 } else {
2649 generic_io:
2bec46dc 2650 unmap_linear_vram(s);
8926b517
FB		 2651 }
2652 }
2653}
2654
2655
e6e5ad80
FB		 2656/* I/O ports */
2657
2658static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2659{
2660 CirrusVGAState *s = opaque;
2661 int val, index;
2662
2663 /* check port range access depending on color/monochrome mode */
4e12cd94 2664 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
e6e5ad80 2665 || (addr >= 0x3d0 && addr <= 0x3df
4e12cd94 2666 && !(s->vga.msr & MSR_COLOR_EMULATION))) {
e6e5ad80
FB		 2667 val = 0xff;
2668 } else {
2669 switch (addr) {
2670 case 0x3c0:
4e12cd94
AK		 2671 if (s->vga.ar_flip_flop == 0) {
2672 val = s->vga.ar_index;
e6e5ad80
FB		 2673 } else {
2674 val = 0;
2675 }
2676 break;
2677 case 0x3c1:
4e12cd94 2678 index = s->vga.ar_index & 0x1f;
e6e5ad80 2679 if (index < 21)
4e12cd94 2680 val = s->vga.ar[index];
e6e5ad80
FB		 2681 else
2682 val = 0;
2683 break;
2684 case 0x3c2:
4e12cd94 2685 val = s->vga.st00;
e6e5ad80
FB		 2686 break;
2687 case 0x3c4:
4e12cd94 2688 val = s->vga.sr_index;
e6e5ad80
FB		 2689 break;
2690 case 0x3c5:
4e12cd94 2691 if (cirrus_hook_read_sr(s, s->vga.sr_index, &val))
e6e5ad80 2692 break;
4e12cd94 2693 val = s->vga.sr[s->vga.sr_index];
e6e5ad80 2694#ifdef DEBUG_VGA_REG
4e12cd94 2695 printf("vga: read SR%x = 0x%02x\n", s->vga.sr_index, val);
e6e5ad80
FB		 2696#endif
2697 break;
2698 case 0x3c6:
2699 cirrus_read_hidden_dac(s, &val);
2700 break;
2701 case 0x3c7:
4e12cd94 2702 val = s->vga.dac_state;
e6e5ad80 2703 break;
ae184e4a 2704 case 0x3c8:
4e12cd94 2705 val = s->vga.dac_write_index;
ae184e4a
FB		 2706 s->cirrus_hidden_dac_lockindex = 0;
2707 break;
2708 case 0x3c9:
e6e5ad80
FB		 2709 if (cirrus_hook_read_palette(s, &val))
2710 break;
4e12cd94
AK		 2711 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
2712 if (++s->vga.dac_sub_index == 3) {
2713 s->vga.dac_sub_index = 0;
2714 s->vga.dac_read_index++;
e6e5ad80
FB		 2715 }
2716 break;
2717 case 0x3ca:
4e12cd94 2718 val = s->vga.fcr;
e6e5ad80
FB		 2719 break;
2720 case 0x3cc:
4e12cd94 2721 val = s->vga.msr;
e6e5ad80
FB		 2722 break;
2723 case 0x3ce:
4e12cd94 2724 val = s->vga.gr_index;
e6e5ad80
FB		 2725 break;
2726 case 0x3cf:
4e12cd94 2727 if (cirrus_hook_read_gr(s, s->vga.gr_index, &val))
e6e5ad80 2728 break;
4e12cd94 2729 val = s->vga.gr[s->vga.gr_index];
e6e5ad80 2730#ifdef DEBUG_VGA_REG
4e12cd94 2731 printf("vga: read GR%x = 0x%02x\n", s->vga.gr_index, val);
e6e5ad80
FB		 2732#endif
2733 break;
2734 case 0x3b4:
2735 case 0x3d4:
4e12cd94 2736 val = s->vga.cr_index;
e6e5ad80
FB		 2737 break;
2738 case 0x3b5:
2739 case 0x3d5:
4e12cd94 2740 if (cirrus_hook_read_cr(s, s->vga.cr_index, &val))
e6e5ad80 2741 break;
4e12cd94 2742 val = s->vga.cr[s->vga.cr_index];
e6e5ad80 2743#ifdef DEBUG_VGA_REG
4e12cd94 2744 printf("vga: read CR%x = 0x%02x\n", s->vga.cr_index, val);
e6e5ad80
FB		 2745#endif
2746 break;
2747 case 0x3ba:
2748 case 0x3da:
2749 /* just toggle to fool polling */
4e12cd94
AK		 2750 val = s->vga.st01 = s->vga.retrace(&s->vga);
2751 s->vga.ar_flip_flop = 0;
e6e5ad80
FB		 2752 break;
2753 default:
2754 val = 0x00;
2755 break;
2756 }
2757 }
2758#if defined(DEBUG_VGA)
2759 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2760#endif
2761 return val;
2762}
2763
2764static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2765{
2766 CirrusVGAState *s = opaque;
2767 int index;
2768
2769 /* check port range access depending on color/monochrome mode */
4e12cd94 2770 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
e6e5ad80 2771 || (addr >= 0x3d0 && addr <= 0x3df
4e12cd94 2772 && !(s->vga.msr & MSR_COLOR_EMULATION)))
e6e5ad80
FB		 2773 return;
2774
2775#ifdef DEBUG_VGA
2776 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2777#endif
2778
2779 switch (addr) {
2780 case 0x3c0:
4e12cd94 2781 if (s->vga.ar_flip_flop == 0) {
e6e5ad80 2782 val &= 0x3f;
4e12cd94 2783 s->vga.ar_index = val;
e6e5ad80 2784 } else {
4e12cd94 2785 index = s->vga.ar_index & 0x1f;
e6e5ad80
FB		 2786 switch (index) {
2787 case 0x00 ... 0x0f:
4e12cd94 2788 s->vga.ar[index] = val & 0x3f;
e6e5ad80
FB		 2789 break;
2790 case 0x10:
4e12cd94 2791 s->vga.ar[index] = val & ~0x10;
e6e5ad80
FB		 2792 break;
2793 case 0x11:
4e12cd94 2794 s->vga.ar[index] = val;
e6e5ad80
FB		 2795 break;
2796 case 0x12:
4e12cd94 2797 s->vga.ar[index] = val & ~0xc0;
e6e5ad80
FB		 2798 break;
2799 case 0x13:
4e12cd94 2800 s->vga.ar[index] = val & ~0xf0;
e6e5ad80
FB		 2801 break;
2802 case 0x14:
4e12cd94 2803 s->vga.ar[index] = val & ~0xf0;
e6e5ad80
FB		 2804 break;
2805 default:
2806 break;
2807 }
2808 }
4e12cd94 2809 s->vga.ar_flip_flop ^= 1;
e6e5ad80
FB		 2810 break;
2811 case 0x3c2:
4e12cd94
AK		 2812 s->vga.msr = val & ~0x10;
2813 s->vga.update_retrace_info(&s->vga);
e6e5ad80
FB		 2814 break;
2815 case 0x3c4:
4e12cd94 2816 s->vga.sr_index = val;
e6e5ad80
FB		 2817 break;
2818 case 0x3c5:
4e12cd94 2819 if (cirrus_hook_write_sr(s, s->vga.sr_index, val))
e6e5ad80
FB		 2820 break;
2821#ifdef DEBUG_VGA_REG
4e12cd94 2822 printf("vga: write SR%x = 0x%02x\n", s->vga.sr_index, val);
e6e5ad80 2823#endif
4e12cd94
AK		 2824 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
2825 if (s->vga.sr_index == 1) s->vga.update_retrace_info(&s->vga);
e6e5ad80
FB		 2826 break;
2827 case 0x3c6:
2828 cirrus_write_hidden_dac(s, val);
2829 break;
2830 case 0x3c7:
4e12cd94
AK		 2831 s->vga.dac_read_index = val;
2832 s->vga.dac_sub_index = 0;
2833 s->vga.dac_state = 3;
e6e5ad80
FB		 2834 break;
2835 case 0x3c8:
4e12cd94
AK		 2836 s->vga.dac_write_index = val;
2837 s->vga.dac_sub_index = 0;
2838 s->vga.dac_state = 0;
e6e5ad80
FB		 2839 break;
2840 case 0x3c9:
2841 if (cirrus_hook_write_palette(s, val))
2842 break;
4e12cd94
AK		 2843 s->vga.dac_cache[s->vga.dac_sub_index] = val;
2844 if (++s->vga.dac_sub_index == 3) {
2845 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
2846 s->vga.dac_sub_index = 0;
2847 s->vga.dac_write_index++;
e6e5ad80
FB		 2848 }
2849 break;
2850 case 0x3ce:
4e12cd94 2851 s->vga.gr_index = val;
e6e5ad80
FB		 2852 break;
2853 case 0x3cf:
4e12cd94 2854 if (cirrus_hook_write_gr(s, s->vga.gr_index, val))
e6e5ad80
FB		 2855 break;
2856#ifdef DEBUG_VGA_REG
4e12cd94 2857 printf("vga: write GR%x = 0x%02x\n", s->vga.gr_index, val);
e6e5ad80 2858#endif
4e12cd94 2859 s->vga.gr[s->vga.gr_index] = val & gr_mask[s->vga.gr_index];
e6e5ad80
FB		 2860 break;
2861 case 0x3b4:
2862 case 0x3d4:
4e12cd94 2863 s->vga.cr_index = val;
e6e5ad80
FB		 2864 break;
2865 case 0x3b5:
2866 case 0x3d5:
4e12cd94 2867 if (cirrus_hook_write_cr(s, s->vga.cr_index, val))
e6e5ad80
FB		 2868 break;
2869#ifdef DEBUG_VGA_REG
4e12cd94 2870 printf("vga: write CR%x = 0x%02x\n", s->vga.cr_index, val);
e6e5ad80
FB		 2871#endif
2872 /* handle CR0-7 protection */
4e12cd94 2873 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
e6e5ad80 2874 /* can always write bit 4 of CR7 */
4e12cd94
AK		 2875 if (s->vga.cr_index == 7)
2876 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (val & 0x10);
e6e5ad80
FB		 2877 return;
2878 }
4e12cd94 2879 switch (s->vga.cr_index) {
e6e5ad80
FB		 2880 case 0x01: /* horizontal display end */
2881 case 0x07:
2882 case 0x09:
2883 case 0x0c:
2884 case 0x0d:
e91c8a77 2885 case 0x12: /* vertical display end */
4e12cd94 2886 s->vga.cr[s->vga.cr_index] = val;
e6e5ad80
FB		 2887 break;
2888
2889 default:
4e12cd94 2890 s->vga.cr[s->vga.cr_index] = val;
e6e5ad80
FB		 2891 break;
2892 }
cb5a7aa8 2893
4e12cd94 2894 switch(s->vga.cr_index) {
cb5a7aa8 2895 case 0x00:
2896 case 0x04:
2897 case 0x05:
2898 case 0x06:
2899 case 0x07:
2900 case 0x11:
2901 case 0x17:
4e12cd94 2902 s->vga.update_retrace_info(&s->vga);
cb5a7aa8 2903 break;
2904 }
e6e5ad80
FB		 2905 break;
2906 case 0x3ba:
2907 case 0x3da:
4e12cd94 2908 s->vga.fcr = val & 0x10;
e6e5ad80
FB		 2909 break;
2910 }
2911}
2912
e36f36e1
FB		 2913/***************************************
2914 *
2915 * memory-mapped I/O access
2916 *
2917 ***************************************/
2918
2919static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2920{
2921 CirrusVGAState *s = (CirrusVGAState *) opaque;
2922
2923 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2924
2925 if (addr >= 0x100) {
2926 return cirrus_mmio_blt_read(s, addr - 0x100);
2927 } else {
2928 return vga_ioport_read(s, addr + 0x3c0);
2929 }
2930}
2931
2932static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2933{
2934 uint32_t v;
2935#ifdef TARGET_WORDS_BIGENDIAN
2936 v = cirrus_mmio_readb(opaque, addr) << 8;
2937 v |= cirrus_mmio_readb(opaque, addr + 1);
2938#else
2939 v = cirrus_mmio_readb(opaque, addr);
2940 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2941#endif
2942 return v;
2943}
2944
2945static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2946{
2947 uint32_t v;
2948#ifdef TARGET_WORDS_BIGENDIAN
2949 v = cirrus_mmio_readb(opaque, addr) << 24;
2950 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2951 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2952 v |= cirrus_mmio_readb(opaque, addr + 3);
2953#else
2954 v = cirrus_mmio_readb(opaque, addr);
2955 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2956 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2957 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2958#endif
2959 return v;
2960}
2961
2962static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2963 uint32_t val)
2964{
2965 CirrusVGAState *s = (CirrusVGAState *) opaque;
2966
2967 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2968
2969 if (addr >= 0x100) {
2970 cirrus_mmio_blt_write(s, addr - 0x100, val);
2971 } else {
2972 vga_ioport_write(s, addr + 0x3c0, val);
2973 }
2974}
2975
2976static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2977 uint32_t val)
2978{
2979#ifdef TARGET_WORDS_BIGENDIAN
2980 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2981 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2982#else
2983 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2984 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2985#endif
2986}
2987
2988static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2989 uint32_t val)
2990{
2991#ifdef TARGET_WORDS_BIGENDIAN
2992 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2993 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2994 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2995 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2996#else
2997 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2998 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2999 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3000 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3001#endif
3002}
3003
3004
3005static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3006 cirrus_mmio_readb,
3007 cirrus_mmio_readw,
3008 cirrus_mmio_readl,
3009};
3010
3011static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3012 cirrus_mmio_writeb,
3013 cirrus_mmio_writew,
3014 cirrus_mmio_writel,
3015};
3016
2c6ab832
FB		 3017/* load/save state */
3018
3019static void cirrus_vga_save(QEMUFile *f, void *opaque)
3020{
3021 CirrusVGAState *s = opaque;
3022
4e12cd94
AK		 3023 if (s->vga.pci_dev)
3024 pci_device_save(s->vga.pci_dev, f);
d2269f6f 3025
4e12cd94
AK		 3026 qemu_put_be32s(f, &s->vga.latch);
3027 qemu_put_8s(f, &s->vga.sr_index);
3028 qemu_put_buffer(f, s->vga.sr, 256);
3029 qemu_put_8s(f, &s->vga.gr_index);
2c6ab832
FB		 3030 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3031 qemu_put_8s(f, &s->cirrus_shadow_gr1);
4e12cd94
AK		 3032 qemu_put_buffer(f, s->vga.gr + 2, 254);
3033 qemu_put_8s(f, &s->vga.ar_index);
3034 qemu_put_buffer(f, s->vga.ar, 21);
3035 qemu_put_be32(f, s->vga.ar_flip_flop);
3036 qemu_put_8s(f, &s->vga.cr_index);
3037 qemu_put_buffer(f, s->vga.cr, 256);
3038 qemu_put_8s(f, &s->vga.msr);
3039 qemu_put_8s(f, &s->vga.fcr);
3040 qemu_put_8s(f, &s->vga.st00);
3041 qemu_put_8s(f, &s->vga.st01);
3042
3043 qemu_put_8s(f, &s->vga.dac_state);
3044 qemu_put_8s(f, &s->vga.dac_sub_index);
3045 qemu_put_8s(f, &s->vga.dac_read_index);
3046 qemu_put_8s(f, &s->vga.dac_write_index);
3047 qemu_put_buffer(f, s->vga.dac_cache, 3);
3048 qemu_put_buffer(f, s->vga.palette, 768);
3049
3050 qemu_put_be32(f, s->vga.bank_offset);
2c6ab832
FB		 3051
3052 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3053 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3054
3055 qemu_put_be32s(f, &s->hw_cursor_x);
3056 qemu_put_be32s(f, &s->hw_cursor_y);
3057 /* XXX: we do not save the bitblt state - we assume we do not save
3058 the state when the blitter is active */
3059}
3060
3061static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3062{
3063 CirrusVGAState *s = opaque;
d2269f6f 3064 int ret;
2c6ab832 3065
d2269f6f 3066 if (version_id > 2)
2c6ab832
FB		 3067 return -EINVAL;
3068
4e12cd94
AK		 3069 if (s->vga.pci_dev && version_id >= 2) {
3070 ret = pci_device_load(s->vga.pci_dev, f);
d2269f6f
FB		 3071 if (ret < 0)
3072 return ret;
3073 }
3074
4e12cd94
AK		 3075 qemu_get_be32s(f, &s->vga.latch);
3076 qemu_get_8s(f, &s->vga.sr_index);
3077 qemu_get_buffer(f, s->vga.sr, 256);
3078 qemu_get_8s(f, &s->vga.gr_index);
2c6ab832
FB		 3079 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3080 qemu_get_8s(f, &s->cirrus_shadow_gr1);
4e12cd94
AK		 3081 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3082 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3083 qemu_get_buffer(f, s->vga.gr + 2, 254);
3084 qemu_get_8s(f, &s->vga.ar_index);
3085 qemu_get_buffer(f, s->vga.ar, 21);
3086 s->vga.ar_flip_flop=qemu_get_be32(f);
3087 qemu_get_8s(f, &s->vga.cr_index);
3088 qemu_get_buffer(f, s->vga.cr, 256);
3089 qemu_get_8s(f, &s->vga.msr);
3090 qemu_get_8s(f, &s->vga.fcr);
3091 qemu_get_8s(f, &s->vga.st00);
3092 qemu_get_8s(f, &s->vga.st01);
3093
3094 qemu_get_8s(f, &s->vga.dac_state);
3095 qemu_get_8s(f, &s->vga.dac_sub_index);
3096 qemu_get_8s(f, &s->vga.dac_read_index);
3097 qemu_get_8s(f, &s->vga.dac_write_index);
3098 qemu_get_buffer(f, s->vga.dac_cache, 3);
3099 qemu_get_buffer(f, s->vga.palette, 768);
3100
3101 s->vga.bank_offset = qemu_get_be32(f);
2c6ab832
FB		 3102
3103 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3104 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3105
3106 qemu_get_be32s(f, &s->hw_cursor_x);
3107 qemu_get_be32s(f, &s->hw_cursor_y);
3108
2bec46dc 3109 cirrus_update_memory_access(s);
2c6ab832 3110 /* force refresh */
4e12cd94 3111 s->vga.graphic_mode = -1;
2c6ab832
FB		 3112 cirrus_update_bank_ptr(s, 0);
3113 cirrus_update_bank_ptr(s, 1);
3114 return 0;
3115}
3116
e6e5ad80
FB		 3117/***************************************
3118 *
3119 * initialize
3120 *
3121 ***************************************/
3122
4abc796d 3123static void cirrus_reset(void *opaque)
e6e5ad80 3124{
4abc796d 3125 CirrusVGAState *s = opaque;
e6e5ad80 3126
4abc796d 3127 vga_reset(s);
ee50c6bc 3128 unmap_linear_vram(s);
4e12cd94 3129 s->vga.sr[0x06] = 0x0f;
4abc796d 3130 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 3131 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 3132 s->vga.sr[0x1F] = 0x2d; // MemClock
3133 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
3134 s->vga.sr[0x0f] = 0x98;
3135 s->vga.sr[0x17] = 0x20;
3136 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 3137 } else {
4e12cd94
AK		 3138 s->vga.sr[0x1F] = 0x22; // MemClock
3139 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3140 s->vga.sr[0x17] = s->bustype;
3141 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 3142 }
4e12cd94 3143 s->vga.cr[0x27] = s->device_id;
e6e5ad80 3144
78e127ef
FB		 3145 /* Win2K seems to assume that the pattern buffer is at 0xff
3146 initially ! */
4e12cd94 3147 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 3148
e6e5ad80
FB		 3149 s->cirrus_hidden_dac_lockindex = 5;
3150 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 3151}
3152
3153static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3154{
3155 int i;
3156 static int inited;
3157
3158 if (!inited) {
3159 inited = 1;
3160 for(i = 0;i < 256; i++)
3161 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3162 rop_to_index[CIRRUS_ROP_0] = 0;
3163 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3164 rop_to_index[CIRRUS_ROP_NOP] = 2;
3165 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3166 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3167 rop_to_index[CIRRUS_ROP_SRC] = 5;
3168 rop_to_index[CIRRUS_ROP_1] = 6;
3169 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3170 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3171 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3172 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3173 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3174 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3175 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3176 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3177 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3178 s->device_id = device_id;
3179 if (is_pci)
3180 s->bustype = CIRRUS_BUSTYPE_PCI;
3181 else
3182 s->bustype = CIRRUS_BUSTYPE_ISA;
3183 }
3184
3185 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3186
3187 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3188 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3189 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3190 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3191
3192 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3193
3194 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3195 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3196 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3197 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3198
1eed09cb 3199 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
4e12cd94 3200 cirrus_vga_mem_write, s);
4abc796d 3201 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
4e12cd94 3202 s->vga.vga_io_memory);
4abc796d 3203 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2c6ab832 3204
fefe54e3
AL		 3205 /* I/O handler for LFB */
3206 s->cirrus_linear_io_addr =
1eed09cb 3207 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
fefe54e3
AL		 3208
3209 /* I/O handler for LFB */
3210 s->cirrus_linear_bitblt_io_addr =
1eed09cb 3211 cpu_register_io_memory(cirrus_linear_bitblt_read,
fefe54e3
AL		 3212 cirrus_linear_bitblt_write, s);
3213
3214 /* I/O handler for memory-mapped I/O */
3215 s->cirrus_mmio_io_addr =
1eed09cb 3216 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
fefe54e3
AL		 3217
3218 s->real_vram_size =
3219 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3220
4e12cd94 3221 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 3222 s->cirrus_addr_mask = s->real_vram_size - 1;
3223 s->linear_mmio_mask = s->real_vram_size - 256;
3224
4e12cd94
AK		 3225 s->vga.get_bpp = cirrus_get_bpp;
3226 s->vga.get_offsets = cirrus_get_offsets;
3227 s->vga.get_resolution = cirrus_get_resolution;
3228 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3229 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 3230
a08d4367 3231 qemu_register_reset(cirrus_reset, s);
4abc796d 3232 cirrus_reset(s);
d2269f6f 3233 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
e6e5ad80
FB		 3234}
3235
3236/***************************************
3237 *
3238 * ISA bus support
3239 *
3240 ***************************************/
3241
fbe1b595 3242void isa_cirrus_vga_init(void)
e6e5ad80
FB		 3243{
3244 CirrusVGAState *s;
3245
3246 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3247
fbe1b595 3248 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3249 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 3250 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3251 s->vga.screen_dump, s->vga.text_update,
3252 &s->vga);
e6e5ad80
FB		 3253 /* XXX ISA-LFB support */
3254}
3255
3256/***************************************
3257 *
3258 * PCI bus support
3259 *
3260 ***************************************/
3261
3262static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3263 uint32_t addr, uint32_t size, int type)
3264{
3265 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3266
a5082316 3267 /* XXX: add byte swapping apertures */
4e12cd94 3268 cpu_register_physical_memory(addr, s->vga.vram_size,
e6e5ad80 3269 s->cirrus_linear_io_addr);
a5082316
FB		 3270 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3271 s->cirrus_linear_bitblt_io_addr);
2bec46dc 3272
4e12cd94
AK		 3273 s->vga.map_addr = s->vga.map_end = 0;
3274 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3275 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2bec46dc 3276 /* account for overflow */
4e12cd94
AK		 3277 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3278 s->vga.lfb_end = addr + VGA_RAM_SIZE;
ba7349cd 3279
4e12cd94 3280 vga_dirty_log_start(&s->vga);
e6e5ad80
FB		 3281}
3282
3283static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3284 uint32_t addr, uint32_t size, int type)
3285{
3286 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3287
3288 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3289 s->cirrus_mmio_io_addr);
3290}
3291
ba7349cd
AL		 3292static void pci_cirrus_write_config(PCIDevice *d,
3293 uint32_t address, uint32_t val, int len)
3294{
3295 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3296 CirrusVGAState *s = &pvs->cirrus_vga;
3297
ba7349cd 3298 pci_default_write_config(d, address, val, len);
4e12cd94
AK		 3299 if (s->vga.map_addr && pvs->dev.io_regions[0].addr == -1)
3300 s->vga.map_addr = 0;
ba7349cd 3301 cirrus_update_memory_access(s);
ba7349cd
AL		 3302}
3303
fbe1b595 3304void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80
FB		 3305{
3306 PCICirrusVGAState *d;
3307 uint8_t *pci_conf;
3308 CirrusVGAState *s;
20ba3ae1 3309 int device_id;
3b46e624 3310
20ba3ae1 3311 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 3312
3313 /* setup PCI configuration registers */
5fafdf24
TS		 3314 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3315 sizeof(PCICirrusVGAState),
ba7349cd 3316 -1, NULL, pci_cirrus_write_config);
e6e5ad80 3317 pci_conf = d->dev.config;
deb54399
AL		 3318 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3319 pci_config_set_device_id(pci_conf, device_id);
e6e5ad80 3320 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
173a543b 3321 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
6407f373 3322 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
e6e5ad80
FB		 3323
3324 /* setup VGA */
3325 s = &d->cirrus_vga;
fbe1b595 3326 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3327 cirrus_init_common(s, device_id, 1);
d34cab9f 3328
4e12cd94
AK		 3329 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3330 s->vga.screen_dump, s->vga.text_update,
3331 &s->vga);
d34cab9f 3332
4e12cd94 3333 s->vga.pci_dev = (PCIDevice *)d;
e6e5ad80
FB		 3334
3335 /* setup memory space */
3336 /* memory #0 LFB */
3337 /* memory #1 memory-mapped I/O */
4e12cd94 3338 /* XXX: s->vga.vram_size must be a power of two */
28c2c264 3339 pci_register_bar((PCIDevice *)d, 0, 0x2000000,
a21ae81d 3340 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 3341 if (device_id == CIRRUS_ID_CLGD5446) {
28c2c264 3342 pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
a21ae81d
FB		 3343 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3344 }
e6e5ad80
FB		 3345 /* XXX: ROM BIOS */
3346}
Qemu copy for testing