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Commit | Line | Data |
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d537cf6c PB |
1 | /* |
2 | * QEMU IRQ/GPIO common code. | |
5fafdf24 | 3 | * |
d537cf6c | 4 | * Copyright (c) 2007 CodeSourcery. |
5fafdf24 | 5 | * |
d537cf6c PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b | 24 | #include "qemu-common.h" |
83c9f4ca | 25 | #include "hw/irq.h" |
d537cf6c PB |
26 | |
27 | struct IRQState { | |
28 | qemu_irq_handler handler; | |
29 | void *opaque; | |
30 | int n; | |
31 | }; | |
32 | ||
33 | void qemu_set_irq(qemu_irq irq, int level) | |
34 | { | |
35 | if (!irq) | |
36 | return; | |
37 | ||
38 | irq->handler(irq->opaque, irq->n, level); | |
39 | } | |
40 | ||
1e5b31e6 PC |
41 | qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, |
42 | void *opaque, int n) | |
d537cf6c PB |
43 | { |
44 | qemu_irq *s; | |
45 | struct IRQState *p; | |
46 | int i; | |
47 | ||
1e5b31e6 PC |
48 | if (!old) { |
49 | n_old = 0; | |
50 | } | |
51 | s = old ? g_renew(qemu_irq, old, n + n_old) : g_new(qemu_irq, n); | |
52 | p = old ? g_renew(struct IRQState, s[0], n + n_old) : | |
53 | g_new(struct IRQState, n); | |
54 | for (i = 0; i < n + n_old; i++) { | |
55 | if (i >= n_old) { | |
56 | p->handler = handler; | |
57 | p->opaque = opaque; | |
58 | p->n = i; | |
59 | } | |
d537cf6c PB |
60 | s[i] = p; |
61 | p++; | |
62 | } | |
63 | return s; | |
64 | } | |
65 | ||
1e5b31e6 PC |
66 | qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) |
67 | { | |
68 | return qemu_extend_irqs(NULL, 0, handler, opaque, n); | |
69 | } | |
70 | ||
a8a9d30b MA |
71 | qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) |
72 | { | |
73 | struct IRQState *irq; | |
74 | ||
75 | irq = g_new(struct IRQState, 1); | |
76 | irq->handler = handler; | |
77 | irq->opaque = opaque; | |
78 | irq->n = n; | |
79 | ||
80 | return irq; | |
81 | } | |
1e5b31e6 | 82 | |
51bf9e7e AL |
83 | void qemu_free_irqs(qemu_irq *s) |
84 | { | |
7267c094 AL |
85 | g_free(s[0]); |
86 | g_free(s); | |
51bf9e7e AL |
87 | } |
88 | ||
a8a9d30b MA |
89 | void qemu_free_irq(qemu_irq irq) |
90 | { | |
91 | g_free(irq); | |
92 | } | |
93 | ||
b50a6563 AZ |
94 | static void qemu_notirq(void *opaque, int line, int level) |
95 | { | |
96 | struct IRQState *irq = opaque; | |
97 | ||
98 | irq->handler(irq->opaque, irq->n, !level); | |
99 | } | |
100 | ||
101 | qemu_irq qemu_irq_invert(qemu_irq irq) | |
102 | { | |
cf0dbb21 PB |
103 | /* The default state for IRQs is low, so raise the output now. */ |
104 | qemu_irq_raise(irq); | |
b50a6563 AZ |
105 | return qemu_allocate_irqs(qemu_notirq, irq, 1)[0]; |
106 | } | |
9793212b PM |
107 | |
108 | static void qemu_splitirq(void *opaque, int line, int level) | |
109 | { | |
110 | struct IRQState **irq = opaque; | |
111 | irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | |
112 | irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | |
113 | } | |
114 | ||
115 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) | |
116 | { | |
7267c094 | 117 | qemu_irq *s = g_malloc0(2 * sizeof(qemu_irq)); |
9793212b PM |
118 | s[0] = irq1; |
119 | s[1] = irq2; | |
120 | return qemu_allocate_irqs(qemu_splitirq, s, 1)[0]; | |
121 | } | |
22ec3283 AK |
122 | |
123 | static void proxy_irq_handler(void *opaque, int n, int level) | |
124 | { | |
125 | qemu_irq **target = opaque; | |
126 | ||
127 | if (*target) { | |
128 | qemu_set_irq((*target)[n], level); | |
129 | } | |
130 | } | |
131 | ||
132 | qemu_irq *qemu_irq_proxy(qemu_irq **target, int n) | |
133 | { | |
134 | return qemu_allocate_irqs(proxy_irq_handler, target, n); | |
135 | } | |
20288345 PB |
136 | |
137 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | |
138 | { | |
139 | int i; | |
140 | qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n); | |
141 | for (i = 0; i < n; i++) { | |
142 | *old_irqs[i] = *gpio_in[i]; | |
143 | gpio_in[i]->handler = handler; | |
144 | gpio_in[i]->opaque = old_irqs; | |
145 | } | |
146 | } | |
147 | ||
148 | void qemu_irq_intercept_out(qemu_irq **gpio_out, qemu_irq_handler handler, int n) | |
149 | { | |
150 | qemu_irq *old_irqs = *gpio_out; | |
151 | *gpio_out = qemu_allocate_irqs(handler, old_irqs, n); | |
152 | } |