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f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
83c9f4ca | 11 | #include "hw/sysbus.h" |
b12080cd | 12 | |
5126fec7 AF |
13 | #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" |
14 | #define A9MPCORE_PRIV(obj) \ | |
15 | OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV) | |
16 | ||
845769fc | 17 | typedef struct A9MPPrivState { |
5126fec7 AF |
18 | /*< private >*/ |
19 | SysBusDevice parent_obj; | |
20 | /*< public >*/ | |
21 | ||
b12080cd | 22 | uint32_t num_cpu; |
b12080cd PM |
23 | MemoryRegion container; |
24 | DeviceState *mptimer; | |
cde4577f | 25 | DeviceState *wdt; |
ddd76165 | 26 | DeviceState *gic; |
353575f0 | 27 | DeviceState *scu; |
a32134aa | 28 | uint32_t num_irq; |
845769fc | 29 | } A9MPPrivState; |
b12080cd | 30 | |
ddd76165 PM |
31 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
32 | { | |
845769fc | 33 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
ddd76165 PM |
34 | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
35 | } | |
36 | ||
b12080cd PM |
37 | static int a9mp_priv_init(SysBusDevice *dev) |
38 | { | |
5126fec7 | 39 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
353575f0 | 40 | SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; |
b12080cd PM |
41 | int i; |
42 | ||
ddd76165 PM |
43 | s->gic = qdev_create(NULL, "arm_gic"); |
44 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | |
45 | qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); | |
46 | qdev_init_nofail(s->gic); | |
1356b98d | 47 | gicbusdev = SYS_BUS_DEVICE(s->gic); |
ddd76165 PM |
48 | |
49 | /* Pass through outbound IRQ lines from the GIC */ | |
50 | sysbus_pass_irq(dev, gicbusdev); | |
51 | ||
52 | /* Pass through inbound GPIO lines to the GIC */ | |
5126fec7 | 53 | qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 54 | |
353575f0 PC |
55 | s->scu = qdev_create(NULL, "a9-scu"); |
56 | qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); | |
57 | qdev_init_nofail(s->scu); | |
58 | scubusdev = SYS_BUS_DEVICE(s->scu); | |
59 | ||
b12080cd PM |
60 | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
61 | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); | |
62 | qdev_init_nofail(s->mptimer); | |
cde4577f PC |
63 | timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
64 | ||
65 | s->wdt = qdev_create(NULL, "arm_mptimer"); | |
66 | qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); | |
67 | qdev_init_nofail(s->wdt); | |
68 | wdtbusdev = SYS_BUS_DEVICE(s->wdt); | |
b12080cd PM |
69 | |
70 | /* Memory map (addresses are offsets from PERIPHBASE): | |
71 | * 0x0000-0x00ff -- Snoop Control Unit | |
72 | * 0x0100-0x01ff -- GIC CPU interface | |
73 | * 0x0200-0x02ff -- Global Timer | |
74 | * 0x0300-0x05ff -- nothing | |
75 | * 0x0600-0x06ff -- private timers and watchdogs | |
76 | * 0x0700-0x0fff -- nothing | |
77 | * 0x1000-0x1fff -- GIC Distributor | |
78 | * | |
79 | * We should implement the global timer but don't currently do so. | |
80 | */ | |
300b1fc6 | 81 | memory_region_init(&s->container, OBJECT(s), "a9mp-priv-container", 0x2000); |
353575f0 PC |
82 | memory_region_add_subregion(&s->container, 0, |
83 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 84 | /* GIC CPU interface */ |
ddd76165 PM |
85 | memory_region_add_subregion(&s->container, 0x100, |
86 | sysbus_mmio_get_region(gicbusdev, 1)); | |
b12080cd PM |
87 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
88 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
89 | */ | |
90 | memory_region_add_subregion(&s->container, 0x600, | |
cde4577f | 91 | sysbus_mmio_get_region(timerbusdev, 0)); |
b12080cd | 92 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 93 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
94 | memory_region_add_subregion(&s->container, 0x1000, |
95 | sysbus_mmio_get_region(gicbusdev, 0)); | |
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96 | |
97 | sysbus_init_mmio(dev, &s->container); | |
98 | ||
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99 | /* Wire up the interrupt from each watchdog and timer. |
100 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
101 | */ | |
102 | for (i = 0; i < s->num_cpu; i++) { | |
103 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 104 | sysbus_connect_irq(timerbusdev, i, |
ddd76165 | 105 | qdev_get_gpio_in(s->gic, ppibase + 29)); |
cde4577f | 106 | sysbus_connect_irq(wdtbusdev, i, |
ddd76165 | 107 | qdev_get_gpio_in(s->gic, ppibase + 30)); |
b12080cd PM |
108 | } |
109 | return 0; | |
110 | } | |
111 | ||
39bffca2 | 112 | static Property a9mp_priv_properties[] = { |
845769fc | 113 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
114 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
115 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
116 | * is the number provided by the Cortex-A9MP test chip in the | |
117 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
118 | * Other boards may differ and should set this property appropriately. | |
119 | */ | |
845769fc | 120 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
121 | DEFINE_PROP_END_OF_LIST(), |
122 | }; | |
123 | ||
999e12bb AL |
124 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
125 | { | |
39bffca2 | 126 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
127 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
128 | ||
129 | k->init = a9mp_priv_init; | |
39bffca2 | 130 | dc->props = a9mp_priv_properties; |
999e12bb AL |
131 | } |
132 | ||
8c43a6f0 | 133 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 134 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 135 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 136 | .instance_size = sizeof(A9MPPrivState), |
39bffca2 | 137 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
138 | }; |
139 | ||
83f7d43a | 140 | static void a9mp_register_types(void) |
f7c70325 | 141 | { |
39bffca2 | 142 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
143 | } |
144 | ||
83f7d43a | 145 | type_init(a9mp_register_types) |