[qemu.git] / hw / cpu / arm11mpcore.c

/*
 * ARM11MPCore internal peripheral emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "qemu/timer.h"

/* MPCore private memory region.  */

#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
#define ARM11MPCORE_PRIV(obj) \
    OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)

typedef struct ARM11MPCorePriveState {
    SysBusDevice parent_obj;

    uint32_t scu_control;
    int iomemtype;
    uint32_t old_timer_status[8];
    uint32_t num_cpu;
    MemoryRegion iomem;
    MemoryRegion container;
    DeviceState *mptimer;
    DeviceState *wdtimer;
    DeviceState *gic;
    uint32_t num_irq;
} ARM11MPCorePriveState;

/* Per-CPU private memory mapped IO.  */

static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
    int id;
    /* SCU */
    switch (offset) {
    case 0x00: /* Control.  */
        return s->scu_control;
    case 0x04: /* Configuration.  */
        id = ((1 << s->num_cpu) - 1) << 4;
        return id | (s->num_cpu - 1);
    case 0x08: /* CPU status.  */
        return 0;
    case 0x0c: /* Invalidate all.  */
        return 0;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void mpcore_scu_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
    /* SCU */
    switch (offset) {
    case 0: /* Control register.  */
        s->scu_control = value & 1;
        break;
    case 0x0c: /* Invalidate all.  */
        /* This is a no-op as cache is not emulated.  */
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
    }
}

static const MemoryRegionOps mpcore_scu_ops = {
    .read = mpcore_scu_read,
    .write = mpcore_scu_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
    ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
    qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}

static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
{
    int i;
    SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
    SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
    SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
    memory_region_init(&s->container, OBJECT(s),
                       "mpcode-priv-container", 0x2000);
    memory_region_init_io(&s->iomem, OBJECT(s),
                          &mpcore_scu_ops, s, "mpcore-scu", 0x100);
    memory_region_add_subregion(&s->container, 0, &s->iomem);
    /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
     * at 0x200, 0x300...
     */
    for (i = 0; i < (s->num_cpu + 1); i++) {
        hwaddr offset = 0x100 + (i * 0x100);
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(gicbusdev, i + 1));
    }
    /* Add the regions for timer and watchdog for "current CPU" and
     * for each specific CPU.
     */
    for (i = 0; i < (s->num_cpu + 1); i++) {
        /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
        hwaddr offset = 0x600 + i * 0x100;
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(timerbusdev, i));
        memory_region_add_subregion(&s->container, offset + 0x20,
                                    sysbus_mmio_get_region(wdtbusdev, i));
    }
    memory_region_add_subregion(&s->container, 0x1000,
                                sysbus_mmio_get_region(gicbusdev, 0));
    /* Wire up the interrupt from each watchdog and timer.
     * For each core the timer is PPI 29 and the watchdog PPI 30.
     */
    for (i = 0; i < s->num_cpu; i++) {
        int ppibase = (s->num_irq - 32) + i * 32;
        sysbus_connect_irq(timerbusdev, i,
                           qdev_get_gpio_in(s->gic, ppibase + 29));
        sysbus_connect_irq(wdtbusdev, i,
                           qdev_get_gpio_in(s->gic, ppibase + 30));
    }
}

static int mpcore_priv_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);

    s->gic = qdev_create(NULL, "arm_gic");
    qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
    qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
    /* Request the legacy 11MPCore GIC behaviour: */
    qdev_prop_set_uint32(s->gic, "revision", 0);
    qdev_init_nofail(s->gic);

    /* Pass through outbound IRQ lines from the GIC */
    sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic));

    /* Pass through inbound GPIO lines to the GIC */
    qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);

    s->mptimer = qdev_create(NULL, "arm_mptimer");
    qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
    qdev_init_nofail(s->mptimer);

    s->wdtimer = qdev_create(NULL, "arm_mptimer");
    qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu);
    qdev_init_nofail(s->wdtimer);

    mpcore_priv_map_setup(s);
    sysbus_init_mmio(sbd, &s->container);
    return 0;
}

#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
#define REALVIEW_MPCORE_RIRQ(obj) \
    OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)

/* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
   controllers.  The output of these, plus some of the raw input lines
   are fed into a single SMP-aware interrupt controller on the CPU.  */
typedef struct {
    SysBusDevice parent_obj;

    SysBusDevice *priv;
    qemu_irq cpuic[32];
    qemu_irq rvic[4][64];
    uint32_t num_cpu;
} mpcore_rirq_state;

/* Map baseboard IRQs onto CPU IRQ lines.  */
static const int mpcore_irq_map[32] = {
    -1, -1, -1, -1,  1,  2, -1, -1,
    -1, -1,  6, -1,  4,  5, -1, -1,
    -1, 14, 15,  0,  7,  8, -1, -1,
    -1, -1, -1, -1,  9,  3, -1, -1,
};

static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
{
    mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
    int i;

    for (i = 0; i < 4; i++) {
        qemu_set_irq(s->rvic[i][irq], level);
    }
    if (irq < 32) {
        irq = mpcore_irq_map[irq];
        if (irq >= 0) {
            qemu_set_irq(s->cpuic[irq], level);
        }
    }
}

static int realview_mpcore_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
    DeviceState *gic;
    DeviceState *priv;
    int n;
    int i;

    priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
    qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
    qdev_init_nofail(priv);
    s->priv = SYS_BUS_DEVICE(priv);
    sysbus_pass_irq(sbd, s->priv);
    for (i = 0; i < 32; i++) {
        s->cpuic[i] = qdev_get_gpio_in(priv, i);
    }
    /* ??? IRQ routing is hardcoded to "normal" mode.  */
    for (n = 0; n < 4; n++) {
        gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
                                   s->cpuic[10 + n]);
        for (i = 0; i < 64; i++) {
            s->rvic[n][i] = qdev_get_gpio_in(gic, i);
        }
    }
    qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
    sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
    return 0;
}

static Property mpcore_rirq_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = realview_mpcore_init;
    dc->props = mpcore_rirq_properties;
}

static const TypeInfo mpcore_rirq_info = {
    .name          = TYPE_REALVIEW_MPCORE_RIRQ,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mpcore_rirq_state),
    .class_init    = mpcore_rirq_class_init,
};

static Property mpcore_priv_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
    /* The ARM11 MPCORE TRM says the on-chip controller may have
     * anything from 0 to 224 external interrupt IRQ lines (with another
     * 32 internal). We default to 32+32, which is the number provided by
     * the ARM11 MPCore test chip in the Realview Versatile Express
     * coretile. Other boards may differ and should set this property
     * appropriately. Some Linux kernels may not boot if the hardware
     * has more IRQ lines than the kernel expects.
     */
    DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_priv_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mpcore_priv_init;
    dc->props = mpcore_priv_properties;
}

static const TypeInfo mpcore_priv_info = {
    .name          = TYPE_ARM11MPCORE_PRIV,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ARM11MPCorePriveState),
    .class_init    = mpcore_priv_class_init,
};

static void arm11mpcore_register_types(void)
{
    type_register_static(&mpcore_rirq_info);
    type_register_static(&mpcore_priv_info);
}

type_init(arm11mpcore_register_types)
Commit	Line	Data
f7c70325 PB	1	/*
	2	* ARM11MPCore internal peripheral emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
f7c70325 PB	8	*/
f7c70325 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
1de7afc9	11	#include "qemu/timer.h"
2a6ab1e3	12
2a6ab1e3 PM	13	/* MPCore private memory region. */
2a6ab1e3 PM	14
56fc0281 AF	15	#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
	16	#define ARM11MPCORE_PRIV(obj) \
	17	OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
	18
845769fc	19	typedef struct ARM11MPCorePriveState {
56fc0281 AF	20	SysBusDevice parent_obj;
56fc0281 AF	21
2a6ab1e3 PM	22	uint32_t scu_control;
	23	int iomemtype;
	24	uint32_t old_timer_status[8];
	25	uint32_t num_cpu;
2a6ab1e3 PM	26	MemoryRegion iomem;
	27	MemoryRegion container;
	28	DeviceState *mptimer;
cde4577f	29	DeviceState *wdtimer;
2e9dfe20	30	DeviceState *gic;
a32134aa	31	uint32_t num_irq;
845769fc	32	} ARM11MPCorePriveState;
2a6ab1e3 PM	33
	34	/* Per-CPU private memory mapped IO. */
	35
a8170e5e	36	static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
2a6ab1e3 PM	37	unsigned size)
2a6ab1e3 PM	38	{
845769fc	39	ARM11MPCorePriveState s = (ARM11MPCorePriveState )opaque;
2a6ab1e3	40	int id;
2a6ab1e3 PM	41	/* SCU */
	42	switch (offset) {
	43	case 0x00: /* Control. */
	44	return s->scu_control;
	45	case 0x04: /* Configuration. */
	46	id = ((1 << s->num_cpu) - 1) << 4;
	47	return id \| (s->num_cpu - 1);
	48	case 0x08: /* CPU status. */
	49	return 0;
	50	case 0x0c: /* Invalidate all. */
	51	return 0;
	52	default:
f9fe7bda PM	53	qemu_log_mask(LOG_GUEST_ERROR,
	54	"mpcore_priv_read: Bad offset %x\n", (int)offset);
	55	return 0;
2a6ab1e3 PM	56	}
	57	}
	58
a8170e5e	59	static void mpcore_scu_write(void *opaque, hwaddr offset,
2a6ab1e3 PM	60	uint64_t value, unsigned size)
2a6ab1e3 PM	61	{
845769fc	62	ARM11MPCorePriveState s = (ARM11MPCorePriveState )opaque;
2a6ab1e3 PM	63	/* SCU */
	64	switch (offset) {
	65	case 0: /* Control register. */
	66	s->scu_control = value & 1;
	67	break;
	68	case 0x0c: /* Invalidate all. */
	69	/* This is a no-op as cache is not emulated. */
	70	break;
	71	default:
f9fe7bda PM	72	qemu_log_mask(LOG_GUEST_ERROR,
f9fe7bda PM	73	"mpcore_priv_read: Bad offset %x\n", (int)offset);
2a6ab1e3 PM	74	}
	75	}
	76
	77	static const MemoryRegionOps mpcore_scu_ops = {
	78	.read = mpcore_scu_read,
	79	.write = mpcore_scu_write,
	80	.endianness = DEVICE_NATIVE_ENDIAN,
	81	};
	82
2e9dfe20	83	static void mpcore_priv_set_irq(void *opaque, int irq, int level)
2a6ab1e3	84	{
845769fc	85	ARM11MPCorePriveState s = (ARM11MPCorePriveState )opaque;
2e9dfe20	86	qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
2a6ab1e3 PM	87	}
2a6ab1e3 PM	88
845769fc	89	static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
2a6ab1e3 PM	90	{
2a6ab1e3 PM	91	int i;
1356b98d	92	SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
cde4577f PC	93	SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
cde4577f PC	94	SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
300b1fc6 PB	95	memory_region_init(&s->container, OBJECT(s),
	96	"mpcode-priv-container", 0x2000);
	97	memory_region_init_io(&s->iomem, OBJECT(s),
	98	&mpcore_scu_ops, s, "mpcore-scu", 0x100);
2a6ab1e3 PM	99	memory_region_add_subregion(&s->container, 0, &s->iomem);
	100	/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
	101	* at 0x200, 0x300...
	102	*/
	103	for (i = 0; i < (s->num_cpu + 1); i++) {
a8170e5e	104	hwaddr offset = 0x100 + (i * 0x100);
2e9dfe20 PM	105	memory_region_add_subregion(&s->container, offset,
2e9dfe20 PM	106	sysbus_mmio_get_region(gicbusdev, i + 1));
2a6ab1e3 PM	107	}
	108	/* Add the regions for timer and watchdog for "current CPU" and
	109	* for each specific CPU.
	110	*/
cde4577f	111	for (i = 0; i < (s->num_cpu + 1); i++) {
2a6ab1e3	112	/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
cde4577f	113	hwaddr offset = 0x600 + i * 0x100;
2a6ab1e3	114	memory_region_add_subregion(&s->container, offset,
cde4577f PC	115	sysbus_mmio_get_region(timerbusdev, i));
	116	memory_region_add_subregion(&s->container, offset + 0x20,
	117	sysbus_mmio_get_region(wdtbusdev, i));
2a6ab1e3	118	}
2e9dfe20 PM	119	memory_region_add_subregion(&s->container, 0x1000,
	120	sysbus_mmio_get_region(gicbusdev, 0));
	121	/* Wire up the interrupt from each watchdog and timer.
	122	* For each core the timer is PPI 29 and the watchdog PPI 30.
	123	*/
	124	for (i = 0; i < s->num_cpu; i++) {
	125	int ppibase = (s->num_irq - 32) + i * 32;
cde4577f	126	sysbus_connect_irq(timerbusdev, i,
2e9dfe20	127	qdev_get_gpio_in(s->gic, ppibase + 29));
cde4577f	128	sysbus_connect_irq(wdtbusdev, i,
2e9dfe20	129	qdev_get_gpio_in(s->gic, ppibase + 30));
2a6ab1e3 PM	130	}
	131	}
	132
56fc0281	133	static int mpcore_priv_init(SysBusDevice *sbd)
2a6ab1e3	134	{
56fc0281 AF	135	DeviceState *dev = DEVICE(sbd);
56fc0281 AF	136	ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
2e9dfe20 PM	137
	138	s->gic = qdev_create(NULL, "arm_gic");
	139	qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
	140	qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
306a571a PM	141	/* Request the legacy 11MPCore GIC behaviour: */
306a571a PM	142	qdev_prop_set_uint32(s->gic, "revision", 0);
2e9dfe20 PM	143	qdev_init_nofail(s->gic);
	144
	145	/* Pass through outbound IRQ lines from the GIC */
56fc0281	146	sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic));
2e9dfe20 PM	147
2e9dfe20 PM	148	/* Pass through inbound GPIO lines to the GIC */
56fc0281	149	qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
2a6ab1e3	150
2a6ab1e3 PM	151	s->mptimer = qdev_create(NULL, "arm_mptimer");
	152	qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
	153	qdev_init_nofail(s->mptimer);
cde4577f PC	154
	155	s->wdtimer = qdev_create(NULL, "arm_mptimer");
	156	qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu);
	157	qdev_init_nofail(s->wdtimer);
	158
2a6ab1e3	159	mpcore_priv_map_setup(s);
56fc0281	160	sysbus_init_mmio(sbd, &s->container);
2a6ab1e3 PM	161	return 0;
2a6ab1e3 PM	162	}
f7c70325	163
45c0a675 AF	164	#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
	165	#define REALVIEW_MPCORE_RIRQ(obj) \
	166	OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
	167
f7c70325 PB	168	/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
	169	controllers. The output of these, plus some of the raw input lines
	170	are fed into a single SMP-aware interrupt controller on the CPU. */
	171	typedef struct {
45c0a675 AF	172	SysBusDevice parent_obj;
45c0a675 AF	173
f7c70325 PB	174	SysBusDevice *priv;
	175	qemu_irq cpuic[32];
	176	qemu_irq rvic[4][64];
	177	uint32_t num_cpu;
	178	} mpcore_rirq_state;
	179
	180	/* Map baseboard IRQs onto CPU IRQ lines. */
	181	static const int mpcore_irq_map[32] = {
	182	-1, -1, -1, -1, 1, 2, -1, -1,
	183	-1, -1, 6, -1, 4, 5, -1, -1,
	184	-1, 14, 15, 0, 7, 8, -1, -1,
	185	-1, -1, -1, -1, 9, 3, -1, -1,
	186	};
	187
	188	static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
	189	{
	190	mpcore_rirq_state s = (mpcore_rirq_state )opaque;
	191	int i;
	192
	193	for (i = 0; i < 4; i++) {
	194	qemu_set_irq(s->rvic[i][irq], level);
	195	}
	196	if (irq < 32) {
	197	irq = mpcore_irq_map[irq];
	198	if (irq >= 0) {
	199	qemu_set_irq(s->cpuic[irq], level);
	200	}
	201	}
	202	}
	203
45c0a675	204	static int realview_mpcore_init(SysBusDevice *sbd)
f7c70325	205	{
45c0a675 AF	206	DeviceState *dev = DEVICE(sbd);
45c0a675 AF	207	mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
f7c70325 PB	208	DeviceState *gic;
	209	DeviceState *priv;
	210	int n;
	211	int i;
	212
56fc0281	213	priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
f7c70325 PB	214	qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
f7c70325 PB	215	qdev_init_nofail(priv);
1356b98d	216	s->priv = SYS_BUS_DEVICE(priv);
45c0a675	217	sysbus_pass_irq(sbd, s->priv);
f7c70325 PB	218	for (i = 0; i < 32; i++) {
	219	s->cpuic[i] = qdev_get_gpio_in(priv, i);
	220	}
	221	/* ??? IRQ routing is hardcoded to "normal" mode. */
	222	for (n = 0; n < 4; n++) {
	223	gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
	224	s->cpuic[10 + n]);
	225	for (i = 0; i < 64; i++) {
	226	s->rvic[n][i] = qdev_get_gpio_in(gic, i);
	227	}
	228	}
45c0a675 AF	229	qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
45c0a675 AF	230	sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
f7c70325 PB	231	return 0;
	232	}
	233
999e12bb	234	static Property mpcore_rirq_properties[] = {
0f58a188	235	DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
999e12bb	236	DEFINE_PROP_END_OF_LIST(),
f7c70325 PB	237	};
f7c70325 PB	238
999e12bb AL	239	static void mpcore_rirq_class_init(ObjectClass klass, void data)
999e12bb AL	240	{
39bffca2	241	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	242	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	243
	244	k->init = realview_mpcore_init;
39bffca2	245	dc->props = mpcore_rirq_properties;
999e12bb AL	246	}
999e12bb AL	247
8c43a6f0	248	static const TypeInfo mpcore_rirq_info = {
45c0a675	249	.name = TYPE_REALVIEW_MPCORE_RIRQ,
39bffca2 AL	250	.parent = TYPE_SYS_BUS_DEVICE,
	251	.instance_size = sizeof(mpcore_rirq_state),
	252	.class_init = mpcore_rirq_class_init,
999e12bb AL	253	};
	254
	255	static Property mpcore_priv_properties[] = {
845769fc	256	DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
0f58a188 PM	257	/* The ARM11 MPCORE TRM says the on-chip controller may have
	258	* anything from 0 to 224 external interrupt IRQ lines (with another
	259	* 32 internal). We default to 32+32, which is the number provided by
	260	* the ARM11 MPCore test chip in the Realview Versatile Express
	261	* coretile. Other boards may differ and should set this property
	262	* appropriately. Some Linux kernels may not boot if the hardware
	263	* has more IRQ lines than the kernel expects.
	264	*/
845769fc	265	DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
999e12bb AL	266	DEFINE_PROP_END_OF_LIST(),
	267	};
	268
	269	static void mpcore_priv_class_init(ObjectClass klass, void data)
	270	{
39bffca2	271	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	272	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	273
	274	k->init = mpcore_priv_init;
39bffca2	275	dc->props = mpcore_priv_properties;
999e12bb AL	276	}
999e12bb AL	277
8c43a6f0	278	static const TypeInfo mpcore_priv_info = {
56fc0281	279	.name = TYPE_ARM11MPCORE_PRIV,
39bffca2	280	.parent = TYPE_SYS_BUS_DEVICE,
845769fc	281	.instance_size = sizeof(ARM11MPCorePriveState),
39bffca2	282	.class_init = mpcore_priv_class_init,
f7c70325 PB	283	};
f7c70325 PB	284
83f7d43a	285	static void arm11mpcore_register_types(void)
f7c70325	286	{
39bffca2 AL	287	type_register_static(&mpcore_rirq_info);
39bffca2 AL	288	type_register_static(&mpcore_priv_info);
f7c70325 PB	289	}
f7c70325 PB	290
83f7d43a	291	type_init(arm11mpcore_register_types)