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Commit | Line | Data |
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f7c70325 PB |
1 | /* |
2 | * ARM11MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
f7c70325 PB |
8 | */ |
9 | ||
83c9f4ca | 10 | #include "hw/sysbus.h" |
1de7afc9 | 11 | #include "qemu/timer.h" |
2a6ab1e3 | 12 | |
2a6ab1e3 PM |
13 | /* MPCore private memory region. */ |
14 | ||
56fc0281 AF |
15 | #define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv" |
16 | #define ARM11MPCORE_PRIV(obj) \ | |
17 | OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV) | |
18 | ||
845769fc | 19 | typedef struct ARM11MPCorePriveState { |
56fc0281 AF |
20 | SysBusDevice parent_obj; |
21 | ||
2a6ab1e3 | 22 | uint32_t scu_control; |
2a6ab1e3 | 23 | uint32_t num_cpu; |
2a6ab1e3 PM |
24 | MemoryRegion iomem; |
25 | MemoryRegion container; | |
26 | DeviceState *mptimer; | |
cde4577f | 27 | DeviceState *wdtimer; |
2e9dfe20 | 28 | DeviceState *gic; |
a32134aa | 29 | uint32_t num_irq; |
845769fc | 30 | } ARM11MPCorePriveState; |
2a6ab1e3 PM |
31 | |
32 | /* Per-CPU private memory mapped IO. */ | |
33 | ||
a8170e5e | 34 | static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, |
2a6ab1e3 PM |
35 | unsigned size) |
36 | { | |
845769fc | 37 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2a6ab1e3 | 38 | int id; |
2a6ab1e3 PM |
39 | /* SCU */ |
40 | switch (offset) { | |
41 | case 0x00: /* Control. */ | |
42 | return s->scu_control; | |
43 | case 0x04: /* Configuration. */ | |
44 | id = ((1 << s->num_cpu) - 1) << 4; | |
45 | return id | (s->num_cpu - 1); | |
46 | case 0x08: /* CPU status. */ | |
47 | return 0; | |
48 | case 0x0c: /* Invalidate all. */ | |
49 | return 0; | |
50 | default: | |
f9fe7bda PM |
51 | qemu_log_mask(LOG_GUEST_ERROR, |
52 | "mpcore_priv_read: Bad offset %x\n", (int)offset); | |
53 | return 0; | |
2a6ab1e3 PM |
54 | } |
55 | } | |
56 | ||
a8170e5e | 57 | static void mpcore_scu_write(void *opaque, hwaddr offset, |
2a6ab1e3 PM |
58 | uint64_t value, unsigned size) |
59 | { | |
845769fc | 60 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2a6ab1e3 PM |
61 | /* SCU */ |
62 | switch (offset) { | |
63 | case 0: /* Control register. */ | |
64 | s->scu_control = value & 1; | |
65 | break; | |
66 | case 0x0c: /* Invalidate all. */ | |
67 | /* This is a no-op as cache is not emulated. */ | |
68 | break; | |
69 | default: | |
f9fe7bda PM |
70 | qemu_log_mask(LOG_GUEST_ERROR, |
71 | "mpcore_priv_read: Bad offset %x\n", (int)offset); | |
2a6ab1e3 PM |
72 | } |
73 | } | |
74 | ||
75 | static const MemoryRegionOps mpcore_scu_ops = { | |
76 | .read = mpcore_scu_read, | |
77 | .write = mpcore_scu_write, | |
78 | .endianness = DEVICE_NATIVE_ENDIAN, | |
79 | }; | |
80 | ||
2e9dfe20 | 81 | static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
2a6ab1e3 | 82 | { |
845769fc | 83 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2e9dfe20 | 84 | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
2a6ab1e3 PM |
85 | } |
86 | ||
845769fc | 87 | static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
2a6ab1e3 PM |
88 | { |
89 | int i; | |
1356b98d | 90 | SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); |
cde4577f PC |
91 | SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
92 | SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); | |
300b1fc6 PB |
93 | memory_region_init_io(&s->iomem, OBJECT(s), |
94 | &mpcore_scu_ops, s, "mpcore-scu", 0x100); | |
2a6ab1e3 PM |
95 | memory_region_add_subregion(&s->container, 0, &s->iomem); |
96 | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs | |
97 | * at 0x200, 0x300... | |
98 | */ | |
99 | for (i = 0; i < (s->num_cpu + 1); i++) { | |
a8170e5e | 100 | hwaddr offset = 0x100 + (i * 0x100); |
2e9dfe20 PM |
101 | memory_region_add_subregion(&s->container, offset, |
102 | sysbus_mmio_get_region(gicbusdev, i + 1)); | |
2a6ab1e3 PM |
103 | } |
104 | /* Add the regions for timer and watchdog for "current CPU" and | |
105 | * for each specific CPU. | |
106 | */ | |
cde4577f | 107 | for (i = 0; i < (s->num_cpu + 1); i++) { |
2a6ab1e3 | 108 | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
cde4577f | 109 | hwaddr offset = 0x600 + i * 0x100; |
2a6ab1e3 | 110 | memory_region_add_subregion(&s->container, offset, |
cde4577f PC |
111 | sysbus_mmio_get_region(timerbusdev, i)); |
112 | memory_region_add_subregion(&s->container, offset + 0x20, | |
113 | sysbus_mmio_get_region(wdtbusdev, i)); | |
2a6ab1e3 | 114 | } |
2e9dfe20 PM |
115 | memory_region_add_subregion(&s->container, 0x1000, |
116 | sysbus_mmio_get_region(gicbusdev, 0)); | |
117 | /* Wire up the interrupt from each watchdog and timer. | |
118 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
119 | */ | |
120 | for (i = 0; i < s->num_cpu; i++) { | |
121 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 122 | sysbus_connect_irq(timerbusdev, i, |
2e9dfe20 | 123 | qdev_get_gpio_in(s->gic, ppibase + 29)); |
cde4577f | 124 | sysbus_connect_irq(wdtbusdev, i, |
2e9dfe20 | 125 | qdev_get_gpio_in(s->gic, ppibase + 30)); |
2a6ab1e3 PM |
126 | } |
127 | } | |
128 | ||
56fc0281 | 129 | static int mpcore_priv_init(SysBusDevice *sbd) |
2a6ab1e3 | 130 | { |
56fc0281 AF |
131 | DeviceState *dev = DEVICE(sbd); |
132 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); | |
2e9dfe20 PM |
133 | |
134 | s->gic = qdev_create(NULL, "arm_gic"); | |
135 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | |
136 | qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); | |
306a571a PM |
137 | /* Request the legacy 11MPCore GIC behaviour: */ |
138 | qdev_prop_set_uint32(s->gic, "revision", 0); | |
2e9dfe20 PM |
139 | qdev_init_nofail(s->gic); |
140 | ||
141 | /* Pass through outbound IRQ lines from the GIC */ | |
56fc0281 | 142 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic)); |
2e9dfe20 PM |
143 | |
144 | /* Pass through inbound GPIO lines to the GIC */ | |
56fc0281 | 145 | qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); |
2a6ab1e3 | 146 | |
2a6ab1e3 PM |
147 | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
148 | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); | |
149 | qdev_init_nofail(s->mptimer); | |
cde4577f PC |
150 | |
151 | s->wdtimer = qdev_create(NULL, "arm_mptimer"); | |
152 | qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); | |
153 | qdev_init_nofail(s->wdtimer); | |
154 | ||
2a6ab1e3 | 155 | mpcore_priv_map_setup(s); |
2a6ab1e3 PM |
156 | return 0; |
157 | } | |
f7c70325 | 158 | |
2c42c3a0 AF |
159 | static void mpcore_priv_initfn(Object *obj) |
160 | { | |
161 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
162 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); | |
163 | ||
164 | memory_region_init(&s->container, OBJECT(s), | |
165 | "mpcore-priv-container", 0x2000); | |
166 | sysbus_init_mmio(sbd, &s->container); | |
167 | } | |
168 | ||
45c0a675 AF |
169 | #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" |
170 | #define REALVIEW_MPCORE_RIRQ(obj) \ | |
171 | OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) | |
172 | ||
f7c70325 PB |
173 | /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ |
174 | controllers. The output of these, plus some of the raw input lines | |
175 | are fed into a single SMP-aware interrupt controller on the CPU. */ | |
176 | typedef struct { | |
45c0a675 AF |
177 | SysBusDevice parent_obj; |
178 | ||
f7c70325 PB |
179 | SysBusDevice *priv; |
180 | qemu_irq cpuic[32]; | |
181 | qemu_irq rvic[4][64]; | |
182 | uint32_t num_cpu; | |
183 | } mpcore_rirq_state; | |
184 | ||
185 | /* Map baseboard IRQs onto CPU IRQ lines. */ | |
186 | static const int mpcore_irq_map[32] = { | |
187 | -1, -1, -1, -1, 1, 2, -1, -1, | |
188 | -1, -1, 6, -1, 4, 5, -1, -1, | |
189 | -1, 14, 15, 0, 7, 8, -1, -1, | |
190 | -1, -1, -1, -1, 9, 3, -1, -1, | |
191 | }; | |
192 | ||
193 | static void mpcore_rirq_set_irq(void *opaque, int irq, int level) | |
194 | { | |
195 | mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; | |
196 | int i; | |
197 | ||
198 | for (i = 0; i < 4; i++) { | |
199 | qemu_set_irq(s->rvic[i][irq], level); | |
200 | } | |
201 | if (irq < 32) { | |
202 | irq = mpcore_irq_map[irq]; | |
203 | if (irq >= 0) { | |
204 | qemu_set_irq(s->cpuic[irq], level); | |
205 | } | |
206 | } | |
207 | } | |
208 | ||
45c0a675 | 209 | static int realview_mpcore_init(SysBusDevice *sbd) |
f7c70325 | 210 | { |
45c0a675 AF |
211 | DeviceState *dev = DEVICE(sbd); |
212 | mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); | |
f7c70325 PB |
213 | DeviceState *gic; |
214 | DeviceState *priv; | |
215 | int n; | |
216 | int i; | |
217 | ||
56fc0281 | 218 | priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV); |
f7c70325 PB |
219 | qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); |
220 | qdev_init_nofail(priv); | |
1356b98d | 221 | s->priv = SYS_BUS_DEVICE(priv); |
45c0a675 | 222 | sysbus_pass_irq(sbd, s->priv); |
f7c70325 PB |
223 | for (i = 0; i < 32; i++) { |
224 | s->cpuic[i] = qdev_get_gpio_in(priv, i); | |
225 | } | |
226 | /* ??? IRQ routing is hardcoded to "normal" mode. */ | |
227 | for (n = 0; n < 4; n++) { | |
228 | gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, | |
229 | s->cpuic[10 + n]); | |
230 | for (i = 0; i < 64; i++) { | |
231 | s->rvic[n][i] = qdev_get_gpio_in(gic, i); | |
232 | } | |
233 | } | |
45c0a675 AF |
234 | qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); |
235 | sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0)); | |
f7c70325 PB |
236 | return 0; |
237 | } | |
238 | ||
999e12bb | 239 | static Property mpcore_rirq_properties[] = { |
0f58a188 | 240 | DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
999e12bb | 241 | DEFINE_PROP_END_OF_LIST(), |
f7c70325 PB |
242 | }; |
243 | ||
999e12bb AL |
244 | static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
245 | { | |
39bffca2 | 246 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
247 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
248 | ||
249 | k->init = realview_mpcore_init; | |
39bffca2 | 250 | dc->props = mpcore_rirq_properties; |
999e12bb AL |
251 | } |
252 | ||
8c43a6f0 | 253 | static const TypeInfo mpcore_rirq_info = { |
45c0a675 | 254 | .name = TYPE_REALVIEW_MPCORE_RIRQ, |
39bffca2 AL |
255 | .parent = TYPE_SYS_BUS_DEVICE, |
256 | .instance_size = sizeof(mpcore_rirq_state), | |
257 | .class_init = mpcore_rirq_class_init, | |
999e12bb AL |
258 | }; |
259 | ||
260 | static Property mpcore_priv_properties[] = { | |
845769fc | 261 | DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), |
0f58a188 PM |
262 | /* The ARM11 MPCORE TRM says the on-chip controller may have |
263 | * anything from 0 to 224 external interrupt IRQ lines (with another | |
264 | * 32 internal). We default to 32+32, which is the number provided by | |
265 | * the ARM11 MPCore test chip in the Realview Versatile Express | |
266 | * coretile. Other boards may differ and should set this property | |
267 | * appropriately. Some Linux kernels may not boot if the hardware | |
268 | * has more IRQ lines than the kernel expects. | |
269 | */ | |
845769fc | 270 | DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), |
999e12bb AL |
271 | DEFINE_PROP_END_OF_LIST(), |
272 | }; | |
273 | ||
274 | static void mpcore_priv_class_init(ObjectClass *klass, void *data) | |
275 | { | |
39bffca2 | 276 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
277 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
278 | ||
279 | k->init = mpcore_priv_init; | |
39bffca2 | 280 | dc->props = mpcore_priv_properties; |
999e12bb AL |
281 | } |
282 | ||
8c43a6f0 | 283 | static const TypeInfo mpcore_priv_info = { |
56fc0281 | 284 | .name = TYPE_ARM11MPCORE_PRIV, |
39bffca2 | 285 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 286 | .instance_size = sizeof(ARM11MPCorePriveState), |
2c42c3a0 | 287 | .instance_init = mpcore_priv_initfn, |
39bffca2 | 288 | .class_init = mpcore_priv_class_init, |
f7c70325 PB |
289 | }; |
290 | ||
83f7d43a | 291 | static void arm11mpcore_register_types(void) |
f7c70325 | 292 | { |
39bffca2 AL |
293 | type_register_static(&mpcore_rirq_info); |
294 | type_register_static(&mpcore_priv_info); | |
f7c70325 PB |
295 | } |
296 | ||
83f7d43a | 297 | type_init(arm11mpcore_register_types) |