[qemu.git] / hw / cuda.c

/*
 * QEMU PowerMac CUDA device support
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "ppc_mac.h"

/* XXX: implement all timer modes */

//#define DEBUG_CUDA
//#define DEBUG_CUDA_PACKET

/* Bits in B data register: all active low */
#define TREQ		0x08		/* Transfer request (input) */
#define TACK		0x10		/* Transfer acknowledge (output) */
#define TIP		0x20		/* Transfer in progress (output) */

/* Bits in ACR */
#define SR_CTRL		0x1c		/* Shift register control bits */
#define SR_EXT		0x0c		/* Shift on external clock */
#define SR_OUT		0x10		/* Shift out if 1 */

/* Bits in IFR and IER */
#define IER_SET		0x80		/* set bits in IER */
#define IER_CLR		0		/* clear bits in IER */
#define SR_INT		0x04		/* Shift register full/empty */
#define T1_INT          0x40            /* Timer 1 interrupt */
#define T2_INT          0x20            /* Timer 2 interrupt */

/* Bits in ACR */
#define T1MODE          0xc0            /* Timer 1 mode */
#define T1MODE_CONT     0x40            /*  continuous interrupts */

/* commands (1st byte) */
#define ADB_PACKET	0
#define CUDA_PACKET	1
#define ERROR_PACKET	2
#define TIMER_PACKET	3
#define POWER_PACKET	4
#define MACIIC_PACKET	5
#define PMU_PACKET	6


/* CUDA commands (2nd byte) */
#define CUDA_WARM_START			0x0
#define CUDA_AUTOPOLL			0x1
#define CUDA_GET_6805_ADDR		0x2
#define CUDA_GET_TIME			0x3
#define CUDA_GET_PRAM			0x7
#define CUDA_SET_6805_ADDR		0x8
#define CUDA_SET_TIME			0x9
#define CUDA_POWERDOWN			0xa
#define CUDA_POWERUP_TIME		0xb
#define CUDA_SET_PRAM			0xc
#define CUDA_MS_RESET			0xd
#define CUDA_SEND_DFAC			0xe
#define CUDA_BATTERY_SWAP_SENSE		0x10
#define CUDA_RESET_SYSTEM		0x11
#define CUDA_SET_IPL			0x12
#define CUDA_FILE_SERVER_FLAG		0x13
#define CUDA_SET_AUTO_RATE		0x14
#define CUDA_GET_AUTO_RATE		0x16
#define CUDA_SET_DEVICE_LIST		0x19
#define CUDA_GET_DEVICE_LIST		0x1a
#define CUDA_SET_ONE_SECOND_MODE	0x1b
#define CUDA_SET_POWER_MESSAGES		0x21
#define CUDA_GET_SET_IIC		0x22
#define CUDA_WAKEUP			0x23
#define CUDA_TIMER_TICKLE		0x24
#define CUDA_COMBINED_FORMAT_IIC	0x25

#define CUDA_TIMER_FREQ (4700000 / 6)
#define CUDA_ADB_POLL_FREQ 50

/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
#define RTC_OFFSET                      2082844800

typedef struct CUDATimer {
    int index;
    uint16_t latch;
    uint16_t counter_value; /* counter value at load time */
    int64_t load_time;
    int64_t next_irq_time;
    QEMUTimer *timer;
} CUDATimer;

typedef struct CUDAState {
    /* cuda registers */
    uint8_t b;      /* B-side data */
    uint8_t a;      /* A-side data */
    uint8_t dirb;   /* B-side direction (1=output) */
    uint8_t dira;   /* A-side direction (1=output) */
    uint8_t sr;     /* Shift register */
    uint8_t acr;    /* Auxiliary control register */
    uint8_t pcr;    /* Peripheral control register */
    uint8_t ifr;    /* Interrupt flag register */
    uint8_t ier;    /* Interrupt enable register */
    uint8_t anh;    /* A-side data, no handshake */

    CUDATimer timers[2];

    uint8_t last_b; /* last value of B register */
    uint8_t last_acr; /* last value of B register */

    int data_in_size;
    int data_in_index;
    int data_out_index;

    qemu_irq irq;
    uint8_t autopoll;
    uint8_t data_in[128];
    uint8_t data_out[16];
    QEMUTimer *adb_poll_timer;
} CUDAState;

static CUDAState cuda_state;
ADBBusState adb_bus;

static void cuda_update(CUDAState *s);
static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len);
static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time);

static void cuda_update_irq(CUDAState *s)
{
    if (s->ifr & s->ier & (SR_INT | T1_INT)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static unsigned int get_counter(CUDATimer *s)
{
    int64_t d;
    unsigned int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    if (s->index == 0) {
        /* the timer goes down from latch to -1 (period of latch + 2) */
        if (d <= (s->counter_value + 1)) {
            counter = (s->counter_value - d) & 0xffff;
        } else {
            counter = (d - (s->counter_value + 1)) % (s->latch + 2);
            counter = (s->latch - counter) & 0xffff;
        }
    } else {
        counter = (s->counter_value - d) & 0xffff;
    }
    return counter;
}

static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{
#ifdef DEBUG_CUDA
    printf("cuda: T%d.counter=%d\n",
           1 + (ti->timer == NULL), val);
#endif
    ti->load_time = qemu_get_clock(vm_clock);
    ti->counter_value = val;
    cuda_timer_update(s, ti, ti->load_time);
}

static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
{
    int64_t d, next_time;
    unsigned int counter;

    /* current counter value */
    d = muldiv64(current_time - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    /* the timer goes down from latch to -1 (period of latch + 2) */
    if (d <= (s->counter_value + 1)) {
        counter = (s->counter_value - d) & 0xffff;
    } else {
        counter = (d - (s->counter_value + 1)) % (s->latch + 2);
        counter = (s->latch - counter) & 0xffff;
    }

    /* Note: we consider the irq is raised on 0 */
    if (counter == 0xffff) {
        next_time = d + s->latch + 1;
    } else if (counter == 0) {
        next_time = d + s->latch + 2;
    } else {
        next_time = d + counter;
    }
#if 0
#ifdef DEBUG_CUDA
    printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
           s->latch, d, next_time - d);
#endif
#endif
    next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
        s->load_time;
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time)
{
    if (!ti->timer)
        return;
    if ((s->acr & T1MODE) != T1MODE_CONT) {
        qemu_del_timer(ti->timer);
    } else {
        ti->next_irq_time = get_next_irq_time(ti, current_time);
        qemu_mod_timer(ti->timer, ti->next_irq_time);
    }
}

static void cuda_timer1(void *opaque)
{
    CUDAState *s = opaque;
    CUDATimer *ti = &s->timers[0];

    cuda_timer_update(s, ti, ti->next_irq_time);
    s->ifr |= T1_INT;
    cuda_update_irq(s);
}

static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
    CUDAState *s = opaque;
    uint32_t val;

    addr = (addr >> 9) & 0xf;
    switch(addr) {
    case 0:
        val = s->b;
        break;
    case 1:
        val = s->a;
        break;
    case 2:
        val = s->dirb;
        break;
    case 3:
        val = s->dira;
        break;
    case 4:
        val = get_counter(&s->timers[0]) & 0xff;
        s->ifr &= ~T1_INT;
        cuda_update_irq(s);
        break;
    case 5:
        val = get_counter(&s->timers[0]) >> 8;
        cuda_update_irq(s);
        break;
    case 6:
        val = s->timers[0].latch & 0xff;
        break;
    case 7:
        /* XXX: check this */
        val = (s->timers[0].latch >> 8) & 0xff;
        break;
    case 8:
        val = get_counter(&s->timers[1]) & 0xff;
        s->ifr &= ~T2_INT;
        break;
    case 9:
        val = get_counter(&s->timers[1]) >> 8;
        break;
    case 10:
        val = s->sr;
        s->ifr &= ~SR_INT;
        cuda_update_irq(s);
        break;
    case 11:
        val = s->acr;
        break;
    case 12:
        val = s->pcr;
        break;
    case 13:
        val = s->ifr;
        if (s->ifr & s->ier)
            val |= 0x80;
        break;
    case 14:
        val = s->ier | 0x80;
        break;
    default:
    case 15:
        val = s->anh;
        break;
    }
#ifdef DEBUG_CUDA
    if (addr != 13 || val != 0)
        printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
#endif
    return val;
}

static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    CUDAState *s = opaque;

    addr = (addr >> 9) & 0xf;
#ifdef DEBUG_CUDA
    printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
#endif

    switch(addr) {
    case 0:
        s->b = val;
        cuda_update(s);
        break;
    case 1:
        s->a = val;
        break;
    case 2:
        s->dirb = val;
        break;
    case 3:
        s->dira = val;
        break;
    case 4:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 5:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        set_counter(s, &s->timers[0], s->timers[0].latch);
        break;
    case 6:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 7:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 8:
        s->timers[1].latch = val;
        set_counter(s, &s->timers[1], val);
        break;
    case 9:
        set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
        break;
    case 10:
        s->sr = val;
        break;
    case 11:
        s->acr = val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        cuda_update(s);
        break;
    case 12:
        s->pcr = val;
        break;
    case 13:
        /* reset bits */
        s->ifr &= ~val;
        cuda_update_irq(s);
        break;
    case 14:
        if (val & IER_SET) {
            /* set bits */
            s->ier |= val & 0x7f;
        } else {
            /* reset bits */
            s->ier &= ~val;
        }
        cuda_update_irq(s);
        break;
    default:
    case 15:
        s->anh = val;
        break;
    }
}

/* NOTE: TIP and TREQ are negated */
static void cuda_update(CUDAState *s)
{
    int packet_received, len;

    packet_received = 0;
    if (!(s->b & TIP)) {
        /* transfer requested from host */

        if (s->acr & SR_OUT) {
            /* data output */
            if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                if (s->data_out_index < sizeof(s->data_out)) {
#ifdef DEBUG_CUDA
                    printf("cuda: send: %02x\n", s->sr);
#endif
                    s->data_out[s->data_out_index++] = s->sr;
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        } else {
            if (s->data_in_index < s->data_in_size) {
                /* data input */
                if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                    s->sr = s->data_in[s->data_in_index++];
#ifdef DEBUG_CUDA
                    printf("cuda: recv: %02x\n", s->sr);
#endif
                    /* indicate end of transfer */
                    if (s->data_in_index >= s->data_in_size) {
                        s->b = (s->b | TREQ);
                    }
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        }
    } else {
        /* no transfer requested: handle sync case */
        if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
            /* update TREQ state each time TACK change state */
            if (s->b & TACK)
                s->b = (s->b | TREQ);
            else
                s->b = (s->b & ~TREQ);
            s->ifr |= SR_INT;
            cuda_update_irq(s);
        } else {
            if (!(s->last_b & TIP)) {
                /* handle end of host to cuda transfer */
                packet_received = (s->data_out_index > 0);
                /* always an IRQ at the end of transfer */
                s->ifr |= SR_INT;
                cuda_update_irq(s);
            }
            /* signal if there is data to read */
            if (s->data_in_index < s->data_in_size) {
                s->b = (s->b & ~TREQ);
            }
        }
    }

    s->last_acr = s->acr;
    s->last_b = s->b;

    /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
       recursively */
    if (packet_received) {
        len = s->data_out_index;
        s->data_out_index = 0;
        cuda_receive_packet_from_host(s, s->data_out, len);
    }
}

static void cuda_send_packet_to_host(CUDAState *s,
                                     const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_send_packet_to_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    memcpy(s->data_in, data, len);
    s->data_in_size = len;
    s->data_in_index = 0;
    cuda_update(s);
    s->ifr |= SR_INT;
    cuda_update_irq(s);
}

static void cuda_adb_poll(void *opaque)
{
    CUDAState *s = opaque;
    uint8_t obuf[ADB_MAX_OUT_LEN + 2];
    int olen;

    olen = adb_poll(&adb_bus, obuf + 2);
    if (olen > 0) {
        obuf[0] = ADB_PACKET;
        obuf[1] = 0x40; /* polled data */
        cuda_send_packet_to_host(s, obuf, olen + 2);
    }
    qemu_mod_timer(s->adb_poll_timer,
                   qemu_get_clock(vm_clock) +
                   (ticks_per_sec / CUDA_ADB_POLL_FREQ));
}

static void cuda_receive_packet(CUDAState *s,
                                const uint8_t *data, int len)
{
    uint8_t obuf[16];
    int ti, autopoll;

    switch(data[0]) {
    case CUDA_AUTOPOLL:
        autopoll = (data[1] != 0);
        if (autopoll != s->autopoll) {
            s->autopoll = autopoll;
            if (autopoll) {
                qemu_mod_timer(s->adb_poll_timer,
                               qemu_get_clock(vm_clock) +
                               (ticks_per_sec / CUDA_ADB_POLL_FREQ));
            } else {
                qemu_del_timer(s->adb_poll_timer);
            }
        }
        obuf[0] = CUDA_PACKET;
        obuf[1] = data[1];
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_GET_TIME:
    case CUDA_SET_TIME:
        /* XXX: add time support ? */
        ti = time(NULL) + RTC_OFFSET;
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        obuf[2] = 0;
        obuf[3] = ti >> 24;
        obuf[4] = ti >> 16;
        obuf[5] = ti >> 8;
        obuf[6] = ti;
        cuda_send_packet_to_host(s, obuf, 7);
        break;
    case CUDA_FILE_SERVER_FLAG:
    case CUDA_SET_DEVICE_LIST:
    case CUDA_SET_AUTO_RATE:
    case CUDA_SET_POWER_MESSAGES:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_POWERDOWN:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
	qemu_system_shutdown_request();
	break;
    case CUDA_RESET_SYSTEM:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
        qemu_system_reset_request();
        break;
    default:
        break;
    }
}

static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_receive_packet_from_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    switch(data[0]) {
    case ADB_PACKET:
        {
            uint8_t obuf[ADB_MAX_OUT_LEN + 2];
            int olen;
            olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
            if (olen > 0) {
                obuf[0] = ADB_PACKET;
                obuf[1] = 0x00;
            } else {
                /* error */
                obuf[0] = ADB_PACKET;
                obuf[1] = -olen;
                olen = 0;
            }
            cuda_send_packet_to_host(s, obuf, olen + 2);
        }
        break;
    case CUDA_PACKET:
        cuda_receive_packet(s, data + 1, len - 1);
        break;
    }
}

static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *cuda_write[] = {
    &cuda_writeb,
    &cuda_writew,
    &cuda_writel,
};

static CPUReadMemoryFunc *cuda_read[] = {
    &cuda_readb,
    &cuda_readw,
    &cuda_readl,
};

void cuda_init (int *cuda_mem_index, qemu_irq irq)
{
    CUDAState *s = &cuda_state;

    s->irq = irq;

    s->timers[0].index = 0;
    s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
    s->timers[0].latch = 0xffff;
    set_counter(s, &s->timers[0], 0xffff);

    s->timers[1].index = 1;
    s->timers[1].latch = 0;
    //    s->ier = T1_INT | SR_INT;
    s->ier = 0;
    set_counter(s, &s->timers[1], 0xffff);

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
    *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
}
Commit	Line	Data
267002cd	1	/*
3cbee15b	2	* QEMU PowerMac CUDA device support
5fafdf24	3	*
3cbee15b JM	4	* Copyright (c) 2004-2007 Fabrice Bellard
3cbee15b JM	5	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	6	*
267002cd FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "vl.h"
3cbee15b	26	#include "ppc_mac.h"
267002cd	27
61271e5c FB	28	/* XXX: implement all timer modes */
61271e5c FB	29
819e712b FB	30	//#define DEBUG_CUDA
	31	//#define DEBUG_CUDA_PACKET
	32
267002cd FB	33	/* Bits in B data register: all active low */
	34	#define TREQ 0x08 /* Transfer request (input) */
	35	#define TACK 0x10 /* Transfer acknowledge (output) */
	36	#define TIP 0x20 /* Transfer in progress (output) */
	37
	38	/* Bits in ACR */
	39	#define SR_CTRL 0x1c /* Shift register control bits */
	40	#define SR_EXT 0x0c /* Shift on external clock */
	41	#define SR_OUT 0x10 /* Shift out if 1 */
	42
	43	/* Bits in IFR and IER */
	44	#define IER_SET 0x80 /* set bits in IER */
	45	#define IER_CLR 0 /* clear bits in IER */
	46	#define SR_INT 0x04 /* Shift register full/empty */
	47	#define T1_INT 0x40 /* Timer 1 interrupt */
61271e5c	48	#define T2_INT 0x20 /* Timer 2 interrupt */
267002cd FB	49
	50	/* Bits in ACR */
	51	#define T1MODE 0xc0 /* Timer 1 mode */
	52	#define T1MODE_CONT 0x40 /* continuous interrupts */
	53
	54	/* commands (1st byte) */
	55	#define ADB_PACKET 0
	56	#define CUDA_PACKET 1
	57	#define ERROR_PACKET 2
	58	#define TIMER_PACKET 3
	59	#define POWER_PACKET 4
	60	#define MACIIC_PACKET 5
	61	#define PMU_PACKET 6
	62
	63
	64	/* CUDA commands (2nd byte) */
	65	#define CUDA_WARM_START 0x0
	66	#define CUDA_AUTOPOLL 0x1
	67	#define CUDA_GET_6805_ADDR 0x2
	68	#define CUDA_GET_TIME 0x3
	69	#define CUDA_GET_PRAM 0x7
	70	#define CUDA_SET_6805_ADDR 0x8
	71	#define CUDA_SET_TIME 0x9
	72	#define CUDA_POWERDOWN 0xa
	73	#define CUDA_POWERUP_TIME 0xb
	74	#define CUDA_SET_PRAM 0xc
	75	#define CUDA_MS_RESET 0xd
	76	#define CUDA_SEND_DFAC 0xe
	77	#define CUDA_BATTERY_SWAP_SENSE 0x10
	78	#define CUDA_RESET_SYSTEM 0x11
	79	#define CUDA_SET_IPL 0x12
	80	#define CUDA_FILE_SERVER_FLAG 0x13
	81	#define CUDA_SET_AUTO_RATE 0x14
	82	#define CUDA_GET_AUTO_RATE 0x16
	83	#define CUDA_SET_DEVICE_LIST 0x19
	84	#define CUDA_GET_DEVICE_LIST 0x1a
	85	#define CUDA_SET_ONE_SECOND_MODE 0x1b
	86	#define CUDA_SET_POWER_MESSAGES 0x21
	87	#define CUDA_GET_SET_IIC 0x22
	88	#define CUDA_WAKEUP 0x23
	89	#define CUDA_TIMER_TICKLE 0x24
	90	#define CUDA_COMBINED_FORMAT_IIC 0x25
	91
	92	#define CUDA_TIMER_FREQ (4700000 / 6)
e2733d20	93	#define CUDA_ADB_POLL_FREQ 50
267002cd	94
d7ce296f FB	95	/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
	96	#define RTC_OFFSET 2082844800
	97
267002cd	98	typedef struct CUDATimer {
5fafdf24	99	int index;
61271e5c	100	uint16_t latch;
267002cd FB	101	uint16_t counter_value; /* counter value at load time */
	102	int64_t load_time;
	103	int64_t next_irq_time;
	104	QEMUTimer *timer;
	105	} CUDATimer;
	106
	107	typedef struct CUDAState {
	108	/* cuda registers */
	109	uint8_t b; /* B-side data */
	110	uint8_t a; /* A-side data */
	111	uint8_t dirb; /* B-side direction (1=output) */
	112	uint8_t dira; /* A-side direction (1=output) */
	113	uint8_t sr; /* Shift register */
	114	uint8_t acr; /* Auxiliary control register */
	115	uint8_t pcr; /* Peripheral control register */
	116	uint8_t ifr; /* Interrupt flag register */
	117	uint8_t ier; /* Interrupt enable register */
	118	uint8_t anh; /* A-side data, no handshake */
	119
	120	CUDATimer timers[2];
3b46e624	121
267002cd FB	122	uint8_t last_b; /* last value of B register */
267002cd FB	123	uint8_t last_acr; /* last value of B register */
3b46e624	124
267002cd FB	125	int data_in_size;
	126	int data_in_index;
	127	int data_out_index;
	128
d537cf6c	129	qemu_irq irq;
267002cd FB	130	uint8_t autopoll;
	131	uint8_t data_in[128];
	132	uint8_t data_out[16];
e2733d20	133	QEMUTimer *adb_poll_timer;
267002cd FB	134	} CUDAState;
	135
	136	static CUDAState cuda_state;
	137	ADBBusState adb_bus;
	138
	139	static void cuda_update(CUDAState *s);
5fafdf24	140	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd	141	const uint8_t *data, int len);
5fafdf24	142	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b	143	int64_t current_time);
267002cd FB	144
	145	static void cuda_update_irq(CUDAState *s)
	146	{
819e712b	147	if (s->ifr & s->ier & (SR_INT \| T1_INT)) {
d537cf6c	148	qemu_irq_raise(s->irq);
267002cd	149	} else {
d537cf6c	150	qemu_irq_lower(s->irq);
267002cd FB	151	}
	152	}
	153
	154	static unsigned int get_counter(CUDATimer *s)
	155	{
	156	int64_t d;
	157	unsigned int counter;
	158
5fafdf24	159	d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
267002cd	160	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	161	if (s->index == 0) {
	162	/* the timer goes down from latch to -1 (period of latch + 2) */
	163	if (d <= (s->counter_value + 1)) {
	164	counter = (s->counter_value - d) & 0xffff;
	165	} else {
	166	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	167	counter = (s->latch - counter) & 0xffff;
61271e5c	168	}
267002cd	169	} else {
61271e5c	170	counter = (s->counter_value - d) & 0xffff;
267002cd FB	171	}
	172	return counter;
	173	}
	174
819e712b	175	static void set_counter(CUDAState s, CUDATimer ti, unsigned int val)
267002cd	176	{
819e712b FB	177	#ifdef DEBUG_CUDA
	178	printf("cuda: T%d.counter=%d\n",
	179	1 + (ti->timer == NULL), val);
	180	#endif
	181	ti->load_time = qemu_get_clock(vm_clock);
	182	ti->counter_value = val;
	183	cuda_timer_update(s, ti, ti->load_time);
267002cd FB	184	}
	185
	186	static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
	187	{
61271e5c FB	188	int64_t d, next_time;
	189	unsigned int counter;
	190
267002cd	191	/* current counter value */
5fafdf24	192	d = muldiv64(current_time - s->load_time,
267002cd	193	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	194	/* the timer goes down from latch to -1 (period of latch + 2) */
	195	if (d <= (s->counter_value + 1)) {
	196	counter = (s->counter_value - d) & 0xffff;
	197	} else {
	198	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	199	counter = (s->latch - counter) & 0xffff;
61271e5c	200	}
3b46e624	201
61271e5c FB	202	/* Note: we consider the irq is raised on 0 */
	203	if (counter == 0xffff) {
	204	next_time = d + s->latch + 1;
	205	} else if (counter == 0) {
	206	next_time = d + s->latch + 2;
	207	} else {
	208	next_time = d + counter;
267002cd	209	}
dccfafc4	210	#if 0
819e712b	211	#ifdef DEBUG_CUDA
5fafdf24	212	printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
819e712b	213	s->latch, d, next_time - d);
dccfafc4	214	#endif
819e712b	215	#endif
5fafdf24	216	next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
267002cd FB	217	s->load_time;
	218	if (next_time <= current_time)
	219	next_time = current_time + 1;
	220	return next_time;
	221	}
	222
5fafdf24	223	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b FB	224	int64_t current_time)
	225	{
	226	if (!ti->timer)
	227	return;
	228	if ((s->acr & T1MODE) != T1MODE_CONT) {
	229	qemu_del_timer(ti->timer);
	230	} else {
	231	ti->next_irq_time = get_next_irq_time(ti, current_time);
	232	qemu_mod_timer(ti->timer, ti->next_irq_time);
	233	}
	234	}
	235
267002cd FB	236	static void cuda_timer1(void *opaque)
	237	{
	238	CUDAState *s = opaque;
	239	CUDATimer *ti = &s->timers[0];
	240
819e712b	241	cuda_timer_update(s, ti, ti->next_irq_time);
267002cd FB	242	s->ifr \|= T1_INT;
	243	cuda_update_irq(s);
	244	}
	245
	246	static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
	247	{
	248	CUDAState *s = opaque;
	249	uint32_t val;
	250
	251	addr = (addr >> 9) & 0xf;
	252	switch(addr) {
	253	case 0:
	254	val = s->b;
	255	break;
	256	case 1:
	257	val = s->a;
	258	break;
	259	case 2:
	260	val = s->dirb;
	261	break;
	262	case 3:
	263	val = s->dira;
	264	break;
	265	case 4:
	266	val = get_counter(&s->timers[0]) & 0xff;
	267	s->ifr &= ~T1_INT;
	268	cuda_update_irq(s);
	269	break;
	270	case 5:
	271	val = get_counter(&s->timers[0]) >> 8;
267002cd FB	272	cuda_update_irq(s);
	273	break;
	274	case 6:
	275	val = s->timers[0].latch & 0xff;
	276	break;
	277	case 7:
61271e5c	278	/* XXX: check this */
267002cd FB	279	val = (s->timers[0].latch >> 8) & 0xff;
	280	break;
	281	case 8:
	282	val = get_counter(&s->timers[1]) & 0xff;
61271e5c	283	s->ifr &= ~T2_INT;
267002cd FB	284	break;
	285	case 9:
	286	val = get_counter(&s->timers[1]) >> 8;
	287	break;
	288	case 10:
819e712b FB	289	val = s->sr;
	290	s->ifr &= ~SR_INT;
	291	cuda_update_irq(s);
267002cd FB	292	break;
	293	case 11:
	294	val = s->acr;
	295	break;
	296	case 12:
	297	val = s->pcr;
	298	break;
	299	case 13:
	300	val = s->ifr;
5fafdf24	301	if (s->ifr & s->ier)
b7c7b181	302	val \|= 0x80;
267002cd FB	303	break;
267002cd FB	304	case 14:
b7c7b181	305	val = s->ier \| 0x80;
267002cd FB	306	break;
	307	default:
	308	case 15:
	309	val = s->anh;
	310	break;
	311	}
	312	#ifdef DEBUG_CUDA
819e712b FB	313	if (addr != 13 \|\| val != 0)
819e712b FB	314	printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
267002cd FB	315	#endif
	316	return val;
	317	}
	318
	319	static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	320	{
	321	CUDAState *s = opaque;
3b46e624	322
267002cd FB	323	addr = (addr >> 9) & 0xf;
	324	#ifdef DEBUG_CUDA
	325	printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
	326	#endif
	327
	328	switch(addr) {
	329	case 0:
	330	s->b = val;
	331	cuda_update(s);
	332	break;
	333	case 1:
	334	s->a = val;
	335	break;
	336	case 2:
	337	s->dirb = val;
	338	break;
	339	case 3:
	340	s->dira = val;
	341	break;
	342	case 4:
61271e5c FB	343	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
61271e5c FB	344	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	345	break;
267002cd FB	346	case 5:
61271e5c FB	347	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
	348	s->ifr &= ~T1_INT;
	349	set_counter(s, &s->timers[0], s->timers[0].latch);
267002cd FB	350	break;
	351	case 6:
	352	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
819e712b	353	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	354	break;
	355	case 7:
	356	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
61271e5c	357	s->ifr &= ~T1_INT;
819e712b	358	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	359	break;
267002cd FB	360	case 8:
61271e5c	361	s->timers[1].latch = val;
819e712b	362	set_counter(s, &s->timers[1], val);
267002cd FB	363	break;
267002cd FB	364	case 9:
61271e5c	365	set_counter(s, &s->timers[1], (val << 8) \| s->timers[1].latch);
267002cd FB	366	break;
	367	case 10:
	368	s->sr = val;
	369	break;
	370	case 11:
	371	s->acr = val;
819e712b	372	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	373	cuda_update(s);
	374	break;
	375	case 12:
	376	s->pcr = val;
	377	break;
	378	case 13:
	379	/* reset bits */
	380	s->ifr &= ~val;
	381	cuda_update_irq(s);
	382	break;
	383	case 14:
	384	if (val & IER_SET) {
	385	/* set bits */
	386	s->ier \|= val & 0x7f;
	387	} else {
	388	/* reset bits */
	389	s->ier &= ~val;
	390	}
	391	cuda_update_irq(s);
	392	break;
	393	default:
	394	case 15:
	395	s->anh = val;
	396	break;
	397	}
	398	}
	399
	400	/* NOTE: TIP and TREQ are negated */
	401	static void cuda_update(CUDAState *s)
	402	{
819e712b FB	403	int packet_received, len;
	404
	405	packet_received = 0;
	406	if (!(s->b & TIP)) {
	407	/* transfer requested from host */
267002cd	408
819e712b FB	409	if (s->acr & SR_OUT) {
	410	/* data output */
	411	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	412	if (s->data_out_index < sizeof(s->data_out)) {
	413	#ifdef DEBUG_CUDA
	414	printf("cuda: send: %02x\n", s->sr);
	415	#endif
	416	s->data_out[s->data_out_index++] = s->sr;
	417	s->ifr \|= SR_INT;
	418	cuda_update_irq(s);
	419	}
	420	}
	421	} else {
	422	if (s->data_in_index < s->data_in_size) {
	423	/* data input */
	424	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	425	s->sr = s->data_in[s->data_in_index++];
	426	#ifdef DEBUG_CUDA
	427	printf("cuda: recv: %02x\n", s->sr);
	428	#endif
	429	/* indicate end of transfer */
	430	if (s->data_in_index >= s->data_in_size) {
	431	s->b = (s->b \| TREQ);
	432	}
	433	s->ifr \|= SR_INT;
	434	cuda_update_irq(s);
	435	}
267002cd	436	}
819e712b FB	437	}
	438	} else {
	439	/* no transfer requested: handle sync case */
	440	if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
	441	/* update TREQ state each time TACK change state */
	442	if (s->b & TACK)
	443	s->b = (s->b \| TREQ);
	444	else
	445	s->b = (s->b & ~TREQ);
267002cd FB	446	s->ifr \|= SR_INT;
267002cd FB	447	cuda_update_irq(s);
819e712b FB	448	} else {
819e712b FB	449	if (!(s->last_b & TIP)) {
e91c8a77	450	/* handle end of host to cuda transfer */
819e712b	451	packet_received = (s->data_out_index > 0);
e91c8a77	452	/* always an IRQ at the end of transfer */
819e712b FB	453	s->ifr \|= SR_INT;
	454	cuda_update_irq(s);
	455	}
	456	/* signal if there is data to read */
	457	if (s->data_in_index < s->data_in_size) {
	458	s->b = (s->b & ~TREQ);
	459	}
267002cd FB	460	}
	461	}
	462
267002cd FB	463	s->last_acr = s->acr;
267002cd FB	464	s->last_b = s->b;
819e712b FB	465
	466	/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
	467	recursively */
	468	if (packet_received) {
	469	len = s->data_out_index;
	470	s->data_out_index = 0;
	471	cuda_receive_packet_from_host(s, s->data_out, len);
	472	}
267002cd FB	473	}
267002cd FB	474
5fafdf24	475	static void cuda_send_packet_to_host(CUDAState *s,
267002cd FB	476	const uint8_t *data, int len)
267002cd FB	477	{
819e712b FB	478	#ifdef DEBUG_CUDA_PACKET
	479	{
	480	int i;
	481	printf("cuda_send_packet_to_host:\n");
	482	for(i = 0; i < len; i++)
	483	printf(" %02x", data[i]);
	484	printf("\n");
	485	}
	486	#endif
267002cd FB	487	memcpy(s->data_in, data, len);
	488	s->data_in_size = len;
	489	s->data_in_index = 0;
	490	cuda_update(s);
	491	s->ifr \|= SR_INT;
	492	cuda_update_irq(s);
	493	}
	494
7db4eea6	495	static void cuda_adb_poll(void *opaque)
e2733d20 FB	496	{
	497	CUDAState *s = opaque;
	498	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	499	int olen;
	500
	501	olen = adb_poll(&adb_bus, obuf + 2);
	502	if (olen > 0) {
	503	obuf[0] = ADB_PACKET;
	504	obuf[1] = 0x40; /* polled data */
	505	cuda_send_packet_to_host(s, obuf, olen + 2);
	506	}
5fafdf24 TS	507	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	508	qemu_get_clock(vm_clock) +
e2733d20 FB	509	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	510	}
	511
5fafdf24	512	static void cuda_receive_packet(CUDAState *s,
267002cd FB	513	const uint8_t *data, int len)
	514	{
	515	uint8_t obuf[16];
e2733d20	516	int ti, autopoll;
267002cd FB	517
	518	switch(data[0]) {
	519	case CUDA_AUTOPOLL:
e2733d20 FB	520	autopoll = (data[1] != 0);
	521	if (autopoll != s->autopoll) {
	522	s->autopoll = autopoll;
	523	if (autopoll) {
5fafdf24 TS	524	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	525	qemu_get_clock(vm_clock) +
e2733d20 FB	526	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	527	} else {
	528	qemu_del_timer(s->adb_poll_timer);
	529	}
	530	}
267002cd FB	531	obuf[0] = CUDA_PACKET;
	532	obuf[1] = data[1];
	533	cuda_send_packet_to_host(s, obuf, 2);
	534	break;
	535	case CUDA_GET_TIME:
dccfafc4	536	case CUDA_SET_TIME:
267002cd	537	/* XXX: add time support ? */
d7ce296f	538	ti = time(NULL) + RTC_OFFSET;
267002cd FB	539	obuf[0] = CUDA_PACKET;
	540	obuf[1] = 0;
	541	obuf[2] = 0;
	542	obuf[3] = ti >> 24;
	543	obuf[4] = ti >> 16;
	544	obuf[5] = ti >> 8;
	545	obuf[6] = ti;
	546	cuda_send_packet_to_host(s, obuf, 7);
	547	break;
267002cd FB	548	case CUDA_FILE_SERVER_FLAG:
	549	case CUDA_SET_DEVICE_LIST:
	550	case CUDA_SET_AUTO_RATE:
	551	case CUDA_SET_POWER_MESSAGES:
	552	obuf[0] = CUDA_PACKET;
	553	obuf[1] = 0;
	554	cuda_send_packet_to_host(s, obuf, 2);
	555	break;
d7ce296f FB	556	case CUDA_POWERDOWN:
	557	obuf[0] = CUDA_PACKET;
	558	obuf[1] = 0;
	559	cuda_send_packet_to_host(s, obuf, 2);
	560	qemu_system_shutdown_request();
	561	break;
0686970f JM	562	case CUDA_RESET_SYSTEM:
	563	obuf[0] = CUDA_PACKET;
	564	obuf[1] = 0;
	565	cuda_send_packet_to_host(s, obuf, 2);
	566	qemu_system_reset_request();
	567	break;
267002cd FB	568	default:
	569	break;
	570	}
	571	}
	572
5fafdf24	573	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd FB	574	const uint8_t *data, int len)
267002cd FB	575	{
819e712b FB	576	#ifdef DEBUG_CUDA_PACKET
	577	{
	578	int i;
cadae95f	579	printf("cuda_receive_packet_from_host:\n");
819e712b FB	580	for(i = 0; i < len; i++)
	581	printf(" %02x", data[i]);
	582	printf("\n");
	583	}
	584	#endif
267002cd FB	585	switch(data[0]) {
267002cd FB	586	case ADB_PACKET:
e2733d20 FB	587	{
	588	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	589	int olen;
	590	olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
38f0b147	591	if (olen > 0) {
e2733d20 FB	592	obuf[0] = ADB_PACKET;
	593	obuf[1] = 0x00;
	594	} else {
38f0b147	595	/* error */
e2733d20	596	obuf[0] = ADB_PACKET;
38f0b147 FB	597	obuf[1] = -olen;
38f0b147 FB	598	olen = 0;
e2733d20 FB	599	}
	600	cuda_send_packet_to_host(s, obuf, olen + 2);
	601	}
267002cd FB	602	break;
	603	case CUDA_PACKET:
	604	cuda_receive_packet(s, data + 1, len - 1);
	605	break;
	606	}
	607	}
	608
	609	static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	610	{
	611	}
	612
	613	static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	614	{
	615	}
	616
	617	static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
	618	{
	619	return 0;
	620	}
	621
	622	static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
	623	{
	624	return 0;
	625	}
	626
	627	static CPUWriteMemoryFunc *cuda_write[] = {
	628	&cuda_writeb,
	629	&cuda_writew,
	630	&cuda_writel,
	631	};
	632
	633	static CPUReadMemoryFunc *cuda_read[] = {
	634	&cuda_readb,
	635	&cuda_readw,
	636	&cuda_readl,
	637	};
	638
3cbee15b	639	void cuda_init (int *cuda_mem_index, qemu_irq irq)
267002cd FB	640	{
267002cd FB	641	CUDAState *s = &cuda_state;
267002cd	642
819e712b FB	643	s->irq = irq;
819e712b FB	644
61271e5c	645	s->timers[0].index = 0;
267002cd	646	s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
61271e5c	647	s->timers[0].latch = 0xffff;
819e712b	648	set_counter(s, &s->timers[0], 0xffff);
61271e5c FB	649
	650	s->timers[1].index = 1;
	651	s->timers[1].latch = 0;
cadae95f FB	652	// s->ier = T1_INT \| SR_INT;
cadae95f FB	653	s->ier = 0;
819e712b	654	set_counter(s, &s->timers[1], 0xffff);
e2733d20 FB	655
e2733d20 FB	656	s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
3cbee15b	657	*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
267002cd	658	}