[qemu.git] / hw / cuda.c

/*
 * QEMU PowerMac CUDA device support
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "qemu-timer.h"
#include "sysemu.h"

/* XXX: implement all timer modes */

//#define DEBUG_CUDA
//#define DEBUG_CUDA_PACKET

/* Bits in B data register: all active low */
#define TREQ		0x08		/* Transfer request (input) */
#define TACK		0x10		/* Transfer acknowledge (output) */
#define TIP		0x20		/* Transfer in progress (output) */

/* Bits in ACR */
#define SR_CTRL		0x1c		/* Shift register control bits */
#define SR_EXT		0x0c		/* Shift on external clock */
#define SR_OUT		0x10		/* Shift out if 1 */

/* Bits in IFR and IER */
#define IER_SET		0x80		/* set bits in IER */
#define IER_CLR		0		/* clear bits in IER */
#define SR_INT		0x04		/* Shift register full/empty */
#define T1_INT          0x40            /* Timer 1 interrupt */
#define T2_INT          0x20            /* Timer 2 interrupt */

/* Bits in ACR */
#define T1MODE          0xc0            /* Timer 1 mode */
#define T1MODE_CONT     0x40            /*  continuous interrupts */

/* commands (1st byte) */
#define ADB_PACKET	0
#define CUDA_PACKET	1
#define ERROR_PACKET	2
#define TIMER_PACKET	3
#define POWER_PACKET	4
#define MACIIC_PACKET	5
#define PMU_PACKET	6


/* CUDA commands (2nd byte) */
#define CUDA_WARM_START			0x0
#define CUDA_AUTOPOLL			0x1
#define CUDA_GET_6805_ADDR		0x2
#define CUDA_GET_TIME			0x3
#define CUDA_GET_PRAM			0x7
#define CUDA_SET_6805_ADDR		0x8
#define CUDA_SET_TIME			0x9
#define CUDA_POWERDOWN			0xa
#define CUDA_POWERUP_TIME		0xb
#define CUDA_SET_PRAM			0xc
#define CUDA_MS_RESET			0xd
#define CUDA_SEND_DFAC			0xe
#define CUDA_BATTERY_SWAP_SENSE		0x10
#define CUDA_RESET_SYSTEM		0x11
#define CUDA_SET_IPL			0x12
#define CUDA_FILE_SERVER_FLAG		0x13
#define CUDA_SET_AUTO_RATE		0x14
#define CUDA_GET_AUTO_RATE		0x16
#define CUDA_SET_DEVICE_LIST		0x19
#define CUDA_GET_DEVICE_LIST		0x1a
#define CUDA_SET_ONE_SECOND_MODE	0x1b
#define CUDA_SET_POWER_MESSAGES		0x21
#define CUDA_GET_SET_IIC		0x22
#define CUDA_WAKEUP			0x23
#define CUDA_TIMER_TICKLE		0x24
#define CUDA_COMBINED_FORMAT_IIC	0x25

#define CUDA_TIMER_FREQ (4700000 / 6)
#define CUDA_ADB_POLL_FREQ 50

/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
#define RTC_OFFSET                      2082844800

typedef struct CUDATimer {
    int index;
    uint16_t latch;
    uint16_t counter_value; /* counter value at load time */
    int64_t load_time;
    int64_t next_irq_time;
    QEMUTimer *timer;
} CUDATimer;

typedef struct CUDAState {
    /* cuda registers */
    uint8_t b;      /* B-side data */
    uint8_t a;      /* A-side data */
    uint8_t dirb;   /* B-side direction (1=output) */
    uint8_t dira;   /* A-side direction (1=output) */
    uint8_t sr;     /* Shift register */
    uint8_t acr;    /* Auxiliary control register */
    uint8_t pcr;    /* Peripheral control register */
    uint8_t ifr;    /* Interrupt flag register */
    uint8_t ier;    /* Interrupt enable register */
    uint8_t anh;    /* A-side data, no handshake */

    CUDATimer timers[2];

    uint8_t last_b; /* last value of B register */
    uint8_t last_acr; /* last value of B register */

    int data_in_size;
    int data_in_index;
    int data_out_index;

    qemu_irq irq;
    uint8_t autopoll;
    uint8_t data_in[128];
    uint8_t data_out[16];
    QEMUTimer *adb_poll_timer;
} CUDAState;

static CUDAState cuda_state;
ADBBusState adb_bus;

static void cuda_update(CUDAState *s);
static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len);
static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time);

static void cuda_update_irq(CUDAState *s)
{
    if (s->ifr & s->ier & (SR_INT | T1_INT)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static unsigned int get_counter(CUDATimer *s)
{
    int64_t d;
    unsigned int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    if (s->index == 0) {
        /* the timer goes down from latch to -1 (period of latch + 2) */
        if (d <= (s->counter_value + 1)) {
            counter = (s->counter_value - d) & 0xffff;
        } else {
            counter = (d - (s->counter_value + 1)) % (s->latch + 2);
            counter = (s->latch - counter) & 0xffff;
        }
    } else {
        counter = (s->counter_value - d) & 0xffff;
    }
    return counter;
}

static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{
#ifdef DEBUG_CUDA
    printf("cuda: T%d.counter=%d\n",
           1 + (ti->timer == NULL), val);
#endif
    ti->load_time = qemu_get_clock(vm_clock);
    ti->counter_value = val;
    cuda_timer_update(s, ti, ti->load_time);
}

static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
{
    int64_t d, next_time;
    unsigned int counter;

    /* current counter value */
    d = muldiv64(current_time - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    /* the timer goes down from latch to -1 (period of latch + 2) */
    if (d <= (s->counter_value + 1)) {
        counter = (s->counter_value - d) & 0xffff;
    } else {
        counter = (d - (s->counter_value + 1)) % (s->latch + 2);
        counter = (s->latch - counter) & 0xffff;
    }

    /* Note: we consider the irq is raised on 0 */
    if (counter == 0xffff) {
        next_time = d + s->latch + 1;
    } else if (counter == 0) {
        next_time = d + s->latch + 2;
    } else {
        next_time = d + counter;
    }
#if 0
#ifdef DEBUG_CUDA
    printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
           s->latch, d, next_time - d);
#endif
#endif
    next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
        s->load_time;
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time)
{
    if (!ti->timer)
        return;
    if ((s->acr & T1MODE) != T1MODE_CONT) {
        qemu_del_timer(ti->timer);
    } else {
        ti->next_irq_time = get_next_irq_time(ti, current_time);
        qemu_mod_timer(ti->timer, ti->next_irq_time);
    }
}

static void cuda_timer1(void *opaque)
{
    CUDAState *s = opaque;
    CUDATimer *ti = &s->timers[0];

    cuda_timer_update(s, ti, ti->next_irq_time);
    s->ifr |= T1_INT;
    cuda_update_irq(s);
}

static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
    CUDAState *s = opaque;
    uint32_t val;

    addr = (addr >> 9) & 0xf;
    switch(addr) {
    case 0:
        val = s->b;
        break;
    case 1:
        val = s->a;
        break;
    case 2:
        val = s->dirb;
        break;
    case 3:
        val = s->dira;
        break;
    case 4:
        val = get_counter(&s->timers[0]) & 0xff;
        s->ifr &= ~T1_INT;
        cuda_update_irq(s);
        break;
    case 5:
        val = get_counter(&s->timers[0]) >> 8;
        cuda_update_irq(s);
        break;
    case 6:
        val = s->timers[0].latch & 0xff;
        break;
    case 7:
        /* XXX: check this */
        val = (s->timers[0].latch >> 8) & 0xff;
        break;
    case 8:
        val = get_counter(&s->timers[1]) & 0xff;
        s->ifr &= ~T2_INT;
        break;
    case 9:
        val = get_counter(&s->timers[1]) >> 8;
        break;
    case 10:
        val = s->sr;
        s->ifr &= ~SR_INT;
        cuda_update_irq(s);
        break;
    case 11:
        val = s->acr;
        break;
    case 12:
        val = s->pcr;
        break;
    case 13:
        val = s->ifr;
        if (s->ifr & s->ier)
            val |= 0x80;
        break;
    case 14:
        val = s->ier | 0x80;
        break;
    default:
    case 15:
        val = s->anh;
        break;
    }
#ifdef DEBUG_CUDA
    if (addr != 13 || val != 0)
        printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
#endif
    return val;
}

static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    CUDAState *s = opaque;

    addr = (addr >> 9) & 0xf;
#ifdef DEBUG_CUDA
    printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
#endif

    switch(addr) {
    case 0:
        s->b = val;
        cuda_update(s);
        break;
    case 1:
        s->a = val;
        break;
    case 2:
        s->dirb = val;
        break;
    case 3:
        s->dira = val;
        break;
    case 4:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 5:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        set_counter(s, &s->timers[0], s->timers[0].latch);
        break;
    case 6:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 7:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 8:
        s->timers[1].latch = val;
        set_counter(s, &s->timers[1], val);
        break;
    case 9:
        set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
        break;
    case 10:
        s->sr = val;
        break;
    case 11:
        s->acr = val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        cuda_update(s);
        break;
    case 12:
        s->pcr = val;
        break;
    case 13:
        /* reset bits */
        s->ifr &= ~val;
        cuda_update_irq(s);
        break;
    case 14:
        if (val & IER_SET) {
            /* set bits */
            s->ier |= val & 0x7f;
        } else {
            /* reset bits */
            s->ier &= ~val;
        }
        cuda_update_irq(s);
        break;
    default:
    case 15:
        s->anh = val;
        break;
    }
}

/* NOTE: TIP and TREQ are negated */
static void cuda_update(CUDAState *s)
{
    int packet_received, len;

    packet_received = 0;
    if (!(s->b & TIP)) {
        /* transfer requested from host */

        if (s->acr & SR_OUT) {
            /* data output */
            if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                if (s->data_out_index < sizeof(s->data_out)) {
#ifdef DEBUG_CUDA
                    printf("cuda: send: %02x\n", s->sr);
#endif
                    s->data_out[s->data_out_index++] = s->sr;
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        } else {
            if (s->data_in_index < s->data_in_size) {
                /* data input */
                if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                    s->sr = s->data_in[s->data_in_index++];
#ifdef DEBUG_CUDA
                    printf("cuda: recv: %02x\n", s->sr);
#endif
                    /* indicate end of transfer */
                    if (s->data_in_index >= s->data_in_size) {
                        s->b = (s->b | TREQ);
                    }
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        }
    } else {
        /* no transfer requested: handle sync case */
        if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
            /* update TREQ state each time TACK change state */
            if (s->b & TACK)
                s->b = (s->b | TREQ);
            else
                s->b = (s->b & ~TREQ);
            s->ifr |= SR_INT;
            cuda_update_irq(s);
        } else {
            if (!(s->last_b & TIP)) {
                /* handle end of host to cuda transfer */
                packet_received = (s->data_out_index > 0);
                /* always an IRQ at the end of transfer */
                s->ifr |= SR_INT;
                cuda_update_irq(s);
            }
            /* signal if there is data to read */
            if (s->data_in_index < s->data_in_size) {
                s->b = (s->b & ~TREQ);
            }
        }
    }

    s->last_acr = s->acr;
    s->last_b = s->b;

    /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
       recursively */
    if (packet_received) {
        len = s->data_out_index;
        s->data_out_index = 0;
        cuda_receive_packet_from_host(s, s->data_out, len);
    }
}

static void cuda_send_packet_to_host(CUDAState *s,
                                     const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_send_packet_to_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    memcpy(s->data_in, data, len);
    s->data_in_size = len;
    s->data_in_index = 0;
    cuda_update(s);
    s->ifr |= SR_INT;
    cuda_update_irq(s);
}

static void cuda_adb_poll(void *opaque)
{
    CUDAState *s = opaque;
    uint8_t obuf[ADB_MAX_OUT_LEN + 2];
    int olen;

    olen = adb_poll(&adb_bus, obuf + 2);
    if (olen > 0) {
        obuf[0] = ADB_PACKET;
        obuf[1] = 0x40; /* polled data */
        cuda_send_packet_to_host(s, obuf, olen + 2);
    }
    qemu_mod_timer(s->adb_poll_timer,
                   qemu_get_clock(vm_clock) +
                   (ticks_per_sec / CUDA_ADB_POLL_FREQ));
}

static void cuda_receive_packet(CUDAState *s,
                                const uint8_t *data, int len)
{
    uint8_t obuf[16];
    int ti, autopoll;

    switch(data[0]) {
    case CUDA_AUTOPOLL:
        autopoll = (data[1] != 0);
        if (autopoll != s->autopoll) {
            s->autopoll = autopoll;
            if (autopoll) {
                qemu_mod_timer(s->adb_poll_timer,
                               qemu_get_clock(vm_clock) +
                               (ticks_per_sec / CUDA_ADB_POLL_FREQ));
            } else {
                qemu_del_timer(s->adb_poll_timer);
            }
        }
        obuf[0] = CUDA_PACKET;
        obuf[1] = data[1];
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_GET_TIME:
    case CUDA_SET_TIME:
        /* XXX: add time support ? */
        ti = time(NULL) + RTC_OFFSET;
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        obuf[2] = 0;
        obuf[3] = ti >> 24;
        obuf[4] = ti >> 16;
        obuf[5] = ti >> 8;
        obuf[6] = ti;
        cuda_send_packet_to_host(s, obuf, 7);
        break;
    case CUDA_FILE_SERVER_FLAG:
    case CUDA_SET_DEVICE_LIST:
    case CUDA_SET_AUTO_RATE:
    case CUDA_SET_POWER_MESSAGES:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_POWERDOWN:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
	qemu_system_shutdown_request();
	break;
    case CUDA_RESET_SYSTEM:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
        qemu_system_reset_request();
        break;
    default:
        break;
    }
}

static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_receive_packet_from_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    switch(data[0]) {
    case ADB_PACKET:
        {
            uint8_t obuf[ADB_MAX_OUT_LEN + 2];
            int olen;
            olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
            if (olen > 0) {
                obuf[0] = ADB_PACKET;
                obuf[1] = 0x00;
            } else {
                /* error */
                obuf[0] = ADB_PACKET;
                obuf[1] = -olen;
                olen = 0;
            }
            cuda_send_packet_to_host(s, obuf, olen + 2);
        }
        break;
    case CUDA_PACKET:
        cuda_receive_packet(s, data + 1, len - 1);
        break;
    }
}

static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *cuda_write[] = {
    &cuda_writeb,
    &cuda_writew,
    &cuda_writel,
};

static CPUReadMemoryFunc *cuda_read[] = {
    &cuda_readb,
    &cuda_readw,
    &cuda_readl,
};

void cuda_init (int *cuda_mem_index, qemu_irq irq)
{
    CUDAState *s = &cuda_state;

    s->irq = irq;

    s->timers[0].index = 0;
    s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
    s->timers[0].latch = 0xffff;
    set_counter(s, &s->timers[0], 0xffff);

    s->timers[1].index = 1;
    s->timers[1].latch = 0;
    //    s->ier = T1_INT | SR_INT;
    s->ier = 0;
    set_counter(s, &s->timers[1], 0xffff);

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
    *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
}
Commit	Line	Data
267002cd	1	/*
3cbee15b	2	* QEMU PowerMac CUDA device support
5fafdf24	3	*
3cbee15b JM	4	* Copyright (c) 2004-2007 Fabrice Bellard
3cbee15b JM	5	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	6	*
267002cd FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b	25	#include "hw.h"
3cbee15b	26	#include "ppc_mac.h"
87ecb68b PB	27	#include "qemu-timer.h"
87ecb68b PB	28	#include "sysemu.h"
267002cd	29
61271e5c FB	30	/* XXX: implement all timer modes */
61271e5c FB	31
819e712b FB	32	//#define DEBUG_CUDA
	33	//#define DEBUG_CUDA_PACKET
	34
267002cd FB	35	/* Bits in B data register: all active low */
	36	#define TREQ 0x08 /* Transfer request (input) */
	37	#define TACK 0x10 /* Transfer acknowledge (output) */
	38	#define TIP 0x20 /* Transfer in progress (output) */
	39
	40	/* Bits in ACR */
	41	#define SR_CTRL 0x1c /* Shift register control bits */
	42	#define SR_EXT 0x0c /* Shift on external clock */
	43	#define SR_OUT 0x10 /* Shift out if 1 */
	44
	45	/* Bits in IFR and IER */
	46	#define IER_SET 0x80 /* set bits in IER */
	47	#define IER_CLR 0 /* clear bits in IER */
	48	#define SR_INT 0x04 /* Shift register full/empty */
	49	#define T1_INT 0x40 /* Timer 1 interrupt */
61271e5c	50	#define T2_INT 0x20 /* Timer 2 interrupt */
267002cd FB	51
	52	/* Bits in ACR */
	53	#define T1MODE 0xc0 /* Timer 1 mode */
	54	#define T1MODE_CONT 0x40 /* continuous interrupts */
	55
	56	/* commands (1st byte) */
	57	#define ADB_PACKET 0
	58	#define CUDA_PACKET 1
	59	#define ERROR_PACKET 2
	60	#define TIMER_PACKET 3
	61	#define POWER_PACKET 4
	62	#define MACIIC_PACKET 5
	63	#define PMU_PACKET 6
	64
	65
	66	/* CUDA commands (2nd byte) */
	67	#define CUDA_WARM_START 0x0
	68	#define CUDA_AUTOPOLL 0x1
	69	#define CUDA_GET_6805_ADDR 0x2
	70	#define CUDA_GET_TIME 0x3
	71	#define CUDA_GET_PRAM 0x7
	72	#define CUDA_SET_6805_ADDR 0x8
	73	#define CUDA_SET_TIME 0x9
	74	#define CUDA_POWERDOWN 0xa
	75	#define CUDA_POWERUP_TIME 0xb
	76	#define CUDA_SET_PRAM 0xc
	77	#define CUDA_MS_RESET 0xd
	78	#define CUDA_SEND_DFAC 0xe
	79	#define CUDA_BATTERY_SWAP_SENSE 0x10
	80	#define CUDA_RESET_SYSTEM 0x11
	81	#define CUDA_SET_IPL 0x12
	82	#define CUDA_FILE_SERVER_FLAG 0x13
	83	#define CUDA_SET_AUTO_RATE 0x14
	84	#define CUDA_GET_AUTO_RATE 0x16
	85	#define CUDA_SET_DEVICE_LIST 0x19
	86	#define CUDA_GET_DEVICE_LIST 0x1a
	87	#define CUDA_SET_ONE_SECOND_MODE 0x1b
	88	#define CUDA_SET_POWER_MESSAGES 0x21
	89	#define CUDA_GET_SET_IIC 0x22
	90	#define CUDA_WAKEUP 0x23
	91	#define CUDA_TIMER_TICKLE 0x24
	92	#define CUDA_COMBINED_FORMAT_IIC 0x25
	93
	94	#define CUDA_TIMER_FREQ (4700000 / 6)
e2733d20	95	#define CUDA_ADB_POLL_FREQ 50
267002cd	96
d7ce296f FB	97	/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
	98	#define RTC_OFFSET 2082844800
	99
267002cd	100	typedef struct CUDATimer {
5fafdf24	101	int index;
61271e5c	102	uint16_t latch;
267002cd FB	103	uint16_t counter_value; /* counter value at load time */
	104	int64_t load_time;
	105	int64_t next_irq_time;
	106	QEMUTimer *timer;
	107	} CUDATimer;
	108
	109	typedef struct CUDAState {
	110	/* cuda registers */
	111	uint8_t b; /* B-side data */
	112	uint8_t a; /* A-side data */
	113	uint8_t dirb; /* B-side direction (1=output) */
	114	uint8_t dira; /* A-side direction (1=output) */
	115	uint8_t sr; /* Shift register */
	116	uint8_t acr; /* Auxiliary control register */
	117	uint8_t pcr; /* Peripheral control register */
	118	uint8_t ifr; /* Interrupt flag register */
	119	uint8_t ier; /* Interrupt enable register */
	120	uint8_t anh; /* A-side data, no handshake */
	121
	122	CUDATimer timers[2];
3b46e624	123
267002cd FB	124	uint8_t last_b; /* last value of B register */
267002cd FB	125	uint8_t last_acr; /* last value of B register */
3b46e624	126
267002cd FB	127	int data_in_size;
	128	int data_in_index;
	129	int data_out_index;
	130
d537cf6c	131	qemu_irq irq;
267002cd FB	132	uint8_t autopoll;
	133	uint8_t data_in[128];
	134	uint8_t data_out[16];
e2733d20	135	QEMUTimer *adb_poll_timer;
267002cd FB	136	} CUDAState;
	137
	138	static CUDAState cuda_state;
	139	ADBBusState adb_bus;
	140
	141	static void cuda_update(CUDAState *s);
5fafdf24	142	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd	143	const uint8_t *data, int len);
5fafdf24	144	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b	145	int64_t current_time);
267002cd FB	146
	147	static void cuda_update_irq(CUDAState *s)
	148	{
819e712b	149	if (s->ifr & s->ier & (SR_INT \| T1_INT)) {
d537cf6c	150	qemu_irq_raise(s->irq);
267002cd	151	} else {
d537cf6c	152	qemu_irq_lower(s->irq);
267002cd FB	153	}
	154	}
	155
	156	static unsigned int get_counter(CUDATimer *s)
	157	{
	158	int64_t d;
	159	unsigned int counter;
	160
5fafdf24	161	d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
267002cd	162	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	163	if (s->index == 0) {
	164	/* the timer goes down from latch to -1 (period of latch + 2) */
	165	if (d <= (s->counter_value + 1)) {
	166	counter = (s->counter_value - d) & 0xffff;
	167	} else {
	168	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	169	counter = (s->latch - counter) & 0xffff;
61271e5c	170	}
267002cd	171	} else {
61271e5c	172	counter = (s->counter_value - d) & 0xffff;
267002cd FB	173	}
	174	return counter;
	175	}
	176
819e712b	177	static void set_counter(CUDAState s, CUDATimer ti, unsigned int val)
267002cd	178	{
819e712b FB	179	#ifdef DEBUG_CUDA
	180	printf("cuda: T%d.counter=%d\n",
	181	1 + (ti->timer == NULL), val);
	182	#endif
	183	ti->load_time = qemu_get_clock(vm_clock);
	184	ti->counter_value = val;
	185	cuda_timer_update(s, ti, ti->load_time);
267002cd FB	186	}
	187
	188	static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
	189	{
61271e5c FB	190	int64_t d, next_time;
	191	unsigned int counter;
	192
267002cd	193	/* current counter value */
5fafdf24	194	d = muldiv64(current_time - s->load_time,
267002cd	195	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	196	/* the timer goes down from latch to -1 (period of latch + 2) */
	197	if (d <= (s->counter_value + 1)) {
	198	counter = (s->counter_value - d) & 0xffff;
	199	} else {
	200	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	201	counter = (s->latch - counter) & 0xffff;
61271e5c	202	}
3b46e624	203
61271e5c FB	204	/* Note: we consider the irq is raised on 0 */
	205	if (counter == 0xffff) {
	206	next_time = d + s->latch + 1;
	207	} else if (counter == 0) {
	208	next_time = d + s->latch + 2;
	209	} else {
	210	next_time = d + counter;
267002cd	211	}
dccfafc4	212	#if 0
819e712b	213	#ifdef DEBUG_CUDA
5fafdf24	214	printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
819e712b	215	s->latch, d, next_time - d);
dccfafc4	216	#endif
819e712b	217	#endif
5fafdf24	218	next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
267002cd FB	219	s->load_time;
	220	if (next_time <= current_time)
	221	next_time = current_time + 1;
	222	return next_time;
	223	}
	224
5fafdf24	225	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b FB	226	int64_t current_time)
	227	{
	228	if (!ti->timer)
	229	return;
	230	if ((s->acr & T1MODE) != T1MODE_CONT) {
	231	qemu_del_timer(ti->timer);
	232	} else {
	233	ti->next_irq_time = get_next_irq_time(ti, current_time);
	234	qemu_mod_timer(ti->timer, ti->next_irq_time);
	235	}
	236	}
	237
267002cd FB	238	static void cuda_timer1(void *opaque)
	239	{
	240	CUDAState *s = opaque;
	241	CUDATimer *ti = &s->timers[0];
	242
819e712b	243	cuda_timer_update(s, ti, ti->next_irq_time);
267002cd FB	244	s->ifr \|= T1_INT;
	245	cuda_update_irq(s);
	246	}
	247
	248	static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
	249	{
	250	CUDAState *s = opaque;
	251	uint32_t val;
	252
	253	addr = (addr >> 9) & 0xf;
	254	switch(addr) {
	255	case 0:
	256	val = s->b;
	257	break;
	258	case 1:
	259	val = s->a;
	260	break;
	261	case 2:
	262	val = s->dirb;
	263	break;
	264	case 3:
	265	val = s->dira;
	266	break;
	267	case 4:
	268	val = get_counter(&s->timers[0]) & 0xff;
	269	s->ifr &= ~T1_INT;
	270	cuda_update_irq(s);
	271	break;
	272	case 5:
	273	val = get_counter(&s->timers[0]) >> 8;
267002cd FB	274	cuda_update_irq(s);
	275	break;
	276	case 6:
	277	val = s->timers[0].latch & 0xff;
	278	break;
	279	case 7:
61271e5c	280	/* XXX: check this */
267002cd FB	281	val = (s->timers[0].latch >> 8) & 0xff;
	282	break;
	283	case 8:
	284	val = get_counter(&s->timers[1]) & 0xff;
61271e5c	285	s->ifr &= ~T2_INT;
267002cd FB	286	break;
	287	case 9:
	288	val = get_counter(&s->timers[1]) >> 8;
	289	break;
	290	case 10:
819e712b FB	291	val = s->sr;
	292	s->ifr &= ~SR_INT;
	293	cuda_update_irq(s);
267002cd FB	294	break;
	295	case 11:
	296	val = s->acr;
	297	break;
	298	case 12:
	299	val = s->pcr;
	300	break;
	301	case 13:
	302	val = s->ifr;
5fafdf24	303	if (s->ifr & s->ier)
b7c7b181	304	val \|= 0x80;
267002cd FB	305	break;
267002cd FB	306	case 14:
b7c7b181	307	val = s->ier \| 0x80;
267002cd FB	308	break;
	309	default:
	310	case 15:
	311	val = s->anh;
	312	break;
	313	}
	314	#ifdef DEBUG_CUDA
819e712b FB	315	if (addr != 13 \|\| val != 0)
819e712b FB	316	printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
267002cd FB	317	#endif
	318	return val;
	319	}
	320
	321	static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	322	{
	323	CUDAState *s = opaque;
3b46e624	324
267002cd FB	325	addr = (addr >> 9) & 0xf;
	326	#ifdef DEBUG_CUDA
	327	printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
	328	#endif
	329
	330	switch(addr) {
	331	case 0:
	332	s->b = val;
	333	cuda_update(s);
	334	break;
	335	case 1:
	336	s->a = val;
	337	break;
	338	case 2:
	339	s->dirb = val;
	340	break;
	341	case 3:
	342	s->dira = val;
	343	break;
	344	case 4:
61271e5c FB	345	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
61271e5c FB	346	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	347	break;
267002cd FB	348	case 5:
61271e5c FB	349	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
	350	s->ifr &= ~T1_INT;
	351	set_counter(s, &s->timers[0], s->timers[0].latch);
267002cd FB	352	break;
	353	case 6:
	354	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
819e712b	355	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	356	break;
	357	case 7:
	358	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
61271e5c	359	s->ifr &= ~T1_INT;
819e712b	360	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	361	break;
267002cd FB	362	case 8:
61271e5c	363	s->timers[1].latch = val;
819e712b	364	set_counter(s, &s->timers[1], val);
267002cd FB	365	break;
267002cd FB	366	case 9:
61271e5c	367	set_counter(s, &s->timers[1], (val << 8) \| s->timers[1].latch);
267002cd FB	368	break;
	369	case 10:
	370	s->sr = val;
	371	break;
	372	case 11:
	373	s->acr = val;
819e712b	374	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	375	cuda_update(s);
	376	break;
	377	case 12:
	378	s->pcr = val;
	379	break;
	380	case 13:
	381	/* reset bits */
	382	s->ifr &= ~val;
	383	cuda_update_irq(s);
	384	break;
	385	case 14:
	386	if (val & IER_SET) {
	387	/* set bits */
	388	s->ier \|= val & 0x7f;
	389	} else {
	390	/* reset bits */
	391	s->ier &= ~val;
	392	}
	393	cuda_update_irq(s);
	394	break;
	395	default:
	396	case 15:
	397	s->anh = val;
	398	break;
	399	}
	400	}
	401
	402	/* NOTE: TIP and TREQ are negated */
	403	static void cuda_update(CUDAState *s)
	404	{
819e712b FB	405	int packet_received, len;
	406
	407	packet_received = 0;
	408	if (!(s->b & TIP)) {
	409	/* transfer requested from host */
267002cd	410
819e712b FB	411	if (s->acr & SR_OUT) {
	412	/* data output */
	413	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	414	if (s->data_out_index < sizeof(s->data_out)) {
	415	#ifdef DEBUG_CUDA
	416	printf("cuda: send: %02x\n", s->sr);
	417	#endif
	418	s->data_out[s->data_out_index++] = s->sr;
	419	s->ifr \|= SR_INT;
	420	cuda_update_irq(s);
	421	}
	422	}
	423	} else {
	424	if (s->data_in_index < s->data_in_size) {
	425	/* data input */
	426	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	427	s->sr = s->data_in[s->data_in_index++];
	428	#ifdef DEBUG_CUDA
	429	printf("cuda: recv: %02x\n", s->sr);
	430	#endif
	431	/* indicate end of transfer */
	432	if (s->data_in_index >= s->data_in_size) {
	433	s->b = (s->b \| TREQ);
	434	}
	435	s->ifr \|= SR_INT;
	436	cuda_update_irq(s);
	437	}
267002cd	438	}
819e712b FB	439	}
	440	} else {
	441	/* no transfer requested: handle sync case */
	442	if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
	443	/* update TREQ state each time TACK change state */
	444	if (s->b & TACK)
	445	s->b = (s->b \| TREQ);
	446	else
	447	s->b = (s->b & ~TREQ);
267002cd FB	448	s->ifr \|= SR_INT;
267002cd FB	449	cuda_update_irq(s);
819e712b FB	450	} else {
819e712b FB	451	if (!(s->last_b & TIP)) {
e91c8a77	452	/* handle end of host to cuda transfer */
819e712b	453	packet_received = (s->data_out_index > 0);
e91c8a77	454	/* always an IRQ at the end of transfer */
819e712b FB	455	s->ifr \|= SR_INT;
	456	cuda_update_irq(s);
	457	}
	458	/* signal if there is data to read */
	459	if (s->data_in_index < s->data_in_size) {
	460	s->b = (s->b & ~TREQ);
	461	}
267002cd FB	462	}
	463	}
	464
267002cd FB	465	s->last_acr = s->acr;
267002cd FB	466	s->last_b = s->b;
819e712b FB	467
	468	/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
	469	recursively */
	470	if (packet_received) {
	471	len = s->data_out_index;
	472	s->data_out_index = 0;
	473	cuda_receive_packet_from_host(s, s->data_out, len);
	474	}
267002cd FB	475	}
267002cd FB	476
5fafdf24	477	static void cuda_send_packet_to_host(CUDAState *s,
267002cd FB	478	const uint8_t *data, int len)
267002cd FB	479	{
819e712b FB	480	#ifdef DEBUG_CUDA_PACKET
	481	{
	482	int i;
	483	printf("cuda_send_packet_to_host:\n");
	484	for(i = 0; i < len; i++)
	485	printf(" %02x", data[i]);
	486	printf("\n");
	487	}
	488	#endif
267002cd FB	489	memcpy(s->data_in, data, len);
	490	s->data_in_size = len;
	491	s->data_in_index = 0;
	492	cuda_update(s);
	493	s->ifr \|= SR_INT;
	494	cuda_update_irq(s);
	495	}
	496
7db4eea6	497	static void cuda_adb_poll(void *opaque)
e2733d20 FB	498	{
	499	CUDAState *s = opaque;
	500	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	501	int olen;
	502
	503	olen = adb_poll(&adb_bus, obuf + 2);
	504	if (olen > 0) {
	505	obuf[0] = ADB_PACKET;
	506	obuf[1] = 0x40; /* polled data */
	507	cuda_send_packet_to_host(s, obuf, olen + 2);
	508	}
5fafdf24 TS	509	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	510	qemu_get_clock(vm_clock) +
e2733d20 FB	511	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	512	}
	513
5fafdf24	514	static void cuda_receive_packet(CUDAState *s,
267002cd FB	515	const uint8_t *data, int len)
	516	{
	517	uint8_t obuf[16];
e2733d20	518	int ti, autopoll;
267002cd FB	519
	520	switch(data[0]) {
	521	case CUDA_AUTOPOLL:
e2733d20 FB	522	autopoll = (data[1] != 0);
	523	if (autopoll != s->autopoll) {
	524	s->autopoll = autopoll;
	525	if (autopoll) {
5fafdf24 TS	526	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	527	qemu_get_clock(vm_clock) +
e2733d20 FB	528	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	529	} else {
	530	qemu_del_timer(s->adb_poll_timer);
	531	}
	532	}
267002cd FB	533	obuf[0] = CUDA_PACKET;
	534	obuf[1] = data[1];
	535	cuda_send_packet_to_host(s, obuf, 2);
	536	break;
	537	case CUDA_GET_TIME:
dccfafc4	538	case CUDA_SET_TIME:
267002cd	539	/* XXX: add time support ? */
d7ce296f	540	ti = time(NULL) + RTC_OFFSET;
267002cd FB	541	obuf[0] = CUDA_PACKET;
	542	obuf[1] = 0;
	543	obuf[2] = 0;
	544	obuf[3] = ti >> 24;
	545	obuf[4] = ti >> 16;
	546	obuf[5] = ti >> 8;
	547	obuf[6] = ti;
	548	cuda_send_packet_to_host(s, obuf, 7);
	549	break;
267002cd FB	550	case CUDA_FILE_SERVER_FLAG:
	551	case CUDA_SET_DEVICE_LIST:
	552	case CUDA_SET_AUTO_RATE:
	553	case CUDA_SET_POWER_MESSAGES:
	554	obuf[0] = CUDA_PACKET;
	555	obuf[1] = 0;
	556	cuda_send_packet_to_host(s, obuf, 2);
	557	break;
d7ce296f FB	558	case CUDA_POWERDOWN:
	559	obuf[0] = CUDA_PACKET;
	560	obuf[1] = 0;
	561	cuda_send_packet_to_host(s, obuf, 2);
	562	qemu_system_shutdown_request();
	563	break;
0686970f JM	564	case CUDA_RESET_SYSTEM:
	565	obuf[0] = CUDA_PACKET;
	566	obuf[1] = 0;
	567	cuda_send_packet_to_host(s, obuf, 2);
	568	qemu_system_reset_request();
	569	break;
267002cd FB	570	default:
	571	break;
	572	}
	573	}
	574
5fafdf24	575	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd FB	576	const uint8_t *data, int len)
267002cd FB	577	{
819e712b FB	578	#ifdef DEBUG_CUDA_PACKET
	579	{
	580	int i;
cadae95f	581	printf("cuda_receive_packet_from_host:\n");
819e712b FB	582	for(i = 0; i < len; i++)
	583	printf(" %02x", data[i]);
	584	printf("\n");
	585	}
	586	#endif
267002cd FB	587	switch(data[0]) {
267002cd FB	588	case ADB_PACKET:
e2733d20 FB	589	{
	590	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	591	int olen;
	592	olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
38f0b147	593	if (olen > 0) {
e2733d20 FB	594	obuf[0] = ADB_PACKET;
	595	obuf[1] = 0x00;
	596	} else {
38f0b147	597	/* error */
e2733d20	598	obuf[0] = ADB_PACKET;
38f0b147 FB	599	obuf[1] = -olen;
38f0b147 FB	600	olen = 0;
e2733d20 FB	601	}
	602	cuda_send_packet_to_host(s, obuf, olen + 2);
	603	}
267002cd FB	604	break;
	605	case CUDA_PACKET:
	606	cuda_receive_packet(s, data + 1, len - 1);
	607	break;
	608	}
	609	}
	610
	611	static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	612	{
	613	}
	614
	615	static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	616	{
	617	}
	618
	619	static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
	620	{
	621	return 0;
	622	}
	623
	624	static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
	625	{
	626	return 0;
	627	}
	628
	629	static CPUWriteMemoryFunc *cuda_write[] = {
	630	&cuda_writeb,
	631	&cuda_writew,
	632	&cuda_writel,
	633	};
	634
	635	static CPUReadMemoryFunc *cuda_read[] = {
	636	&cuda_readb,
	637	&cuda_readw,
	638	&cuda_readl,
	639	};
	640
3cbee15b	641	void cuda_init (int *cuda_mem_index, qemu_irq irq)
267002cd FB	642	{
267002cd FB	643	CUDAState *s = &cuda_state;
267002cd	644
819e712b FB	645	s->irq = irq;
819e712b FB	646
61271e5c	647	s->timers[0].index = 0;
267002cd	648	s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
61271e5c	649	s->timers[0].latch = 0xffff;
819e712b	650	set_counter(s, &s->timers[0], 0xffff);
61271e5c FB	651
	652	s->timers[1].index = 1;
	653	s->timers[1].latch = 0;
cadae95f FB	654	// s->ier = T1_INT \| SR_INT;
cadae95f FB	655	s->ier = 0;
819e712b	656	set_counter(s, &s->timers[1], 0xffff);
e2733d20 FB	657
e2733d20 FB	658	s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
3cbee15b	659	*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
267002cd	660	}