[mirror_qemu.git] / hw / display / ati_2d.c

/*
 * QEMU ATI SVGA emulation
 * 2D engine functions
 *
 * Copyright (c) 2019 BALATON Zoltan
 *
 * This work is licensed under the GNU GPL license version 2 or later.
 */

#include "qemu/osdep.h"
#include "ati_int.h"
#include "ati_regs.h"
#include "qemu/log.h"
#include "ui/pixel_ops.h"

/*
 * NOTE:
 * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
 * reinvent the wheel (unlikely to get better with a naive implementation than
 * existing libraries) and avoid (poorly) reimplementing gfx primitives.
 * That is unnecessary and would become a performance problem. Instead, try to
 * map to and reuse existing optimised facilities (e.g. pixman) wherever
 * possible.
 */

static int ati_bpp_from_datatype(ATIVGAState *s)
{
    switch (s->regs.dp_datatype & 0xf) {
    case 2:
        return 8;
    case 3:
    case 4:
        return 16;
    case 5:
        return 24;
    case 6:
        return 32;
    default:
        qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
                      s->regs.dp_datatype & 0xf);
        return 0;
    }
}

#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)

void ati_2d_blt(ATIVGAState *s)
{
    /* FIXME it is probably more complex than this and may need to be */
    /* rewritten but for now as a start just to get some output: */
    DisplaySurface *ds = qemu_console_surface(s->vga.con);
    DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
            s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
            surface_bits_per_pixel(ds),
            (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
                      s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
    unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                      s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
    int bpp = ati_bpp_from_datatype(s);
    if (!bpp) {
        qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
        return;
    }
    int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
    if (!dst_stride) {
        qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
        return;
    }
    uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                        s->regs.dst_offset : s->regs.default_offset);

    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
        dst_bits += s->regs.crtc_offset & 0x07ffffff;
        dst_stride *= bpp;
    }
    uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
    if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end
        || dst_bits + dst_x
         + (dst_y + s->regs.dst_height) * dst_stride >= end) {
        qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
        return;
    }
    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
            s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
            s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
            s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
            s->regs.dst_width, s->regs.dst_height,
            (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
            (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
    switch (s->regs.dp_mix & GMC_ROP3_MASK) {
    case ROP3_SRCCOPY:
    {
        unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
                       s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
        unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                       s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
        int src_stride = DEFAULT_CNTL ?
                         s->regs.src_pitch : s->regs.default_pitch;
        if (!src_stride) {
            qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
            return;
        }
        uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                            s->regs.src_offset : s->regs.default_offset);

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
            src_bits += s->regs.crtc_offset & 0x07ffffff;
            src_stride *= bpp;
        }
        if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end
            || src_bits + src_x
             + (src_y + s->regs.dst_height) * src_stride >= end) {
            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
            return;
        }

        src_stride /= sizeof(uint32_t);
        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
                src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
                src_x, src_y, dst_x, dst_y,
                s->regs.dst_width, s->regs.dst_height);
        if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
            s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
            pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
                       src_stride, dst_stride, bpp, bpp,
                       src_x, src_y, dst_x, dst_y,
                       s->regs.dst_width, s->regs.dst_height);
        } else {
            /* FIXME: We only really need a temporary if src and dst overlap */
            int llb = s->regs.dst_width * (bpp / 8);
            int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
            uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
                                     s->regs.dst_height);
            pixman_blt((uint32_t *)src_bits, tmp,
                       src_stride, tmp_stride, bpp, bpp,
                       src_x, src_y, 0, 0,
                       s->regs.dst_width, s->regs.dst_height);
            pixman_blt(tmp, (uint32_t *)dst_bits,
                       tmp_stride, dst_stride, bpp, bpp,
                       0, 0, dst_x, dst_y,
                       s->regs.dst_width, s->regs.dst_height);
            g_free(tmp);
        }
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
                         dst_x + s->regs.dst_width : dst_x);
        s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                         dst_y + s->regs.dst_height : dst_y);
        break;
    }
    case ROP3_PATCOPY:
    case ROP3_BLACKNESS:
    case ROP3_WHITENESS:
    {
        uint32_t filler = 0;

        switch (s->regs.dp_mix & GMC_ROP3_MASK) {
        case ROP3_PATCOPY:
            filler = s->regs.dp_brush_frgd_clr;
            break;
        case ROP3_BLACKNESS:
            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
                     s->vga.palette[1], s->vga.palette[2]);
            break;
        case ROP3_WHITENESS:
            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
                     s->vga.palette[4], s->vga.palette[5]);
            break;
        }

        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
                dst_bits, dst_stride, bpp,
                s->regs.dst_x, s->regs.dst_y,
                s->regs.dst_width, s->regs.dst_height,
                filler);
        pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
                    s->regs.dst_x, s->regs.dst_y,
                    s->regs.dst_width, s->regs.dst_height,
                    filler);
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                         dst_y + s->regs.dst_height : dst_y);
        break;
    }
    default:
        qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
                      (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    }
}
Commit	Line	Data
862b4a29 BZ	1	/*
	2	* QEMU ATI SVGA emulation
	3	* 2D engine functions
	4	*
	5	* Copyright (c) 2019 BALATON Zoltan
	6	*
	7	* This work is licensed under the GNU GPL license version 2 or later.
	8	*/
	9
bbfff196	10	#include "qemu/osdep.h"
862b4a29 BZ	11	#include "ati_int.h"
	12	#include "ati_regs.h"
	13	#include "qemu/log.h"
	14	#include "ui/pixel_ops.h"
	15
	16	/*
	17	* NOTE:
	18	* This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
	19	* reinvent the wheel (unlikely to get better with a naive implementation than
	20	* existing libraries) and avoid (poorly) reimplementing gfx primitives.
	21	* That is unnecessary and would become a performance problem. Instead, try to
	22	* map to and reuse existing optimised facilities (e.g. pixman) wherever
	23	* possible.
	24	*/
	25
	26	static int ati_bpp_from_datatype(ATIVGAState *s)
	27	{
	28	switch (s->regs.dp_datatype & 0xf) {
	29	case 2:
	30	return 8;
	31	case 3:
	32	case 4:
	33	return 16;
	34	case 5:
	35	return 24;
	36	case 6:
	37	return 32;
	38	default:
	39	qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
	40	s->regs.dp_datatype & 0xf);
	41	return 0;
	42	}
	43	}
	44
c799d2ee BZ	45	#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
c799d2ee BZ	46
862b4a29 BZ	47	void ati_2d_blt(ATIVGAState *s)
	48	{
	49	/* FIXME it is probably more complex than this and may need to be */
	50	/* rewritten but for now as a start just to get some output: */
	51	DisplaySurface *ds = qemu_console_surface(s->vga.con);
	52	DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
	53	s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
	54	surface_bits_per_pixel(ds),
	55	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
ac2071c3 BZ	56	unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
	57	s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
	58	unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
	59	s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
c799d2ee	60	int bpp = ati_bpp_from_datatype(s);
ac2071c3 BZ	61	if (!bpp) {
	62	qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
	63	return;
	64	}
c799d2ee	65	int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
ac2071c3 BZ	66	if (!dst_stride) {
	67	qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
	68	return;
	69	}
c799d2ee BZ	70	uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
	71	s->regs.dst_offset : s->regs.default_offset);
	72
	73	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	74	dst_bits += s->regs.crtc_offset & 0x07ffffff;
	75	dst_stride *= bpp;
	76	}
	77	uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
ca1f9cbf PP	78	if (dst_x > 0x3fff \|\| dst_y > 0x3fff \|\| dst_bits >= end
	79	\|\| dst_bits + dst_x
	80	+ (dst_y + s->regs.dst_height) * dst_stride >= end) {
c799d2ee BZ	81	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	82	return;
	83	}
584acf34	84	DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
866ad5f5 BZ	85	s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
866ad5f5 BZ	86	s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
862b4a29	87	s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
584acf34 BZ	88	s->regs.dst_width, s->regs.dst_height,
	89	(s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
	90	(s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
862b4a29 BZ	91	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	92	case ROP3_SRCCOPY:
	93	{
ac2071c3 BZ	94	unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
	95	s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
	96	unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
	97	s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
c799d2ee BZ	98	int src_stride = DEFAULT_CNTL ?
c799d2ee BZ	99	s->regs.src_pitch : s->regs.default_pitch;
ac2071c3 BZ	100	if (!src_stride) {
	101	qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
	102	return;
	103	}
c799d2ee BZ	104	uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
c799d2ee BZ	105	s->regs.src_offset : s->regs.default_offset);
862b4a29 BZ	106
	107	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	108	src_bits += s->regs.crtc_offset & 0x07ffffff;
862b4a29	109	src_stride *= bpp;
862b4a29	110	}
ca1f9cbf PP	111	if (src_x > 0x3fff \|\| src_y > 0x3fff \|\| src_bits >= end
	112	\|\| src_bits + src_x
	113	+ (src_y + s->regs.dst_height) * src_stride >= end) {
c799d2ee BZ	114	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	115	return;
	116	}
	117
862b4a29 BZ	118	src_stride /= sizeof(uint32_t);
862b4a29 BZ	119	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	120	DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
862b4a29 BZ	121	src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
584acf34	122	src_x, src_y, dst_x, dst_y,
862b4a29	123	s->regs.dst_width, s->regs.dst_height);
584acf34 BZ	124	if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
	125	s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
	126	pixman_blt((uint32_t )src_bits, (uint32_t )dst_bits,
	127	src_stride, dst_stride, bpp, bpp,
	128	src_x, src_y, dst_x, dst_y,
	129	s->regs.dst_width, s->regs.dst_height);
	130	} else {
	131	/* FIXME: We only really need a temporary if src and dst overlap */
	132	int llb = s->regs.dst_width * (bpp / 8);
	133	int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
	134	uint32_t tmp = g_malloc(tmp_stride sizeof(uint32_t) *
	135	s->regs.dst_height);
	136	pixman_blt((uint32_t *)src_bits, tmp,
	137	src_stride, tmp_stride, bpp, bpp,
	138	src_x, src_y, 0, 0,
	139	s->regs.dst_width, s->regs.dst_height);
	140	pixman_blt(tmp, (uint32_t *)dst_bits,
	141	tmp_stride, dst_stride, bpp, bpp,
	142	0, 0, dst_x, dst_y,
	143	s->regs.dst_width, s->regs.dst_height);
	144	g_free(tmp);
	145	}
862b4a29 BZ	146	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	147	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	148	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	149	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	150	s->regs.dst_offset +
584acf34	151	dst_y * surface_stride(ds),
862b4a29 BZ	152	s->regs.dst_height * surface_stride(ds));
862b4a29 BZ	153	}
ac2071c3 BZ	154	s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
	155	dst_x + s->regs.dst_width : dst_x);
	156	s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
	157	dst_y + s->regs.dst_height : dst_y);
862b4a29 BZ	158	break;
	159	}
	160	case ROP3_PATCOPY:
	161	case ROP3_BLACKNESS:
	162	case ROP3_WHITENESS:
	163	{
862b4a29	164	uint32_t filler = 0;
862b4a29 BZ	165
	166	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	167	case ROP3_PATCOPY:
a3812741	168	filler = s->regs.dp_brush_frgd_clr;
862b4a29 BZ	169	break;
862b4a29 BZ	170	case ROP3_BLACKNESS:
a3812741 BZ	171	filler = 0xffUL << 24 \| rgb_to_pixel32(s->vga.palette[0],
a3812741 BZ	172	s->vga.palette[1], s->vga.palette[2]);
862b4a29 BZ	173	break;
862b4a29 BZ	174	case ROP3_WHITENESS:
a3812741 BZ	175	filler = 0xffUL << 24 \| rgb_to_pixel32(s->vga.palette[3],
a3812741 BZ	176	s->vga.palette[4], s->vga.palette[5]);
862b4a29 BZ	177	break;
	178	}
	179
c799d2ee	180	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	181	DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
	182	dst_bits, dst_stride, bpp,
	183	s->regs.dst_x, s->regs.dst_y,
	184	s->regs.dst_width, s->regs.dst_height,
	185	filler);
862b4a29	186	pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
c799d2ee BZ	187	s->regs.dst_x, s->regs.dst_y,
	188	s->regs.dst_width, s->regs.dst_height,
	189	filler);
862b4a29 BZ	190	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	191	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	192	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	193	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	194	s->regs.dst_offset +
584acf34	195	dst_y * surface_stride(ds),
862b4a29 BZ	196	s->regs.dst_height * surface_stride(ds));
862b4a29 BZ	197	}
ac2071c3 BZ	198	s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
ac2071c3 BZ	199	dst_y + s->regs.dst_height : dst_y);
862b4a29 BZ	200	break;
	201	}
	202	default:
	203	qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
	204	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
	205	}
	206	}