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1fc3d392
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1/*
2 * QEMU G364 framebuffer Emulator.
3 *
97a3f6ff 4 * Copyright (c) 2007-2011 Herve Poussineau
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5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 */
19
47df5154 20#include "qemu/osdep.h"
f0353b0d 21#include "qemu/units.h"
83c9f4ca 22#include "hw/hw.h"
64552b6b 23#include "hw/irq.h"
a27bd6c7 24#include "hw/qdev-properties.h"
d49b6836 25#include "qemu/error-report.h"
0b8fa32f 26#include "qemu/module.h"
28ecbaee
PB
27#include "ui/console.h"
28#include "ui/pixel_ops.h"
b213b370 29#include "trace.h"
83c9f4ca 30#include "hw/sysbus.h"
d6454270 31#include "migration/vmstate.h"
db1015e9 32#include "qom/object.h"
0add30cf 33
1fc3d392 34typedef struct G364State {
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35 /* hardware */
36 uint8_t *vram;
97a3f6ff 37 uint32_t vram_size;
0add30cf 38 qemu_irq irq;
97a3f6ff
HP
39 MemoryRegion mem_vram;
40 MemoryRegion mem_ctrl;
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41 /* registers */
42 uint8_t color_palette[256][3];
43 uint8_t cursor_palette[3][3];
44 uint16_t cursor[512];
45 uint32_t cursor_position;
1fc3d392 46 uint32_t ctla;
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47 uint32_t top_of_screen;
48 uint32_t width, height; /* in pixels */
1fc3d392 49 /* display refresh support */
c78f7137 50 QemuConsole *con;
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51 int depth;
52 int blanked;
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53} G364State;
54
97a3f6ff
HP
55#define REG_BOOT 0x000000
56#define REG_DISPLAY 0x000118
57#define REG_VDISPLAY 0x000150
58#define REG_CTLA 0x000300
59#define REG_TOP 0x000400
60#define REG_CURS_PAL 0x000508
61#define REG_CURS_POS 0x000638
62#define REG_CLR_PAL 0x000800
63#define REG_CURS_PAT 0x001000
64#define REG_RESET 0x100000
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65
66#define CTLA_FORCE_BLANK 0x00000400
67#define CTLA_NO_CURSOR 0x00800000
68
1213406b
BS
69#define G364_PAGE_SIZE 4096
70
f7189ac8 71static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page)
0add30cf 72{
f7189ac8 73 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE);
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AJ
74}
75
76static void g364fb_draw_graphic8(G364State *s)
1fc3d392 77{
c78f7137 78 DisplaySurface *surface = qemu_console_surface(s->con);
f7189ac8 79 DirtyBitmapSnapshot *snap;
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80 int i, w;
81 uint8_t *vram;
82 uint8_t *data_display, *dd;
7fcf0c24 83 ram_addr_t page;
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84 int x, y;
85 int xmin, xmax;
86 int ymin, ymax;
87 int xcursor, ycursor;
88 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
89
c78f7137 90 switch (surface_bits_per_pixel(surface)) {
1fc3d392 91 case 8:
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92 rgb_to_pixel = rgb_to_pixel8;
93 w = 1;
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94 break;
95 case 15:
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96 rgb_to_pixel = rgb_to_pixel15;
97 w = 2;
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98 break;
99 case 16:
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100 rgb_to_pixel = rgb_to_pixel16;
101 w = 2;
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102 break;
103 case 32:
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104 rgb_to_pixel = rgb_to_pixel32;
105 w = 4;
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106 break;
107 default:
b213b370 108 hw_error("g364: unknown host depth %d",
c78f7137 109 surface_bits_per_pixel(surface));
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110 return;
111 }
112
97a3f6ff 113 page = 0;
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114
115 x = y = 0;
116 xmin = s->width;
117 xmax = 0;
118 ymin = s->height;
119 ymax = 0;
120
121 if (!(s->ctla & CTLA_NO_CURSOR)) {
122 xcursor = s->cursor_position >> 12;
123 ycursor = s->cursor_position & 0xfff;
124 } else {
125 xcursor = ycursor = -65;
126 }
127
128 vram = s->vram + s->top_of_screen;
129 /* XXX: out of range in vram? */
c78f7137 130 data_display = dd = surface_data(surface);
f7189ac8
PB
131 snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size,
132 DIRTY_MEMORY_VGA);
0add30cf 133 while (y < s->height) {
f7189ac8 134 if (check_dirty(s, snap, page)) {
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135 if (y < ymin)
136 ymin = ymax = y;
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137 if (x < xmin)
138 xmin = x;
1213406b 139 for (i = 0; i < G364_PAGE_SIZE; i++) {
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140 uint8_t index;
141 unsigned int color;
142 if (unlikely((y >= ycursor && y < ycursor + 64) &&
143 (x >= xcursor && x < xcursor + 64))) {
144 /* pointer area */
145 int xdiff = x - xcursor;
146 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
147 int op = (curs >> ((xdiff & 7) * 2)) & 3;
148 if (likely(op == 0)) {
149 /* transparent */
150 index = *vram;
151 color = (*rgb_to_pixel)(
152 s->color_palette[index][0],
153 s->color_palette[index][1],
154 s->color_palette[index][2]);
155 } else {
156 /* get cursor color */
157 index = op - 1;
158 color = (*rgb_to_pixel)(
159 s->cursor_palette[index][0],
160 s->cursor_palette[index][1],
161 s->cursor_palette[index][2]);
162 }
163 } else {
164 /* normal area */
165 index = *vram;
166 color = (*rgb_to_pixel)(
167 s->color_palette[index][0],
168 s->color_palette[index][1],
169 s->color_palette[index][2]);
170 }
171 memcpy(dd, &color, w);
172 dd += w;
173 x++;
174 vram++;
175 if (x == s->width) {
176 xmax = s->width - 1;
177 y++;
178 if (y == s->height) {
179 ymax = s->height - 1;
180 goto done;
181 }
c78f7137 182 data_display = dd = data_display + surface_stride(surface);
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183 xmin = 0;
184 x = 0;
185 }
186 }
187 if (x > xmax)
188 xmax = x;
189 if (y > ymax)
190 ymax = y;
191 } else {
192 int dy;
7fcf0c24 193 if (xmax || ymax) {
c78f7137 194 dpy_gfx_update(s->con, xmin, ymin,
a93a4a22 195 xmax - xmin + 1, ymax - ymin + 1);
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196 xmin = s->width;
197 xmax = 0;
198 ymin = s->height;
199 ymax = 0;
200 }
1213406b 201 x += G364_PAGE_SIZE;
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202 dy = x / s->width;
203 x = x % s->width;
204 y += dy;
1213406b 205 vram += G364_PAGE_SIZE;
c78f7137 206 data_display += dy * surface_stride(surface);
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207 dd = data_display + x * w;
208 }
1213406b 209 page += G364_PAGE_SIZE;
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210 }
211
212done:
7fcf0c24 213 if (xmax || ymax) {
c78f7137 214 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
0add30cf 215 }
723250d6 216 g_free(snap);
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AJ
217}
218
0add30cf 219static void g364fb_draw_blank(G364State *s)
1fc3d392 220{
c78f7137 221 DisplaySurface *surface = qemu_console_surface(s->con);
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222 int i, w;
223 uint8_t *d;
224
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225 if (s->blanked) {
226 /* Screen is already blank. No need to redraw it */
1fc3d392 227 return;
0add30cf 228 }
1fc3d392 229
c78f7137
GH
230 w = s->width * surface_bytes_per_pixel(surface);
231 d = surface_data(surface);
0add30cf 232 for (i = 0; i < s->height; i++) {
1fc3d392 233 memset(d, 0, w);
c78f7137 234 d += surface_stride(surface);
1fc3d392 235 }
221bb2d5 236
91155f8b 237 dpy_gfx_update_full(s->con);
0add30cf 238 s->blanked = 1;
1fc3d392
AJ
239}
240
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241static void g364fb_update_display(void *opaque)
242{
243 G364State *s = opaque;
c78f7137 244 DisplaySurface *surface = qemu_console_surface(s->con);
1fc3d392 245
e9a07334
JK
246 qemu_flush_coalesced_mmio_buffer();
247
0add30cf 248 if (s->width == 0 || s->height == 0)
221bb2d5
AJ
249 return;
250
c78f7137
GH
251 if (s->width != surface_width(surface) ||
252 s->height != surface_height(surface)) {
253 qemu_console_resize(s->con, s->width, s->height);
221bb2d5 254 }
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255
256 if (s->ctla & CTLA_FORCE_BLANK) {
257 g364fb_draw_blank(s);
258 } else if (s->depth == 8) {
259 g364fb_draw_graphic8(s);
260 } else {
b213b370 261 error_report("g364: unknown guest depth %d", s->depth);
1fc3d392 262 }
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263
264 qemu_irq_raise(s->irq);
1fc3d392
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265}
266
86178a57 267static inline void g364fb_invalidate_display(void *opaque)
1fc3d392
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268{
269 G364State *s = opaque;
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270
271 s->blanked = 0;
fd4aa979 272 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
1fc3d392
AJ
273}
274
97a3f6ff 275static void g364fb_reset(G364State *s)
1fc3d392 276{
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277 qemu_irq_lower(s->irq);
278
279 memset(s->color_palette, 0, sizeof(s->color_palette));
280 memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
281 memset(s->cursor, 0, sizeof(s->cursor));
282 s->cursor_position = 0;
283 s->ctla = 0;
284 s->top_of_screen = 0;
285 s->width = s->height = 0;
286 memset(s->vram, 0, s->vram_size);
97a3f6ff 287 g364fb_invalidate_display(s);
1fc3d392
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288}
289
1fc3d392 290/* called for accesses to io ports */
97a3f6ff 291static uint64_t g364fb_ctrl_read(void *opaque,
a8170e5e 292 hwaddr addr,
97a3f6ff 293 unsigned int size)
1fc3d392 294{
0add30cf 295 G364State *s = opaque;
1fc3d392
AJ
296 uint32_t val;
297
0add30cf
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298 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
299 /* cursor pattern */
300 int idx = (addr - REG_CURS_PAT) >> 3;
301 val = s->cursor[idx];
302 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
303 /* cursor palette */
304 int idx = (addr - REG_CURS_PAL) >> 3;
305 val = ((uint32_t)s->cursor_palette[idx][0] << 16);
306 val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
307 val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
308 } else {
309 switch (addr) {
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310 case REG_DISPLAY:
311 val = s->width / 4;
312 break;
313 case REG_VDISPLAY:
314 val = s->height * 2;
315 break;
316 case REG_CTLA:
317 val = s->ctla;
318 break;
319 default:
320 {
b213b370
HP
321 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
322 addr);
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323 val = 0;
324 break;
325 }
326 }
1fc3d392
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327 }
328
b213b370 329 trace_g364fb_read(addr, val);
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330
331 return val;
332}
333
0add30cf 334static void g364fb_update_depth(G364State *s)
1fc3d392 335{
38972938 336 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
0add30cf
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337 s->depth = depths[(s->ctla & 0x00700000) >> 20];
338}
1fc3d392 339
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340static void g364_invalidate_cursor_position(G364State *s)
341{
c78f7137 342 DisplaySurface *surface = qemu_console_surface(s->con);
fd4aa979 343 int ymin, ymax, start, end;
1fc3d392 344
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345 /* invalidate only near the cursor */
346 ymin = s->cursor_position & 0xfff;
347 ymax = MIN(s->height, ymin + 64);
c78f7137
GH
348 start = ymin * surface_stride(surface);
349 end = (ymax + 1) * surface_stride(surface);
1fc3d392 350
fd4aa979 351 memory_region_set_dirty(&s->mem_vram, start, end - start);
0add30cf
AJ
352}
353
97a3f6ff 354static void g364fb_ctrl_write(void *opaque,
a8170e5e 355 hwaddr addr,
97a3f6ff
HP
356 uint64_t val,
357 unsigned int size)
0add30cf
AJ
358{
359 G364State *s = opaque;
360
b213b370 361 trace_g364fb_write(addr, val);
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362
363 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
1fc3d392 364 /* color palette */
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365 int idx = (addr - REG_CLR_PAL) >> 3;
366 s->color_palette[idx][0] = (val >> 16) & 0xff;
367 s->color_palette[idx][1] = (val >> 8) & 0xff;
368 s->color_palette[idx][2] = val & 0xff;
369 g364fb_invalidate_display(s);
370 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
371 /* cursor pattern */
372 int idx = (addr - REG_CURS_PAT) >> 3;
373 s->cursor[idx] = val;
374 g364fb_invalidate_display(s);
375 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
376 /* cursor palette */
377 int idx = (addr - REG_CURS_PAL) >> 3;
378 s->cursor_palette[idx][0] = (val >> 16) & 0xff;
379 s->cursor_palette[idx][1] = (val >> 8) & 0xff;
380 s->cursor_palette[idx][2] = val & 0xff;
381 g364fb_invalidate_display(s);
1fc3d392
AJ
382 } else {
383 switch (addr) {
97a3f6ff
HP
384 case REG_BOOT: /* Boot timing */
385 case 0x00108: /* Line timing: half sync */
386 case 0x00110: /* Line timing: back porch */
387 case 0x00120: /* Line timing: short display */
388 case 0x00128: /* Frame timing: broad pulse */
389 case 0x00130: /* Frame timing: v sync */
390 case 0x00138: /* Frame timing: v preequalise */
391 case 0x00140: /* Frame timing: v postequalise */
392 case 0x00148: /* Frame timing: v blank */
393 case 0x00158: /* Line timing: line time */
394 case 0x00160: /* Frame store: line start */
395 case 0x00168: /* vram cycle: mem init */
396 case 0x00170: /* vram cycle: transfer delay */
397 case 0x00200: /* vram cycle: mask register */
398 /* ignore */
399 break;
400 case REG_TOP:
401 s->top_of_screen = val;
402 g364fb_invalidate_display(s);
403 break;
404 case REG_DISPLAY:
405 s->width = val * 4;
406 break;
407 case REG_VDISPLAY:
408 s->height = val / 2;
409 break;
410 case REG_CTLA:
411 s->ctla = val;
412 g364fb_update_depth(s);
413 g364fb_invalidate_display(s);
414 break;
415 case REG_CURS_POS:
416 g364_invalidate_cursor_position(s);
417 s->cursor_position = val;
418 g364_invalidate_cursor_position(s);
419 break;
420 case REG_RESET:
421 g364fb_reset(s);
422 break;
423 default:
424 error_report("g364: invalid write of 0x%" PRIx64
425 " at [" TARGET_FMT_plx "]", val, addr);
426 break;
1fc3d392
AJ
427 }
428 }
0add30cf 429 qemu_irq_lower(s->irq);
1fc3d392
AJ
430}
431
97a3f6ff
HP
432static const MemoryRegionOps g364fb_ctrl_ops = {
433 .read = g364fb_ctrl_read,
434 .write = g364fb_ctrl_write,
435 .endianness = DEVICE_LITTLE_ENDIAN,
436 .impl.min_access_size = 4,
437 .impl.max_access_size = 4,
1fc3d392
AJ
438};
439
97a3f6ff 440static int g364fb_post_load(void *opaque, int version_id)
1fc3d392
AJ
441{
442 G364State *s = opaque;
0add30cf
AJ
443
444 /* force refresh */
445 g364fb_update_depth(s);
446 g364fb_invalidate_display(s);
1fc3d392 447
0add30cf 448 return 0;
1fc3d392
AJ
449}
450
97a3f6ff
HP
451static const VMStateDescription vmstate_g364fb = {
452 .name = "g364fb",
453 .version_id = 1,
454 .minimum_version_id = 1,
97a3f6ff
HP
455 .post_load = g364fb_post_load,
456 .fields = (VMStateField[]) {
59046ec2 457 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size),
97a3f6ff
HP
458 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
459 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
460 VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
461 VMSTATE_UINT32(cursor_position, G364State),
462 VMSTATE_UINT32(ctla, G364State),
463 VMSTATE_UINT32(top_of_screen, G364State),
464 VMSTATE_UINT32(width, G364State),
465 VMSTATE_UINT32(height, G364State),
466 VMSTATE_END_OF_LIST()
467 }
468};
1fc3d392 469
380cd056
GH
470static const GraphicHwOps g364fb_ops = {
471 .invalidate = g364fb_invalidate_display,
472 .gfx_update = g364fb_update_display,
473};
474
97a3f6ff 475static void g364fb_init(DeviceState *dev, G364State *s)
1fc3d392 476{
97a3f6ff 477 s->vram = g_malloc0(s->vram_size);
1fc3d392 478
5643706a 479 s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
1fc3d392 480
b9fc4f6e
PMD
481 memory_region_init_io(&s->mem_ctrl, OBJECT(dev), &g364fb_ctrl_ops, s,
482 "ctrl", 0x180000);
2c9b15ca 483 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
97a3f6ff 484 s->vram_size, s->vram);
c5705a77 485 vmstate_register_ram(&s->mem_vram, dev);
74259ae5 486 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA);
97a3f6ff
HP
487}
488
0f31aa86 489#define TYPE_G364 "sysbus-g364"
8063396b 490OBJECT_DECLARE_SIMPLE_TYPE(G364SysBusState, G364)
0f31aa86 491
db1015e9 492struct G364SysBusState {
0f31aa86
AF
493 SysBusDevice parent_obj;
494
97a3f6ff 495 G364State g364;
db1015e9 496};
1fc3d392 497
0323ee43 498static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
97a3f6ff 499{
0f31aa86
AF
500 G364SysBusState *sbs = G364(dev);
501 G364State *s = &sbs->g364;
0323ee43 502 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
97a3f6ff 503
0f31aa86
AF
504 g364fb_init(dev, s);
505 sysbus_init_irq(sbd, &s->irq);
506 sysbus_init_mmio(sbd, &s->mem_ctrl);
507 sysbus_init_mmio(sbd, &s->mem_vram);
1fc3d392 508}
97a3f6ff
HP
509
510static void g364fb_sysbus_reset(DeviceState *d)
511{
0f31aa86
AF
512 G364SysBusState *s = G364(d);
513
97a3f6ff
HP
514 g364fb_reset(&s->g364);
515}
516
999e12bb 517static Property g364fb_sysbus_properties[] = {
f0353b0d 518 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB),
999e12bb
AL
519 DEFINE_PROP_END_OF_LIST(),
520};
521
522static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
523{
39bffca2 524 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 525
0323ee43 526 dc->realize = g364fb_sysbus_realize;
125ee0ed 527 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
39bffca2
AL
528 dc->desc = "G364 framebuffer";
529 dc->reset = g364fb_sysbus_reset;
530 dc->vmsd = &vmstate_g364fb;
4f67d30b 531 device_class_set_props(dc, g364fb_sysbus_properties);
999e12bb
AL
532}
533
8c43a6f0 534static const TypeInfo g364fb_sysbus_info = {
0f31aa86 535 .name = TYPE_G364,
39bffca2
AL
536 .parent = TYPE_SYS_BUS_DEVICE,
537 .instance_size = sizeof(G364SysBusState),
538 .class_init = g364fb_sysbus_class_init,
97a3f6ff
HP
539};
540
83f7d43a 541static void g364fb_register_types(void)
97a3f6ff 542{
39bffca2 543 type_register_static(&g364fb_sysbus_info);
97a3f6ff
HP
544}
545
83f7d43a 546type_init(g364fb_register_types)