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target/arm: Move GTimer definitions to new 'gtimer.h' header
[mirror_qemu.git] / hw / display / omap_dss.c
CommitLineData
827df9f3
AZ		 1/*
2 * OMAP2 Display Subsystem.
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
827df9f3 19 */
64552b6b 20
47df5154 21#include "qemu/osdep.h"
cd617484 22#include "qemu/log.h"
83c9f4ca 23#include "hw/hw.h"
64552b6b 24#include "hw/irq.h"
28ecbaee 25#include "ui/console.h"
0d09e41a 26#include "hw/arm/omap.h"
827df9f3
AZ		 27
28struct omap_dss_s {
827df9f3
AZ		 29 qemu_irq irq;
30 qemu_irq drq;
31 DisplayState *state;
4852e5d8 32 MemoryRegion iomem_diss1, iomem_disc1, iomem_rfbi1, iomem_venc1, iomem_im3;
827df9f3
AZ		 33
34 int autoidle;
35 int control;
36 int enable;
37
38 struct omap_dss_panel_s {
39 int enable;
40 int nx;
41 int ny;
42
43 int x;
44 int y;
45 } dig, lcd;
46
47 struct {
48 uint32_t idlemode;
49 uint32_t irqst;
50 uint32_t irqen;
51 uint32_t control;
52 uint32_t config;
53 uint32_t capable;
f3d8b1eb 54 uint32_t timing[4];
827df9f3
AZ		 55 int line;
56 uint32_t bg[2];
57 uint32_t trans[2];
58
59 struct omap_dss_plane_s {
60 int enable;
61 int bpp;
62 int posx;
63 int posy;
64 int nx;
65 int ny;
66
a8170e5e 67 hwaddr addr[3];
827df9f3
AZ		 68
69 uint32_t attr;
70 uint32_t tresh;
71 int rowinc;
72 int colinc;
73 int wininc;
74 } l[3];
75
76 int invalidate;
77 uint16_t palette[256];
78 } dispc;
79
80 struct {
81 int idlemode;
82 uint32_t control;
83 int enable;
84 int pixels;
85 int busy;
86 int skiplines;
87 uint16_t rxbuf;
88 uint32_t config[2];
89 uint32_t time[4];
90 uint32_t data[6];
91 uint16_t vsync;
92 uint16_t hsync;
93 struct rfbi_chip_s *chip[2];
94 } rfbi;
95};
96
97static void omap_dispc_interrupt_update(struct omap_dss_s *s)
98{
99 qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen);
100}
101
102static void omap_rfbi_reset(struct omap_dss_s *s)
103{
104 s->rfbi.idlemode = 0;
105 s->rfbi.control = 2;
106 s->rfbi.enable = 0;
107 s->rfbi.pixels = 0;
108 s->rfbi.skiplines = 0;
109 s->rfbi.busy = 0;
110 s->rfbi.config[0] = 0x00310000;
111 s->rfbi.config[1] = 0x00310000;
112 s->rfbi.time[0] = 0;
113 s->rfbi.time[1] = 0;
114 s->rfbi.time[2] = 0;
115 s->rfbi.time[3] = 0;
116 s->rfbi.data[0] = 0;
117 s->rfbi.data[1] = 0;
118 s->rfbi.data[2] = 0;
119 s->rfbi.data[3] = 0;
120 s->rfbi.data[4] = 0;
121 s->rfbi.data[5] = 0;
122 s->rfbi.vsync = 0;
123 s->rfbi.hsync = 0;
124}
125
126void omap_dss_reset(struct omap_dss_s *s)
127{
128 s->autoidle = 0;
129 s->control = 0;
130 s->enable = 0;
131
132 s->dig.enable = 0;
133 s->dig.nx = 1;
134 s->dig.ny = 1;
135
136 s->lcd.enable = 0;
137 s->lcd.nx = 1;
138 s->lcd.ny = 1;
139
140 s->dispc.idlemode = 0;
141 s->dispc.irqst = 0;
142 s->dispc.irqen = 0;
143 s->dispc.control = 0;
144 s->dispc.config = 0;
145 s->dispc.capable = 0x161;
146 s->dispc.timing[0] = 0;
147 s->dispc.timing[1] = 0;
148 s->dispc.timing[2] = 0;
f3d8b1eb 149 s->dispc.timing[3] = 0;
827df9f3
AZ		 150 s->dispc.line = 0;
151 s->dispc.bg[0] = 0;
152 s->dispc.bg[1] = 0;
153 s->dispc.trans[0] = 0;
154 s->dispc.trans[1] = 0;
155
156 s->dispc.l[0].enable = 0;
157 s->dispc.l[0].bpp = 0;
158 s->dispc.l[0].addr[0] = 0;
159 s->dispc.l[0].addr[1] = 0;
160 s->dispc.l[0].addr[2] = 0;
161 s->dispc.l[0].posx = 0;
162 s->dispc.l[0].posy = 0;
163 s->dispc.l[0].nx = 1;
164 s->dispc.l[0].ny = 1;
165 s->dispc.l[0].attr = 0;
166 s->dispc.l[0].tresh = 0;
167 s->dispc.l[0].rowinc = 1;
168 s->dispc.l[0].colinc = 1;
169 s->dispc.l[0].wininc = 0;
170
171 omap_rfbi_reset(s);
172 omap_dispc_interrupt_update(s);
173}
174
a8170e5e 175static uint64_t omap_diss_read(void *opaque, hwaddr addr,
4852e5d8 176 unsigned size)
827df9f3 177{
a75ed3c4 178 struct omap_dss_s *s = opaque;
827df9f3 179
4852e5d8
AK		 180 if (size != 4) {
181 return omap_badwidth_read32(opaque, addr);
182 }
183
8da3ff18 184 switch (addr) {
a076a3dc 185 case 0x00: /* DSS_REVISIONNUMBER */
827df9f3
AZ		 186 return 0x20;
187
a076a3dc 188 case 0x10: /* DSS_SYSCONFIG */
827df9f3
AZ		 189 return s->autoidle;
190
a076a3dc
AG		 191 case 0x14: /* DSS_SYSSTATUS */
192 return 1; /* RESETDONE */
827df9f3 193
a076a3dc 194 case 0x40: /* DSS_CONTROL */
827df9f3
AZ		 195 return s->control;
196
a076a3dc
AG		 197 case 0x50: /* DSS_PSA_LCD_REG_1 */
198 case 0x54: /* DSS_PSA_LCD_REG_2 */
199 case 0x58: /* DSS_PSA_VIDEO_REG */
827df9f3
AZ		 200 /* TODO: fake some values when appropriate s->control bits are set */
201 return 0;
202
a076a3dc 203 case 0x5c: /* DSS_STATUS */
827df9f3
AZ		 204 return 1 + (s->control & 1);
205
206 default:
207 break;
208 }
209 OMAP_BAD_REG(addr);
210 return 0;
211}
212
a8170e5e 213static void omap_diss_write(void *opaque, hwaddr addr,
4852e5d8 214 uint64_t value, unsigned size)
827df9f3 215{
a75ed3c4 216 struct omap_dss_s *s = opaque;
827df9f3 217
4852e5d8 218 if (size != 4) {
77a8257e
SW		 219 omap_badwidth_write32(opaque, addr, value);
220 return;
4852e5d8
AK		 221 }
222
8da3ff18 223 switch (addr) {
a076a3dc
AG		 224 case 0x00: /* DSS_REVISIONNUMBER */
225 case 0x14: /* DSS_SYSSTATUS */
226 case 0x50: /* DSS_PSA_LCD_REG_1 */
227 case 0x54: /* DSS_PSA_LCD_REG_2 */
228 case 0x58: /* DSS_PSA_VIDEO_REG */
229 case 0x5c: /* DSS_STATUS */
827df9f3
AZ		 230 OMAP_RO_REG(addr);
231 break;
232
a076a3dc
AG		 233 case 0x10: /* DSS_SYSCONFIG */
234 if (value & 2) /* SOFTRESET */
827df9f3
AZ		 235 omap_dss_reset(s);
236 s->autoidle = value & 1;
237 break;
238
a076a3dc 239 case 0x40: /* DSS_CONTROL */
827df9f3
AZ		 240 s->control = value & 0x3dd;
241 break;
242
243 default:
244 OMAP_BAD_REG(addr);
245 }
246}
247
4852e5d8
AK		 248static const MemoryRegionOps omap_diss_ops = {
249 .read = omap_diss_read,
250 .write = omap_diss_write,
251 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 252};
253
a8170e5e 254static uint64_t omap_disc_read(void *opaque, hwaddr addr,
4852e5d8 255 unsigned size)
827df9f3 256{
a75ed3c4 257 struct omap_dss_s *s = opaque;
827df9f3 258
4852e5d8
AK		 259 if (size != 4) {
260 return omap_badwidth_read32(opaque, addr);
261 }
262
8da3ff18 263 switch (addr) {
a076a3dc 264 case 0x000: /* DISPC_REVISION */
827df9f3
AZ		 265 return 0x20;
266
a076a3dc 267 case 0x010: /* DISPC_SYSCONFIG */
827df9f3
AZ		 268 return s->dispc.idlemode;
269
a076a3dc
AG		 270 case 0x014: /* DISPC_SYSSTATUS */
271 return 1; /* RESETDONE */
827df9f3 272
a076a3dc 273 case 0x018: /* DISPC_IRQSTATUS */
827df9f3
AZ		 274 return s->dispc.irqst;
275
a076a3dc 276 case 0x01c: /* DISPC_IRQENABLE */
827df9f3
AZ		 277 return s->dispc.irqen;
278
a076a3dc 279 case 0x040: /* DISPC_CONTROL */
827df9f3
AZ		 280 return s->dispc.control;
281
a076a3dc 282 case 0x044: /* DISPC_CONFIG */
827df9f3
AZ		 283 return s->dispc.config;
284
a076a3dc 285 case 0x048: /* DISPC_CAPABLE */
827df9f3
AZ		 286 return s->dispc.capable;
287
a076a3dc 288 case 0x04c: /* DISPC_DEFAULT_COLOR0 */
827df9f3 289 return s->dispc.bg[0];
a076a3dc 290 case 0x050: /* DISPC_DEFAULT_COLOR1 */
827df9f3 291 return s->dispc.bg[1];
a076a3dc 292 case 0x054: /* DISPC_TRANS_COLOR0 */
827df9f3 293 return s->dispc.trans[0];
a076a3dc 294 case 0x058: /* DISPC_TRANS_COLOR1 */
827df9f3
AZ		 295 return s->dispc.trans[1];
296
a076a3dc 297 case 0x05c: /* DISPC_LINE_STATUS */
827df9f3 298 return 0x7ff;
a076a3dc 299 case 0x060: /* DISPC_LINE_NUMBER */
827df9f3
AZ		 300 return s->dispc.line;
301
a076a3dc 302 case 0x064: /* DISPC_TIMING_H */
827df9f3 303 return s->dispc.timing[0];
a076a3dc 304 case 0x068: /* DISPC_TIMING_V */
827df9f3 305 return s->dispc.timing[1];
a076a3dc 306 case 0x06c: /* DISPC_POL_FREQ */
827df9f3 307 return s->dispc.timing[2];
a076a3dc 308 case 0x070: /* DISPC_DIVISOR */
827df9f3
AZ		 309 return s->dispc.timing[3];
310
a076a3dc 311 case 0x078: /* DISPC_SIZE_DIG */
827df9f3 312 return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);
a076a3dc 313 case 0x07c: /* DISPC_SIZE_LCD */
827df9f3
AZ		 314 return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);
315
a076a3dc 316 case 0x080: /* DISPC_GFX_BA0 */
827df9f3 317 return s->dispc.l[0].addr[0];
a076a3dc 318 case 0x084: /* DISPC_GFX_BA1 */
827df9f3 319 return s->dispc.l[0].addr[1];
a076a3dc 320 case 0x088: /* DISPC_GFX_POSITION */
827df9f3 321 return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;
a076a3dc 322 case 0x08c: /* DISPC_GFX_SIZE */
827df9f3 323 return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);
a076a3dc 324 case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
827df9f3 325 return s->dispc.l[0].attr;
a076a3dc 326 case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
827df9f3 327 return s->dispc.l[0].tresh;
a076a3dc 328 case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
827df9f3 329 return 256;
a076a3dc 330 case 0x0ac: /* DISPC_GFX_ROW_INC */
827df9f3 331 return s->dispc.l[0].rowinc;
a076a3dc 332 case 0x0b0: /* DISPC_GFX_PIXEL_INC */
827df9f3 333 return s->dispc.l[0].colinc;
a076a3dc 334 case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
827df9f3 335 return s->dispc.l[0].wininc;
a076a3dc 336 case 0x0b8: /* DISPC_GFX_TABLE_BA */
827df9f3
AZ		 337 return s->dispc.l[0].addr[2];
338
a076a3dc
AG		 339 case 0x0bc: /* DISPC_VID1_BA0 */
340 case 0x0c0: /* DISPC_VID1_BA1 */
341 case 0x0c4: /* DISPC_VID1_POSITION */
342 case 0x0c8: /* DISPC_VID1_SIZE */
343 case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
344 case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
345 case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
346 case 0x0d8: /* DISPC_VID1_ROW_INC */
347 case 0x0dc: /* DISPC_VID1_PIXEL_INC */
348 case 0x0e0: /* DISPC_VID1_FIR */
349 case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
350 case 0x0e8: /* DISPC_VID1_ACCU0 */
351 case 0x0ec: /* DISPC_VID1_ACCU1 */
352 case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
353 case 0x14c: /* DISPC_VID2_BA0 */
354 case 0x150: /* DISPC_VID2_BA1 */
355 case 0x154: /* DISPC_VID2_POSITION */
356 case 0x158: /* DISPC_VID2_SIZE */
357 case 0x15c: /* DISPC_VID2_ATTRIBUTES */
358 case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
359 case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
360 case 0x168: /* DISPC_VID2_ROW_INC */
361 case 0x16c: /* DISPC_VID2_PIXEL_INC */
362 case 0x170: /* DISPC_VID2_FIR */
363 case 0x174: /* DISPC_VID2_PICTURE_SIZE */
364 case 0x178: /* DISPC_VID2_ACCU0 */
365 case 0x17c: /* DISPC_VID2_ACCU1 */
366 case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
367 case 0x1d4: /* DISPC_DATA_CYCLE1 */
368 case 0x1d8: /* DISPC_DATA_CYCLE2 */
369 case 0x1dc: /* DISPC_DATA_CYCLE3 */
827df9f3
AZ		 370 return 0;
371
372 default:
373 break;
374 }
375 OMAP_BAD_REG(addr);
376 return 0;
377}
378
a8170e5e 379static void omap_disc_write(void *opaque, hwaddr addr,
4852e5d8 380 uint64_t value, unsigned size)
827df9f3 381{
a75ed3c4 382 struct omap_dss_s *s = opaque;
827df9f3 383
4852e5d8 384 if (size != 4) {
77a8257e
SW		 385 omap_badwidth_write32(opaque, addr, value);
386 return;
4852e5d8
AK		 387 }
388
8da3ff18 389 switch (addr) {
a076a3dc
AG		 390 case 0x010: /* DISPC_SYSCONFIG */
391 if (value & 2) /* SOFTRESET */
827df9f3
AZ		 392 omap_dss_reset(s);
393 s->dispc.idlemode = value & 0x301b;
394 break;
395
a076a3dc 396 case 0x018: /* DISPC_IRQSTATUS */
827df9f3
AZ		 397 s->dispc.irqst &= ~value;
398 omap_dispc_interrupt_update(s);
399 break;
400
a076a3dc 401 case 0x01c: /* DISPC_IRQENABLE */
827df9f3
AZ		 402 s->dispc.irqen = value & 0xffff;
403 omap_dispc_interrupt_update(s);
404 break;
405
a076a3dc 406 case 0x040: /* DISPC_CONTROL */
827df9f3
AZ		 407 s->dispc.control = value & 0x07ff9fff;
408 s->dig.enable = (value >> 1) & 1;
409 s->lcd.enable = (value >> 0) & 1;
a076a3dc 410 if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
95117be5
PM		 411 if (!((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) {
412 fprintf(stderr, "%s: Overlay Optimization when no overlay "
413 "region effectively exists leads to "
414 "unpredictable behaviour!\n", __func__);
415 }
a076a3dc 416 if (value & (1 << 6)) { /* GODIGITAL */
827df9f3
AZ		 417 /* XXX: Shadowed fields are:
418 * s->dispc.config
419 * s->dispc.capable
420 * s->dispc.bg[0]
421 * s->dispc.bg[1]
422 * s->dispc.trans[0]
423 * s->dispc.trans[1]
424 * s->dispc.line
425 * s->dispc.timing[0]
426 * s->dispc.timing[1]
427 * s->dispc.timing[2]
428 * s->dispc.timing[3]
429 * s->lcd.nx
430 * s->lcd.ny
431 * s->dig.nx
432 * s->dig.ny
433 * s->dispc.l[0].addr[0]
434 * s->dispc.l[0].addr[1]
435 * s->dispc.l[0].addr[2]
436 * s->dispc.l[0].posx
437 * s->dispc.l[0].posy
438 * s->dispc.l[0].nx
439 * s->dispc.l[0].ny
440 * s->dispc.l[0].tresh
441 * s->dispc.l[0].rowinc
442 * s->dispc.l[0].colinc
443 * s->dispc.l[0].wininc
444 * All they need to be loaded here from their shadow registers.
445 */
446 }
a076a3dc 447 if (value & (1 << 5)) { /* GOLCD */
827df9f3
AZ		 448 /* XXX: Likewise for LCD here. */
449 }
450 s->dispc.invalidate = 1;
451 break;
452
a076a3dc 453 case 0x044: /* DISPC_CONFIG */
827df9f3
AZ		 454 s->dispc.config = value & 0x3fff;
455 /* XXX:
456 * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
457 * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
458 */
459 s->dispc.invalidate = 1;
460 break;
461
a076a3dc 462 case 0x048: /* DISPC_CAPABLE */
827df9f3
AZ		 463 s->dispc.capable = value & 0x3ff;
464 break;
465
a076a3dc 466 case 0x04c: /* DISPC_DEFAULT_COLOR0 */
827df9f3
AZ		 467 s->dispc.bg[0] = value & 0xffffff;
468 s->dispc.invalidate = 1;
469 break;
a076a3dc 470 case 0x050: /* DISPC_DEFAULT_COLOR1 */
827df9f3
AZ		 471 s->dispc.bg[1] = value & 0xffffff;
472 s->dispc.invalidate = 1;
473 break;
a076a3dc 474 case 0x054: /* DISPC_TRANS_COLOR0 */
827df9f3
AZ		 475 s->dispc.trans[0] = value & 0xffffff;
476 s->dispc.invalidate = 1;
477 break;
a076a3dc 478 case 0x058: /* DISPC_TRANS_COLOR1 */
827df9f3
AZ		 479 s->dispc.trans[1] = value & 0xffffff;
480 s->dispc.invalidate = 1;
481 break;
482
a076a3dc 483 case 0x060: /* DISPC_LINE_NUMBER */
827df9f3
AZ		 484 s->dispc.line = value & 0x7ff;
485 break;
486
a076a3dc 487 case 0x064: /* DISPC_TIMING_H */
827df9f3
AZ		 488 s->dispc.timing[0] = value & 0x0ff0ff3f;
489 break;
a076a3dc 490 case 0x068: /* DISPC_TIMING_V */
827df9f3
AZ		 491 s->dispc.timing[1] = value & 0x0ff0ff3f;
492 break;
a076a3dc 493 case 0x06c: /* DISPC_POL_FREQ */
827df9f3
AZ		 494 s->dispc.timing[2] = value & 0x0003ffff;
495 break;
a076a3dc 496 case 0x070: /* DISPC_DIVISOR */
827df9f3
AZ		 497 s->dispc.timing[3] = value & 0x00ff00ff;
498 break;
499
a076a3dc
AG		 500 case 0x078: /* DISPC_SIZE_DIG */
501 s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
502 s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
827df9f3
AZ		 503 s->dispc.invalidate = 1;
504 break;
a076a3dc
AG		 505 case 0x07c: /* DISPC_SIZE_LCD */
506 s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
507 s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
827df9f3
AZ		 508 s->dispc.invalidate = 1;
509 break;
a076a3dc 510 case 0x080: /* DISPC_GFX_BA0 */
a8170e5e 511 s->dispc.l[0].addr[0] = (hwaddr) value;
827df9f3
AZ		 512 s->dispc.invalidate = 1;
513 break;
a076a3dc 514 case 0x084: /* DISPC_GFX_BA1 */
a8170e5e 515 s->dispc.l[0].addr[1] = (hwaddr) value;
827df9f3
AZ		 516 s->dispc.invalidate = 1;
517 break;
a076a3dc
AG		 518 case 0x088: /* DISPC_GFX_POSITION */
519 s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
520 s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
827df9f3
AZ		 521 s->dispc.invalidate = 1;
522 break;
a076a3dc
AG		 523 case 0x08c: /* DISPC_GFX_SIZE */
524 s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
525 s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
827df9f3
AZ		 526 s->dispc.invalidate = 1;
527 break;
a076a3dc 528 case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
827df9f3
AZ		 529 s->dispc.l[0].attr = value & 0x7ff;
530 if (value & (3 << 9))
531 fprintf(stderr, "%s: Big-endian pixel format not supported\n",
a89f364a 532 __func__);
827df9f3
AZ		 533 s->dispc.l[0].enable = value & 1;
534 s->dispc.l[0].bpp = (value >> 1) & 0xf;
535 s->dispc.invalidate = 1;
536 break;
a076a3dc 537 case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
827df9f3
AZ		 538 s->dispc.l[0].tresh = value & 0x01ff01ff;
539 break;
a076a3dc 540 case 0x0ac: /* DISPC_GFX_ROW_INC */
827df9f3
AZ		 541 s->dispc.l[0].rowinc = value;
542 s->dispc.invalidate = 1;
543 break;
a076a3dc 544 case 0x0b0: /* DISPC_GFX_PIXEL_INC */
827df9f3
AZ		 545 s->dispc.l[0].colinc = value;
546 s->dispc.invalidate = 1;
547 break;
a076a3dc 548 case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
827df9f3
AZ		 549 s->dispc.l[0].wininc = value;
550 break;
a076a3dc 551 case 0x0b8: /* DISPC_GFX_TABLE_BA */
a8170e5e 552 s->dispc.l[0].addr[2] = (hwaddr) value;
827df9f3
AZ		 553 s->dispc.invalidate = 1;
554 break;
555
a076a3dc
AG		 556 case 0x0bc: /* DISPC_VID1_BA0 */
557 case 0x0c0: /* DISPC_VID1_BA1 */
558 case 0x0c4: /* DISPC_VID1_POSITION */
559 case 0x0c8: /* DISPC_VID1_SIZE */
560 case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
561 case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
562 case 0x0d8: /* DISPC_VID1_ROW_INC */
563 case 0x0dc: /* DISPC_VID1_PIXEL_INC */
564 case 0x0e0: /* DISPC_VID1_FIR */
565 case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
566 case 0x0e8: /* DISPC_VID1_ACCU0 */
567 case 0x0ec: /* DISPC_VID1_ACCU1 */
568 case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
569 case 0x14c: /* DISPC_VID2_BA0 */
570 case 0x150: /* DISPC_VID2_BA1 */
571 case 0x154: /* DISPC_VID2_POSITION */
572 case 0x158: /* DISPC_VID2_SIZE */
573 case 0x15c: /* DISPC_VID2_ATTRIBUTES */
574 case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
575 case 0x168: /* DISPC_VID2_ROW_INC */
576 case 0x16c: /* DISPC_VID2_PIXEL_INC */
577 case 0x170: /* DISPC_VID2_FIR */
578 case 0x174: /* DISPC_VID2_PICTURE_SIZE */
579 case 0x178: /* DISPC_VID2_ACCU0 */
580 case 0x17c: /* DISPC_VID2_ACCU1 */
581 case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
582 case 0x1d4: /* DISPC_DATA_CYCLE1 */
583 case 0x1d8: /* DISPC_DATA_CYCLE2 */
584 case 0x1dc: /* DISPC_DATA_CYCLE3 */
827df9f3
AZ		 585 break;
586
587 default:
588 OMAP_BAD_REG(addr);
589 }
590}
591
4852e5d8
AK		 592static const MemoryRegionOps omap_disc_ops = {
593 .read = omap_disc_read,
594 .write = omap_disc_write,
595 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 596};
597
827df9f3
AZ		 598static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
599{
600 if (!s->rfbi.busy)
601 return;
602
603 /* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
604
605 s->rfbi.busy = 0;
606}
607
608static void omap_rfbi_transfer_start(struct omap_dss_s *s)
609{
610 void *data;
a8170e5e
AK		 611 hwaddr len;
612 hwaddr data_addr;
827df9f3 613 int pitch;
5c130f65 614 static void *bounce_buffer;
a8170e5e 615 static hwaddr bounce_len;
827df9f3
AZ		 616
617 if (!s->rfbi.enable || s->rfbi.busy)
618 return;
619
a076a3dc 620 if (s->rfbi.control & (1 << 1)) { /* BYPASS */
827df9f3
AZ		 621 /* TODO: in non-Bypass mode we probably need to just assert the
622 * DRQ and wait for DMA to write the pixels. */
00a946a3 623 qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
827df9f3
AZ		 624 return;
625 }
626
a076a3dc 627 if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
827df9f3
AZ		 628 return;
629 /* TODO: check that LCD output is enabled in DISPC. */
630
631 s->rfbi.busy = 1;
632
5c130f65
PB		 633 len = s->rfbi.pixels * 2;
634
635 data_addr = s->dispc.l[0].addr[0];
85eb7c18 636 data = cpu_physical_memory_map(data_addr, &len, false);
5c130f65
PB		 637 if (data && len != s->rfbi.pixels * 2) {
638 cpu_physical_memory_unmap(data, len, 0, 0);
639 data = NULL;
640 len = s->rfbi.pixels * 2;
641 }
642 if (!data) {
643 if (len > bounce_len) {
7267c094 644 bounce_buffer = g_realloc(bounce_buffer, len);
5c130f65
PB		 645 }
646 data = bounce_buffer;
647 cpu_physical_memory_read(data_addr, data, len);
648 }
827df9f3
AZ		 649
650 /* TODO bpp */
827df9f3
AZ		 651 s->rfbi.pixels = 0;
652
653 /* TODO: negative values */
654 pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2;
655
656 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
657 s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch);
658 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
659 s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch);
660
5c130f65
PB		 661 if (data != bounce_buffer) {
662 cpu_physical_memory_unmap(data, len, 0, len);
663 }
664
827df9f3
AZ		 665 omap_rfbi_transfer_stop(s);
666
667 /* TODO */
a076a3dc 668 s->dispc.irqst |= 1; /* FRAMEDONE */
827df9f3
AZ		 669 omap_dispc_interrupt_update(s);
670}
671
a75ed3c4 672static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
827df9f3 673{
a75ed3c4 674 struct omap_dss_s *s = opaque;
827df9f3 675
4852e5d8
AK		 676 if (size != 4) {
677 return omap_badwidth_read32(opaque, addr);
678 }
679
8da3ff18 680 switch (addr) {
a076a3dc 681 case 0x00: /* RFBI_REVISION */
827df9f3
AZ		 682 return 0x10;
683
a076a3dc 684 case 0x10: /* RFBI_SYSCONFIG */
827df9f3
AZ		 685 return s->rfbi.idlemode;
686
a076a3dc
AG		 687 case 0x14: /* RFBI_SYSSTATUS */
688 return 1 | (s->rfbi.busy << 8); /* RESETDONE */
827df9f3 689
a076a3dc 690 case 0x40: /* RFBI_CONTROL */
827df9f3
AZ		 691 return s->rfbi.control;
692
a076a3dc 693 case 0x44: /* RFBI_PIXELCNT */
827df9f3
AZ		 694 return s->rfbi.pixels;
695
a076a3dc 696 case 0x48: /* RFBI_LINE_NUMBER */
827df9f3
AZ		 697 return s->rfbi.skiplines;
698
a076a3dc
AG		 699 case 0x58: /* RFBI_READ */
700 case 0x5c: /* RFBI_STATUS */
827df9f3
AZ		 701 return s->rfbi.rxbuf;
702
a076a3dc 703 case 0x60: /* RFBI_CONFIG0 */
827df9f3 704 return s->rfbi.config[0];
a076a3dc 705 case 0x64: /* RFBI_ONOFF_TIME0 */
827df9f3 706 return s->rfbi.time[0];
a076a3dc 707 case 0x68: /* RFBI_CYCLE_TIME0 */
827df9f3 708 return s->rfbi.time[1];
a076a3dc 709 case 0x6c: /* RFBI_DATA_CYCLE1_0 */
827df9f3 710 return s->rfbi.data[0];
a076a3dc 711 case 0x70: /* RFBI_DATA_CYCLE2_0 */
827df9f3 712 return s->rfbi.data[1];
a076a3dc 713 case 0x74: /* RFBI_DATA_CYCLE3_0 */
827df9f3
AZ		 714 return s->rfbi.data[2];
715
a076a3dc 716 case 0x78: /* RFBI_CONFIG1 */
827df9f3 717 return s->rfbi.config[1];
a076a3dc 718 case 0x7c: /* RFBI_ONOFF_TIME1 */
827df9f3 719 return s->rfbi.time[2];
a076a3dc 720 case 0x80: /* RFBI_CYCLE_TIME1 */
827df9f3 721 return s->rfbi.time[3];
a076a3dc 722 case 0x84: /* RFBI_DATA_CYCLE1_1 */
827df9f3 723 return s->rfbi.data[3];
a076a3dc 724 case 0x88: /* RFBI_DATA_CYCLE2_1 */
827df9f3 725 return s->rfbi.data[4];
a076a3dc 726 case 0x8c: /* RFBI_DATA_CYCLE3_1 */
827df9f3
AZ		 727 return s->rfbi.data[5];
728
a076a3dc 729 case 0x90: /* RFBI_VSYNC_WIDTH */
827df9f3 730 return s->rfbi.vsync;
a076a3dc 731 case 0x94: /* RFBI_HSYNC_WIDTH */
827df9f3
AZ		 732 return s->rfbi.hsync;
733 }
734 OMAP_BAD_REG(addr);
735 return 0;
736}
737
a8170e5e 738static void omap_rfbi_write(void *opaque, hwaddr addr,
4852e5d8 739 uint64_t value, unsigned size)
827df9f3 740{
a75ed3c4 741 struct omap_dss_s *s = opaque;
827df9f3 742
4852e5d8 743 if (size != 4) {
77a8257e
SW		 744 omap_badwidth_write32(opaque, addr, value);
745 return;
4852e5d8
AK		 746 }
747
8da3ff18 748 switch (addr) {
a076a3dc
AG		 749 case 0x10: /* RFBI_SYSCONFIG */
750 if (value & 2) /* SOFTRESET */
827df9f3
AZ		 751 omap_rfbi_reset(s);
752 s->rfbi.idlemode = value & 0x19;
753 break;
754
a076a3dc 755 case 0x40: /* RFBI_CONTROL */
827df9f3
AZ		 756 s->rfbi.control = value & 0xf;
757 s->rfbi.enable = value & 1;
a076a3dc 758 if (value & (1 << 4) && /* ITE */
827df9f3
AZ		 759 !(s->rfbi.config[0] & s->rfbi.config[1] & 0xc))
760 omap_rfbi_transfer_start(s);
761 break;
762
a076a3dc 763 case 0x44: /* RFBI_PIXELCNT */
827df9f3
AZ		 764 s->rfbi.pixels = value;
765 break;
766
a076a3dc 767 case 0x48: /* RFBI_LINE_NUMBER */
827df9f3
AZ		 768 s->rfbi.skiplines = value & 0x7ff;
769 break;
770
a076a3dc 771 case 0x4c: /* RFBI_CMD */
827df9f3
AZ		 772 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
773 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
774 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
775 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
776 break;
a076a3dc 777 case 0x50: /* RFBI_PARAM */
827df9f3
AZ		 778 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
779 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
780 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
781 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
782 break;
a076a3dc 783 case 0x54: /* RFBI_DATA */
827df9f3
AZ		 784 /* TODO: take into account the format set up in s->rfbi.config[?] and
785 * s->rfbi.data[?], but special-case the most usual scenario so that
786 * speed doesn't suffer. */
787 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) {
788 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
789 s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16);
790 }
791 if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) {
792 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
793 s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16);
794 }
795 if (!-- s->rfbi.pixels)
796 omap_rfbi_transfer_stop(s);
797 break;
a076a3dc 798 case 0x58: /* RFBI_READ */
827df9f3
AZ		 799 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
800 s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
801 else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
3c8359d1 802 s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 1);
827df9f3
AZ		 803 if (!-- s->rfbi.pixels)
804 omap_rfbi_transfer_stop(s);
805 break;
806
a076a3dc 807 case 0x5c: /* RFBI_STATUS */
827df9f3
AZ		 808 if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
809 s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
810 else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
3c8359d1 811 s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 0);
827df9f3
AZ		 812 if (!-- s->rfbi.pixels)
813 omap_rfbi_transfer_stop(s);
814 break;
815
a076a3dc 816 case 0x60: /* RFBI_CONFIG0 */
827df9f3
AZ		 817 s->rfbi.config[0] = value & 0x003f1fff;
818 break;
819
a076a3dc 820 case 0x64: /* RFBI_ONOFF_TIME0 */
827df9f3
AZ		 821 s->rfbi.time[0] = value & 0x3fffffff;
822 break;
a076a3dc 823 case 0x68: /* RFBI_CYCLE_TIME0 */
827df9f3
AZ		 824 s->rfbi.time[1] = value & 0x0fffffff;
825 break;
a076a3dc 826 case 0x6c: /* RFBI_DATA_CYCLE1_0 */
827df9f3
AZ		 827 s->rfbi.data[0] = value & 0x0f1f0f1f;
828 break;
a076a3dc 829 case 0x70: /* RFBI_DATA_CYCLE2_0 */
827df9f3
AZ		 830 s->rfbi.data[1] = value & 0x0f1f0f1f;
831 break;
a076a3dc 832 case 0x74: /* RFBI_DATA_CYCLE3_0 */
827df9f3
AZ		 833 s->rfbi.data[2] = value & 0x0f1f0f1f;
834 break;
a076a3dc 835 case 0x78: /* RFBI_CONFIG1 */
827df9f3
AZ		 836 s->rfbi.config[1] = value & 0x003f1fff;
837 break;
838
a076a3dc 839 case 0x7c: /* RFBI_ONOFF_TIME1 */
827df9f3
AZ		 840 s->rfbi.time[2] = value & 0x3fffffff;
841 break;
a076a3dc 842 case 0x80: /* RFBI_CYCLE_TIME1 */
827df9f3
AZ		 843 s->rfbi.time[3] = value & 0x0fffffff;
844 break;
a076a3dc 845 case 0x84: /* RFBI_DATA_CYCLE1_1 */
827df9f3
AZ		 846 s->rfbi.data[3] = value & 0x0f1f0f1f;
847 break;
a076a3dc 848 case 0x88: /* RFBI_DATA_CYCLE2_1 */
827df9f3
AZ		 849 s->rfbi.data[4] = value & 0x0f1f0f1f;
850 break;
a076a3dc 851 case 0x8c: /* RFBI_DATA_CYCLE3_1 */
827df9f3
AZ		 852 s->rfbi.data[5] = value & 0x0f1f0f1f;
853 break;
854
a076a3dc 855 case 0x90: /* RFBI_VSYNC_WIDTH */
827df9f3
AZ		 856 s->rfbi.vsync = value & 0xffff;
857 break;
a076a3dc 858 case 0x94: /* RFBI_HSYNC_WIDTH */
827df9f3
AZ		 859 s->rfbi.hsync = value & 0xffff;
860 break;
861
862 default:
863 OMAP_BAD_REG(addr);
864 }
865}
866
4852e5d8
AK		 867static const MemoryRegionOps omap_rfbi_ops = {
868 .read = omap_rfbi_read,
869 .write = omap_rfbi_write,
870 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 871};
872
a8170e5e 873static uint64_t omap_venc_read(void *opaque, hwaddr addr,
4852e5d8 874 unsigned size)
827df9f3 875{
4852e5d8
AK		 876 if (size != 4) {
877 return omap_badwidth_read32(opaque, addr);
878 }
879
8da3ff18 880 switch (addr) {
a076a3dc
AG		 881 case 0x00: /* REV_ID */
882 case 0x04: /* STATUS */
883 case 0x08: /* F_CONTROL */
884 case 0x10: /* VIDOUT_CTRL */
885 case 0x14: /* SYNC_CTRL */
886 case 0x1c: /* LLEN */
887 case 0x20: /* FLENS */
888 case 0x24: /* HFLTR_CTRL */
889 case 0x28: /* CC_CARR_WSS_CARR */
890 case 0x2c: /* C_PHASE */
891 case 0x30: /* GAIN_U */
892 case 0x34: /* GAIN_V */
893 case 0x38: /* GAIN_Y */
894 case 0x3c: /* BLACK_LEVEL */
895 case 0x40: /* BLANK_LEVEL */
896 case 0x44: /* X_COLOR */
897 case 0x48: /* M_CONTROL */
898 case 0x4c: /* BSTAMP_WSS_DATA */
899 case 0x50: /* S_CARR */
900 case 0x54: /* LINE21 */
901 case 0x58: /* LN_SEL */
902 case 0x5c: /* L21__WC_CTL */
903 case 0x60: /* HTRIGGER_VTRIGGER */
904 case 0x64: /* SAVID__EAVID */
905 case 0x68: /* FLEN__FAL */
906 case 0x6c: /* LAL__PHASE_RESET */
907 case 0x70: /* HS_INT_START_STOP_X */
908 case 0x74: /* HS_EXT_START_STOP_X */
909 case 0x78: /* VS_INT_START_X */
910 case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
911 case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
912 case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
913 case 0x88: /* VS_EXT_STOP_Y */
914 case 0x90: /* AVID_START_STOP_X */
915 case 0x94: /* AVID_START_STOP_Y */
916 case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
917 case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
918 case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
919 case 0xb0: /* TVDETGP_INT_START_STOP_X */
920 case 0xb4: /* TVDETGP_INT_START_STOP_Y */
921 case 0xb8: /* GEN_CTRL */
922 case 0xc4: /* DAC_TST__DAC_A */
923 case 0xc8: /* DAC_B__DAC_C */
827df9f3
AZ		 924 return 0;
925
926 default:
927 break;
928 }
929 OMAP_BAD_REG(addr);
930 return 0;
931}
932
a8170e5e 933static void omap_venc_write(void *opaque, hwaddr addr,
4852e5d8 934 uint64_t value, unsigned size)
827df9f3 935{
4852e5d8 936 if (size != 4) {
77a8257e
SW		 937 omap_badwidth_write32(opaque, addr, size);
938 return;
4852e5d8
AK		 939 }
940
8da3ff18 941 switch (addr) {
a076a3dc
AG		 942 case 0x08: /* F_CONTROL */
943 case 0x10: /* VIDOUT_CTRL */
944 case 0x14: /* SYNC_CTRL */
945 case 0x1c: /* LLEN */
946 case 0x20: /* FLENS */
947 case 0x24: /* HFLTR_CTRL */
948 case 0x28: /* CC_CARR_WSS_CARR */
949 case 0x2c: /* C_PHASE */
950 case 0x30: /* GAIN_U */
951 case 0x34: /* GAIN_V */
952 case 0x38: /* GAIN_Y */
953 case 0x3c: /* BLACK_LEVEL */
954 case 0x40: /* BLANK_LEVEL */
955 case 0x44: /* X_COLOR */
956 case 0x48: /* M_CONTROL */
957 case 0x4c: /* BSTAMP_WSS_DATA */
958 case 0x50: /* S_CARR */
959 case 0x54: /* LINE21 */
960 case 0x58: /* LN_SEL */
961 case 0x5c: /* L21__WC_CTL */
962 case 0x60: /* HTRIGGER_VTRIGGER */
963 case 0x64: /* SAVID__EAVID */
964 case 0x68: /* FLEN__FAL */
965 case 0x6c: /* LAL__PHASE_RESET */
966 case 0x70: /* HS_INT_START_STOP_X */
967 case 0x74: /* HS_EXT_START_STOP_X */
968 case 0x78: /* VS_INT_START_X */
969 case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
970 case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
971 case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
972 case 0x88: /* VS_EXT_STOP_Y */
973 case 0x90: /* AVID_START_STOP_X */
974 case 0x94: /* AVID_START_STOP_Y */
975 case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
976 case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
977 case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
978 case 0xb0: /* TVDETGP_INT_START_STOP_X */
979 case 0xb4: /* TVDETGP_INT_START_STOP_Y */
980 case 0xb8: /* GEN_CTRL */
981 case 0xc4: /* DAC_TST__DAC_A */
982 case 0xc8: /* DAC_B__DAC_C */
827df9f3
AZ		 983 break;
984
985 default:
986 OMAP_BAD_REG(addr);
987 }
988}
989
4852e5d8
AK		 990static const MemoryRegionOps omap_venc_ops = {
991 .read = omap_venc_read,
992 .write = omap_venc_write,
993 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 994};
995
a8170e5e 996static uint64_t omap_im3_read(void *opaque, hwaddr addr,
4852e5d8 997 unsigned size)
827df9f3 998{
4852e5d8
AK		 999 if (size != 4) {
1000 return omap_badwidth_read32(opaque, addr);
1001 }
1002
8da3ff18 1003 switch (addr) {
a076a3dc
AG		 1004 case 0x0a8: /* SBIMERRLOGA */
1005 case 0x0b0: /* SBIMERRLOG */
1006 case 0x190: /* SBIMSTATE */
1007 case 0x198: /* SBTMSTATE_L */
1008 case 0x19c: /* SBTMSTATE_H */
1009 case 0x1a8: /* SBIMCONFIG_L */
1010 case 0x1ac: /* SBIMCONFIG_H */
1011 case 0x1f8: /* SBID_L */
1012 case 0x1fc: /* SBID_H */
827df9f3
AZ		 1013 return 0;
1014
1015 default:
1016 break;
1017 }
1018 OMAP_BAD_REG(addr);
1019 return 0;
1020}
1021
a8170e5e 1022static void omap_im3_write(void *opaque, hwaddr addr,
4852e5d8 1023 uint64_t value, unsigned size)
827df9f3 1024{
4852e5d8 1025 if (size != 4) {
77a8257e
SW		 1026 omap_badwidth_write32(opaque, addr, value);
1027 return;
4852e5d8
AK		 1028 }
1029
8da3ff18 1030 switch (addr) {
a076a3dc
AG		 1031 case 0x0b0: /* SBIMERRLOG */
1032 case 0x190: /* SBIMSTATE */
1033 case 0x198: /* SBTMSTATE_L */
1034 case 0x19c: /* SBTMSTATE_H */
1035 case 0x1a8: /* SBIMCONFIG_L */
1036 case 0x1ac: /* SBIMCONFIG_H */
827df9f3
AZ		 1037 break;
1038
1039 default:
1040 OMAP_BAD_REG(addr);
1041 }
1042}
1043
4852e5d8
AK		 1044static const MemoryRegionOps omap_im3_ops = {
1045 .read = omap_im3_read,
1046 .write = omap_im3_write,
1047 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 1048};
1049
1050struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
4852e5d8 1051 MemoryRegion *sysmem,
a8170e5e 1052 hwaddr l3_base,
827df9f3
AZ		 1053 qemu_irq irq, qemu_irq drq,
1054 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
1055 omap_clk ick1, omap_clk ick2)
1056{
b45c03f5 1057 struct omap_dss_s *s = g_new0(struct omap_dss_s, 1);
827df9f3
AZ		 1058
1059 s->irq = irq;
1060 s->drq = drq;
827df9f3
AZ		 1061 omap_dss_reset(s);
1062
2c9b15ca 1063 memory_region_init_io(&s->iomem_diss1, NULL, &omap_diss_ops, s, "omap.diss1",
4852e5d8 1064 omap_l4_region_size(ta, 0));
2c9b15ca 1065 memory_region_init_io(&s->iomem_disc1, NULL, &omap_disc_ops, s, "omap.disc1",
4852e5d8 1066 omap_l4_region_size(ta, 1));
2c9b15ca 1067 memory_region_init_io(&s->iomem_rfbi1, NULL, &omap_rfbi_ops, s, "omap.rfbi1",
4852e5d8 1068 omap_l4_region_size(ta, 2));
2c9b15ca 1069 memory_region_init_io(&s->iomem_venc1, NULL, &omap_venc_ops, s, "omap.venc1",
4852e5d8 1070 omap_l4_region_size(ta, 3));
2c9b15ca 1071 memory_region_init_io(&s->iomem_im3, NULL, &omap_im3_ops, s,
4852e5d8
AK		 1072 "omap.im3", 0x1000);
1073
f44336c5
AK		 1074 omap_l4_attach(ta, 0, &s->iomem_diss1);
1075 omap_l4_attach(ta, 1, &s->iomem_disc1);
1076 omap_l4_attach(ta, 2, &s->iomem_rfbi1);
1077 omap_l4_attach(ta, 3, &s->iomem_venc1);
4852e5d8 1078 memory_region_add_subregion(sysmem, l3_base, &s->iomem_im3);
827df9f3
AZ		 1079
1080#if 0
3023f332
AL		 1081 s->state = graphic_console_init(omap_update_display,
1082 omap_invalidate_display, omap_screen_dump, s);
827df9f3
AZ		 1083#endif
1084
1085 return s;
1086}
1087
1088void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip)
1089{
1090 if (cs < 0 || cs > 1)
a89f364a 1091 hw_error("%s: wrong CS %i\n", __func__, cs);
827df9f3
AZ		 1092 s->rfbi.chip[cs] = chip;
1093}
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