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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <kraxel@redhat.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
a639ab04 AL |
21 | #include <zlib.h> |
22 | ||
a19cbfb3 | 23 | #include "qemu-common.h" |
1de7afc9 PB |
24 | #include "qemu/timer.h" |
25 | #include "qemu/queue.h" | |
83c9089e | 26 | #include "monitor/monitor.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
c480bb7d | 28 | #include "trace.h" |
a19cbfb3 | 29 | |
47b43a1f | 30 | #include "qxl.h" |
a19cbfb3 | 31 | |
0b81c478 AL |
32 | /* |
33 | * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as | |
34 | * such can be changed by the guest, so to avoid a guest trigerrable | |
0a530548 | 35 | * abort we just qxl_set_guest_bug and set the return to NULL. Still |
0b81c478 AL |
36 | * it may happen as a result of emulator bug as well. |
37 | */ | |
a19cbfb3 | 38 | #undef SPICE_RING_PROD_ITEM |
0b81c478 | 39 | #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ |
a19cbfb3 | 40 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ |
bc5f92e5 | 41 | if (prod >= ARRAY_SIZE((r)->items)) { \ |
0a530548 | 42 | qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ |
bc5f92e5 | 43 | "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ |
0b81c478 AL |
44 | ret = NULL; \ |
45 | } else { \ | |
bc5f92e5 | 46 | ret = &(r)->items[prod].el; \ |
a19cbfb3 | 47 | } \ |
a19cbfb3 GH |
48 | } |
49 | ||
50 | #undef SPICE_RING_CONS_ITEM | |
0b81c478 | 51 | #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ |
a19cbfb3 | 52 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ |
bc5f92e5 | 53 | if (cons >= ARRAY_SIZE((r)->items)) { \ |
0a530548 | 54 | qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ |
bc5f92e5 | 55 | "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ |
0b81c478 AL |
56 | ret = NULL; \ |
57 | } else { \ | |
bc5f92e5 | 58 | ret = &(r)->items[cons].el; \ |
a19cbfb3 | 59 | } \ |
a19cbfb3 GH |
60 | } |
61 | ||
62 | #undef ALIGN | |
63 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
64 | ||
65 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
66 | ||
67 | #define QXL_MODE(_x, _y, _b, _o) \ | |
68 | { .x_res = _x, \ | |
69 | .y_res = _y, \ | |
70 | .bits = _b, \ | |
71 | .stride = (_x) * (_b) / 8, \ | |
72 | .x_mili = PIXEL_SIZE * (_x), \ | |
73 | .y_mili = PIXEL_SIZE * (_y), \ | |
74 | .orientation = _o, \ | |
75 | } | |
76 | ||
77 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
78 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
79 | QXL_MODE(x_res, y_res, 32, orientation) | |
80 | ||
81 | #define QXL_MODE_EX(x_res, y_res) \ | |
82 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
038c1879 | 83 | QXL_MODE_16_32(x_res, y_res, 1) |
a19cbfb3 GH |
84 | |
85 | static QXLMode qxl_modes[] = { | |
86 | QXL_MODE_EX(640, 480), | |
87 | QXL_MODE_EX(800, 480), | |
88 | QXL_MODE_EX(800, 600), | |
89 | QXL_MODE_EX(832, 624), | |
90 | QXL_MODE_EX(960, 640), | |
91 | QXL_MODE_EX(1024, 600), | |
92 | QXL_MODE_EX(1024, 768), | |
93 | QXL_MODE_EX(1152, 864), | |
94 | QXL_MODE_EX(1152, 870), | |
95 | QXL_MODE_EX(1280, 720), | |
96 | QXL_MODE_EX(1280, 760), | |
97 | QXL_MODE_EX(1280, 768), | |
98 | QXL_MODE_EX(1280, 800), | |
99 | QXL_MODE_EX(1280, 960), | |
100 | QXL_MODE_EX(1280, 1024), | |
101 | QXL_MODE_EX(1360, 768), | |
102 | QXL_MODE_EX(1366, 768), | |
103 | QXL_MODE_EX(1400, 1050), | |
104 | QXL_MODE_EX(1440, 900), | |
105 | QXL_MODE_EX(1600, 900), | |
106 | QXL_MODE_EX(1600, 1200), | |
107 | QXL_MODE_EX(1680, 1050), | |
108 | QXL_MODE_EX(1920, 1080), | |
a19cbfb3 GH |
109 | /* these modes need more than 8 MB video memory */ |
110 | QXL_MODE_EX(1920, 1200), | |
111 | QXL_MODE_EX(1920, 1440), | |
5c74fb27 | 112 | QXL_MODE_EX(2000, 2000), |
a19cbfb3 | 113 | QXL_MODE_EX(2048, 1536), |
5c74fb27 | 114 | QXL_MODE_EX(2048, 2048), |
a19cbfb3 GH |
115 | QXL_MODE_EX(2560, 1440), |
116 | QXL_MODE_EX(2560, 1600), | |
a19cbfb3 GH |
117 | /* these modes need more than 16 MB video memory */ |
118 | QXL_MODE_EX(2560, 2048), | |
119 | QXL_MODE_EX(2800, 2100), | |
120 | QXL_MODE_EX(3200, 2400), | |
d4bcb199 GH |
121 | QXL_MODE_EX(3840, 2160), /* 4k mainstream */ |
122 | QXL_MODE_EX(4096, 2160), /* 4k */ | |
123 | QXL_MODE_EX(7680, 4320), /* 8k mainstream */ | |
124 | QXL_MODE_EX(8192, 4320), /* 8k */ | |
a19cbfb3 GH |
125 | }; |
126 | ||
a19cbfb3 | 127 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); |
5ff4e36c | 128 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
a19cbfb3 GH |
129 | static void qxl_reset_memslots(PCIQXLDevice *d); |
130 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
131 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
132 | ||
0a530548 | 133 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 | 134 | { |
917ae08c | 135 | trace_qxl_set_guest_bug(qxl->id); |
2bce0400 | 136 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
087e6a42 | 137 | qxl->guest_bug = 1; |
2bce0400 | 138 | if (qxl->guestdebug) { |
7635392c AL |
139 | va_list ap; |
140 | va_start(ap, msg); | |
141 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
142 | vfprintf(stderr, msg, ap); | |
143 | fprintf(stderr, "\n"); | |
144 | va_end(ap); | |
2bce0400 GH |
145 | } |
146 | } | |
147 | ||
087e6a42 AL |
148 | static void qxl_clear_guest_bug(PCIQXLDevice *qxl) |
149 | { | |
150 | qxl->guest_bug = 0; | |
151 | } | |
aee32bf3 GH |
152 | |
153 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
154 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
155 | uint32_t num_dirty_rects, | |
5ff4e36c | 156 | uint32_t clear_dirty_region, |
2e1a98c9 | 157 | qxl_async_io async, struct QXLCookie *cookie) |
aee32bf3 | 158 | { |
c480bb7d AL |
159 | trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, |
160 | area->top, area->bottom); | |
161 | trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, | |
162 | clear_dirty_region); | |
5ff4e36c AL |
163 | if (async == QXL_SYNC) { |
164 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, | |
165 | dirty_rects, num_dirty_rects, clear_dirty_region); | |
166 | } else { | |
2e1a98c9 | 167 | assert(cookie != NULL); |
5ff4e36c | 168 | spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
5dba0d45 | 169 | clear_dirty_region, (uintptr_t)cookie); |
5ff4e36c | 170 | } |
aee32bf3 GH |
171 | } |
172 | ||
5ff4e36c AL |
173 | static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
174 | uint32_t id) | |
aee32bf3 | 175 | { |
c480bb7d | 176 | trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); |
14898cf6 | 177 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
178 | qxl->guest_surfaces.cmds[id] = 0; |
179 | qxl->guest_surfaces.count--; | |
180 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
181 | } |
182 | ||
5ff4e36c AL |
183 | static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
184 | qxl_async_io async) | |
185 | { | |
2e1a98c9 AL |
186 | QXLCookie *cookie; |
187 | ||
c480bb7d | 188 | trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); |
5ff4e36c | 189 | if (async) { |
2e1a98c9 AL |
190 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
191 | QXL_IO_DESTROY_SURFACE_ASYNC); | |
192 | cookie->u.surface_id = id; | |
5dba0d45 | 193 | spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); |
5ff4e36c AL |
194 | } else { |
195 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); | |
753b8b0d | 196 | qxl_spice_destroy_surface_wait_complete(qxl, id); |
5ff4e36c AL |
197 | } |
198 | } | |
199 | ||
3e16b9c5 AL |
200 | static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
201 | { | |
c480bb7d AL |
202 | trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, |
203 | qxl->num_free_res); | |
2e1a98c9 | 204 | spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
205 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
206 | QXL_IO_FLUSH_SURFACES_ASYNC)); | |
3e16b9c5 | 207 | } |
3e16b9c5 | 208 | |
aee32bf3 GH |
209 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
210 | uint32_t count) | |
211 | { | |
c480bb7d | 212 | trace_qxl_spice_loadvm_commands(qxl->id, ext, count); |
aee32bf3 GH |
213 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
214 | } | |
215 | ||
216 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
217 | { | |
c480bb7d | 218 | trace_qxl_spice_oom(qxl->id); |
aee32bf3 GH |
219 | qxl->ssd.worker->oom(qxl->ssd.worker); |
220 | } | |
221 | ||
222 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
223 | { | |
c480bb7d | 224 | trace_qxl_spice_reset_memslots(qxl->id); |
aee32bf3 GH |
225 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
226 | } | |
227 | ||
5ff4e36c | 228 | static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
aee32bf3 | 229 | { |
c480bb7d | 230 | trace_qxl_spice_destroy_surfaces_complete(qxl->id); |
14898cf6 | 231 | qemu_mutex_lock(&qxl->track_lock); |
ddd8fdc7 | 232 | memset(qxl->guest_surfaces.cmds, 0, |
8bb9f51c | 233 | sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); |
14898cf6 GH |
234 | qxl->guest_surfaces.count = 0; |
235 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
236 | } |
237 | ||
5ff4e36c AL |
238 | static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
239 | { | |
c480bb7d | 240 | trace_qxl_spice_destroy_surfaces(qxl->id, async); |
5ff4e36c | 241 | if (async) { |
2e1a98c9 | 242 | spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
243 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
244 | QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); | |
5ff4e36c AL |
245 | } else { |
246 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); | |
247 | qxl_spice_destroy_surfaces_complete(qxl); | |
248 | } | |
249 | } | |
250 | ||
020af1c4 AL |
251 | static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) |
252 | { | |
253 | trace_qxl_spice_monitors_config(qxl->id); | |
020af1c4 AL |
254 | if (replay) { |
255 | /* | |
256 | * don't use QXL_COOKIE_TYPE_IO: | |
257 | * - we are not running yet (post_load), we will assert | |
258 | * in send_events | |
259 | * - this is not a guest io, but a reply, so async_io isn't set. | |
260 | */ | |
261 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
262 | qxl->guest_monitors_config, | |
263 | MEMSLOT_GROUP_GUEST, | |
264 | (uintptr_t)qxl_cookie_new( | |
265 | QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, | |
266 | 0)); | |
267 | } else { | |
268 | qxl->guest_monitors_config = qxl->ram->monitors_config; | |
269 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
270 | qxl->ram->monitors_config, | |
271 | MEMSLOT_GROUP_GUEST, | |
272 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
273 | QXL_IO_MONITORS_CONFIG_ASYNC)); | |
274 | } | |
020af1c4 AL |
275 | } |
276 | ||
aee32bf3 GH |
277 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) |
278 | { | |
c480bb7d | 279 | trace_qxl_spice_reset_image_cache(qxl->id); |
aee32bf3 GH |
280 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
281 | } | |
282 | ||
283 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
284 | { | |
c480bb7d | 285 | trace_qxl_spice_reset_cursor(qxl->id); |
aee32bf3 | 286 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
30f6da66 YH |
287 | qemu_mutex_lock(&qxl->track_lock); |
288 | qxl->guest_cursor = 0; | |
289 | qemu_mutex_unlock(&qxl->track_lock); | |
958c2bce GH |
290 | if (qxl->ssd.cursor) { |
291 | cursor_put(qxl->ssd.cursor); | |
292 | } | |
293 | qxl->ssd.cursor = cursor_builtin_hidden(); | |
aee32bf3 GH |
294 | } |
295 | ||
296 | ||
a19cbfb3 GH |
297 | static inline uint32_t msb_mask(uint32_t val) |
298 | { | |
299 | uint32_t mask; | |
300 | ||
301 | do { | |
302 | mask = ~(val - 1) & val; | |
303 | val &= ~mask; | |
304 | } while (mask < val); | |
305 | ||
306 | return mask; | |
307 | } | |
308 | ||
309 | static ram_addr_t qxl_rom_size(void) | |
310 | { | |
038c1879 AL |
311 | uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + |
312 | sizeof(qxl_modes); | |
313 | uint32_t rom_size = 8192; /* two pages */ | |
13d1fd44 | 314 | |
038c1879 AL |
315 | required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE); |
316 | required_rom_size = msb_mask(required_rom_size * 2 - 1); | |
317 | assert(required_rom_size <= rom_size); | |
a19cbfb3 GH |
318 | return rom_size; |
319 | } | |
320 | ||
321 | static void init_qxl_rom(PCIQXLDevice *d) | |
322 | { | |
b1950430 | 323 | QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
a19cbfb3 GH |
324 | QXLModes *modes = (QXLModes *)(rom + 1); |
325 | uint32_t ram_header_size; | |
326 | uint32_t surface0_area_size; | |
327 | uint32_t num_pages; | |
13d1fd44 AL |
328 | uint32_t fb; |
329 | int i, n; | |
a19cbfb3 GH |
330 | |
331 | memset(rom, 0, d->rom_size); | |
332 | ||
333 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
334 | rom->id = cpu_to_le32(d->id); | |
335 | rom->log_level = cpu_to_le32(d->guestdebug); | |
336 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
337 | ||
338 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
339 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
340 | rom->slots_start = 1; | |
341 | rom->slots_end = NUM_MEMSLOTS - 1; | |
ddd8fdc7 | 342 | rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); |
a19cbfb3 | 343 | |
13d1fd44 | 344 | for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { |
a19cbfb3 | 345 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
13d1fd44 AL |
346 | if (fb > d->vgamem_size) { |
347 | continue; | |
a19cbfb3 | 348 | } |
13d1fd44 AL |
349 | modes->modes[n].id = cpu_to_le32(i); |
350 | modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
351 | modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
352 | modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); | |
353 | modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); | |
354 | modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
355 | modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
356 | modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
357 | n++; | |
358 | } | |
359 | modes->n_modes = cpu_to_le32(n); | |
a19cbfb3 GH |
360 | |
361 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
13d1fd44 | 362 | surface0_area_size = ALIGN(d->vgamem_size, 4096); |
a19cbfb3 GH |
363 | num_pages = d->vga.vram_size; |
364 | num_pages -= ram_header_size; | |
365 | num_pages -= surface0_area_size; | |
366 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
367 | ||
368 | rom->draw_area_offset = cpu_to_le32(0); | |
369 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
370 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
371 | rom->num_pages = cpu_to_le32(num_pages); | |
372 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
373 | ||
374 | d->shadow_rom = *rom; | |
375 | d->rom = rom; | |
376 | d->modes = modes; | |
377 | } | |
378 | ||
379 | static void init_qxl_ram(PCIQXLDevice *d) | |
380 | { | |
381 | uint8_t *buf; | |
382 | uint64_t *item; | |
383 | ||
384 | buf = d->vga.vram_ptr; | |
385 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
386 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
387 | d->ram->int_pending = cpu_to_le32(0); | |
388 | d->ram->int_mask = cpu_to_le32(0); | |
9f0f352d | 389 | d->ram->update_surface = 0; |
a19cbfb3 GH |
390 | SPICE_RING_INIT(&d->ram->cmd_ring); |
391 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
392 | SPICE_RING_INIT(&d->ram->release_ring); | |
0b81c478 AL |
393 | SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); |
394 | assert(item); | |
a19cbfb3 GH |
395 | *item = 0; |
396 | qxl_ring_set_dirty(d); | |
397 | } | |
398 | ||
399 | /* can be called from spice server thread context */ | |
b1950430 | 400 | static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
a19cbfb3 | 401 | { |
fd4aa979 | 402 | memory_region_set_dirty(mr, addr, end - addr); |
a19cbfb3 GH |
403 | } |
404 | ||
405 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
406 | { | |
b1950430 | 407 | qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); |
a19cbfb3 GH |
408 | } |
409 | ||
410 | /* called from spice server thread context only */ | |
411 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
412 | { | |
a19cbfb3 GH |
413 | void *base = qxl->vga.vram_ptr; |
414 | intptr_t offset; | |
415 | ||
416 | offset = ptr - base; | |
417 | offset &= ~(TARGET_PAGE_SIZE-1); | |
418 | assert(offset < qxl->vga.vram_size); | |
b1950430 | 419 | qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
a19cbfb3 GH |
420 | } |
421 | ||
422 | /* can be called from spice server thread context */ | |
423 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
424 | { | |
b1950430 AK |
425 | ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
426 | ram_addr_t end = qxl->vga.vram_size; | |
427 | qxl_set_dirty(&qxl->vga.vram, addr, end); | |
a19cbfb3 GH |
428 | } |
429 | ||
430 | /* | |
431 | * keep track of some command state, for savevm/loadvm. | |
432 | * called from spice server thread context only | |
433 | */ | |
fae2afb1 | 434 | static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
a19cbfb3 GH |
435 | { |
436 | switch (le32_to_cpu(ext->cmd.type)) { | |
437 | case QXL_CMD_SURFACE: | |
438 | { | |
439 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
440 | |
441 | if (!cmd) { | |
442 | return 1; | |
443 | } | |
a19cbfb3 | 444 | uint32_t id = le32_to_cpu(cmd->surface_id); |
47eddfbf | 445 | |
ddd8fdc7 | 446 | if (id >= qxl->ssd.num_surfaces) { |
0a530548 | 447 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, |
ddd8fdc7 | 448 | qxl->ssd.num_surfaces); |
47eddfbf AL |
449 | return 1; |
450 | } | |
48f4ba67 AL |
451 | if (cmd->type == QXL_SURFACE_CMD_CREATE && |
452 | (cmd->u.surface_create.stride & 0x03) != 0) { | |
453 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", | |
454 | cmd->u.surface_create.stride); | |
455 | return 1; | |
456 | } | |
14898cf6 | 457 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
458 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
459 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
460 | qxl->guest_surfaces.count++; | |
461 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
462 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
463 | } | |
464 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
465 | qxl->guest_surfaces.cmds[id] = 0; | |
466 | qxl->guest_surfaces.count--; | |
467 | } | |
14898cf6 | 468 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
469 | break; |
470 | } | |
471 | case QXL_CMD_CURSOR: | |
472 | { | |
473 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
474 | |
475 | if (!cmd) { | |
476 | return 1; | |
477 | } | |
a19cbfb3 | 478 | if (cmd->type == QXL_CURSOR_SET) { |
30f6da66 | 479 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 | 480 | qxl->guest_cursor = ext->cmd.data; |
30f6da66 | 481 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
482 | } |
483 | break; | |
484 | } | |
485 | } | |
fae2afb1 | 486 | return 0; |
a19cbfb3 GH |
487 | } |
488 | ||
489 | /* spice display interface callbacks */ | |
490 | ||
491 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
492 | { | |
493 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
494 | ||
c480bb7d | 495 | trace_qxl_interface_attach_worker(qxl->id); |
a19cbfb3 GH |
496 | qxl->ssd.worker = qxl_worker; |
497 | } | |
498 | ||
499 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
500 | { | |
501 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
502 | ||
c480bb7d | 503 | trace_qxl_interface_set_compression_level(qxl->id, level); |
a19cbfb3 GH |
504 | qxl->shadow_rom.compression_level = cpu_to_le32(level); |
505 | qxl->rom->compression_level = cpu_to_le32(level); | |
506 | qxl_rom_set_dirty(qxl); | |
507 | } | |
508 | ||
509 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
510 | { | |
511 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
512 | ||
c480bb7d | 513 | trace_qxl_interface_set_mm_time(qxl->id, mm_time); |
a19cbfb3 GH |
514 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
515 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
516 | qxl_rom_set_dirty(qxl); | |
517 | } | |
518 | ||
519 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
520 | { | |
521 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
522 | ||
c480bb7d | 523 | trace_qxl_interface_get_init_info(qxl->id); |
a19cbfb3 GH |
524 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
525 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
526 | info->num_memslots = NUM_MEMSLOTS; | |
527 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
528 | info->internal_groupslot_id = 0; | |
529 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
ddd8fdc7 | 530 | info->n_surfaces = qxl->ssd.num_surfaces; |
a19cbfb3 GH |
531 | } |
532 | ||
5b77870c AL |
533 | static const char *qxl_mode_to_string(int mode) |
534 | { | |
535 | switch (mode) { | |
536 | case QXL_MODE_COMPAT: | |
537 | return "compat"; | |
538 | case QXL_MODE_NATIVE: | |
539 | return "native"; | |
540 | case QXL_MODE_UNDEFINED: | |
541 | return "undefined"; | |
542 | case QXL_MODE_VGA: | |
543 | return "vga"; | |
544 | } | |
545 | return "INVALID"; | |
546 | } | |
547 | ||
8b92e298 AL |
548 | static const char *io_port_to_string(uint32_t io_port) |
549 | { | |
550 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
551 | return "out of range"; | |
552 | } | |
553 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
554 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
555 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
556 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
557 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
558 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
559 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
560 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
561 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
562 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
563 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
564 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
565 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
566 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
567 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
568 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
569 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
8b92e298 AL |
570 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", |
571 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
572 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
573 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
574 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
575 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
576 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
577 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
578 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
020af1c4 | 579 | [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", |
8b92e298 AL |
580 | }; |
581 | return io_port_to_string[io_port]; | |
582 | } | |
583 | ||
a19cbfb3 GH |
584 | /* called from spice server thread context only */ |
585 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
586 | { | |
587 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
588 | SimpleSpiceUpdate *update; | |
589 | QXLCommandRing *ring; | |
590 | QXLCommand *cmd; | |
e0c64d08 | 591 | int notify, ret; |
a19cbfb3 | 592 | |
c480bb7d AL |
593 | trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
594 | ||
a19cbfb3 GH |
595 | switch (qxl->mode) { |
596 | case QXL_MODE_VGA: | |
e0c64d08 GH |
597 | ret = false; |
598 | qemu_mutex_lock(&qxl->ssd.lock); | |
b1af98ba GH |
599 | update = QTAILQ_FIRST(&qxl->ssd.updates); |
600 | if (update != NULL) { | |
601 | QTAILQ_REMOVE(&qxl->ssd.updates, update, next); | |
e0c64d08 GH |
602 | *ext = update->ext; |
603 | ret = true; | |
a19cbfb3 | 604 | } |
e0c64d08 | 605 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 606 | if (ret) { |
c480bb7d | 607 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
608 | qxl_log_command(qxl, "vga", ext); |
609 | } | |
e0c64d08 | 610 | return ret; |
a19cbfb3 GH |
611 | case QXL_MODE_COMPAT: |
612 | case QXL_MODE_NATIVE: | |
613 | case QXL_MODE_UNDEFINED: | |
a19cbfb3 | 614 | ring = &qxl->ram->cmd_ring; |
087e6a42 | 615 | if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { |
a19cbfb3 GH |
616 | return false; |
617 | } | |
0b81c478 AL |
618 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
619 | if (!cmd) { | |
620 | return false; | |
621 | } | |
a19cbfb3 GH |
622 | ext->cmd = *cmd; |
623 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
624 | ext->flags = qxl->cmdflags; | |
625 | SPICE_RING_POP(ring, notify); | |
626 | qxl_ring_set_dirty(qxl); | |
627 | if (notify) { | |
628 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
629 | } | |
630 | qxl->guest_primary.commands++; | |
631 | qxl_track_command(qxl, ext); | |
632 | qxl_log_command(qxl, "cmd", ext); | |
0b81c478 | 633 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
634 | return true; |
635 | default: | |
636 | return false; | |
637 | } | |
638 | } | |
639 | ||
640 | /* called from spice server thread context only */ | |
641 | static int interface_req_cmd_notification(QXLInstance *sin) | |
642 | { | |
643 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
644 | int wait = 1; | |
645 | ||
c480bb7d | 646 | trace_qxl_ring_command_req_notification(qxl->id); |
a19cbfb3 GH |
647 | switch (qxl->mode) { |
648 | case QXL_MODE_COMPAT: | |
649 | case QXL_MODE_NATIVE: | |
650 | case QXL_MODE_UNDEFINED: | |
651 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
652 | qxl_ring_set_dirty(qxl); | |
653 | break; | |
654 | default: | |
655 | /* nothing */ | |
656 | break; | |
657 | } | |
658 | return wait; | |
659 | } | |
660 | ||
661 | /* called from spice server thread context only */ | |
662 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
663 | { | |
664 | QXLReleaseRing *ring = &d->ram->release_ring; | |
665 | uint64_t *item; | |
666 | int notify; | |
667 | ||
668 | #define QXL_FREE_BUNCH_SIZE 32 | |
669 | ||
670 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
671 | /* ring full -- can't push */ | |
672 | return; | |
673 | } | |
674 | if (!flush && d->oom_running) { | |
675 | /* collect everything from oom handler before pushing */ | |
676 | return; | |
677 | } | |
678 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
679 | /* collect a bit more before pushing */ | |
680 | return; | |
681 | } | |
682 | ||
683 | SPICE_RING_PUSH(ring, notify); | |
c480bb7d AL |
684 | trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), |
685 | d->guest_surfaces.count, d->num_free_res, | |
686 | d->last_release, notify ? "yes" : "no"); | |
687 | trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, | |
688 | ring->num_items, ring->prod, ring->cons); | |
a19cbfb3 GH |
689 | if (notify) { |
690 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
691 | } | |
0b81c478 AL |
692 | SPICE_RING_PROD_ITEM(d, ring, item); |
693 | if (!item) { | |
694 | return; | |
695 | } | |
a19cbfb3 GH |
696 | *item = 0; |
697 | d->num_free_res = 0; | |
698 | d->last_release = NULL; | |
699 | qxl_ring_set_dirty(d); | |
700 | } | |
701 | ||
702 | /* called from spice server thread context only */ | |
703 | static void interface_release_resource(QXLInstance *sin, | |
704 | struct QXLReleaseInfoExt ext) | |
705 | { | |
706 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
707 | QXLReleaseRing *ring; | |
708 | uint64_t *item, id; | |
709 | ||
710 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
711 | /* host group -> vga mode update request */ | |
f4a8a424 | 712 | qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); |
a19cbfb3 GH |
713 | return; |
714 | } | |
715 | ||
716 | /* | |
717 | * ext->info points into guest-visible memory | |
718 | * pci bar 0, $command.release_info | |
719 | */ | |
720 | ring = &qxl->ram->release_ring; | |
0b81c478 AL |
721 | SPICE_RING_PROD_ITEM(qxl, ring, item); |
722 | if (!item) { | |
723 | return; | |
724 | } | |
a19cbfb3 GH |
725 | if (*item == 0) { |
726 | /* stick head into the ring */ | |
727 | id = ext.info->id; | |
728 | ext.info->next = 0; | |
729 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
730 | *item = id; | |
731 | qxl_ring_set_dirty(qxl); | |
732 | } else { | |
733 | /* append item to the list */ | |
734 | qxl->last_release->next = ext.info->id; | |
735 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
736 | ext.info->next = 0; | |
737 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
738 | } | |
739 | qxl->last_release = ext.info; | |
740 | qxl->num_free_res++; | |
c480bb7d | 741 | trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); |
a19cbfb3 GH |
742 | qxl_push_free_res(qxl, 0); |
743 | } | |
744 | ||
745 | /* called from spice server thread context only */ | |
746 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
747 | { | |
748 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
749 | QXLCursorRing *ring; | |
750 | QXLCommand *cmd; | |
751 | int notify; | |
752 | ||
c480bb7d AL |
753 | trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
754 | ||
a19cbfb3 GH |
755 | switch (qxl->mode) { |
756 | case QXL_MODE_COMPAT: | |
757 | case QXL_MODE_NATIVE: | |
758 | case QXL_MODE_UNDEFINED: | |
759 | ring = &qxl->ram->cursor_ring; | |
760 | if (SPICE_RING_IS_EMPTY(ring)) { | |
761 | return false; | |
762 | } | |
0b81c478 AL |
763 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
764 | if (!cmd) { | |
765 | return false; | |
766 | } | |
a19cbfb3 GH |
767 | ext->cmd = *cmd; |
768 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
769 | ext->flags = qxl->cmdflags; | |
770 | SPICE_RING_POP(ring, notify); | |
771 | qxl_ring_set_dirty(qxl); | |
772 | if (notify) { | |
773 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
774 | } | |
775 | qxl->guest_primary.commands++; | |
776 | qxl_track_command(qxl, ext); | |
777 | qxl_log_command(qxl, "csr", ext); | |
778 | if (qxl->id == 0) { | |
779 | qxl_render_cursor(qxl, ext); | |
780 | } | |
c480bb7d | 781 | trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
782 | return true; |
783 | default: | |
784 | return false; | |
785 | } | |
786 | } | |
787 | ||
788 | /* called from spice server thread context only */ | |
789 | static int interface_req_cursor_notification(QXLInstance *sin) | |
790 | { | |
791 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
792 | int wait = 1; | |
793 | ||
c480bb7d | 794 | trace_qxl_ring_cursor_req_notification(qxl->id); |
a19cbfb3 GH |
795 | switch (qxl->mode) { |
796 | case QXL_MODE_COMPAT: | |
797 | case QXL_MODE_NATIVE: | |
798 | case QXL_MODE_UNDEFINED: | |
799 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
800 | qxl_ring_set_dirty(qxl); | |
801 | break; | |
802 | default: | |
803 | /* nothing */ | |
804 | break; | |
805 | } | |
806 | return wait; | |
807 | } | |
808 | ||
809 | /* called from spice server thread context */ | |
810 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
811 | { | |
baeae407 AL |
812 | /* |
813 | * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in | |
814 | * use by xf86-video-qxl and is defined out in the qxl windows driver. | |
815 | * Probably was at some earlier version that is prior to git start (2009), | |
816 | * and is still guest trigerrable. | |
817 | */ | |
818 | fprintf(stderr, "%s: deprecated\n", __func__); | |
a19cbfb3 GH |
819 | } |
820 | ||
821 | /* called from spice server thread context only */ | |
822 | static int interface_flush_resources(QXLInstance *sin) | |
823 | { | |
824 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
825 | int ret; | |
826 | ||
a19cbfb3 GH |
827 | ret = qxl->num_free_res; |
828 | if (ret) { | |
829 | qxl_push_free_res(qxl, 1); | |
830 | } | |
831 | return ret; | |
832 | } | |
833 | ||
5ff4e36c AL |
834 | static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
835 | ||
5ff4e36c | 836 | /* called from spice server thread context only */ |
2e1a98c9 | 837 | static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
5ff4e36c | 838 | { |
5ff4e36c AL |
839 | uint32_t current_async; |
840 | ||
841 | qemu_mutex_lock(&qxl->async_lock); | |
842 | current_async = qxl->current_async; | |
843 | qxl->current_async = QXL_UNDEFINED_IO; | |
844 | qemu_mutex_unlock(&qxl->async_lock); | |
845 | ||
c480bb7d | 846 | trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); |
2e1a98c9 AL |
847 | if (!cookie) { |
848 | fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); | |
849 | return; | |
850 | } | |
851 | if (cookie && current_async != cookie->io) { | |
852 | fprintf(stderr, | |
2fce7edf AL |
853 | "qxl: %s: error: current_async = %d != %" |
854 | PRId64 " = cookie->io\n", __func__, current_async, cookie->io); | |
2e1a98c9 | 855 | } |
5ff4e36c | 856 | switch (current_async) { |
81fb6f15 AL |
857 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
858 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
859 | case QXL_IO_UPDATE_AREA_ASYNC: | |
860 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 861 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
81fb6f15 | 862 | break; |
5ff4e36c AL |
863 | case QXL_IO_CREATE_PRIMARY_ASYNC: |
864 | qxl_create_guest_primary_complete(qxl); | |
865 | break; | |
866 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
867 | qxl_spice_destroy_surfaces_complete(qxl); | |
868 | break; | |
869 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
2e1a98c9 | 870 | qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
5ff4e36c | 871 | break; |
81fb6f15 AL |
872 | default: |
873 | fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, | |
874 | current_async); | |
5ff4e36c AL |
875 | } |
876 | qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); | |
877 | } | |
878 | ||
81fb6f15 AL |
879 | /* called from spice server thread context only */ |
880 | static void interface_update_area_complete(QXLInstance *sin, | |
881 | uint32_t surface_id, | |
882 | QXLRect *dirty, uint32_t num_updated_rects) | |
883 | { | |
884 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
885 | int i; | |
886 | int qxl_i; | |
887 | ||
888 | qemu_mutex_lock(&qxl->ssd.lock); | |
889 | if (surface_id != 0 || !qxl->render_update_cookie_num) { | |
890 | qemu_mutex_unlock(&qxl->ssd.lock); | |
891 | return; | |
892 | } | |
c480bb7d AL |
893 | trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, |
894 | dirty->right, dirty->top, dirty->bottom); | |
895 | trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); | |
81fb6f15 AL |
896 | if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { |
897 | /* | |
898 | * overflow - treat this as a full update. Not expected to be common. | |
899 | */ | |
c480bb7d AL |
900 | trace_qxl_interface_update_area_complete_overflow(qxl->id, |
901 | QXL_NUM_DIRTY_RECTS); | |
81fb6f15 AL |
902 | qxl->guest_primary.resized = 1; |
903 | } | |
904 | if (qxl->guest_primary.resized) { | |
905 | /* | |
906 | * Don't bother copying or scheduling the bh since we will flip | |
907 | * the whole area anyway on completion of the update_area async call | |
908 | */ | |
909 | qemu_mutex_unlock(&qxl->ssd.lock); | |
910 | return; | |
911 | } | |
912 | qxl_i = qxl->num_dirty_rects; | |
913 | for (i = 0; i < num_updated_rects; i++) { | |
914 | qxl->dirty[qxl_i++] = dirty[i]; | |
915 | } | |
916 | qxl->num_dirty_rects += num_updated_rects; | |
c480bb7d AL |
917 | trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, |
918 | qxl->num_dirty_rects); | |
81fb6f15 AL |
919 | qemu_bh_schedule(qxl->update_area_bh); |
920 | qemu_mutex_unlock(&qxl->ssd.lock); | |
921 | } | |
922 | ||
2e1a98c9 AL |
923 | /* called from spice server thread context only */ |
924 | static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) | |
925 | { | |
926 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
5dba0d45 | 927 | QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; |
2e1a98c9 AL |
928 | |
929 | switch (cookie->type) { | |
930 | case QXL_COOKIE_TYPE_IO: | |
931 | interface_async_complete_io(qxl, cookie); | |
81fb6f15 AL |
932 | g_free(cookie); |
933 | break; | |
934 | case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: | |
935 | qxl_render_update_area_done(qxl, cookie); | |
2e1a98c9 | 936 | break; |
020af1c4 AL |
937 | case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: |
938 | break; | |
2e1a98c9 AL |
939 | default: |
940 | fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", | |
941 | __func__, cookie->type); | |
81fb6f15 | 942 | g_free(cookie); |
2e1a98c9 | 943 | } |
2e1a98c9 AL |
944 | } |
945 | ||
c10018d6 SSP |
946 | /* called from spice server thread context only */ |
947 | static void interface_set_client_capabilities(QXLInstance *sin, | |
948 | uint8_t client_present, | |
949 | uint8_t caps[58]) | |
950 | { | |
951 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
952 | ||
e0ac6097 AL |
953 | if (qxl->revision < 4) { |
954 | trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, | |
955 | qxl->revision); | |
956 | return; | |
957 | } | |
958 | ||
ab902981 HG |
959 | if (runstate_check(RUN_STATE_INMIGRATE) || |
960 | runstate_check(RUN_STATE_POSTMIGRATE)) { | |
961 | return; | |
962 | } | |
963 | ||
c10018d6 | 964 | qxl->shadow_rom.client_present = client_present; |
08688af0 MA |
965 | memcpy(qxl->shadow_rom.client_capabilities, caps, |
966 | sizeof(qxl->shadow_rom.client_capabilities)); | |
c10018d6 | 967 | qxl->rom->client_present = client_present; |
08688af0 MA |
968 | memcpy(qxl->rom->client_capabilities, caps, |
969 | sizeof(qxl->rom->client_capabilities)); | |
c10018d6 SSP |
970 | qxl_rom_set_dirty(qxl); |
971 | ||
972 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); | |
973 | } | |
974 | ||
a639ab04 AL |
975 | static uint32_t qxl_crc32(const uint8_t *p, unsigned len) |
976 | { | |
977 | /* | |
978 | * zlib xors the seed with 0xffffffff, and xors the result | |
979 | * again with 0xffffffff; Both are not done with linux's crc32, | |
980 | * which we want to be compatible with, so undo that. | |
981 | */ | |
982 | return crc32(0xffffffff, p, len) ^ 0xffffffff; | |
983 | } | |
984 | ||
985 | /* called from main context only */ | |
986 | static int interface_client_monitors_config(QXLInstance *sin, | |
987 | VDAgentMonitorsConfig *monitors_config) | |
988 | { | |
989 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
990 | QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); | |
991 | int i; | |
992 | ||
e0ac6097 AL |
993 | if (qxl->revision < 4) { |
994 | trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, | |
995 | qxl->revision); | |
996 | return 0; | |
997 | } | |
a639ab04 AL |
998 | /* |
999 | * Older windows drivers set int_mask to 0 when their ISR is called, | |
1000 | * then later set it to ~0. So it doesn't relate to the actual interrupts | |
1001 | * handled. However, they are old, so clearly they don't support this | |
1002 | * interrupt | |
1003 | */ | |
1004 | if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || | |
1005 | !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { | |
1006 | trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, | |
1007 | qxl->ram->int_mask, | |
1008 | monitors_config); | |
1009 | return 0; | |
1010 | } | |
1011 | if (!monitors_config) { | |
1012 | return 1; | |
1013 | } | |
1014 | memset(&rom->client_monitors_config, 0, | |
1015 | sizeof(rom->client_monitors_config)); | |
1016 | rom->client_monitors_config.count = monitors_config->num_of_monitors; | |
1017 | /* monitors_config->flags ignored */ | |
1018 | if (rom->client_monitors_config.count >= | |
1019 | ARRAY_SIZE(rom->client_monitors_config.heads)) { | |
1020 | trace_qxl_client_monitors_config_capped(qxl->id, | |
1021 | monitors_config->num_of_monitors, | |
1022 | ARRAY_SIZE(rom->client_monitors_config.heads)); | |
1023 | rom->client_monitors_config.count = | |
1024 | ARRAY_SIZE(rom->client_monitors_config.heads); | |
1025 | } | |
1026 | for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { | |
1027 | VDAgentMonConfig *monitor = &monitors_config->monitors[i]; | |
1028 | QXLURect *rect = &rom->client_monitors_config.heads[i]; | |
1029 | /* monitor->depth ignored */ | |
1030 | rect->left = monitor->x; | |
1031 | rect->top = monitor->y; | |
1032 | rect->right = monitor->x + monitor->width; | |
1033 | rect->bottom = monitor->y + monitor->height; | |
1034 | } | |
1035 | rom->client_monitors_config_crc = qxl_crc32( | |
1036 | (const uint8_t *)&rom->client_monitors_config, | |
1037 | sizeof(rom->client_monitors_config)); | |
1038 | trace_qxl_client_monitors_config_crc(qxl->id, | |
1039 | sizeof(rom->client_monitors_config), | |
1040 | rom->client_monitors_config_crc); | |
1041 | ||
1042 | trace_qxl_interrupt_client_monitors_config(qxl->id, | |
1043 | rom->client_monitors_config.count, | |
1044 | rom->client_monitors_config.heads); | |
1045 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); | |
1046 | return 1; | |
1047 | } | |
a639ab04 | 1048 | |
a19cbfb3 GH |
1049 | static const QXLInterface qxl_interface = { |
1050 | .base.type = SPICE_INTERFACE_QXL, | |
1051 | .base.description = "qxl gpu", | |
1052 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
1053 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
1054 | ||
1055 | .attache_worker = interface_attach_worker, | |
1056 | .set_compression_level = interface_set_compression_level, | |
1057 | .set_mm_time = interface_set_mm_time, | |
1058 | .get_init_info = interface_get_init_info, | |
1059 | ||
1060 | /* the callbacks below are called from spice server thread context */ | |
1061 | .get_command = interface_get_command, | |
1062 | .req_cmd_notification = interface_req_cmd_notification, | |
1063 | .release_resource = interface_release_resource, | |
1064 | .get_cursor_command = interface_get_cursor_command, | |
1065 | .req_cursor_notification = interface_req_cursor_notification, | |
1066 | .notify_update = interface_notify_update, | |
1067 | .flush_resources = interface_flush_resources, | |
5ff4e36c | 1068 | .async_complete = interface_async_complete, |
81fb6f15 | 1069 | .update_area_complete = interface_update_area_complete, |
c10018d6 | 1070 | .set_client_capabilities = interface_set_client_capabilities, |
a639ab04 | 1071 | .client_monitors_config = interface_client_monitors_config, |
a19cbfb3 GH |
1072 | }; |
1073 | ||
1074 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
1075 | { | |
1076 | if (d->mode == QXL_MODE_VGA) { | |
1077 | return; | |
1078 | } | |
c480bb7d | 1079 | trace_qxl_enter_vga_mode(d->id); |
a19cbfb3 GH |
1080 | qemu_spice_create_host_primary(&d->ssd); |
1081 | d->mode = QXL_MODE_VGA; | |
0f7bfd81 | 1082 | vga_dirty_log_start(&d->vga); |
1dbfa005 | 1083 | graphic_hw_update(d->vga.con); |
a19cbfb3 GH |
1084 | } |
1085 | ||
1086 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
1087 | { | |
1088 | if (d->mode != QXL_MODE_VGA) { | |
1089 | return; | |
1090 | } | |
c480bb7d | 1091 | trace_qxl_exit_vga_mode(d->id); |
0f7bfd81 | 1092 | vga_dirty_log_stop(&d->vga); |
5ff4e36c | 1093 | qxl_destroy_primary(d, QXL_SYNC); |
a19cbfb3 GH |
1094 | } |
1095 | ||
40010aea | 1096 | static void qxl_update_irq(PCIQXLDevice *d) |
a19cbfb3 GH |
1097 | { |
1098 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
1099 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
1100 | int level = !!(pending & mask); | |
1101 | qemu_set_irq(d->pci.irq[0], level); | |
1102 | qxl_ring_set_dirty(d); | |
1103 | } | |
1104 | ||
a19cbfb3 GH |
1105 | static void qxl_check_state(PCIQXLDevice *d) |
1106 | { | |
1107 | QXLRam *ram = d->ram; | |
71d388d4 | 1108 | int spice_display_running = qemu_spice_display_is_running(&d->ssd); |
a19cbfb3 | 1109 | |
71d388d4 YH |
1110 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
1111 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
1112 | } |
1113 | ||
1114 | static void qxl_reset_state(PCIQXLDevice *d) | |
1115 | { | |
a19cbfb3 GH |
1116 | QXLRom *rom = d->rom; |
1117 | ||
be48e995 | 1118 | qxl_check_state(d); |
a19cbfb3 GH |
1119 | d->shadow_rom.update_id = cpu_to_le32(0); |
1120 | *rom = d->shadow_rom; | |
1121 | qxl_rom_set_dirty(d); | |
1122 | init_qxl_ram(d); | |
1123 | d->num_free_res = 0; | |
1124 | d->last_release = NULL; | |
1125 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
1126 | } | |
1127 | ||
1128 | static void qxl_soft_reset(PCIQXLDevice *d) | |
1129 | { | |
c480bb7d | 1130 | trace_qxl_soft_reset(d->id); |
a19cbfb3 | 1131 | qxl_check_state(d); |
087e6a42 | 1132 | qxl_clear_guest_bug(d); |
a5f68c22 | 1133 | d->current_async = QXL_UNDEFINED_IO; |
a19cbfb3 GH |
1134 | |
1135 | if (d->id == 0) { | |
1136 | qxl_enter_vga_mode(d); | |
1137 | } else { | |
1138 | d->mode = QXL_MODE_UNDEFINED; | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
1143 | { | |
c480bb7d | 1144 | trace_qxl_hard_reset(d->id, loadvm); |
a19cbfb3 | 1145 | |
aee32bf3 GH |
1146 | qxl_spice_reset_cursor(d); |
1147 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
1148 | qxl_reset_surfaces(d); |
1149 | qxl_reset_memslots(d); | |
1150 | ||
1151 | /* pre loadvm reset must not touch QXLRam. This lives in | |
1152 | * device memory, is migrated together with RAM and thus | |
1153 | * already loaded at this point */ | |
1154 | if (!loadvm) { | |
1155 | qxl_reset_state(d); | |
1156 | } | |
1157 | qemu_spice_create_host_memslot(&d->ssd); | |
1158 | qxl_soft_reset(d); | |
a19cbfb3 GH |
1159 | } |
1160 | ||
1161 | static void qxl_reset_handler(DeviceState *dev) | |
1162 | { | |
1163 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
c480bb7d | 1164 | |
a19cbfb3 GH |
1165 | qxl_hard_reset(d, 0); |
1166 | } | |
1167 | ||
1168 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
1169 | { | |
1170 | VGACommonState *vga = opaque; | |
1171 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
1172 | ||
c480bb7d | 1173 | trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); |
a19cbfb3 | 1174 | if (qxl->mode != QXL_MODE_VGA) { |
5ff4e36c | 1175 | qxl_destroy_primary(qxl, QXL_SYNC); |
a19cbfb3 GH |
1176 | qxl_soft_reset(qxl); |
1177 | } | |
1178 | vga_ioport_write(opaque, addr, val); | |
1179 | } | |
1180 | ||
f67ab77a GH |
1181 | static const MemoryRegionPortio qxl_vga_portio_list[] = { |
1182 | { 0x04, 2, 1, .read = vga_ioport_read, | |
1183 | .write = qxl_vga_ioport_write }, /* 3b4 */ | |
1184 | { 0x0a, 1, 1, .read = vga_ioport_read, | |
1185 | .write = qxl_vga_ioport_write }, /* 3ba */ | |
1186 | { 0x10, 16, 1, .read = vga_ioport_read, | |
1187 | .write = qxl_vga_ioport_write }, /* 3c0 */ | |
1188 | { 0x24, 2, 1, .read = vga_ioport_read, | |
1189 | .write = qxl_vga_ioport_write }, /* 3d4 */ | |
1190 | { 0x2a, 1, 1, .read = vga_ioport_read, | |
1191 | .write = qxl_vga_ioport_write }, /* 3da */ | |
1192 | PORTIO_END_OF_LIST(), | |
1193 | }; | |
1194 | ||
e954ea28 AL |
1195 | static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
1196 | qxl_async_io async) | |
a19cbfb3 GH |
1197 | { |
1198 | static const int regions[] = { | |
1199 | QXL_RAM_RANGE_INDEX, | |
1200 | QXL_VRAM_RANGE_INDEX, | |
6f2b175a | 1201 | QXL_VRAM64_RANGE_INDEX, |
a19cbfb3 GH |
1202 | }; |
1203 | uint64_t guest_start; | |
1204 | uint64_t guest_end; | |
1205 | int pci_region; | |
1206 | pcibus_t pci_start; | |
1207 | pcibus_t pci_end; | |
1208 | intptr_t virt_start; | |
1209 | QXLDevMemSlot memslot; | |
1210 | int i; | |
1211 | ||
1212 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
1213 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
1214 | ||
c480bb7d | 1215 | trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); |
a19cbfb3 | 1216 | |
e954ea28 | 1217 | if (slot_id >= NUM_MEMSLOTS) { |
0a530548 | 1218 | qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, |
e954ea28 AL |
1219 | slot_id, NUM_MEMSLOTS); |
1220 | return 1; | |
1221 | } | |
1222 | if (guest_start > guest_end) { | |
0a530548 | 1223 | qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 |
e954ea28 AL |
1224 | " > 0x%" PRIx64, __func__, guest_start, guest_end); |
1225 | return 1; | |
1226 | } | |
a19cbfb3 GH |
1227 | |
1228 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
1229 | pci_region = regions[i]; | |
1230 | pci_start = d->pci.io_regions[pci_region].addr; | |
1231 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
1232 | /* mapped? */ | |
1233 | if (pci_start == -1) { | |
1234 | continue; | |
1235 | } | |
1236 | /* start address in range ? */ | |
1237 | if (guest_start < pci_start || guest_start > pci_end) { | |
1238 | continue; | |
1239 | } | |
1240 | /* end address in range ? */ | |
1241 | if (guest_end > pci_end) { | |
1242 | continue; | |
1243 | } | |
1244 | /* passed */ | |
1245 | break; | |
1246 | } | |
e954ea28 | 1247 | if (i == ARRAY_SIZE(regions)) { |
0a530548 | 1248 | qxl_set_guest_bug(d, "%s: finished loop without match", __func__); |
e954ea28 AL |
1249 | return 1; |
1250 | } | |
a19cbfb3 GH |
1251 | |
1252 | switch (pci_region) { | |
1253 | case QXL_RAM_RANGE_INDEX: | |
b1950430 | 1254 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
a19cbfb3 GH |
1255 | break; |
1256 | case QXL_VRAM_RANGE_INDEX: | |
6f2b175a | 1257 | case 4 /* vram 64bit */: |
b1950430 | 1258 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
a19cbfb3 GH |
1259 | break; |
1260 | default: | |
1261 | /* should not happen */ | |
0a530548 | 1262 | qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); |
e954ea28 | 1263 | return 1; |
a19cbfb3 GH |
1264 | } |
1265 | ||
1266 | memslot.slot_id = slot_id; | |
1267 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
1268 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
1269 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
1270 | memslot.addr_delta = memslot.virt_start - delta; | |
1271 | memslot.generation = d->rom->slot_generation = 0; | |
1272 | qxl_rom_set_dirty(d); | |
1273 | ||
5ff4e36c | 1274 | qemu_spice_add_memslot(&d->ssd, &memslot, async); |
a19cbfb3 GH |
1275 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
1276 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
1277 | d->guest_slots[slot_id].delta = delta; | |
1278 | d->guest_slots[slot_id].active = 1; | |
e954ea28 | 1279 | return 0; |
a19cbfb3 GH |
1280 | } |
1281 | ||
1282 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
1283 | { | |
5c59d118 | 1284 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
1285 | d->guest_slots[slot_id].active = 0; |
1286 | } | |
1287 | ||
1288 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
1289 | { | |
aee32bf3 | 1290 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
1291 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1292 | } | |
1293 | ||
1294 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
1295 | { | |
c480bb7d | 1296 | trace_qxl_reset_surfaces(d->id); |
a19cbfb3 | 1297 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1298 | qxl_spice_destroy_surfaces(d, QXL_SYNC); |
a19cbfb3 GH |
1299 | } |
1300 | ||
e25139b3 | 1301 | /* can be also called from spice server thread context */ |
a19cbfb3 GH |
1302 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1303 | { | |
1304 | uint64_t phys = le64_to_cpu(pqxl); | |
1305 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
1306 | uint64_t offset = phys & 0xffffffffffff; | |
1307 | ||
1308 | switch (group_id) { | |
1309 | case MEMSLOT_GROUP_HOST: | |
f4a8a424 | 1310 | return (void *)(intptr_t)offset; |
a19cbfb3 | 1311 | case MEMSLOT_GROUP_GUEST: |
4b635c59 | 1312 | if (slot >= NUM_MEMSLOTS) { |
0a530548 AL |
1313 | qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, |
1314 | NUM_MEMSLOTS); | |
4b635c59 AL |
1315 | return NULL; |
1316 | } | |
1317 | if (!qxl->guest_slots[slot].active) { | |
0a530548 | 1318 | qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); |
4b635c59 AL |
1319 | return NULL; |
1320 | } | |
1321 | if (offset < qxl->guest_slots[slot].delta) { | |
0a530548 AL |
1322 | qxl_set_guest_bug(qxl, |
1323 | "slot %d offset %"PRIu64" < delta %"PRIu64"\n", | |
4b635c59 AL |
1324 | slot, offset, qxl->guest_slots[slot].delta); |
1325 | return NULL; | |
1326 | } | |
a19cbfb3 | 1327 | offset -= qxl->guest_slots[slot].delta; |
4b635c59 | 1328 | if (offset > qxl->guest_slots[slot].size) { |
0a530548 AL |
1329 | qxl_set_guest_bug(qxl, |
1330 | "slot %d offset %"PRIu64" > size %"PRIu64"\n", | |
4b635c59 AL |
1331 | slot, offset, qxl->guest_slots[slot].size); |
1332 | return NULL; | |
1333 | } | |
a19cbfb3 | 1334 | return qxl->guest_slots[slot].ptr + offset; |
a19cbfb3 | 1335 | } |
4b635c59 | 1336 | return NULL; |
a19cbfb3 GH |
1337 | } |
1338 | ||
5ff4e36c AL |
1339 | static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1340 | { | |
1341 | /* for local rendering */ | |
1342 | qxl_render_resize(qxl); | |
1343 | } | |
1344 | ||
1345 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, | |
1346 | qxl_async_io async) | |
a19cbfb3 GH |
1347 | { |
1348 | QXLDevSurfaceCreate surface; | |
1349 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
13d1fd44 AL |
1350 | int size; |
1351 | int requested_height = le32_to_cpu(sc->height); | |
1352 | int requested_stride = le32_to_cpu(sc->stride); | |
1353 | ||
1354 | size = abs(requested_stride) * requested_height; | |
1355 | if (size > qxl->vgamem_size) { | |
1356 | qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer" | |
1357 | " size", __func__); | |
1358 | return; | |
1359 | } | |
a19cbfb3 | 1360 | |
ddf9f4b7 | 1361 | if (qxl->mode == QXL_MODE_NATIVE) { |
0a530548 | 1362 | qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", |
ddf9f4b7 AL |
1363 | __func__); |
1364 | } | |
a19cbfb3 GH |
1365 | qxl_exit_vga_mode(qxl); |
1366 | ||
a19cbfb3 GH |
1367 | surface.format = le32_to_cpu(sc->format); |
1368 | surface.height = le32_to_cpu(sc->height); | |
1369 | surface.mem = le64_to_cpu(sc->mem); | |
1370 | surface.position = le32_to_cpu(sc->position); | |
1371 | surface.stride = le32_to_cpu(sc->stride); | |
1372 | surface.width = le32_to_cpu(sc->width); | |
1373 | surface.type = le32_to_cpu(sc->type); | |
1374 | surface.flags = le32_to_cpu(sc->flags); | |
c480bb7d AL |
1375 | trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, |
1376 | sc->format, sc->position); | |
1377 | trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, | |
1378 | sc->flags); | |
a19cbfb3 | 1379 | |
48f4ba67 AL |
1380 | if ((surface.stride & 0x3) != 0) { |
1381 | qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", | |
1382 | surface.stride); | |
1383 | return; | |
1384 | } | |
1385 | ||
a19cbfb3 GH |
1386 | surface.mouse_mode = true; |
1387 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
1388 | if (loadvm) { | |
1389 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
1390 | } | |
1391 | ||
1392 | qxl->mode = QXL_MODE_NATIVE; | |
1393 | qxl->cmdflags = 0; | |
5ff4e36c | 1394 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); |
a19cbfb3 | 1395 | |
5ff4e36c AL |
1396 | if (async == QXL_SYNC) { |
1397 | qxl_create_guest_primary_complete(qxl); | |
1398 | } | |
a19cbfb3 GH |
1399 | } |
1400 | ||
5ff4e36c AL |
1401 | /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or |
1402 | * done (in QXL_SYNC case), 0 otherwise. */ | |
1403 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) | |
a19cbfb3 GH |
1404 | { |
1405 | if (d->mode == QXL_MODE_UNDEFINED) { | |
5ff4e36c | 1406 | return 0; |
a19cbfb3 | 1407 | } |
c480bb7d | 1408 | trace_qxl_destroy_primary(d->id); |
a19cbfb3 | 1409 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1410 | qemu_spice_destroy_primary_surface(&d->ssd, 0, async); |
30f6da66 | 1411 | qxl_spice_reset_cursor(d); |
5ff4e36c | 1412 | return 1; |
a19cbfb3 GH |
1413 | } |
1414 | ||
1415 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1416 | { | |
1417 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1418 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1419 | QXLMode *mode = d->modes->modes + modenr; | |
1420 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1421 | QXLMemSlot slot = { | |
1422 | .mem_start = start, | |
1423 | .mem_end = end | |
1424 | }; | |
1425 | QXLSurfaceCreate surface = { | |
1426 | .width = mode->x_res, | |
1427 | .height = mode->y_res, | |
1428 | .stride = -mode->x_res * 4, | |
1429 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1430 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1431 | .mouse_mode = true, | |
1432 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1433 | }; | |
1434 | ||
c480bb7d AL |
1435 | trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, |
1436 | devmem); | |
a19cbfb3 GH |
1437 | if (!loadvm) { |
1438 | qxl_hard_reset(d, 0); | |
1439 | } | |
1440 | ||
1441 | d->guest_slots[0].slot = slot; | |
e954ea28 | 1442 | assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); |
a19cbfb3 GH |
1443 | |
1444 | d->guest_primary.surface = surface; | |
5ff4e36c | 1445 | qxl_create_guest_primary(d, 0, QXL_SYNC); |
a19cbfb3 GH |
1446 | |
1447 | d->mode = QXL_MODE_COMPAT; | |
1448 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
a19cbfb3 GH |
1449 | if (mode->bits == 16) { |
1450 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1451 | } | |
a19cbfb3 GH |
1452 | d->shadow_rom.mode = cpu_to_le32(modenr); |
1453 | d->rom->mode = cpu_to_le32(modenr); | |
1454 | qxl_rom_set_dirty(d); | |
1455 | } | |
1456 | ||
a8170e5e | 1457 | static void ioport_write(void *opaque, hwaddr addr, |
b1950430 | 1458 | uint64_t val, unsigned size) |
a19cbfb3 GH |
1459 | { |
1460 | PCIQXLDevice *d = opaque; | |
b1950430 | 1461 | uint32_t io_port = addr; |
5ff4e36c | 1462 | qxl_async_io async = QXL_SYNC; |
5ff4e36c | 1463 | uint32_t orig_io_port = io_port; |
a19cbfb3 | 1464 | |
d96aafca | 1465 | if (d->guest_bug && io_port != QXL_IO_RESET) { |
087e6a42 AL |
1466 | return; |
1467 | } | |
1468 | ||
020af1c4 | 1469 | if (d->revision <= QXL_REVISION_STABLE_V10 && |
ffe01e59 | 1470 | io_port > QXL_IO_FLUSH_RELEASE) { |
020af1c4 AL |
1471 | qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", |
1472 | io_port, d->revision); | |
1473 | return; | |
1474 | } | |
1475 | ||
a19cbfb3 GH |
1476 | switch (io_port) { |
1477 | case QXL_IO_RESET: | |
1478 | case QXL_IO_SET_MODE: | |
1479 | case QXL_IO_MEMSLOT_ADD: | |
1480 | case QXL_IO_MEMSLOT_DEL: | |
1481 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1482 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1483 | case QXL_IO_LOG: |
5ff4e36c AL |
1484 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
1485 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
a19cbfb3 GH |
1486 | break; |
1487 | default: | |
e21a298a | 1488 | if (d->mode != QXL_MODE_VGA) { |
a19cbfb3 | 1489 | break; |
e21a298a | 1490 | } |
c480bb7d | 1491 | trace_qxl_io_unexpected_vga_mode(d->id, |
917ae08c | 1492 | addr, val, io_port_to_string(io_port)); |
5ff4e36c AL |
1493 | /* be nice to buggy guest drivers */ |
1494 | if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && | |
020af1c4 | 1495 | io_port < QXL_IO_RANGE_SIZE) { |
5ff4e36c AL |
1496 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
1497 | } | |
a19cbfb3 GH |
1498 | return; |
1499 | } | |
1500 | ||
5ff4e36c AL |
1501 | /* we change the io_port to avoid ifdeffery in the main switch */ |
1502 | orig_io_port = io_port; | |
1503 | switch (io_port) { | |
1504 | case QXL_IO_UPDATE_AREA_ASYNC: | |
1505 | io_port = QXL_IO_UPDATE_AREA; | |
1506 | goto async_common; | |
1507 | case QXL_IO_MEMSLOT_ADD_ASYNC: | |
1508 | io_port = QXL_IO_MEMSLOT_ADD; | |
1509 | goto async_common; | |
1510 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
1511 | io_port = QXL_IO_CREATE_PRIMARY; | |
1512 | goto async_common; | |
1513 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
1514 | io_port = QXL_IO_DESTROY_PRIMARY; | |
1515 | goto async_common; | |
1516 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
1517 | io_port = QXL_IO_DESTROY_SURFACE_WAIT; | |
1518 | goto async_common; | |
1519 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
1520 | io_port = QXL_IO_DESTROY_ALL_SURFACES; | |
3e16b9c5 AL |
1521 | goto async_common; |
1522 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 1523 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
5ff4e36c AL |
1524 | async_common: |
1525 | async = QXL_ASYNC; | |
1526 | qemu_mutex_lock(&d->async_lock); | |
1527 | if (d->current_async != QXL_UNDEFINED_IO) { | |
0a530548 | 1528 | qxl_set_guest_bug(d, "%d async started before last (%d) complete", |
5ff4e36c AL |
1529 | io_port, d->current_async); |
1530 | qemu_mutex_unlock(&d->async_lock); | |
1531 | return; | |
1532 | } | |
1533 | d->current_async = orig_io_port; | |
1534 | qemu_mutex_unlock(&d->async_lock); | |
5ff4e36c AL |
1535 | break; |
1536 | default: | |
1537 | break; | |
1538 | } | |
c480bb7d AL |
1539 | trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, |
1540 | async); | |
5ff4e36c | 1541 | |
a19cbfb3 GH |
1542 | switch (io_port) { |
1543 | case QXL_IO_UPDATE_AREA: | |
1544 | { | |
81fb6f15 | 1545 | QXLCookie *cookie = NULL; |
a19cbfb3 | 1546 | QXLRect update = d->ram->update_area; |
81fb6f15 | 1547 | |
ddd8fdc7 | 1548 | if (d->ram->update_surface > d->ssd.num_surfaces) { |
511b13e2 AL |
1549 | qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", |
1550 | d->ram->update_surface); | |
36a03e0b | 1551 | break; |
511b13e2 | 1552 | } |
36a03e0b MT |
1553 | if (update.left >= update.right || update.top >= update.bottom || |
1554 | update.left < 0 || update.top < 0) { | |
511b13e2 AL |
1555 | qxl_set_guest_bug(d, |
1556 | "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", | |
1557 | update.left, update.top, update.right, update.bottom); | |
ccc2960d DH |
1558 | break; |
1559 | } | |
81fb6f15 AL |
1560 | if (async == QXL_ASYNC) { |
1561 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
1562 | QXL_IO_UPDATE_AREA_ASYNC); | |
1563 | cookie->u.area = update; | |
1564 | } | |
aee32bf3 | 1565 | qxl_spice_update_area(d, d->ram->update_surface, |
81fb6f15 AL |
1566 | cookie ? &cookie->u.area : &update, |
1567 | NULL, 0, 0, async, cookie); | |
a19cbfb3 GH |
1568 | break; |
1569 | } | |
1570 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1571 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1572 | break; |
1573 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1574 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1575 | break; |
1576 | case QXL_IO_UPDATE_IRQ: | |
40010aea | 1577 | qxl_update_irq(d); |
a19cbfb3 GH |
1578 | break; |
1579 | case QXL_IO_NOTIFY_OOM: | |
a19cbfb3 GH |
1580 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { |
1581 | break; | |
1582 | } | |
1583 | d->oom_running = 1; | |
aee32bf3 | 1584 | qxl_spice_oom(d); |
a19cbfb3 GH |
1585 | d->oom_running = 0; |
1586 | break; | |
1587 | case QXL_IO_SET_MODE: | |
a19cbfb3 GH |
1588 | qxl_set_mode(d, val, 0); |
1589 | break; | |
1590 | case QXL_IO_LOG: | |
1a1bc085 | 1591 | trace_qxl_io_log(d->id, d->ram->log_buf); |
a19cbfb3 | 1592 | if (d->guestdebug) { |
a680f7e7 | 1593 | fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
6ebebb55 | 1594 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
a19cbfb3 GH |
1595 | } |
1596 | break; | |
1597 | case QXL_IO_RESET: | |
a19cbfb3 GH |
1598 | qxl_hard_reset(d, 0); |
1599 | break; | |
1600 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 | 1601 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1602 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); |
2bce0400 GH |
1603 | break; |
1604 | } | |
1605 | if (d->guest_slots[val].active) { | |
0a530548 AL |
1606 | qxl_set_guest_bug(d, |
1607 | "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
2bce0400 GH |
1608 | break; |
1609 | } | |
a19cbfb3 | 1610 | d->guest_slots[val].slot = d->ram->mem_slot; |
5ff4e36c | 1611 | qxl_add_memslot(d, val, 0, async); |
a19cbfb3 GH |
1612 | break; |
1613 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 | 1614 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1615 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); |
2bce0400 GH |
1616 | break; |
1617 | } | |
a19cbfb3 GH |
1618 | qxl_del_memslot(d, val); |
1619 | break; | |
1620 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 | 1621 | if (val != 0) { |
0a530548 | 1622 | qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1623 | async); |
1624 | goto cancel_async; | |
2bce0400 | 1625 | } |
a19cbfb3 | 1626 | d->guest_primary.surface = d->ram->create_surface; |
5ff4e36c | 1627 | qxl_create_guest_primary(d, 0, async); |
a19cbfb3 GH |
1628 | break; |
1629 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 | 1630 | if (val != 0) { |
0a530548 | 1631 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1632 | async); |
1633 | goto cancel_async; | |
1634 | } | |
5ff4e36c | 1635 | if (!qxl_destroy_primary(d, async)) { |
c480bb7d AL |
1636 | trace_qxl_io_destroy_primary_ignored(d->id, |
1637 | qxl_mode_to_string(d->mode)); | |
5ff4e36c | 1638 | goto cancel_async; |
2bce0400 | 1639 | } |
a19cbfb3 GH |
1640 | break; |
1641 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
ddd8fdc7 | 1642 | if (val >= d->ssd.num_surfaces) { |
0a530548 | 1643 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" |
5f8daf2e | 1644 | "%" PRIu64 " >= NUM_SURFACES", async, val); |
5ff4e36c AL |
1645 | goto cancel_async; |
1646 | } | |
1647 | qxl_spice_destroy_surface_wait(d, val, async); | |
a19cbfb3 | 1648 | break; |
3e16b9c5 AL |
1649 | case QXL_IO_FLUSH_RELEASE: { |
1650 | QXLReleaseRing *ring = &d->ram->release_ring; | |
1651 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
1652 | fprintf(stderr, | |
1653 | "ERROR: no flush, full release ring [p%d,%dc]\n", | |
1654 | ring->prod, ring->cons); | |
1655 | } | |
1656 | qxl_push_free_res(d, 1 /* flush */); | |
3e16b9c5 AL |
1657 | break; |
1658 | } | |
1659 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
3e16b9c5 AL |
1660 | qxl_spice_flush_surfaces_async(d); |
1661 | break; | |
a19cbfb3 | 1662 | case QXL_IO_DESTROY_ALL_SURFACES: |
5ff4e36c AL |
1663 | d->mode = QXL_MODE_UNDEFINED; |
1664 | qxl_spice_destroy_surfaces(d, async); | |
a19cbfb3 | 1665 | break; |
020af1c4 AL |
1666 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
1667 | qxl_spice_monitors_config_async(d, 0); | |
1668 | break; | |
a19cbfb3 | 1669 | default: |
0a530548 | 1670 | qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); |
a19cbfb3 | 1671 | } |
5ff4e36c AL |
1672 | return; |
1673 | cancel_async: | |
5ff4e36c AL |
1674 | if (async) { |
1675 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1676 | qemu_mutex_lock(&d->async_lock); | |
1677 | d->current_async = QXL_UNDEFINED_IO; | |
1678 | qemu_mutex_unlock(&d->async_lock); | |
1679 | } | |
a19cbfb3 GH |
1680 | } |
1681 | ||
a8170e5e | 1682 | static uint64_t ioport_read(void *opaque, hwaddr addr, |
b1950430 | 1683 | unsigned size) |
a19cbfb3 | 1684 | { |
917ae08c | 1685 | PCIQXLDevice *qxl = opaque; |
a19cbfb3 | 1686 | |
917ae08c | 1687 | trace_qxl_io_read_unexpected(qxl->id); |
a19cbfb3 GH |
1688 | return 0xff; |
1689 | } | |
1690 | ||
b1950430 AK |
1691 | static const MemoryRegionOps qxl_io_ops = { |
1692 | .read = ioport_read, | |
1693 | .write = ioport_write, | |
1694 | .valid = { | |
1695 | .min_access_size = 1, | |
1696 | .max_access_size = 1, | |
1697 | }, | |
1698 | }; | |
a19cbfb3 GH |
1699 | |
1700 | static void pipe_read(void *opaque) | |
1701 | { | |
1702 | PCIQXLDevice *d = opaque; | |
1703 | char dummy; | |
1704 | int len; | |
1705 | ||
1706 | do { | |
1707 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1708 | } while (len == sizeof(dummy)); | |
40010aea | 1709 | qxl_update_irq(d); |
a19cbfb3 GH |
1710 | } |
1711 | ||
a19cbfb3 GH |
1712 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1713 | { | |
1714 | uint32_t old_pending; | |
1715 | uint32_t le_events = cpu_to_le32(events); | |
1716 | ||
917ae08c | 1717 | trace_qxl_send_events(d->id, events); |
511aefb0 AL |
1718 | if (!qemu_spice_display_is_running(&d->ssd)) { |
1719 | /* spice-server tracks guest running state and should not do this */ | |
1720 | fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", | |
1721 | __func__); | |
1722 | trace_qxl_send_events_vm_stopped(d->id, events); | |
1723 | return; | |
1724 | } | |
a19cbfb3 GH |
1725 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
1726 | if ((old_pending & le_events) == le_events) { | |
1727 | return; | |
1728 | } | |
691f5c7b | 1729 | if (qemu_thread_is_self(&d->main)) { |
40010aea | 1730 | qxl_update_irq(d); |
a19cbfb3 GH |
1731 | } else { |
1732 | if (write(d->pipe[1], d, 1) != 1) { | |
75fe0d7b | 1733 | dprint(d, 1, "%s: write to pipe failed\n", __func__); |
a19cbfb3 GH |
1734 | } |
1735 | } | |
1736 | } | |
1737 | ||
1738 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1739 | { | |
aa3db423 AL |
1740 | if (pipe(d->pipe) < 0) { |
1741 | fprintf(stderr, "%s:%s: qxl pipe creation failed\n", | |
1742 | __FILE__, __func__); | |
1743 | exit(1); | |
1744 | } | |
1745 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); | |
1746 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); | |
1747 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1748 | ||
1749 | qemu_thread_get_self(&d->main); | |
1750 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); | |
a19cbfb3 GH |
1751 | } |
1752 | ||
1753 | /* graphics console */ | |
1754 | ||
1755 | static void qxl_hw_update(void *opaque) | |
1756 | { | |
1757 | PCIQXLDevice *qxl = opaque; | |
1758 | VGACommonState *vga = &qxl->vga; | |
1759 | ||
1760 | switch (qxl->mode) { | |
1761 | case QXL_MODE_VGA: | |
380cd056 | 1762 | vga->hw_ops->gfx_update(vga); |
a19cbfb3 GH |
1763 | break; |
1764 | case QXL_MODE_COMPAT: | |
1765 | case QXL_MODE_NATIVE: | |
1766 | qxl_render_update(qxl); | |
1767 | break; | |
1768 | default: | |
1769 | break; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | static void qxl_hw_invalidate(void *opaque) | |
1774 | { | |
1775 | PCIQXLDevice *qxl = opaque; | |
1776 | VGACommonState *vga = &qxl->vga; | |
1777 | ||
bfe528b9 GH |
1778 | if (qxl->mode == QXL_MODE_VGA) { |
1779 | vga->hw_ops->invalidate(vga); | |
1780 | return; | |
1781 | } | |
a19cbfb3 GH |
1782 | } |
1783 | ||
a19cbfb3 GH |
1784 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) |
1785 | { | |
1786 | PCIQXLDevice *qxl = opaque; | |
1787 | VGACommonState *vga = &qxl->vga; | |
1788 | ||
1789 | if (qxl->mode == QXL_MODE_VGA) { | |
380cd056 | 1790 | vga->hw_ops->text_update(vga, chardata); |
a19cbfb3 GH |
1791 | return; |
1792 | } | |
1793 | } | |
1794 | ||
e25139b3 YH |
1795 | static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1796 | { | |
c5825ac6 | 1797 | uintptr_t vram_start; |
e25139b3 YH |
1798 | int i; |
1799 | ||
2aa9e85c | 1800 | if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { |
e25139b3 YH |
1801 | return; |
1802 | } | |
1803 | ||
1804 | /* dirty the primary surface */ | |
1805 | qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, | |
1806 | qxl->shadow_rom.surface0_area_size); | |
1807 | ||
c5825ac6 | 1808 | vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); |
e25139b3 YH |
1809 | |
1810 | /* dirty the off-screen surfaces */ | |
ddd8fdc7 | 1811 | for (i = 0; i < qxl->ssd.num_surfaces; i++) { |
e25139b3 YH |
1812 | QXLSurfaceCmd *cmd; |
1813 | intptr_t surface_offset; | |
1814 | int surface_size; | |
1815 | ||
1816 | if (qxl->guest_surfaces.cmds[i] == 0) { | |
1817 | continue; | |
1818 | } | |
1819 | ||
1820 | cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], | |
1821 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1822 | assert(cmd); |
e25139b3 YH |
1823 | assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
1824 | surface_offset = (intptr_t)qxl_phys2virt(qxl, | |
1825 | cmd->u.surface_create.data, | |
1826 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1827 | assert(surface_offset); |
e25139b3 YH |
1828 | surface_offset -= vram_start; |
1829 | surface_size = cmd->u.surface_create.height * | |
1830 | abs(cmd->u.surface_create.stride); | |
c480bb7d | 1831 | trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); |
e25139b3 YH |
1832 | qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
1833 | } | |
1834 | } | |
1835 | ||
1dfb4dd9 LC |
1836 | static void qxl_vm_change_state_handler(void *opaque, int running, |
1837 | RunState state) | |
a19cbfb3 GH |
1838 | { |
1839 | PCIQXLDevice *qxl = opaque; | |
a19cbfb3 | 1840 | |
efbf2950 YH |
1841 | if (running) { |
1842 | /* | |
1843 | * if qxl_send_events was called from spice server context before | |
40010aea | 1844 | * migration ended, qxl_update_irq for these events might not have been |
efbf2950 YH |
1845 | * called |
1846 | */ | |
40010aea | 1847 | qxl_update_irq(qxl); |
e25139b3 YH |
1848 | } else { |
1849 | /* make sure surfaces are saved before migration */ | |
1850 | qxl_dirty_surfaces(qxl); | |
a19cbfb3 GH |
1851 | } |
1852 | } | |
1853 | ||
1854 | /* display change listener */ | |
1855 | ||
7c20b4a3 | 1856 | static void display_update(DisplayChangeListener *dcl, |
7c20b4a3 | 1857 | int x, int y, int w, int h) |
a19cbfb3 | 1858 | { |
c6c06853 GH |
1859 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1860 | ||
1861 | if (qxl->mode == QXL_MODE_VGA) { | |
1862 | qemu_spice_display_update(&qxl->ssd, x, y, w, h); | |
a19cbfb3 GH |
1863 | } |
1864 | } | |
1865 | ||
c12aeb86 | 1866 | static void display_switch(DisplayChangeListener *dcl, |
c12aeb86 | 1867 | struct DisplaySurface *surface) |
a19cbfb3 | 1868 | { |
c6c06853 GH |
1869 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1870 | ||
71874c17 | 1871 | qxl->ssd.ds = surface; |
c6c06853 | 1872 | if (qxl->mode == QXL_MODE_VGA) { |
c12aeb86 | 1873 | qemu_spice_display_switch(&qxl->ssd, surface); |
a19cbfb3 GH |
1874 | } |
1875 | } | |
1876 | ||
bc2ed970 | 1877 | static void display_refresh(DisplayChangeListener *dcl) |
a19cbfb3 | 1878 | { |
c6c06853 GH |
1879 | PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); |
1880 | ||
1881 | if (qxl->mode == QXL_MODE_VGA) { | |
1882 | qemu_spice_display_refresh(&qxl->ssd); | |
bb5a8cd5 | 1883 | } else { |
c6c06853 GH |
1884 | qemu_mutex_lock(&qxl->ssd.lock); |
1885 | qemu_spice_cursor_refresh_unlocked(&qxl->ssd); | |
1886 | qemu_mutex_unlock(&qxl->ssd.lock); | |
a19cbfb3 GH |
1887 | } |
1888 | } | |
1889 | ||
7c20b4a3 GH |
1890 | static DisplayChangeListenerOps display_listener_ops = { |
1891 | .dpy_name = "spice/qxl", | |
a93a4a22 | 1892 | .dpy_gfx_update = display_update, |
c12aeb86 | 1893 | .dpy_gfx_switch = display_switch, |
7c20b4a3 | 1894 | .dpy_refresh = display_refresh, |
a19cbfb3 GH |
1895 | }; |
1896 | ||
13d1fd44 | 1897 | static void qxl_init_ramsize(PCIQXLDevice *qxl) |
a974192c | 1898 | { |
13d1fd44 AL |
1899 | /* vga mode framebuffer / primary surface (bar 0, first part) */ |
1900 | if (qxl->vgamem_size_mb < 8) { | |
1901 | qxl->vgamem_size_mb = 8; | |
1902 | } | |
1903 | qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; | |
1904 | ||
1905 | /* vga ram (bar 0, total) */ | |
017438ee GH |
1906 | if (qxl->ram_size_mb != -1) { |
1907 | qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; | |
1908 | } | |
13d1fd44 AL |
1909 | if (qxl->vga.vram_size < qxl->vgamem_size * 2) { |
1910 | qxl->vga.vram_size = qxl->vgamem_size * 2; | |
a974192c GH |
1911 | } |
1912 | ||
6f2b175a GH |
1913 | /* vram32 (surfaces, 32bit, bar 1) */ |
1914 | if (qxl->vram32_size_mb != -1) { | |
1915 | qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; | |
1916 | } | |
1917 | if (qxl->vram32_size < 4096) { | |
1918 | qxl->vram32_size = 4096; | |
1919 | } | |
1920 | ||
1921 | /* vram (surfaces, 64bit, bar 4+5) */ | |
017438ee GH |
1922 | if (qxl->vram_size_mb != -1) { |
1923 | qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; | |
1924 | } | |
6f2b175a GH |
1925 | if (qxl->vram_size < qxl->vram32_size) { |
1926 | qxl->vram_size = qxl->vram32_size; | |
a974192c | 1927 | } |
6f2b175a | 1928 | |
a974192c | 1929 | if (qxl->revision == 1) { |
6f2b175a | 1930 | qxl->vram32_size = 4096; |
a974192c GH |
1931 | qxl->vram_size = 4096; |
1932 | } | |
13d1fd44 | 1933 | qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); |
a974192c | 1934 | qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
6f2b175a | 1935 | qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
a974192c GH |
1936 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1937 | } | |
1938 | ||
a19cbfb3 GH |
1939 | static int qxl_init_common(PCIQXLDevice *qxl) |
1940 | { | |
1941 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1942 | uint32_t pci_device_rev; |
1943 | uint32_t io_size; | |
1944 | ||
1945 | qxl->mode = QXL_MODE_UNDEFINED; | |
1946 | qxl->generation = 1; | |
1947 | qxl->num_memslots = NUM_MEMSLOTS; | |
14898cf6 | 1948 | qemu_mutex_init(&qxl->track_lock); |
5ff4e36c AL |
1949 | qemu_mutex_init(&qxl->async_lock); |
1950 | qxl->current_async = QXL_UNDEFINED_IO; | |
087e6a42 | 1951 | qxl->guest_bug = 0; |
a19cbfb3 GH |
1952 | |
1953 | switch (qxl->revision) { | |
1954 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 | 1955 | pci_device_rev = QXL_REVISION_STABLE_V04; |
3f6297b9 | 1956 | io_size = 8; |
a19cbfb3 GH |
1957 | break; |
1958 | case 2: /* spice 0.6 -- qxl-2 */ | |
a19cbfb3 | 1959 | pci_device_rev = QXL_REVISION_STABLE_V06; |
3f6297b9 | 1960 | io_size = 16; |
a19cbfb3 | 1961 | break; |
9197a7c8 | 1962 | case 3: /* qxl-3 */ |
020af1c4 AL |
1963 | pci_device_rev = QXL_REVISION_STABLE_V10; |
1964 | io_size = 32; /* PCI region size must be pow2 */ | |
1965 | break; | |
020af1c4 AL |
1966 | case 4: /* qxl-4 */ |
1967 | pci_device_rev = QXL_REVISION_STABLE_V12; | |
3f6297b9 | 1968 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
9197a7c8 | 1969 | break; |
36839d35 AL |
1970 | default: |
1971 | error_report("Invalid revision %d for qxl device (max %d)", | |
1972 | qxl->revision, QXL_DEFAULT_REVISION); | |
1973 | return -1; | |
a19cbfb3 GH |
1974 | } |
1975 | ||
a19cbfb3 GH |
1976 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1977 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1978 | ||
1979 | qxl->rom_size = qxl_rom_size(); | |
c5705a77 AK |
1980 | memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); |
1981 | vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1982 | init_qxl_rom(qxl); |
1983 | init_qxl_ram(qxl); | |
1984 | ||
ddd8fdc7 | 1985 | qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); |
c5705a77 AK |
1986 | memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); |
1987 | vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); | |
6f2b175a GH |
1988 | memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, |
1989 | 0, qxl->vram32_size); | |
a19cbfb3 | 1990 | |
b1950430 AK |
1991 | memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
1992 | "qxl-ioports", io_size); | |
1993 | if (qxl->id == 0) { | |
1994 | vga_dirty_log_start(&qxl->vga); | |
1995 | } | |
bd8f2f5d | 1996 | memory_region_set_flush_coalesced(&qxl->io_bar); |
b1950430 AK |
1997 | |
1998 | ||
e824b2cc AK |
1999 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
2000 | PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); | |
a19cbfb3 | 2001 | |
e824b2cc AK |
2002 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
2003 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); | |
a19cbfb3 | 2004 | |
e824b2cc AK |
2005 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
2006 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); | |
a19cbfb3 | 2007 | |
e824b2cc | 2008 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
6f2b175a GH |
2009 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
2010 | ||
2011 | if (qxl->vram32_size < qxl->vram_size) { | |
2012 | /* | |
2013 | * Make the 64bit vram bar show up only in case it is | |
2014 | * configured to be larger than the 32bit vram bar. | |
2015 | */ | |
2016 | pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, | |
2017 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
2018 | PCI_BASE_ADDRESS_MEM_TYPE_64 | | |
2019 | PCI_BASE_ADDRESS_MEM_PREFETCH, | |
2020 | &qxl->vram_bar); | |
2021 | } | |
2022 | ||
2023 | /* print pci bar details */ | |
2024 | dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", | |
2025 | qxl->id == 0 ? "pri" : "sec", | |
2026 | qxl->vga.vram_size / (1024*1024)); | |
2027 | dprint(qxl, 1, "vram/32: %d MB [region 1]\n", | |
2028 | qxl->vram32_size / (1024*1024)); | |
2029 | dprint(qxl, 1, "vram/64: %d MB %s\n", | |
2030 | qxl->vram_size / (1024*1024), | |
2031 | qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); | |
a19cbfb3 GH |
2032 | |
2033 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
2034 | qxl->ssd.qxl.id = qxl->id; | |
e25a0651 | 2035 | if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) { |
312fd5f2 | 2036 | error_report("qxl interface %d.%d not supported by spice-server", |
e25a0651 AL |
2037 | SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); |
2038 | return -1; | |
2039 | } | |
a19cbfb3 GH |
2040 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
2041 | ||
2042 | init_pipe_signaling(qxl); | |
2043 | qxl_reset_state(qxl); | |
2044 | ||
81fb6f15 AL |
2045 | qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
2046 | ||
a19cbfb3 GH |
2047 | return 0; |
2048 | } | |
2049 | ||
380cd056 GH |
2050 | static const GraphicHwOps qxl_ops = { |
2051 | .invalidate = qxl_hw_invalidate, | |
2052 | .gfx_update = qxl_hw_update, | |
2053 | .text_update = qxl_hw_text_update, | |
2054 | }; | |
2055 | ||
a19cbfb3 GH |
2056 | static int qxl_init_primary(PCIDevice *dev) |
2057 | { | |
2058 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
2059 | VGACommonState *vga = &qxl->vga; | |
f67ab77a | 2060 | PortioList *qxl_vga_port_list = g_new(PortioList, 1); |
bdd4df33 | 2061 | int rc; |
a19cbfb3 GH |
2062 | |
2063 | qxl->id = 0; | |
13d1fd44 | 2064 | qxl_init_ramsize(qxl); |
4a1e244e GH |
2065 | vga->vram_size_mb = qxl->vga.vram_size >> 20; |
2066 | vga_common_init(vga); | |
0a039dc7 | 2067 | vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); |
f67ab77a GH |
2068 | portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); |
2069 | portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); | |
a19cbfb3 | 2070 | |
aa2beaa1 | 2071 | vga->con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl); |
c78f7137 | 2072 | qemu_spice_display_init_common(&qxl->ssd); |
a19cbfb3 | 2073 | |
bdd4df33 GH |
2074 | rc = qxl_init_common(qxl); |
2075 | if (rc != 0) { | |
2076 | return rc; | |
2077 | } | |
2078 | ||
7c20b4a3 | 2079 | qxl->ssd.dcl.ops = &display_listener_ops; |
284d1c6b | 2080 | qxl->ssd.dcl.con = vga->con; |
5209089f | 2081 | register_displaychangelistener(&qxl->ssd.dcl); |
bdd4df33 | 2082 | return rc; |
a19cbfb3 GH |
2083 | } |
2084 | ||
2085 | static int qxl_init_secondary(PCIDevice *dev) | |
2086 | { | |
2087 | static int device_id = 1; | |
2088 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
a19cbfb3 GH |
2089 | |
2090 | qxl->id = device_id++; | |
13d1fd44 | 2091 | qxl_init_ramsize(qxl); |
c5705a77 AK |
2092 | memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); |
2093 | vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); | |
b1950430 | 2094 | qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
aa2beaa1 | 2095 | qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl); |
a19cbfb3 | 2096 | |
a19cbfb3 GH |
2097 | return qxl_init_common(qxl); |
2098 | } | |
2099 | ||
2100 | static void qxl_pre_save(void *opaque) | |
2101 | { | |
2102 | PCIQXLDevice* d = opaque; | |
2103 | uint8_t *ram_start = d->vga.vram_ptr; | |
2104 | ||
c480bb7d | 2105 | trace_qxl_pre_save(d->id); |
a19cbfb3 GH |
2106 | if (d->last_release == NULL) { |
2107 | d->last_release_offset = 0; | |
2108 | } else { | |
2109 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
2110 | } | |
2111 | assert(d->last_release_offset < d->vga.vram_size); | |
2112 | } | |
2113 | ||
2114 | static int qxl_pre_load(void *opaque) | |
2115 | { | |
2116 | PCIQXLDevice* d = opaque; | |
2117 | ||
c480bb7d | 2118 | trace_qxl_pre_load(d->id); |
a19cbfb3 GH |
2119 | qxl_hard_reset(d, 1); |
2120 | qxl_exit_vga_mode(d); | |
a19cbfb3 GH |
2121 | return 0; |
2122 | } | |
2123 | ||
54825d2e AL |
2124 | static void qxl_create_memslots(PCIQXLDevice *d) |
2125 | { | |
2126 | int i; | |
2127 | ||
2128 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
2129 | if (!d->guest_slots[i].active) { | |
2130 | continue; | |
2131 | } | |
54825d2e AL |
2132 | qxl_add_memslot(d, i, 0, QXL_SYNC); |
2133 | } | |
2134 | } | |
2135 | ||
a19cbfb3 GH |
2136 | static int qxl_post_load(void *opaque, int version) |
2137 | { | |
2138 | PCIQXLDevice* d = opaque; | |
2139 | uint8_t *ram_start = d->vga.vram_ptr; | |
2140 | QXLCommandExt *cmds; | |
54825d2e | 2141 | int in, out, newmode; |
a19cbfb3 | 2142 | |
a19cbfb3 GH |
2143 | assert(d->last_release_offset < d->vga.vram_size); |
2144 | if (d->last_release_offset == 0) { | |
2145 | d->last_release = NULL; | |
2146 | } else { | |
2147 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
2148 | } | |
2149 | ||
2150 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
2151 | ||
c480bb7d | 2152 | trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); |
a19cbfb3 GH |
2153 | newmode = d->mode; |
2154 | d->mode = QXL_MODE_UNDEFINED; | |
54825d2e | 2155 | |
a19cbfb3 GH |
2156 | switch (newmode) { |
2157 | case QXL_MODE_UNDEFINED: | |
fa98efe9 | 2158 | qxl_create_memslots(d); |
a19cbfb3 GH |
2159 | break; |
2160 | case QXL_MODE_VGA: | |
54825d2e | 2161 | qxl_create_memslots(d); |
a19cbfb3 GH |
2162 | qxl_enter_vga_mode(d); |
2163 | break; | |
2164 | case QXL_MODE_NATIVE: | |
54825d2e | 2165 | qxl_create_memslots(d); |
5ff4e36c | 2166 | qxl_create_guest_primary(d, 1, QXL_SYNC); |
a19cbfb3 GH |
2167 | |
2168 | /* replay surface-create and cursor-set commands */ | |
ddd8fdc7 GH |
2169 | cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); |
2170 | for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { | |
a19cbfb3 GH |
2171 | if (d->guest_surfaces.cmds[in] == 0) { |
2172 | continue; | |
2173 | } | |
2174 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
2175 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
2176 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2177 | out++; | |
2178 | } | |
30f6da66 YH |
2179 | if (d->guest_cursor) { |
2180 | cmds[out].cmd.data = d->guest_cursor; | |
2181 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
2182 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2183 | out++; | |
2184 | } | |
aee32bf3 | 2185 | qxl_spice_loadvm_commands(d, cmds, out); |
7267c094 | 2186 | g_free(cmds); |
020af1c4 AL |
2187 | if (d->guest_monitors_config) { |
2188 | qxl_spice_monitors_config_async(d, 1); | |
2189 | } | |
a19cbfb3 GH |
2190 | break; |
2191 | case QXL_MODE_COMPAT: | |
54825d2e AL |
2192 | /* note: no need to call qxl_create_memslots, qxl_set_mode |
2193 | * creates the mem slot. */ | |
a19cbfb3 GH |
2194 | qxl_set_mode(d, d->shadow_rom.mode, 1); |
2195 | break; | |
2196 | } | |
a19cbfb3 GH |
2197 | return 0; |
2198 | } | |
2199 | ||
b67737a6 | 2200 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 | 2201 | |
020af1c4 AL |
2202 | static bool qxl_monitors_config_needed(void *opaque) |
2203 | { | |
2204 | PCIQXLDevice *qxl = opaque; | |
2205 | ||
2206 | return qxl->guest_monitors_config != 0; | |
2207 | } | |
2208 | ||
2209 | ||
a19cbfb3 GH |
2210 | static VMStateDescription qxl_memslot = { |
2211 | .name = "qxl-memslot", | |
2212 | .version_id = QXL_SAVE_VERSION, | |
2213 | .minimum_version_id = QXL_SAVE_VERSION, | |
2214 | .fields = (VMStateField[]) { | |
2215 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
2216 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
2217 | VMSTATE_UINT32(active, struct guest_slots), | |
2218 | VMSTATE_END_OF_LIST() | |
2219 | } | |
2220 | }; | |
2221 | ||
2222 | static VMStateDescription qxl_surface = { | |
2223 | .name = "qxl-surface", | |
2224 | .version_id = QXL_SAVE_VERSION, | |
2225 | .minimum_version_id = QXL_SAVE_VERSION, | |
2226 | .fields = (VMStateField[]) { | |
2227 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
2228 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
2229 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
2230 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
2231 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
2232 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
2233 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
2234 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
2235 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
2236 | VMSTATE_END_OF_LIST() | |
2237 | } | |
2238 | }; | |
2239 | ||
020af1c4 AL |
2240 | static VMStateDescription qxl_vmstate_monitors_config = { |
2241 | .name = "qxl/monitors-config", | |
2242 | .version_id = 1, | |
2243 | .minimum_version_id = 1, | |
2244 | .fields = (VMStateField[]) { | |
2245 | VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), | |
2246 | VMSTATE_END_OF_LIST() | |
2247 | }, | |
2248 | }; | |
2249 | ||
a19cbfb3 GH |
2250 | static VMStateDescription qxl_vmstate = { |
2251 | .name = "qxl", | |
2252 | .version_id = QXL_SAVE_VERSION, | |
2253 | .minimum_version_id = QXL_SAVE_VERSION, | |
2254 | .pre_save = qxl_pre_save, | |
2255 | .pre_load = qxl_pre_load, | |
2256 | .post_load = qxl_post_load, | |
020af1c4 | 2257 | .fields = (VMStateField[]) { |
a19cbfb3 GH |
2258 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
2259 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
2260 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
2261 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
2262 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
2263 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
2264 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
2265 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
2266 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
2267 | qxl_memslot, struct guest_slots), | |
2268 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
2269 | qxl_surface, QXLSurfaceCreate), | |
ddd8fdc7 GH |
2270 | VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), |
2271 | VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, | |
2272 | ssd.num_surfaces, 0, | |
2273 | vmstate_info_uint64, uint64_t), | |
b67737a6 | 2274 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
a19cbfb3 GH |
2275 | VMSTATE_END_OF_LIST() |
2276 | }, | |
020af1c4 AL |
2277 | .subsections = (VMStateSubsection[]) { |
2278 | { | |
2279 | .vmsd = &qxl_vmstate_monitors_config, | |
2280 | .needed = qxl_monitors_config_needed, | |
2281 | }, { | |
2282 | /* empty */ | |
2283 | } | |
2284 | } | |
a19cbfb3 GH |
2285 | }; |
2286 | ||
78e60ba5 GH |
2287 | static Property qxl_properties[] = { |
2288 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, | |
2289 | 64 * 1024 * 1024), | |
6f2b175a | 2290 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, |
78e60ba5 GH |
2291 | 64 * 1024 * 1024), |
2292 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, | |
2293 | QXL_DEFAULT_REVISION), | |
2294 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
2295 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
2296 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
017438ee | 2297 | DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
79ce3567 AL |
2298 | DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), |
2299 | DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), | |
9e56edcf | 2300 | DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), |
ddd8fdc7 | 2301 | DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), |
78e60ba5 GH |
2302 | DEFINE_PROP_END_OF_LIST(), |
2303 | }; | |
2304 | ||
40021f08 AL |
2305 | static void qxl_primary_class_init(ObjectClass *klass, void *data) |
2306 | { | |
39bffca2 | 2307 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2308 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2309 | ||
2310 | k->no_hotplug = 1; | |
2311 | k->init = qxl_init_primary; | |
2312 | k->romfile = "vgabios-qxl.bin"; | |
2313 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2314 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2315 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
39bffca2 AL |
2316 | dc->desc = "Spice QXL GPU (primary, vga compatible)"; |
2317 | dc->reset = qxl_reset_handler; | |
2318 | dc->vmsd = &qxl_vmstate; | |
2319 | dc->props = qxl_properties; | |
40021f08 AL |
2320 | } |
2321 | ||
8c43a6f0 | 2322 | static const TypeInfo qxl_primary_info = { |
39bffca2 AL |
2323 | .name = "qxl-vga", |
2324 | .parent = TYPE_PCI_DEVICE, | |
2325 | .instance_size = sizeof(PCIQXLDevice), | |
2326 | .class_init = qxl_primary_class_init, | |
a19cbfb3 GH |
2327 | }; |
2328 | ||
40021f08 AL |
2329 | static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
2330 | { | |
39bffca2 | 2331 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2332 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2333 | ||
2334 | k->init = qxl_init_secondary; | |
2335 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2336 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2337 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
39bffca2 AL |
2338 | dc->desc = "Spice QXL GPU (secondary)"; |
2339 | dc->reset = qxl_reset_handler; | |
2340 | dc->vmsd = &qxl_vmstate; | |
2341 | dc->props = qxl_properties; | |
40021f08 AL |
2342 | } |
2343 | ||
8c43a6f0 | 2344 | static const TypeInfo qxl_secondary_info = { |
39bffca2 AL |
2345 | .name = "qxl", |
2346 | .parent = TYPE_PCI_DEVICE, | |
2347 | .instance_size = sizeof(PCIQXLDevice), | |
2348 | .class_init = qxl_secondary_class_init, | |
a19cbfb3 GH |
2349 | }; |
2350 | ||
83f7d43a | 2351 | static void qxl_register_types(void) |
a19cbfb3 | 2352 | { |
39bffca2 AL |
2353 | type_register_static(&qxl_primary_info); |
2354 | type_register_static(&qxl_secondary_info); | |
a19cbfb3 GH |
2355 | } |
2356 | ||
83f7d43a | 2357 | type_init(qxl_register_types) |