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Commit | Line | Data |
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cb9c377f | 1 | #ifndef HW_QXL_H |
175de524 | 2 | #define HW_QXL_H |
cb9c377f | 3 | |
edf5ca5d | 4 | #include "hw/pci/pci_device.h" |
47b43a1f | 5 | #include "vga_int.h" |
1de7afc9 | 6 | #include "qemu/thread.h" |
a19cbfb3 GH |
7 | |
8 | #include "ui/qemu-spice.h" | |
9 | #include "ui/spice-display.h" | |
db1015e9 | 10 | #include "qom/object.h" |
a19cbfb3 GH |
11 | |
12 | enum qxl_mode { | |
13 | QXL_MODE_UNDEFINED, | |
14 | QXL_MODE_VGA, | |
15 | QXL_MODE_COMPAT, /* spice 0.4.x */ | |
16 | QXL_MODE_NATIVE, | |
17 | }; | |
18 | ||
6f2b175a GH |
19 | #ifndef QXL_VRAM64_RANGE_INDEX |
20 | #define QXL_VRAM64_RANGE_INDEX 4 | |
21 | #endif | |
22 | ||
5ff4e36c AL |
23 | #define QXL_UNDEFINED_IO UINT32_MAX |
24 | ||
81fb6f15 AL |
25 | #define QXL_NUM_DIRTY_RECTS 64 |
26 | ||
9efc2d8d GH |
27 | #define QXL_PAGE_BITS 12 |
28 | #define QXL_PAGE_SIZE (1 << QXL_PAGE_BITS); | |
29 | ||
db1015e9 | 30 | struct PCIQXLDevice { |
a19cbfb3 | 31 | PCIDevice pci; |
848696bf | 32 | PortioList vga_port_list; |
a19cbfb3 GH |
33 | SimpleSpiceDisplay ssd; |
34 | int id; | |
60e94e43 | 35 | bool have_vga; |
a19cbfb3 GH |
36 | uint32_t debug; |
37 | uint32_t guestdebug; | |
38 | uint32_t cmdlog; | |
087e6a42 AL |
39 | |
40 | uint32_t guest_bug; | |
41 | ||
a19cbfb3 GH |
42 | enum qxl_mode mode; |
43 | uint32_t cmdflags; | |
a19cbfb3 GH |
44 | uint32_t revision; |
45 | ||
46 | int32_t num_memslots; | |
a19cbfb3 | 47 | |
5ff4e36c AL |
48 | uint32_t current_async; |
49 | QemuMutex async_lock; | |
50 | ||
a19cbfb3 GH |
51 | struct guest_slots { |
52 | QXLMemSlot slot; | |
3cb5158f GH |
53 | MemoryRegion *mr; |
54 | uint64_t offset; | |
a19cbfb3 GH |
55 | uint64_t size; |
56 | uint64_t delta; | |
57 | uint32_t active; | |
58 | } guest_slots[NUM_MEMSLOTS]; | |
59 | ||
60 | struct guest_primary { | |
61 | QXLSurfaceCreate surface; | |
62 | uint32_t commands; | |
63 | uint32_t resized; | |
0e2487bd GH |
64 | int32_t qxl_stride; |
65 | uint32_t abs_stride; | |
a19cbfb3 GH |
66 | uint32_t bits_pp; |
67 | uint32_t bytes_pp; | |
4c19ebb5 | 68 | uint8_t *data; |
a19cbfb3 GH |
69 | } guest_primary; |
70 | ||
71 | struct surfaces { | |
ddd8fdc7 | 72 | QXLPHYSICAL *cmds; |
a19cbfb3 GH |
73 | uint32_t count; |
74 | uint32_t max; | |
75 | } guest_surfaces; | |
76 | QXLPHYSICAL guest_cursor; | |
77 | ||
020af1c4 | 78 | QXLPHYSICAL guest_monitors_config; |
979f7ef8 GH |
79 | uint32_t guest_head0_width; |
80 | uint32_t guest_head0_height; | |
020af1c4 | 81 | |
14898cf6 GH |
82 | QemuMutex track_lock; |
83 | ||
a19cbfb3 | 84 | /* thread signaling */ |
4a46c99c | 85 | QEMUBH *update_irq; |
a19cbfb3 GH |
86 | |
87 | /* ram pci bar */ | |
88 | QXLRam *ram; | |
89 | VGACommonState vga; | |
90 | uint32_t num_free_res; | |
91 | QXLReleaseInfo *last_release; | |
92 | uint32_t last_release_offset; | |
93 | uint32_t oom_running; | |
13d1fd44 | 94 | uint32_t vgamem_size; |
a19cbfb3 GH |
95 | |
96 | /* rom pci bar */ | |
97 | QXLRom shadow_rom; | |
98 | QXLRom *rom; | |
99 | QXLModes *modes; | |
100 | uint32_t rom_size; | |
b1950430 | 101 | MemoryRegion rom_bar; |
567161fd | 102 | uint16_t max_outputs; |
a19cbfb3 GH |
103 | |
104 | /* vram pci bar */ | |
de1b9b85 | 105 | uint64_t vram_size; |
b1950430 | 106 | MemoryRegion vram_bar; |
de1b9b85 | 107 | uint64_t vram32_size; |
6f2b175a | 108 | MemoryRegion vram32_bar; |
a19cbfb3 GH |
109 | |
110 | /* io bar */ | |
b1950430 | 111 | MemoryRegion io_bar; |
017438ee GH |
112 | |
113 | /* user-friendly properties (in megabytes) */ | |
114 | uint32_t ram_size_mb; | |
115 | uint32_t vram_size_mb; | |
6f2b175a | 116 | uint32_t vram32_size_mb; |
13d1fd44 | 117 | uint32_t vgamem_size_mb; |
6f663d7b GH |
118 | uint32_t xres; |
119 | uint32_t yres; | |
81fb6f15 AL |
120 | |
121 | /* qxl_render_update state */ | |
122 | int render_update_cookie_num; | |
123 | int num_dirty_rects; | |
124 | QXLRect dirty[QXL_NUM_DIRTY_RECTS]; | |
125 | QEMUBH *update_area_bh; | |
db1015e9 | 126 | }; |
a19cbfb3 | 127 | |
c69f6c7d | 128 | #define TYPE_PCI_QXL "pci-qxl" |
8063396b | 129 | OBJECT_DECLARE_SIMPLE_TYPE(PCIQXLDevice, PCI_QXL) |
c69f6c7d | 130 | |
a19cbfb3 | 131 | #define PANIC_ON(x) if ((x)) { \ |
a89f364a | 132 | printf("%s: PANIC %s failed\n", __func__, #x); \ |
2bce0400 | 133 | abort(); \ |
a19cbfb3 GH |
134 | } |
135 | ||
136 | #define dprint(_qxl, _level, _fmt, ...) \ | |
137 | do { \ | |
138 | if (_qxl->debug >= _level) { \ | |
139 | fprintf(stderr, "qxl-%d: ", _qxl->id); \ | |
140 | fprintf(stderr, _fmt, ## __VA_ARGS__); \ | |
141 | } \ | |
142 | } while (0) | |
143 | ||
ed71c09f | 144 | #define QXL_DEFAULT_REVISION (QXL_REVISION_STABLE_V12 + 1) |
9197a7c8 | 145 | |
a19cbfb3 | 146 | /* qxl.c */ |
b1901de8 PMD |
147 | /** |
148 | * qxl_phys2virt: Get a pointer within a PCI VRAM memory region. | |
149 | * | |
150 | * @qxl: QXL device | |
151 | * @phys: physical offset of buffer within the VRAM | |
152 | * @group_id: memory slot group | |
8efec0ef | 153 | * @size: size of the buffer |
b1901de8 PMD |
154 | * |
155 | * Returns a host pointer to a buffer placed at offset @phys within the | |
156 | * active slot @group_id of the PCI VGA RAM memory region associated with | |
6dbbf055 | 157 | * the @qxl device. If the slot is inactive, or the offset + size are out |
b1901de8 PMD |
158 | * of the memory region, returns NULL. |
159 | * | |
160 | * Use with care; by the time this function returns, the returned pointer is | |
161 | * not protected by RCU anymore. If the caller is not within an RCU critical | |
a4a411fb | 162 | * section and does not hold the BQL, it must have other means of |
b1901de8 PMD |
163 | * protecting the pointer, such as a reference to the region that includes |
164 | * the incoming ram_addr_t. | |
165 | * | |
166 | */ | |
8efec0ef PMD |
167 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id, |
168 | size_t size); | |
0a530548 | 169 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
9edc6313 | 170 | G_GNUC_PRINTF(2, 3); |
a19cbfb3 | 171 | |
aee32bf3 GH |
172 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, |
173 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
174 | uint32_t num_dirty_rects, | |
5ff4e36c | 175 | uint32_t clear_dirty_region, |
2e1a98c9 | 176 | qxl_async_io async, QXLCookie *cookie); |
aee32bf3 GH |
177 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
178 | uint32_t count); | |
179 | void qxl_spice_oom(PCIQXLDevice *qxl); | |
180 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl); | |
aee32bf3 GH |
181 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl); |
182 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl); | |
183 | ||
a19cbfb3 | 184 | /* qxl-logger.c */ |
fae2afb1 AL |
185 | int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id); |
186 | int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext); | |
a19cbfb3 GH |
187 | |
188 | /* qxl-render.c */ | |
189 | void qxl_render_resize(PCIQXLDevice *qxl); | |
190 | void qxl_render_update(PCIQXLDevice *qxl); | |
fae2afb1 | 191 | int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext); |
81fb6f15 AL |
192 | void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie); |
193 | void qxl_render_update_area_bh(void *opaque); | |
cb9c377f PB |
194 | |
195 | #endif |