[mirror_qemu.git] / hw / display / tc6393xb.c

/*
 * Toshiba TC6393XB I/O Controller.
 * Found in Sharp Zaurus SL-6000 (tosa) or some
 * Toshiba e-Series PDAs.
 *
 * Most features are currently unsupported!!!
 *
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/host-utils.h"
#include "hw/hw.h"
#include "hw/devices.h"
#include "hw/block/flash.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
#include "sysemu/blockdev.h"

#define IRQ_TC6393_NAND		0
#define IRQ_TC6393_MMC		1
#define IRQ_TC6393_OHCI		2
#define IRQ_TC6393_SERIAL	3
#define IRQ_TC6393_FB		4

#define	TC6393XB_NR_IRQS	8

#define TC6393XB_GPIOS  16

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_ISR		0x50		/* b Interrupt Status	*/
#define SCR_IMR		0x52		/* b Interrupt Mask	*/
#define SCR_IRR		0x54		/* b Interrupt Routing	*/
#define SCR_GPER	0x60		/* w GP Enable		*/
#define SCR_GPI_SR(i)	(0x64 + (i))	/* b3 GPI Status	*/
#define SCR_GPI_IMR(i)	(0x68 + (i))	/* b3 GPI INT Mask	*/
#define SCR_GPI_EDER(i)	(0x6c + (i))	/* b3 GPI Edge Detect Enable */
#define SCR_GPI_LIR(i)	(0x70 + (i))	/* b3 GPI Level Invert	*/
#define SCR_GPO_DSR(i)	(0x78 + (i))	/* b3 GPO Data Set	*/
#define SCR_GPO_DOECR(i) (0x7c + (i))	/* b3 GPO Data OE Control */
#define SCR_GP_IARCR(i)	(0x80 + (i))	/* b3 GP Internal Active Register Control */
#define SCR_GP_IARLCR(i) (0x84 + (i))	/* b3 GP INTERNAL Active Register Level Control */
#define SCR_GPI_BCR(i)	(0x88 + (i))	/* b3 GPI Buffer Control */
#define SCR_GPA_IARCR	0x8c		/* w GPa Internal Active Register Control */
#define SCR_GPA_IARLCR	0x90		/* w GPa Internal Active Register Level Control */
#define SCR_GPA_BCR	0x94		/* w GPa Buffer Control */
#define SCR_CCR		0x98		/* w Clock Control	*/
#define SCR_PLL2CR	0x9a		/* w PLL2 Control	*/
#define SCR_PLL1CR	0x9c		/* l PLL1 Control	*/
#define SCR_DIARCR	0xa0		/* b Device Internal Active Register Control */
#define SCR_DBOCR	0xa1		/* b Device Buffer Off Control */
#define SCR_FER		0xe0		/* b Function Enable	*/
#define SCR_MCR		0xe4		/* w Mode Control	*/
#define SCR_CONFIG	0xfc		/* b Configuration Control */
#define SCR_DEBUG	0xff		/* b Debug		*/

#define NAND_CFG_COMMAND    0x04    /* w Command        */
#define NAND_CFG_BASE       0x10    /* l Control Base Address */
#define NAND_CFG_INTP       0x3d    /* b Interrupt Pin  */
#define NAND_CFG_INTE       0x48    /* b Int Enable     */
#define NAND_CFG_EC         0x4a    /* b Event Control  */
#define NAND_CFG_ICC        0x4c    /* b Internal Clock Control */
#define NAND_CFG_ECCC       0x5b    /* b ECC Control    */
#define NAND_CFG_NFTC       0x60    /* b NAND Flash Transaction Control */
#define NAND_CFG_NFM        0x61    /* b NAND Flash Monitor */
#define NAND_CFG_NFPSC      0x62    /* b NAND Flash Power Supply Control */
#define NAND_CFG_NFDC       0x63    /* b NAND Flash Detect Control */

#define NAND_DATA   0x00        /* l Data       */
#define NAND_MODE   0x04        /* b Mode       */
#define NAND_STATUS 0x05        /* b Status     */
#define NAND_ISR    0x06        /* b Interrupt Status */
#define NAND_IMR    0x07        /* b Interrupt Mask */

#define NAND_MODE_WP        0x80
#define NAND_MODE_CE        0x10
#define NAND_MODE_ALE       0x02
#define NAND_MODE_CLE       0x01
#define NAND_MODE_ECC_MASK  0x60
#define NAND_MODE_ECC_EN    0x20
#define NAND_MODE_ECC_READ  0x40
#define NAND_MODE_ECC_RST   0x60

struct TC6393xbState {
    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq *sub_irqs;
    struct {
        uint8_t ISR;
        uint8_t IMR;
        uint8_t IRR;
        uint16_t GPER;
        uint8_t GPI_SR[3];
        uint8_t GPI_IMR[3];
        uint8_t GPI_EDER[3];
        uint8_t GPI_LIR[3];
        uint8_t GP_IARCR[3];
        uint8_t GP_IARLCR[3];
        uint8_t GPI_BCR[3];
        uint16_t GPA_IARCR;
        uint16_t GPA_IARLCR;
        uint16_t CCR;
        uint16_t PLL2CR;
        uint32_t PLL1CR;
        uint8_t DIARCR;
        uint8_t DBOCR;
        uint8_t FER;
        uint16_t MCR;
        uint8_t CONFIG;
        uint8_t DEBUG;
    } scr;
    uint32_t gpio_dir;
    uint32_t gpio_level;
    uint32_t prev_level;
    qemu_irq handler[TC6393XB_GPIOS];
    qemu_irq *gpio_in;

    struct {
        uint8_t mode;
        uint8_t isr;
        uint8_t imr;
    } nand;
    int nand_enable;
    uint32_t nand_phys;
    DeviceState *flash;
    ECCState ecc;

    QemuConsole *con;
    MemoryRegion vram;
    uint16_t *vram_ptr;
    uint32_t scr_width, scr_height; /* in pixels */
    qemu_irq l3v;
    unsigned blank : 1,
             blanked : 1;
};

qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
{
    return s->gpio_in;
}

static void tc6393xb_gpio_set(void *opaque, int line, int level)
{
//    TC6393xbState *s = opaque;

    if (line > TC6393XB_GPIOS) {
        printf("%s: No GPIO pin %i\n", __func__, line);
        return;
    }

    // FIXME: how does the chip reflect the GPIO input level change?
}

void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
                    qemu_irq handler)
{
    if (line >= TC6393XB_GPIOS) {
        fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
        return;
    }

    s->handler[line] = handler;
}

static void tc6393xb_gpio_handler_update(TC6393xbState *s)
{
    uint32_t level, diff;
    int bit;

    level = s->gpio_level & s->gpio_dir;
    level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS);

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
        bit = ctz32(diff);
        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
    }

    s->prev_level = level;
}

qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
{
    return s->l3v;
}

static void tc6393xb_l3v(void *opaque, int line, int level)
{
    TC6393xbState *s = opaque;
    s->blank = !level;
    fprintf(stderr, "L3V: %d\n", level);
}

static void tc6393xb_sub_irq(void *opaque, int line, int level) {
    TC6393xbState *s = opaque;
    uint8_t isr = s->scr.ISR;
    if (level)
        isr |= 1 << line;
    else
        isr &= ~(1 << line);
    s->scr.ISR = isr;
    qemu_set_irq(s->irq, isr & s->scr.IMR);
}

#define SCR_REG_B(N)                            \
    case SCR_ ##N: return s->scr.N
#define SCR_REG_W(N)                            \
    case SCR_ ##N: return s->scr.N;             \
    case SCR_ ##N + 1: return s->scr.N >> 8;
#define SCR_REG_L(N)                            \
    case SCR_ ##N: return s->scr.N;             \
    case SCR_ ##N + 1: return s->scr.N >> 8;    \
    case SCR_ ##N + 2: return s->scr.N >> 16;   \
    case SCR_ ##N + 3: return s->scr.N >> 24;
#define SCR_REG_A(N)                            \
    case SCR_ ##N(0): return s->scr.N[0];       \
    case SCR_ ##N(1): return s->scr.N[1];       \
    case SCR_ ##N(2): return s->scr.N[2]

static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
{
    switch (addr) {
        case SCR_REVID:
            return 3;
        case SCR_REVID+1:
            return 0;
        SCR_REG_B(ISR);
        SCR_REG_B(IMR);
        SCR_REG_B(IRR);
        SCR_REG_W(GPER);
        SCR_REG_A(GPI_SR);
        SCR_REG_A(GPI_IMR);
        SCR_REG_A(GPI_EDER);
        SCR_REG_A(GPI_LIR);
        case SCR_GPO_DSR(0):
        case SCR_GPO_DSR(1):
        case SCR_GPO_DSR(2):
            return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
        case SCR_GPO_DOECR(0):
        case SCR_GPO_DOECR(1):
        case SCR_GPO_DOECR(2):
            return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
        SCR_REG_A(GP_IARCR);
        SCR_REG_A(GP_IARLCR);
        SCR_REG_A(GPI_BCR);
        SCR_REG_W(GPA_IARCR);
        SCR_REG_W(GPA_IARLCR);
        SCR_REG_W(CCR);
        SCR_REG_W(PLL2CR);
        SCR_REG_L(PLL1CR);
        SCR_REG_B(DIARCR);
        SCR_REG_B(DBOCR);
        SCR_REG_B(FER);
        SCR_REG_W(MCR);
        SCR_REG_B(CONFIG);
        SCR_REG_B(DEBUG);
    }
    fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
#undef SCR_REG_B
#undef SCR_REG_W
#undef SCR_REG_L
#undef SCR_REG_A

#define SCR_REG_B(N)                                \
    case SCR_ ##N: s->scr.N = value; return;
#define SCR_REG_W(N)                                \
    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
    case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
#define SCR_REG_L(N)                                \
    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return;   \
    case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return;     \
    case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return;   \
    case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
#define SCR_REG_A(N)                                \
    case SCR_ ##N(0): s->scr.N[0] = value; return;   \
    case SCR_ ##N(1): s->scr.N[1] = value; return;   \
    case SCR_ ##N(2): s->scr.N[2] = value; return

static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
{
    switch (addr) {
        SCR_REG_B(ISR);
        SCR_REG_B(IMR);
        SCR_REG_B(IRR);
        SCR_REG_W(GPER);
        SCR_REG_A(GPI_SR);
        SCR_REG_A(GPI_IMR);
        SCR_REG_A(GPI_EDER);
        SCR_REG_A(GPI_LIR);
        case SCR_GPO_DSR(0):
        case SCR_GPO_DSR(1):
        case SCR_GPO_DSR(2):
            s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
            tc6393xb_gpio_handler_update(s);
            return;
        case SCR_GPO_DOECR(0):
        case SCR_GPO_DOECR(1):
        case SCR_GPO_DOECR(2):
            s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
            tc6393xb_gpio_handler_update(s);
            return;
        SCR_REG_A(GP_IARCR);
        SCR_REG_A(GP_IARLCR);
        SCR_REG_A(GPI_BCR);
        SCR_REG_W(GPA_IARCR);
        SCR_REG_W(GPA_IARLCR);
        SCR_REG_W(CCR);
        SCR_REG_W(PLL2CR);
        SCR_REG_L(PLL1CR);
        SCR_REG_B(DIARCR);
        SCR_REG_B(DBOCR);
        SCR_REG_B(FER);
        SCR_REG_W(MCR);
        SCR_REG_B(CONFIG);
        SCR_REG_B(DEBUG);
    }
    fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
                                        (uint32_t) addr, value & 0xff);
}
#undef SCR_REG_B
#undef SCR_REG_W
#undef SCR_REG_L
#undef SCR_REG_A

static void tc6393xb_nand_irq(TC6393xbState *s) {
    qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
            (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}

static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
    switch (addr) {
        case NAND_CFG_COMMAND:
            return s->nand_enable ? 2 : 0;
        case NAND_CFG_BASE:
        case NAND_CFG_BASE + 1:
        case NAND_CFG_BASE + 2:
        case NAND_CFG_BASE + 3:
            return s->nand_phys >> (addr - NAND_CFG_BASE);
    }
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
    switch (addr) {
        case NAND_CFG_COMMAND:
            s->nand_enable = (value & 0x2);
            return;
        case NAND_CFG_BASE:
        case NAND_CFG_BASE + 1:
        case NAND_CFG_BASE + 2:
        case NAND_CFG_BASE + 3:
            s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
            s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
            return;
    }
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
                                        (uint32_t) addr, value & 0xff);
}

static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
    switch (addr) {
        case NAND_DATA + 0:
        case NAND_DATA + 1:
        case NAND_DATA + 2:
        case NAND_DATA + 3:
            return nand_getio(s->flash);
        case NAND_MODE:
            return s->nand.mode;
        case NAND_STATUS:
            return 0x14;
        case NAND_ISR:
            return s->nand.isr;
        case NAND_IMR:
            return s->nand.imr;
    }
    fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
//    fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
//					(uint32_t) addr, value & 0xff);
    switch (addr) {
        case NAND_DATA + 0:
        case NAND_DATA + 1:
        case NAND_DATA + 2:
        case NAND_DATA + 3:
            nand_setio(s->flash, value);
            s->nand.isr |= 1;
            tc6393xb_nand_irq(s);
            return;
        case NAND_MODE:
            s->nand.mode = value;
            nand_setpins(s->flash,
                    value & NAND_MODE_CLE,
                    value & NAND_MODE_ALE,
                    !(value & NAND_MODE_CE),
                    value & NAND_MODE_WP,
                    0); // FIXME: gnd
            switch (value & NAND_MODE_ECC_MASK) {
                case NAND_MODE_ECC_RST:
                    ecc_reset(&s->ecc);
                    break;
                case NAND_MODE_ECC_READ:
                    // FIXME
                    break;
                case NAND_MODE_ECC_EN:
                    ecc_reset(&s->ecc);
            }
            return;
        case NAND_ISR:
            s->nand.isr = value;
            tc6393xb_nand_irq(s);
            return;
        case NAND_IMR:
            s->nand.imr = value;
            tc6393xb_nand_irq(s);
            return;
    }
    fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
                                        (uint32_t) addr, value & 0xff);
}

#define BITS 8
#include "tc6393xb_template.h"
#define BITS 15
#include "tc6393xb_template.h"
#define BITS 16
#include "tc6393xb_template.h"
#define BITS 24
#include "tc6393xb_template.h"
#define BITS 32
#include "tc6393xb_template.h"

static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
{
    DisplaySurface *surface = qemu_console_surface(s->con);

    switch (surface_bits_per_pixel(surface)) {
        case 8:
            tc6393xb_draw_graphic8(s);
            break;
        case 15:
            tc6393xb_draw_graphic15(s);
            break;
        case 16:
            tc6393xb_draw_graphic16(s);
            break;
        case 24:
            tc6393xb_draw_graphic24(s);
            break;
        case 32:
            tc6393xb_draw_graphic32(s);
            break;
        default:
            printf("tc6393xb: unknown depth %d\n",
                   surface_bits_per_pixel(surface));
            return;
    }

    dpy_gfx_update_full(s->con);
}

static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int i, w;
    uint8_t *d;

    if (!full_update)
        return;

    w = s->scr_width * surface_bytes_per_pixel(surface);
    d = surface_data(surface);
    for(i = 0; i < s->scr_height; i++) {
        memset(d, 0, w);
        d += surface_stride(surface);
    }

    dpy_gfx_update_full(s->con);
}

static void tc6393xb_update_display(void *opaque)
{
    TC6393xbState *s = opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);
    int full_update;

    if (s->scr_width == 0 || s->scr_height == 0)
        return;

    full_update = 0;
    if (s->blanked != s->blank) {
        s->blanked = s->blank;
        full_update = 1;
    }
    if (s->scr_width != surface_width(surface) ||
        s->scr_height != surface_height(surface)) {
        qemu_console_resize(s->con, s->scr_width, s->scr_height);
        full_update = 1;
    }
    if (s->blanked)
        tc6393xb_draw_blank(s, full_update);
    else
        tc6393xb_draw_graphic(s, full_update);
}


static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
                               unsigned size)
{
    TC6393xbState *s = opaque;

    switch (addr >> 8) {
        case 0:
            return tc6393xb_scr_readb(s, addr & 0xff);
        case 1:
            return tc6393xb_nand_cfg_readb(s, addr & 0xff);
    };

    if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
//        return tc6393xb_nand_readb(s, addr & 0xff);
        uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
//        fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
        return d;
    }

//    fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}

static void tc6393xb_writeb(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size) {
    TC6393xbState *s = opaque;

    switch (addr >> 8) {
        case 0:
            tc6393xb_scr_writeb(s, addr & 0xff, value);
            return;
        case 1:
            tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
            return;
    };

    if ((addr &~0xff) == s->nand_phys && s->nand_enable)
        tc6393xb_nand_writeb(s, addr & 0xff, value);
    else
        fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
                (uint32_t) addr, (int)value & 0xff);
}

static const GraphicHwOps tc6393xb_gfx_ops = {
    .gfx_update  = tc6393xb_update_display,
};

TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
{
    TC6393xbState *s;
    DriveInfo *nand;
    static const MemoryRegionOps tc6393xb_ops = {
        .read = tc6393xb_readb,
        .write = tc6393xb_writeb,
        .endianness = DEVICE_NATIVE_ENDIAN,
        .impl = {
            .min_access_size = 1,
            .max_access_size = 1,
        },
    };

    s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
    s->irq = irq;
    s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);

    s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
    s->blanked = 1;

    s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);

    nand = drive_get(IF_MTD, 0, 0);
    s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
                         NAND_MFR_TOSHIBA, 0x76);

    memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
                           &error_fatal);
    s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
    memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
    s->scr_width = 480;
    s->scr_height = 640;
    s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);

    return s;
}
Commit	Line	Data
7880febd PB	1	/*
	2	* Toshiba TC6393XB I/O Controller.
	3	* Found in Sharp Zaurus SL-6000 (tosa) or some
	4	* Toshiba e-Series PDAs.
	5	*
	6	* Most features are currently unsupported!!!
	7	*
	8	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	9	*
	10	* Contributions after 2012-01-13 are licensed under the terms of the
	11	* GNU GPL, version 2 or (at your option) any later version.
7880febd	12	*/
47df5154	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
87776ab7	15	#include "qemu/host-utils.h"
83c9f4ca	16	#include "hw/hw.h"
bd2be150	17	#include "hw/devices.h"
0d09e41a	18	#include "hw/block/flash.h"
28ecbaee PB	19	#include "ui/console.h"
28ecbaee PB	20	#include "ui/pixel_ops.h"
9c17d615	21	#include "sysemu/blockdev.h"
a6569fc5 AZ	22
	23	#define IRQ_TC6393_NAND 0
	24	#define IRQ_TC6393_MMC 1
	25	#define IRQ_TC6393_OHCI 2
	26	#define IRQ_TC6393_SERIAL 3
	27	#define IRQ_TC6393_FB 4
	28
	29	#define TC6393XB_NR_IRQS 8
88d2c950 AZ	30
	31	#define TC6393XB_GPIOS 16
	32
	33	#define SCR_REVID 0x08 /* b Revision ID */
	34	#define SCR_ISR 0x50 /* b Interrupt Status */
	35	#define SCR_IMR 0x52 /* b Interrupt Mask */
	36	#define SCR_IRR 0x54 /* b Interrupt Routing */
	37	#define SCR_GPER 0x60 /* w GP Enable */
	38	#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
	39	#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
	40	#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
	41	#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
	42	#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
	43	#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
	44	#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
	45	#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
	46	#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
	47	#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
	48	#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
	49	#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
	50	#define SCR_CCR 0x98 /* w Clock Control */
	51	#define SCR_PLL2CR 0x9a /* w PLL2 Control */
	52	#define SCR_PLL1CR 0x9c /* l PLL1 Control */
	53	#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
	54	#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
	55	#define SCR_FER 0xe0 /* b Function Enable */
	56	#define SCR_MCR 0xe4 /* w Mode Control */
	57	#define SCR_CONFIG 0xfc /* b Configuration Control */
	58	#define SCR_DEBUG 0xff /* b Debug */
	59
a6569fc5 AZ	60	#define NAND_CFG_COMMAND 0x04 /* w Command */
	61	#define NAND_CFG_BASE 0x10 /* l Control Base Address */
	62	#define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
	63	#define NAND_CFG_INTE 0x48 /* b Int Enable */
	64	#define NAND_CFG_EC 0x4a /* b Event Control */
	65	#define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
	66	#define NAND_CFG_ECCC 0x5b /* b ECC Control */
	67	#define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
	68	#define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
	69	#define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
	70	#define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
	71
	72	#define NAND_DATA 0x00 /* l Data */
	73	#define NAND_MODE 0x04 /* b Mode */
	74	#define NAND_STATUS 0x05 /* b Status */
	75	#define NAND_ISR 0x06 /* b Interrupt Status */
	76	#define NAND_IMR 0x07 /* b Interrupt Mask */
	77
	78	#define NAND_MODE_WP 0x80
	79	#define NAND_MODE_CE 0x10
	80	#define NAND_MODE_ALE 0x02
	81	#define NAND_MODE_CLE 0x01
	82	#define NAND_MODE_ECC_MASK 0x60
	83	#define NAND_MODE_ECC_EN 0x20
	84	#define NAND_MODE_ECC_READ 0x40
	85	#define NAND_MODE_ECC_RST 0x60
	86
bc24a225	87	struct TC6393xbState {
fe06bd93	88	MemoryRegion iomem;
a6569fc5 AZ	89	qemu_irq irq;
a6569fc5 AZ	90	qemu_irq *sub_irqs;
88d2c950 AZ	91	struct {
	92	uint8_t ISR;
	93	uint8_t IMR;
	94	uint8_t IRR;
	95	uint16_t GPER;
	96	uint8_t GPI_SR[3];
	97	uint8_t GPI_IMR[3];
	98	uint8_t GPI_EDER[3];
	99	uint8_t GPI_LIR[3];
	100	uint8_t GP_IARCR[3];
	101	uint8_t GP_IARLCR[3];
	102	uint8_t GPI_BCR[3];
	103	uint16_t GPA_IARCR;
	104	uint16_t GPA_IARLCR;
	105	uint16_t CCR;
	106	uint16_t PLL2CR;
	107	uint32_t PLL1CR;
	108	uint8_t DIARCR;
	109	uint8_t DBOCR;
	110	uint8_t FER;
	111	uint16_t MCR;
	112	uint8_t CONFIG;
	113	uint8_t DEBUG;
	114	} scr;
	115	uint32_t gpio_dir;
	116	uint32_t gpio_level;
	117	uint32_t prev_level;
	118	qemu_irq handler[TC6393XB_GPIOS];
	119	qemu_irq *gpio_in;
a6569fc5 AZ	120
	121	struct {
	122	uint8_t mode;
	123	uint8_t isr;
	124	uint8_t imr;
	125	} nand;
	126	int nand_enable;
	127	uint32_t nand_phys;
d4220389	128	DeviceState *flash;
bc24a225	129	ECCState ecc;
64b40bc5	130
c78f7137	131	QemuConsole *con;
fe06bd93	132	MemoryRegion vram;
44654490	133	uint16_t *vram_ptr;
64b40bc5 AZ	134	uint32_t scr_width, scr_height; /* in pixels */
	135	qemu_irq l3v;
	136	unsigned blank : 1,
	137	blanked : 1;
88d2c950 AZ	138	};
88d2c950 AZ	139
bc24a225	140	qemu_irq tc6393xb_gpio_in_get(TC6393xbState s)
88d2c950 AZ	141	{
	142	return s->gpio_in;
	143	}
	144
	145	static void tc6393xb_gpio_set(void *opaque, int line, int level)
	146	{
bc24a225	147	// TC6393xbState *s = opaque;
88d2c950 AZ	148
88d2c950 AZ	149	if (line > TC6393XB_GPIOS) {
a89f364a	150	printf("%s: No GPIO pin %i\n", __func__, line);
88d2c950 AZ	151	return;
	152	}
	153
	154	// FIXME: how does the chip reflect the GPIO input level change?
	155	}
	156
bc24a225	157	void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
88d2c950 AZ	158	qemu_irq handler)
	159	{
	160	if (line >= TC6393XB_GPIOS) {
	161	fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
	162	return;
	163	}
	164
	165	s->handler[line] = handler;
	166	}
	167
bc24a225	168	static void tc6393xb_gpio_handler_update(TC6393xbState *s)
88d2c950 AZ	169	{
	170	uint32_t level, diff;
	171	int bit;
	172
	173	level = s->gpio_level & s->gpio_dir;
d6c3768b	174	level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS);
88d2c950 AZ	175
88d2c950 AZ	176	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
786a4ea8	177	bit = ctz32(diff);
88d2c950 AZ	178	qemu_set_irq(s->handler[bit], (level >> bit) & 1);
	179	}
	180
	181	s->prev_level = level;
	182	}
	183
bc24a225	184	qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
64b40bc5 AZ	185	{
	186	return s->l3v;
	187	}
	188
	189	static void tc6393xb_l3v(void *opaque, int line, int level)
	190	{
bc24a225	191	TC6393xbState *s = opaque;
64b40bc5 AZ	192	s->blank = !level;
	193	fprintf(stderr, "L3V: %d\n", level);
	194	}
	195
a6569fc5	196	static void tc6393xb_sub_irq(void *opaque, int line, int level) {
bc24a225	197	TC6393xbState *s = opaque;
a6569fc5 AZ	198	uint8_t isr = s->scr.ISR;
	199	if (level)
	200	isr \|= 1 << line;
	201	else
	202	isr &= ~(1 << line);
	203	s->scr.ISR = isr;
	204	qemu_set_irq(s->irq, isr & s->scr.IMR);
	205	}
	206
88d2c950 AZ	207	#define SCR_REG_B(N) \
	208	case SCR_ ##N: return s->scr.N
	209	#define SCR_REG_W(N) \
	210	case SCR_ ##N: return s->scr.N; \
	211	case SCR_ ##N + 1: return s->scr.N >> 8;
	212	#define SCR_REG_L(N) \
	213	case SCR_ ##N: return s->scr.N; \
	214	case SCR_ ##N + 1: return s->scr.N >> 8; \
	215	case SCR_ ##N + 2: return s->scr.N >> 16; \
	216	case SCR_ ##N + 3: return s->scr.N >> 24;
	217	#define SCR_REG_A(N) \
	218	case SCR_ ##N(0): return s->scr.N[0]; \
	219	case SCR_ ##N(1): return s->scr.N[1]; \
	220	case SCR_ ##N(2): return s->scr.N[2]
	221
a8170e5e	222	static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
88d2c950	223	{
88d2c950 AZ	224	switch (addr) {
	225	case SCR_REVID:
	226	return 3;
	227	case SCR_REVID+1:
	228	return 0;
	229	SCR_REG_B(ISR);
	230	SCR_REG_B(IMR);
	231	SCR_REG_B(IRR);
	232	SCR_REG_W(GPER);
	233	SCR_REG_A(GPI_SR);
	234	SCR_REG_A(GPI_IMR);
	235	SCR_REG_A(GPI_EDER);
	236	SCR_REG_A(GPI_LIR);
	237	case SCR_GPO_DSR(0):
	238	case SCR_GPO_DSR(1):
	239	case SCR_GPO_DSR(2):
	240	return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
	241	case SCR_GPO_DOECR(0):
	242	case SCR_GPO_DOECR(1):
	243	case SCR_GPO_DOECR(2):
	244	return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
	245	SCR_REG_A(GP_IARCR);
	246	SCR_REG_A(GP_IARLCR);
	247	SCR_REG_A(GPI_BCR);
	248	SCR_REG_W(GPA_IARCR);
	249	SCR_REG_W(GPA_IARLCR);
	250	SCR_REG_W(CCR);
	251	SCR_REG_W(PLL2CR);
	252	SCR_REG_L(PLL1CR);
	253	SCR_REG_B(DIARCR);
	254	SCR_REG_B(DBOCR);
	255	SCR_REG_B(FER);
	256	SCR_REG_W(MCR);
	257	SCR_REG_B(CONFIG);
	258	SCR_REG_B(DEBUG);
	259	}
a6569fc5	260	fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
88d2c950 AZ	261	return 0;
	262	}
	263	#undef SCR_REG_B
	264	#undef SCR_REG_W
	265	#undef SCR_REG_L
	266	#undef SCR_REG_A
	267
	268	#define SCR_REG_B(N) \
a6569fc5	269	case SCR_ ##N: s->scr.N = value; return;
88d2c950	270	#define SCR_REG_W(N) \
a6569fc5 AZ	271	case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) \| (value & 0xff); return; \
a6569fc5 AZ	272	case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) \| (value << 8); return
88d2c950	273	#define SCR_REG_L(N) \
a6569fc5 AZ	274	case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) \| (value & 0xff); return; \
	275	case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) \| (value & (0xff << 8)); return; \
	276	case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) \| (value & (0xff << 16)); return; \
	277	case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) \| (value & (0xff << 24)); return;
88d2c950	278	#define SCR_REG_A(N) \
a6569fc5 AZ	279	case SCR_ ##N(0): s->scr.N[0] = value; return; \
	280	case SCR_ ##N(1): s->scr.N[1] = value; return; \
	281	case SCR_ ##N(2): s->scr.N[2] = value; return
88d2c950	282
a8170e5e	283	static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
88d2c950	284	{
88d2c950 AZ	285	switch (addr) {
	286	SCR_REG_B(ISR);
	287	SCR_REG_B(IMR);
	288	SCR_REG_B(IRR);
	289	SCR_REG_W(GPER);
	290	SCR_REG_A(GPI_SR);
	291	SCR_REG_A(GPI_IMR);
	292	SCR_REG_A(GPI_EDER);
	293	SCR_REG_A(GPI_LIR);
	294	case SCR_GPO_DSR(0):
	295	case SCR_GPO_DSR(1):
	296	case SCR_GPO_DSR(2):
	297	s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))8))) \| ((value & 0xff) << ((addr - SCR_GPO_DSR(0))8));
	298	tc6393xb_gpio_handler_update(s);
a6569fc5	299	return;
88d2c950 AZ	300	case SCR_GPO_DOECR(0):
	301	case SCR_GPO_DOECR(1):
	302	case SCR_GPO_DOECR(2):
	303	s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))8))) \| ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))8));
	304	tc6393xb_gpio_handler_update(s);
a6569fc5	305	return;
88d2c950 AZ	306	SCR_REG_A(GP_IARCR);
	307	SCR_REG_A(GP_IARLCR);
	308	SCR_REG_A(GPI_BCR);
	309	SCR_REG_W(GPA_IARCR);
	310	SCR_REG_W(GPA_IARLCR);
	311	SCR_REG_W(CCR);
	312	SCR_REG_W(PLL2CR);
	313	SCR_REG_L(PLL1CR);
	314	SCR_REG_B(DIARCR);
	315	SCR_REG_B(DBOCR);
	316	SCR_REG_B(FER);
	317	SCR_REG_W(MCR);
	318	SCR_REG_B(CONFIG);
	319	SCR_REG_B(DEBUG);
88d2c950	320	}
a6569fc5	321	fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
7d37435b	322	(uint32_t) addr, value & 0xff);
88d2c950 AZ	323	}
	324	#undef SCR_REG_B
	325	#undef SCR_REG_W
	326	#undef SCR_REG_L
	327	#undef SCR_REG_A
	328
bc24a225	329	static void tc6393xb_nand_irq(TC6393xbState *s) {
a6569fc5 AZ	330	qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
	331	(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
	332	}
	333
a8170e5e	334	static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
a6569fc5 AZ	335	switch (addr) {
	336	case NAND_CFG_COMMAND:
	337	return s->nand_enable ? 2 : 0;
	338	case NAND_CFG_BASE:
	339	case NAND_CFG_BASE + 1:
	340	case NAND_CFG_BASE + 2:
	341	case NAND_CFG_BASE + 3:
	342	return s->nand_phys >> (addr - NAND_CFG_BASE);
	343	}
	344	fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
	345	return 0;
	346	}
a8170e5e	347	static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
a6569fc5 AZ	348	switch (addr) {
	349	case NAND_CFG_COMMAND:
	350	s->nand_enable = (value & 0x2);
	351	return;
	352	case NAND_CFG_BASE:
	353	case NAND_CFG_BASE + 1:
	354	case NAND_CFG_BASE + 2:
	355	case NAND_CFG_BASE + 3:
	356	s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
	357	s->nand_phys \|= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
	358	return;
	359	}
	360	fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
7d37435b	361	(uint32_t) addr, value & 0xff);
a6569fc5 AZ	362	}
a6569fc5 AZ	363
a8170e5e	364	static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
a6569fc5 AZ	365	switch (addr) {
	366	case NAND_DATA + 0:
	367	case NAND_DATA + 1:
	368	case NAND_DATA + 2:
	369	case NAND_DATA + 3:
	370	return nand_getio(s->flash);
	371	case NAND_MODE:
	372	return s->nand.mode;
	373	case NAND_STATUS:
	374	return 0x14;
	375	case NAND_ISR:
	376	return s->nand.isr;
	377	case NAND_IMR:
	378	return s->nand.imr;
	379	}
	380	fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
	381	return 0;
	382	}
a8170e5e	383	static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
a6569fc5 AZ	384	// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
	385	// (uint32_t) addr, value & 0xff);
	386	switch (addr) {
	387	case NAND_DATA + 0:
	388	case NAND_DATA + 1:
	389	case NAND_DATA + 2:
	390	case NAND_DATA + 3:
	391	nand_setio(s->flash, value);
f23c1b2a	392	s->nand.isr \|= 1;
a6569fc5 AZ	393	tc6393xb_nand_irq(s);
	394	return;
	395	case NAND_MODE:
	396	s->nand.mode = value;
	397	nand_setpins(s->flash,
	398	value & NAND_MODE_CLE,
	399	value & NAND_MODE_ALE,
	400	!(value & NAND_MODE_CE),
	401	value & NAND_MODE_WP,
	402	0); // FIXME: gnd
	403	switch (value & NAND_MODE_ECC_MASK) {
	404	case NAND_MODE_ECC_RST:
	405	ecc_reset(&s->ecc);
	406	break;
	407	case NAND_MODE_ECC_READ:
	408	// FIXME
	409	break;
	410	case NAND_MODE_ECC_EN:
	411	ecc_reset(&s->ecc);
	412	}
	413	return;
	414	case NAND_ISR:
	415	s->nand.isr = value;
	416	tc6393xb_nand_irq(s);
	417	return;
	418	case NAND_IMR:
	419	s->nand.imr = value;
	420	tc6393xb_nand_irq(s);
	421	return;
	422	}
	423	fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
7d37435b	424	(uint32_t) addr, value & 0xff);
a6569fc5 AZ	425	}
a6569fc5 AZ	426
64b40bc5	427	#define BITS 8
47b43a1f	428	#include "tc6393xb_template.h"
64b40bc5	429	#define BITS 15
47b43a1f	430	#include "tc6393xb_template.h"
64b40bc5	431	#define BITS 16
47b43a1f	432	#include "tc6393xb_template.h"
64b40bc5	433	#define BITS 24
47b43a1f	434	#include "tc6393xb_template.h"
64b40bc5	435	#define BITS 32
47b43a1f	436	#include "tc6393xb_template.h"
64b40bc5	437
bc24a225	438	static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
64b40bc5	439	{
c78f7137 GH	440	DisplaySurface *surface = qemu_console_surface(s->con);
	441
	442	switch (surface_bits_per_pixel(surface)) {
64b40bc5 AZ	443	case 8:
	444	tc6393xb_draw_graphic8(s);
	445	break;
	446	case 15:
	447	tc6393xb_draw_graphic15(s);
	448	break;
	449	case 16:
	450	tc6393xb_draw_graphic16(s);
	451	break;
	452	case 24:
	453	tc6393xb_draw_graphic24(s);
	454	break;
	455	case 32:
	456	tc6393xb_draw_graphic32(s);
	457	break;
	458	default:
c78f7137 GH	459	printf("tc6393xb: unknown depth %d\n",
c78f7137 GH	460	surface_bits_per_pixel(surface));
64b40bc5 AZ	461	return;
	462	}
	463
91155f8b	464	dpy_gfx_update_full(s->con);
64b40bc5 AZ	465	}
64b40bc5 AZ	466
bc24a225	467	static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
64b40bc5	468	{
c78f7137	469	DisplaySurface *surface = qemu_console_surface(s->con);
64b40bc5 AZ	470	int i, w;
	471	uint8_t *d;
	472
	473	if (!full_update)
	474	return;
	475
c78f7137 GH	476	w = s->scr_width * surface_bytes_per_pixel(surface);
c78f7137 GH	477	d = surface_data(surface);
64b40bc5 AZ	478	for(i = 0; i < s->scr_height; i++) {
64b40bc5 AZ	479	memset(d, 0, w);
c78f7137	480	d += surface_stride(surface);
64b40bc5 AZ	481	}
64b40bc5 AZ	482
91155f8b	483	dpy_gfx_update_full(s->con);
64b40bc5 AZ	484	}
	485
	486	static void tc6393xb_update_display(void *opaque)
	487	{
bc24a225	488	TC6393xbState *s = opaque;
c78f7137	489	DisplaySurface *surface = qemu_console_surface(s->con);
64b40bc5 AZ	490	int full_update;
	491
	492	if (s->scr_width == 0 \|\| s->scr_height == 0)
	493	return;
	494
	495	full_update = 0;
	496	if (s->blanked != s->blank) {
	497	s->blanked = s->blank;
	498	full_update = 1;
	499	}
c78f7137 GH	500	if (s->scr_width != surface_width(surface) \|\|
	501	s->scr_height != surface_height(surface)) {
	502	qemu_console_resize(s->con, s->scr_width, s->scr_height);
64b40bc5 AZ	503	full_update = 1;
	504	}
	505	if (s->blanked)
	506	tc6393xb_draw_blank(s, full_update);
	507	else
	508	tc6393xb_draw_graphic(s, full_update);
	509	}
	510
	511
a8170e5e	512	static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
fe06bd93 AK	513	unsigned size)
fe06bd93 AK	514	{
bc24a225	515	TC6393xbState *s = opaque;
a6569fc5 AZ	516
	517	switch (addr >> 8) {
	518	case 0:
	519	return tc6393xb_scr_readb(s, addr & 0xff);
	520	case 1:
	521	return tc6393xb_nand_cfg_readb(s, addr & 0xff);
	522	};
	523
	524	if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
	525	// return tc6393xb_nand_readb(s, addr & 0xff);
	526	uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
	527	// fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
	528	return d;
	529	}
	530
	531	// fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
	532	return 0;
	533	}
	534
a8170e5e	535	static void tc6393xb_writeb(void *opaque, hwaddr addr,
fe06bd93	536	uint64_t value, unsigned size) {
bc24a225	537	TC6393xbState *s = opaque;
a6569fc5 AZ	538
	539	switch (addr >> 8) {
	540	case 0:
	541	tc6393xb_scr_writeb(s, addr & 0xff, value);
	542	return;
	543	case 1:
	544	tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
	545	return;
	546	};
	547
	548	if ((addr &~0xff) == s->nand_phys && s->nand_enable)
	549	tc6393xb_nand_writeb(s, addr & 0xff, value);
	550	else
	551	fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
fe06bd93	552	(uint32_t) addr, (int)value & 0xff);
88d2c950 AZ	553	}
88d2c950 AZ	554
380cd056 GH	555	static const GraphicHwOps tc6393xb_gfx_ops = {
	556	.gfx_update = tc6393xb_update_display,
	557	};
	558
fe06bd93	559	TC6393xbState tc6393xb_init(MemoryRegion sysmem, uint32_t base, qemu_irq irq)
88d2c950	560	{
bc24a225	561	TC6393xbState *s;
522f253c	562	DriveInfo *nand;
fe06bd93 AK	563	static const MemoryRegionOps tc6393xb_ops = {
	564	.read = tc6393xb_readb,
	565	.write = tc6393xb_writeb,
	566	.endianness = DEVICE_NATIVE_ENDIAN,
	567	.impl = {
	568	.min_access_size = 1,
	569	.max_access_size = 1,
	570	},
88d2c950 AZ	571	};
88d2c950 AZ	572
7267c094	573	s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
a6569fc5	574	s->irq = irq;
88d2c950 AZ	575	s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
88d2c950 AZ	576
26c8acb3	577	s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
64b40bc5 AZ	578	s->blanked = 1;
64b40bc5 AZ	579
a6569fc5 AZ	580	s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
a6569fc5 AZ	581
522f253c	582	nand = drive_get(IF_MTD, 0, 0);
4be74634	583	s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
fa1d36df	584	NAND_MFR_TOSHIBA, 0x76);
a6569fc5	585
2c9b15ca	586	memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
fe06bd93	587	memory_region_add_subregion(sysmem, base, &s->iomem);
64b40bc5	588
98a99ce0	589	memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
f8ed85ac	590	&error_fatal);
fe06bd93 AK	591	s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
fe06bd93 AK	592	memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
3023f332 AL	593	s->scr_width = 480;
3023f332 AL	594	s->scr_height = 640;
5643706a	595	s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);
88d2c950 AZ	596
	597	return s;
	598	}