const struct bochs_header *bochs = (const void *)buf;
if (buf_size < HEADER_SIZE)
- return 0;
+ return 0;
if (!strcmp(bochs->magic, HEADER_MAGIC) &&
- !strcmp(bochs->type, REDOLOG_TYPE) &&
- !strcmp(bochs->subtype, GROWING_TYPE) &&
- ((le32_to_cpu(bochs->version) == HEADER_VERSION) ||
- (le32_to_cpu(bochs->version) == HEADER_V1)))
- return 100;
+ !strcmp(bochs->type, REDOLOG_TYPE) &&
+ !strcmp(bochs->subtype, GROWING_TYPE) &&
+ ((le32_to_cpu(bochs->version) == HEADER_VERSION) ||
+ (le32_to_cpu(bochs->version) == HEADER_V1)))
+ return 100;
return 0;
}
if (strcmp(bochs.magic, HEADER_MAGIC) ||
strcmp(bochs.type, REDOLOG_TYPE) ||
strcmp(bochs.subtype, GROWING_TYPE) ||
- ((le32_to_cpu(bochs.version) != HEADER_VERSION) &&
- (le32_to_cpu(bochs.version) != HEADER_V1))) {
+ ((le32_to_cpu(bochs.version) != HEADER_VERSION) &&
+ (le32_to_cpu(bochs.version) != HEADER_V1))) {
error_setg(errp, "Image not in Bochs format");
return -EINVAL;
}
}
for (i = 0; i < s->catalog_size; i++)
- le32_to_cpus(&s->catalog_bitmap[i]);
+ le32_to_cpus(&s->catalog_bitmap[i]);
s->data_offset = le32_to_cpu(bochs.header) + (s->catalog_size * 4);
extent_offset = (offset % s->extent_size) / 512;
if (s->catalog_bitmap[extent_index] == 0xffffffff) {
- return 0; /* not allocated */
+ return 0; /* not allocated */
}
bitmap_offset = s->data_offset +
}
if (!((bitmap_entry >> (extent_offset % 8)) & 1)) {
- return 0; /* not allocated */
+ return 0; /* not allocated */
}
return bitmap_offset + (512 * (s->bitmap_blocks + extent_offset));
#endif
if (!fstat(fd, &sb) && (S_IFCHR & sb.st_mode)) {
#ifdef DIOCGMEDIASIZE
- if (ioctl(fd, DIOCGMEDIASIZE, (off_t *)&size))
+ if (ioctl(fd, DIOCGMEDIASIZE, (off_t *)&size))
#elif defined(DIOCGPART)
{
struct partinfo pi;
BOOL res;
if ((GetVersion() & 0x80000000UL) && (length >> 32) != 0)
- return -1;
+ return -1;
h = (HANDLE)_get_osfhandle(fd);
li.HighPart = 0;
li.LowPart = SetFilePointer (h, 0, &li.HighPart, FILE_CURRENT);
if (li.LowPart == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
- return -1;
+ return -1;
}
high = length >> 32;
dw = SetFilePointer(h, (DWORD) length, &high, FILE_BEGIN);
if (dw == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
- return -1;
+ return -1;
}
res = SetEndOfFile(h);
{
DWORD returned;
return (int) DeviceIoControl((HANDLE)_get_osfhandle(fd), FSCTL_SET_SPARSE,
- NULL, 0, NULL, 0, &returned, NULL);
+ NULL, 0, NULL, 0, &returned, NULL);
}
static void raw_detach_aio_context(BlockDriverState *bs)
switch (type) {
case QEMU_AIO_WRITE:
io_prep_pwritev(iocbs, fd, qiov->iov, qiov->niov, offset);
- break;
+ break;
case QEMU_AIO_READ:
io_prep_preadv(iocbs, fd, qiov->iov, qiov->niov, offset);
- break;
+ break;
/* Currently Linux kernel does not support other operations */
default:
fprintf(stderr, "%s: invalid AIO request type 0x%x.\n",
}
}
- return i;
+ return i;
}
/*
static int vpc_probe(const uint8_t *buf, int buf_size, const char *filename)
{
if (buf_size >= 8 && !strncmp((char *)buf, "conectix", 8))
- return 100;
+ return 100;
return 0;
}
if (!have_guest_base) {
/*
* Go through ELF program header table and find out whether
- * any of the segments drop below our current mmap_min_addr and
+ * any of the segments drop below our current mmap_min_addr and
* in that case set guest_base to corresponding address.
*/
for (i = 0, elf_ppnt = elf_phdata; i < elf_ex.e_phnum;
static int fill_context(KDDEBUGGER_DATA64 *kdbg,
struct va_space *vs, QEMU_Elf *qe)
{
- int i;
+ int i;
for (i = 0; i < qe->state_nr; i++) {
uint64_t Prcb;
uint64_t Context;
pte_addr |= (addr & (wsm | 0xfe000)) >> 10;
return pte_translate(pte_addr, ret);
} else {
- /* Direct-mapped translation. */
- return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
+ /* Direct-mapped translation. */
+ return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
}
}
/* Check the fourth window for DAC disable. */
if ((pchip->win[3].wba & 0x80000000000ull) == 0
- && window_translate(&pchip->win[3], addr, &ret)) {
+ && window_translate(&pchip->win[3], addr, &ret)) {
goto success;
}
} else {
if (pchip->ctl & 0x40) {
/* See 10.1.4.4; in particular <39:35> is ignored. */
make_iommu_tlbe(0, 0x007ffffffffull, &ret);
- goto success;
+ goto success;
}
}
pte_addr = pchip->win[3].tba & 0x7ffc00000ull;
pte_addr |= (addr & 0xffffe000u) >> 10;
if (pte_translate(pte_addr, &ret)) {
- goto success;
- }
+ goto success;
+ }
}
}
}
s->state |= 1;
if ((s->control & 0x20)) {
/* Output trigger. */
- qemu_irq_pulse(s->trigger);
+ qemu_irq_pulse(s->trigger);
}
if (s->mode[0] & 1) {
/* One-shot. */
#ifdef DEBUG_SERIAL
printf("sh_serial: write offs=0x%02x val=0x%02x\n",
- offs, val);
+ offs, val);
#endif
switch(offs) {
case 0x00: /* SMR */
return;
case 0x04: /* BRR */
s->brr = val;
- return;
+ return;
case 0x08: /* SCR */
/* TODO : For SH7751, SCIF mask should be 0xfb. */
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
if (!(val & (1 << 5)))
s->flags |= SH_SERIAL_FLAG_TEND;
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
- qemu_set_irq(s->txi, val & (1 << 7));
+ qemu_set_irq(s->txi, val & (1 << 7));
}
if (!(val & (1 << 6))) {
- qemu_set_irq(s->rxi, 0);
+ qemu_set_irq(s->rxi, 0);
}
return;
case 0x0c: /* FTDR / TDR */
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
- s->dr = val;
- s->flags &= ~SH_SERIAL_FLAG_TDE;
+ }
+ s->dr = val;
+ s->flags &= ~SH_SERIAL_FLAG_TDE;
return;
#if 0
case 0x14: /* FRDR / RDR */
break;
case 0x04:
ret = s->brr;
- break;
+ break;
case 0x08:
ret = s->scr;
break;
}
#ifdef DEBUG_SERIAL
printf("sh_serial: read offs=0x%02x val=0x%x\n",
- offs, ret);
+ offs, ret);
#endif
if (ret & ~((1 << 16) - 1)) {
qemu_put_byte(f, port->guest_connected);
qemu_put_byte(f, port->host_connected);
- elem_popped = 0;
+ elem_popped = 0;
if (port->elem) {
elem_popped = 1;
}
size = prod - cons;
if ((size == 0) || (size > sizeof(intf->out)))
- return;
+ return;
if ((buffer->capacity - buffer->size) < size) {
- buffer->capacity += (size + 1024);
- buffer->data = g_realloc(buffer->data, buffer->capacity);
+ buffer->capacity += (size + 1024);
+ buffer->data = g_realloc(buffer->data, buffer->capacity);
}
while (cons != prod)
- buffer->data[buffer->size++] = intf->out[
- MASK_XENCONS_IDX(cons++, intf->out)];
+ buffer->data[buffer->size++] = intf->out[
+ MASK_XENCONS_IDX(cons++, intf->out)];
xen_mb();
intf->out_cons = cons;
xen_pv_send_notify(&con->xendev);
if (buffer->max_capacity &&
- buffer->size > buffer->max_capacity) {
- /* Discard the middle of the data. */
+ buffer->size > buffer->max_capacity) {
+ /* Discard the middle of the data. */
- size_t over = buffer->size - buffer->max_capacity;
- uint8_t *maxpos = buffer->data + buffer->max_capacity;
+ size_t over = buffer->size - buffer->max_capacity;
+ uint8_t *maxpos = buffer->data + buffer->max_capacity;
- memmove(maxpos - over, maxpos, over);
- buffer->data = g_realloc(buffer->data, buffer->max_capacity);
- buffer->size = buffer->capacity = buffer->max_capacity;
+ memmove(maxpos - over, maxpos, over);
+ buffer->data = g_realloc(buffer->data, buffer->max_capacity);
+ buffer->size = buffer->capacity = buffer->max_capacity;
- if (buffer->consumed > buffer->max_capacity - over)
- buffer->consumed = buffer->max_capacity - over;
+ if (buffer->consumed > buffer->max_capacity - over)
+ buffer->consumed = buffer->max_capacity - over;
}
}
{
buffer->consumed += len;
if (buffer->consumed == buffer->size) {
- buffer->consumed = 0;
- buffer->size = 0;
+ buffer->consumed = 0;
+ buffer->size = 0;
}
}
space = prod - cons;
if (space > sizeof(intf->in))
- return 0; /* ring is screwed: ignore it */
+ return 0; /* ring is screwed: ignore it */
return (sizeof(intf->in) - space);
}
max = ring_free_bytes(con);
/* The can_receive() func limits this, but check again anyway */
if (max < len)
- len = max;
+ len = max;
prod = intf->in_prod;
for (i = 0; i < len; i++) {
- intf->in[MASK_XENCONS_IDX(prod++, intf->in)] =
- buf[i];
+ intf->in[MASK_XENCONS_IDX(prod++, intf->in)] =
+ buf[i];
}
xen_wmb();
intf->in_prod = prod;
int limit;
if (xenstore_read_int(con->console, "ring-ref", &con->ring_ref) == -1)
- return -1;
+ return -1;
if (xenstore_read_int(con->console, "port", &con->xendev.remote_port) == -1)
- return -1;
+ return -1;
if (xenstore_read_int(con->console, "limit", &limit) == 0)
- con->buffer.max_capacity = limit;
+ con->buffer.max_capacity = limit;
if (!xendev->dev) {
xen_pfn_t mfn = con->ring_ref;
PROT_READ | PROT_WRITE);
}
if (!con->sring)
- return -1;
+ return -1;
xen_be_bind_evtchn(&con->xendev);
qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
xen_pv_printf(xendev, 1,
"ring mfn %d, remote port %d, local port %d, limit %zd\n",
- con->ring_ref,
- con->xendev.remote_port,
- con->xendev.local_port,
- con->buffer.max_capacity);
+ con->ring_ref,
+ con->xendev.remote_port,
+ con->xendev.local_port,
+ con->buffer.max_capacity);
return 0;
}
buffer_append(con);
if (con->buffer.size - con->buffer.consumed)
- xencons_send(con);
+ xencons_send(con);
}
/* -------------------------------------------------------------------- */
case OMAGIC:
if (e.a_text + e.a_data > max_sz)
goto fail;
- lseek(fd, N_TXTOFF(e), SEEK_SET);
- size = read_targphys(filename, fd, addr, e.a_text + e.a_data);
- if (size < 0)
- goto fail;
- break;
+ lseek(fd, N_TXTOFF(e), SEEK_SET);
+ size = read_targphys(filename, fd, addr, e.a_text + e.a_data);
+ if (size < 0)
+ goto fail;
+ break;
case NMAGIC:
if (N_DATADDR(e, target_page_size) + e.a_data > max_sz)
goto fail;
- lseek(fd, N_TXTOFF(e), SEEK_SET);
- size = read_targphys(filename, fd, addr, e.a_text);
- if (size < 0)
- goto fail;
+ lseek(fd, N_TXTOFF(e), SEEK_SET);
+ size = read_targphys(filename, fd, addr, e.a_text);
+ if (size < 0)
+ goto fail;
ret = read_targphys(filename, fd, addr + N_DATADDR(e, target_page_size),
e.a_data);
- if (ret < 0)
- goto fail;
- size += ret;
- break;
+ if (ret < 0)
+ goto fail;
+ size += ret;
+ break;
default:
- goto fail;
+ goto fail;
}
close(fd);
return size;
SCR_REG_B(DEBUG);
}
fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
#undef SCR_REG_B
#undef SCR_REG_W
return;
}
fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
return;
}
fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
#define BITS 8
#define cbswap_32(__x) \
((uint32_t)( \
- (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
- (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
- (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
- (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
+ (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
+ (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
+ (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
+ (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
#ifdef HOST_WORDS_BIGENDIAN
#define PAT(x) cbswap_32(x)
QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
/*
- * the guest can end up emitting fences out of order
- * so we should check all fenced cmds not just the first one.
- */
+ * the guest can end up emitting fences out of order
+ * so we should check all fenced cmds not just the first one.
+ */
if (cmd->cmd_hdr.fence_id > fence) {
continue;
}
!(ch->state & DCSR_NODESCFETCH))
pxa2xx_dma_descriptor_fetch(s, c);
break;
- }
+ }
}
ch->cmd = (ch->cmd & ~DCMD_LEN) | length;
case DCSR0 ... DCSR31:
channel = offset >> 2;
- if (s->chan[channel].request)
+ if (s->chan[channel].request)
return s->chan[channel].state | DCSR_REQPEND;
return s->chan[channel].state;
while (entry < dma->memmap + dma->memmap_size &&
entry->addr <= virt_base)
entry ++;
- }
+ }
memmove(entry + 1, entry,
(uint8_t *) (dma->memmap + dma->memmap_size ++) -
break;
case 0x00: /* Input port - ignore writes */
- break;
+ break;
default:
#ifdef VERBOSE
printf("%s: unknown register %02x\n", __func__, s->command);
}
static void xen_device_realize(DeviceListener *listener,
- DeviceState *dev)
+ DeviceState *dev)
{
XenIOState *state = container_of(listener, XenIOState, device_listener);
}
static void xen_device_unrealize(DeviceListener *listener,
- DeviceState *dev)
+ DeviceState *dev)
{
XenIOState *state = container_of(listener, XenIOState, device_listener);
int64_t sector_num;
if (s->select & 0x40) {
/* lba */
- if (!s->lba48) {
- sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
- (s->lcyl << 8) | s->sector;
- } else {
- sector_num = ((int64_t)s->hob_hcyl << 40) |
- ((int64_t) s->hob_lcyl << 32) |
- ((int64_t) s->hob_sector << 24) |
- ((int64_t) s->hcyl << 16) |
- ((int64_t) s->lcyl << 8) | s->sector;
- }
+ if (!s->lba48) {
+ sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
+ (s->lcyl << 8) | s->sector;
+ } else {
+ sector_num = ((int64_t)s->hob_hcyl << 40) |
+ ((int64_t) s->hob_lcyl << 32) |
+ ((int64_t) s->hob_sector << 24) |
+ ((int64_t) s->hcyl << 16) |
+ ((int64_t) s->lcyl << 8) | s->sector;
+ }
} else {
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
(s->select & 0x0f) * s->sectors + (s->sector - 1);
{
unsigned int cyl, r;
if (s->select & 0x40) {
- if (!s->lba48) {
+ if (!s->lba48) {
s->select = (s->select & 0xf0) | (sector_num >> 24);
s->hcyl = (sector_num >> 16);
s->lcyl = (sector_num >> 8);
s->sector = (sector_num);
- } else {
- s->sector = sector_num;
- s->lcyl = sector_num >> 8;
- s->hcyl = sector_num >> 16;
- s->hob_sector = sector_num >> 24;
- s->hob_lcyl = sector_num >> 32;
- s->hob_hcyl = sector_num >> 40;
- }
+ } else {
+ s->sector = sector_num;
+ s->lcyl = sector_num >> 8;
+ s->hcyl = sector_num >> 16;
+ s->hob_sector = sector_num >> 24;
+ s->hob_lcyl = sector_num >> 32;
+ s->hob_hcyl = sector_num >> 40;
+ }
} else {
cyl = sector_num / (s->heads * s->sectors);
r = sector_num % (s->heads * s->sectors);
* full sector count in ->nsector and ignore ->hob_nsector from now
*/
if (!s->lba48) {
- if (!s->nsector)
- s->nsector = 256;
+ if (!s->nsector)
+ s->nsector = 256;
} else {
- if (!s->nsector && !s->hob_nsector)
- s->nsector = 65536;
- else {
- int lo = s->nsector;
- int hi = s->hob_nsector;
+ if (!s->nsector && !s->hob_nsector)
+ s->nsector = 65536;
+ else {
+ int lo = s->nsector;
+ int hi = s->hob_nsector;
- s->nsector = (hi << 8) | lo;
- }
+ s->nsector = (hi << 8) | lo;
+ }
}
}
bus->ifs[1].feature = val;
break;
case ATA_IOPORT_WR_SECTOR_COUNT:
- ide_clear_hob(bus);
- bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
- bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
+ bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
bus->ifs[0].nsector = val;
bus->ifs[1].nsector = val;
break;
case ATA_IOPORT_WR_SECTOR_NUMBER:
- ide_clear_hob(bus);
- bus->ifs[0].hob_sector = bus->ifs[0].sector;
- bus->ifs[1].hob_sector = bus->ifs[1].sector;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_sector = bus->ifs[0].sector;
+ bus->ifs[1].hob_sector = bus->ifs[1].sector;
bus->ifs[0].sector = val;
bus->ifs[1].sector = val;
break;
case ATA_IOPORT_WR_CYLINDER_LOW:
- ide_clear_hob(bus);
- bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
- bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
+ bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
bus->ifs[0].lcyl = val;
bus->ifs[1].lcyl = val;
break;
case ATA_IOPORT_WR_CYLINDER_HIGH:
- ide_clear_hob(bus);
- bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
- bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
+ bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
bus->ifs[0].hcyl = val;
bus->ifs[1].hcyl = val;
break;
case ATA_IOPORT_WR_DEVICE_HEAD:
- /* FIXME: HOB readback uses bit 7 */
+ /* FIXME: HOB readback uses bit 7 */
bus->ifs[0].select = (val & ~0x10) | 0xa0;
bus->ifs[1].select = (val | 0x10) | 0xa0;
/* select drive */
} else if (!hob) {
ret = s->error;
} else {
- ret = s->hob_feature;
+ ret = s->hob_feature;
}
break;
case ATA_IOPORT_RR_SECTOR_COUNT:
} else if (!hob) {
ret = s->nsector & 0xff;
} else {
- ret = s->hob_nsector;
+ ret = s->hob_nsector;
}
break;
case ATA_IOPORT_RR_SECTOR_NUMBER:
} else if (!hob) {
ret = s->sector;
} else {
- ret = s->hob_sector;
+ ret = s->hob_sector;
}
break;
case ATA_IOPORT_RR_CYLINDER_LOW:
} else if (!hob) {
ret = s->lcyl;
} else {
- ret = s->hob_lcyl;
+ ret = s->hob_lcyl;
}
break;
case ATA_IOPORT_RR_CYLINDER_HIGH:
} else if (!hob) {
ret = s->hcyl;
} else {
- ret = s->hob_hcyl;
+ ret = s->hob_hcyl;
}
break;
case ATA_IOPORT_RR_DEVICE_HEAD:
.fields = (VMStateField[]) {
VMSTATE_INT32(req_nb_sectors, IDEState),
VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
- vmstate_info_uint8, uint8_t),
+ vmstate_info_uint8, uint8_t),
VMSTATE_INT32(cur_io_buffer_offset, IDEState),
VMSTATE_INT32(cur_io_buffer_len, IDEState),
VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
struct {
uint16_t file[256];
- uint8_t faddr;
+ uint8_t faddr;
uint8_t addr[3];
QEMUTimer *tm[3];
} pwm;
#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
#define KBD_CCMD_WRITE_OBUF 0xD2
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
+ initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
s->pin_func = value >> 14;
- else {
+ else {
s->kb.scan = (value >> 14) & 1;
s->kb.debounce = (value >> 11) & 7;
if (s->kb.intr && s->kb.scan) {
for (i = 0; i < MAX_APICS; i++) {
apic = local_apics[i];
- if (apic && apic->id == dest)
+ if (apic && apic->id == dest)
return i;
if (!apic)
break;
s->regs[GT_CPU] = val;
break;
case GT_MULTI:
- /* Read-only register as only one GT64xxx is present on the CPU bus */
+ /* Read-only register as only one GT64xxx is present on the CPU bus */
break;
/* CPU Address Decode */
case GT_CPUERR_DATALO:
case GT_CPUERR_DATAHI:
case GT_CPUERR_PARITY:
- /* Read-only registers, do nothing */
+ /* Read-only registers, do nothing */
break;
/* CPU Sync Barrier */
case GT_PCI0SYNC:
case GT_PCI1SYNC:
- /* Read-only registers, do nothing */
+ /* Read-only registers, do nothing */
break;
/* SDRAM and Device Address Decode */
sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
- }
+ }
} else if (!qtest_enabled()) {
/* not fatal */
warn_report("could not load MIPS bios '%s'", bios_name);
for(i = 0; i < MAX_IDE_BUS; i++)
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[MAX_IDE_DEVS * i],
- hd[MAX_IDE_DEVS * i + 1]);
+ hd[MAX_IDE_DEVS * i + 1]);
isa_create_simple(isa_bus, TYPE_I8042);
}
#define CB_START (1 << 7)
#define CHANNEL_NUM(v, b0, b1, b2) \
- ((((v) >> (2 + (b0))) & 4) | \
- (((v) >> (3 + (b1))) & 2) | \
- (((v) >> (4 + (b2))) & 1))
+ ((((v) >> (2 + (b0))) & 4) | \
+ (((v) >> (3 + (b1))) & 2) | \
+ (((v) >> (4 + (b2))) & 1))
static uint32_t max111x_read(MAX111xState *s)
{
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
const struct omap_l4_region_s *regions,
- const struct omap_l4_agent_info_s *agents,
- int cs)
+ const struct omap_l4_agent_info_s *agents,
+ int cs)
{
int i;
struct omap_target_agent_s *ta = NULL;
addr &= 0x3f;
switch (addr) {
case MIPSNET_DEV_ID:
- ret = be32_to_cpu(0x4d495053); /* MIPS */
+ ret = be32_to_cpu(0x4d495053); /* MIPS */
break;
case MIPSNET_DEV_ID + 4:
- ret = be32_to_cpu(0x4e455430); /* NET0 */
+ ret = be32_to_cpu(0x4e455430); /* NET0 */
break;
case MIPSNET_BUSY:
- ret = s->busy;
+ ret = s->busy;
break;
case MIPSNET_RX_DATA_COUNT:
- ret = s->rx_count;
+ ret = s->rx_count;
break;
case MIPSNET_TX_DATA_COUNT:
- ret = s->tx_count;
+ ret = s->tx_count;
break;
case MIPSNET_INT_CTL:
- ret = s->intctl;
+ ret = s->intctl;
s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
break;
case MIPSNET_INTERRUPT_INFO:
/* XXX: This seems to be a per-VPE interrupt number. */
- ret = 0;
+ ret = 0;
break;
case MIPSNET_RX_DATA_BUFFER:
if (s->rx_count) {
trace_mipsnet_write(addr, val);
switch (addr) {
case MIPSNET_TX_DATA_COUNT:
- s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
+ s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
s->tx_written = 0;
break;
case MIPSNET_INT_CTL:
isr = (s->isr & s->imr) & 0x7f;
#if defined(DEBUG_NE2000)
printf("NE2000: Set IRQ to %d (%02x %02x)\n",
- isr ? 1 : 0, s->isr, s->imr);
+ isr ? 1 : 0, s->isr, s->imr);
#endif
qemu_set_irq(s->irq, (isr != 0));
}
case EN0_ISR:
ret = s->isr;
break;
- case EN0_RSARLO:
- ret = s->rsar & 0x00ff;
- break;
- case EN0_RSARHI:
- ret = s->rsar >> 8;
- break;
+ case EN0_RSARLO:
+ ret = s->rsar & 0x00ff;
+ break;
+ case EN0_RSARHI:
+ ret = s->rsar >> 8;
+ break;
case EN1_PHYS ... EN1_PHYS + 5:
ret = s->phys[offset - EN1_PHYS];
break;
case EN2_STOPPG:
ret = s->stop >> 8;
break;
- case EN0_RTL8029ID0:
- ret = 0x50;
- break;
- case EN0_RTL8029ID1:
- ret = 0x43;
- break;
- case EN3_CONFIG0:
- ret = 0; /* 10baseT media */
- break;
- case EN3_CONFIG2:
- ret = 0x40; /* 10baseT active */
- break;
- case EN3_CONFIG3:
- ret = 0x40; /* Full duplex */
- break;
+ case EN0_RTL8029ID0:
+ ret = 0x50;
+ break;
+ case EN0_RTL8029ID1:
+ ret = 0x43;
+ break;
+ case EN3_CONFIG0:
+ ret = 0; /* 10baseT media */
+ break;
+ case EN3_CONFIG2:
+ ret = 0x40; /* 10baseT active */
+ break;
+ case EN3_CONFIG3:
+ ret = 0x40; /* Full duplex */
+ break;
default:
ret = 0x00;
break;
for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
if (strcmp(name, world_name(r->worlds[i])) == 0) {
return r->worlds[i];
- }
+ }
}
return NULL;
}
n->guest_hdr_len, -1);
if (out_num == VIRTQUEUE_MAX_SIZE) {
goto drop;
- }
+ }
out_num += 1;
out_sg = sg2;
- }
+ }
}
/*
* If host wants to see the guest header as is, we can
OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
static inline void vmxnet3_ring_init(PCIDevice *d,
- Vmxnet3Ring *ring,
+ Vmxnet3Ring *ring,
hwaddr pa,
uint32_t size,
uint32_t cell_size,
}
static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
- void *buff)
+ void *buff)
{
vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
}
static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
- void *buff)
+ void *buff)
{
vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
}
}
msix_clear_all_vectors(dev);
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
- ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
+ ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
msix_mask_all(dev, dev->msix_entries_nr);
static inline int pci_irq_state(PCIDevice *d, int irq_num)
{
- return (d->irq_state >> irq_num) & 0x1;
+ return (d->irq_state >> irq_num) & 0x1;
}
static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
{
- d->irq_state &= ~(0x1 << irq_num);
- d->irq_state |= level << irq_num;
+ d->irq_state &= ~(0x1 << irq_num);
+ d->irq_state |= level << irq_num;
}
static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
0, vmstate_info_pci_config,
PCIE_CONFIG_SPACE_SIZE),
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
- vmstate_info_pci_irq_state,
- PCI_NUM_PINS * sizeof(int32_t)),
+ vmstate_info_pci_irq_state,
+ PCI_NUM_PINS * sizeof(int32_t)),
VMSTATE_END_OF_LIST()
}
};
p = addr;
val = strtoul(p, &e, 16);
if (e == p)
- return -1;
+ return -1;
if (*e == ':') {
- bus = val;
- p = e + 1;
- val = strtoul(p, &e, 16);
- if (e == p)
- return -1;
- if (*e == ':') {
- dom = bus;
- bus = val;
- p = e + 1;
- val = strtoul(p, &e, 16);
- if (e == p)
- return -1;
- }
+ bus = val;
+ p = e + 1;
+ val = strtoul(p, &e, 16);
+ if (e == p)
+ return -1;
+ if (*e == ':') {
+ dom = bus;
+ bus = val;
+ p = e + 1;
+ val = strtoul(p, &e, 16);
+ if (e == p)
+ return -1;
+ }
}
slot = val;
/* if funcp == NULL func is 0 */
if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
- return -1;
+ return -1;
if (*e)
- return -1;
+ return -1;
*domp = dom;
*busp = bus;
}
static pcibus_t pci_bar_address(PCIDevice *d,
- int reg, uint8_t type, pcibus_t size)
+ int reg, uint8_t type, pcibus_t size)
{
pcibus_t new_addr, last_addr;
int bar = pci_bar(d, reg);
* let users address the bus using the device name.
*/
if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
- br->bus_name = dev->qdev.id;
+ br->bus_name = dev->qdev.id;
}
qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- /* XXX 405EP has no ECC interrupt */
+ /* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
ram_bases, ram_sizes, do_init);
/* External bus controller */
nb_nics1 = NE2000_NB_MAX;
for(i = 0; i < nb_nics1; i++) {
if (nd_table[i].model == NULL) {
- nd_table[i].model = g_strdup("ne2k_isa");
+ nd_table[i].model = g_strdup("ne2k_isa");
}
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
for(i = 0; i < MAX_IDE_BUS; i++) {
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[2 * i],
- hd[2 * i + 1]);
+ hd[2 * i + 1]);
}
cpu = POWERPC_CPU(first_cpu);
break;
case 0x0a: case 0x0b:
/* Openserver writes to these readonly registers on startup */
- return;
+ return;
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
/* Linux writes to these readonly registers on startup. */
return;
/* nothing to do */
break;
case 0x1a: /* CTEST2 */
- s->ctest2 = val & LSI_CTEST2_PCICIE;
- break;
+ s->ctest2 = val & LSI_CTEST2_PCICIE;
+ break;
case 0x1b: /* CTEST3 */
s->ctest3 = val & 0x0f;
break;
case PA_IRLMSK:
return s->irlmsk;
case PA_OUTPORT:
- return s->outport;
+ return s->outport;
case PA_POWOFF:
- return 0x00;
+ return 0x00;
case PA_VERREG:
- return 0x10;
+ return 0x10;
}
return 0;
case PA_IRLMSK:
s->irlmsk = value;
update_irl(s);
- break;
+ break;
case PA_OUTPORT:
- s->outport = value;
- break;
+ s->outport = value;
+ break;
case PA_POWOFF:
if (value & 1) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
break;
case PA_VERREG:
- /* Discard writes */
- break;
+ /* Discard writes */
+ break;
}
}
struct usb_hci_out_fifo_s {
uint8_t data[4096];
- int len;
+ int len;
} outcmd, outacl, outsco;
};
switch (value >> 8) {
case 0x22:
if (hs->kind == HID_MOUSE) {
- memcpy(data, qemu_mouse_hid_report_descriptor,
- sizeof(qemu_mouse_hid_report_descriptor));
+ memcpy(data, qemu_mouse_hid_report_descriptor,
+ sizeof(qemu_mouse_hid_report_descriptor));
p->actual_length = sizeof(qemu_mouse_hid_report_descriptor);
} else if (hs->kind == HID_TABLET) {
memcpy(data, qemu_tablet_hid_report_descriptor,
- sizeof(qemu_tablet_hid_report_descriptor));
+ sizeof(qemu_tablet_hid_report_descriptor));
p->actual_length = sizeof(qemu_tablet_hid_report_descriptor);
} else if (hs->kind == HID_KEYBOARD) {
memcpy(data, qemu_keyboard_hid_report_descriptor,
static const uint8_t qemu_hub_hub_descriptor[] =
{
- 0x00, /* u8 bLength; patched in later */
- 0x29, /* u8 bDescriptorType; Hub-descriptor */
- 0x00, /* u8 bNbrPorts; (patched later) */
- 0x0a, /* u16 wHubCharacteristics; */
- 0x00, /* (per-port OC, no power switching) */
- 0x01, /* u8 bPwrOn2pwrGood; 2ms */
- 0x00 /* u8 bHubContrCurrent; 0 mA */
+ 0x00, /* u8 bLength; patched in later */
+ 0x29, /* u8 bDescriptorType; Hub-descriptor */
+ 0x00, /* u8 bNbrPorts; (patched later) */
+ 0x0a, /* u16 wHubCharacteristics; */
+ 0x00, /* (per-port OC, no power switching) */
+ 0x01, /* u8 bPwrOn2pwrGood; 2ms */
+ 0x00 /* u8 bHubContrCurrent; 0 mA */
/* DeviceRemovable and PortPwrCtrlMask patched in later */
};
/* ------------------------------------------------------------- */
static int xen_config_dev_dirs(const char *ftype, const char *btype, int vdev,
- char *fe, char *be, int len)
+ char *fe, char *be, int len)
{
char *dom;
if (!xs_mkdir(xenstore, 0, path)) {
fprintf(stderr, "%s: xs_mkdir %s: failed\n", __func__, path);
- return -1;
+ return -1;
}
if (!xs_set_permissions(xenstore, 0, path, perms_ro, 2)) {
fprintf(stderr, "%s: xs_set_permissions failed\n", __func__);
- return -1;
+ return -1;
}
for (i = 0; writable[i]; i++) {
/* cpus */
for (i = 0; i < smp_cpus; i++) {
- snprintf(path, sizeof(path), "cpu/%d/availability",i);
- xenstore_write_str(dom, path, "online");
+ snprintf(path, sizeof(path), "cpu/%d/availability",i);
+ xenstore_write_str(dom, path, "online");
}
xenstore_write_int(vm, "vcpu_avail", smp_cpus);
xenstore_write_int(vm, "vcpus", smp_cpus);
/* ARM-specific values for sh_flags */
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined
- in the input to a link step */
+ in the input to a link step */
/* ARM-specific program header flags */
#define PF_ARM_SB 0x10000000 /* Segment contains the location
- addressed by the static base */
+ addressed by the static base */
/* ARM relocs. */
#define R_ARM_NONE 0 /* No reloc */
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative
- offset to GOT */
+ offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch
- prediction. */
+ prediction. */
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
/* Additional section indeces. */
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared
- symbols in ANSI C. */
+ symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
/* Legal values for sh_type field of Elf32_Shdr. */
#define ACPI_BITMASK_WAKE_STATUS 0x8000
#define ACPI_BITMASK_ALL_FIXED_STATUS (\
- ACPI_BITMASK_TIMER_STATUS | \
- ACPI_BITMASK_BUS_MASTER_STATUS | \
- ACPI_BITMASK_GLOBAL_LOCK_STATUS | \
- ACPI_BITMASK_POWER_BUTTON_STATUS | \
- ACPI_BITMASK_SLEEP_BUTTON_STATUS | \
- ACPI_BITMASK_RT_CLOCK_STATUS | \
- ACPI_BITMASK_WAKE_STATUS)
+ ACPI_BITMASK_TIMER_STATUS | \
+ ACPI_BITMASK_BUS_MASTER_STATUS | \
+ ACPI_BITMASK_GLOBAL_LOCK_STATUS | \
+ ACPI_BITMASK_POWER_BUTTON_STATUS | \
+ ACPI_BITMASK_SLEEP_BUTTON_STATUS | \
+ ACPI_BITMASK_RT_CLOCK_STATUS | \
+ ACPI_BITMASK_WAKE_STATUS)
/* PM1x_EN */
#define ACPI_BITMASK_TIMER_ENABLE 0x0001
}
if (pentry)
- *pentry = (uint64_t)(elf_sword)ehdr.e_entry;
+ *pentry = (uint64_t)(elf_sword)ehdr.e_entry;
glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, sym_cb);
extern const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT];
#define ide_cmd_is_read(s) \
- ((s)->dma_cmd == IDE_DMA_READ)
+ ((s)->dma_cmd == IDE_DMA_READ)
typedef struct IDEBufferedRequest {
QLIST_ENTRY(IDEBufferedRequest) list;
int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
void sh_intc_toggle_source(struct intc_source *source,
- int enable_adj, int assert_adj);
+ int enable_adj, int assert_adj);
void sh_intc_register_sources(struct intc_desc *desc,
- struct intc_vect *vectors,
- int nr_vectors,
- struct intc_group *groups,
- int nr_groups);
+ struct intc_vect *vectors,
+ int nr_vectors,
+ struct intc_group *groups,
+ int nr_groups);
int sh_intc_init(MemoryRegion *sysmem,
struct intc_desc *desc,
- int nr_sources,
- struct intc_mask_reg *mask_regs,
- int nr_mask_regs,
- struct intc_prio_reg *prio_regs,
- int nr_prio_regs);
+ int nr_sources,
+ struct intc_mask_reg *mask_regs,
+ int nr_mask_regs,
+ struct intc_prio_reg *prio_regs,
+ int nr_prio_regs);
void sh_intc_set_irl(void *opaque, int n, int level);
* to be ineffective where _req is a struct which consists of only bitfields.
*/
#define RING_COPY_REQUEST(_r, _idx, _req) do { \
- /* Use volatile to force the copy into _req. */ \
- *(_req) = *(volatile typeof(_req))RING_GET_REQUEST(_r, _idx); \
+ /* Use volatile to force the copy into _req. */ \
+ *(_req) = *(volatile typeof(_req))RING_GET_REQUEST(_r, _idx); \
} while (0)
#define RING_GET_RESPONSE(_r, _idx) \
qemu_acl *qemu_acl_find(const char *aclname);
int qemu_acl_party_is_allowed(qemu_acl *acl,
- const char *party);
+ const char *party);
void qemu_acl_reset(qemu_acl *acl);
int qemu_acl_append(qemu_acl *acl,
- int deny,
- const char *match);
+ int deny,
+ const char *match);
int qemu_acl_insert(qemu_acl *acl,
- int deny,
- const char *match,
- int index);
+ int deny,
+ const char *match,
+ int index);
int qemu_acl_remove(qemu_acl *acl,
- const char *match);
+ const char *match);
#endif /* QEMU_ACL_H */
size_t iov_from_buf_full(const struct iovec *iov, unsigned int iov_cnt,
size_t offset, const void *buf, size_t bytes);
size_t iov_to_buf_full(const struct iovec *iov, const unsigned int iov_cnt,
- size_t offset, void *buf, size_t bytes);
+ size_t offset, void *buf, size_t bytes);
static inline size_t
iov_from_buf(const struct iovec *iov, unsigned int iov_cnt,
#define TYPE_ROM 0x05
#define TYPE_SCANNER 0x06
#define TYPE_MOD 0x07 /* Magneto-optical disk -
- * - treated as TYPE_DISK */
+ * - treated as TYPE_DISK */
#define TYPE_MEDIUM_CHANGER 0x08
#define TYPE_STORAGE_ARRAY 0x0c /* Storage array device */
#define TYPE_ENCLOSURE 0x0d /* Enclosure Services Device */
typedef void (QEMUBalloonStatus)(void *opaque, BalloonInfo *info);
int qemu_add_balloon_handler(QEMUBalloonEvent *event_func,
- QEMUBalloonStatus *stat_func, void *opaque);
+ QEMUBalloonStatus *stat_func, void *opaque);
void qemu_remove_balloon_handler(void *opaque);
bool qemu_balloon_is_inhibited(void);
void qemu_balloon_inhibit(bool state);
int retval;
if(fstat(bprm->fd, &st) < 0) {
- return(-errno);
+ return(-errno);
}
mode = st.st_mode;
if(!S_ISREG(mode)) { /* Must be regular file */
- return(-EACCES);
+ return(-EACCES);
}
if(!(mode & 0111)) { /* Must have at least one execute bit set */
- return(-EACCES);
+ return(-EACCES);
}
bprm->e_uid = geteuid();
/* Set-uid? */
if(mode & S_ISUID) {
- bprm->e_uid = st.st_uid;
+ bprm->e_uid = st.st_uid;
}
/* Set-gid? */
* executable.
*/
if ((mode & (S_ISGID | S_IXGRP)) == (S_ISGID | S_IXGRP)) {
- bprm->e_gid = st.st_gid;
+ bprm->e_gid = st.st_gid;
}
retval = read(bprm->fd, bprm->buf, BPRM_BUF_SIZE);
if (retval < 0) {
- perror("prepare_binprm");
- exit(-1);
+ perror("prepare_binprm");
+ exit(-1);
}
if (retval < BPRM_BUF_SIZE) {
/* Make sure the rest of the loader won't read garbage. */
target_argc = argc - optind;
target_argv = calloc(target_argc + 1, sizeof (char *));
if (target_argv == NULL) {
- (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
- exit(EXIT_FAILURE);
+ (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
+ exit(EXIT_FAILURE);
}
/*
end = start + len;
real_end = HOST_PAGE_ALIGN(end);
- /*
- * Test if requested memory area fits target address space
- * It can fail only on 64-bit host with 32-bit target.
- * On any other target/host host mmap() handles this error correctly.
- */
+ /*
+ * Test if requested memory area fits target address space
+ * It can fail only on 64-bit host with 32-bit target.
+ * On any other target/host host mmap() handles this error correctly.
+ */
if (!guest_range_valid(start, len)) {
errno = ENOMEM;
goto fail;
abi_ulong env_strings;
abi_ulong file_string;
uint32_t elf_flags;
- int personality;
+ int personality;
abi_ulong alignment;
/* The fields below are used in FDPIC mode. */
struct linux_binprm {
char buf[BPRM_BUF_SIZE] __attribute__((aligned));
abi_ulong p;
- int fd;
+ int fd;
int e_uid, e_gid;
int argc, envc;
char **argv;
}
#endif
- ret = -TARGET_EFAULT;
+ ret = -TARGET_EFAULT;
if (!lock_user_struct(VERIFY_READ, uss, uss_addr, 1)) {
goto out;
}
__get_user(ss.ss_flags, &uss->ss_flags);
unlock_user_struct(uss, uss_addr, 0);
- ret = -TARGET_EPERM;
- if (on_sig_stack(sp))
+ ret = -TARGET_EPERM;
+ if (on_sig_stack(sp))
goto out;
- ret = -TARGET_EINVAL;
- if (ss.ss_flags != TARGET_SS_DISABLE
+ ret = -TARGET_EINVAL;
+ if (ss.ss_flags != TARGET_SS_DISABLE
&& ss.ss_flags != TARGET_SS_ONSTACK
&& ss.ss_flags != 0)
goto out;
- if (ss.ss_flags == TARGET_SS_DISABLE) {
+ if (ss.ss_flags == TARGET_SS_DISABLE) {
ss.ss_size = 0;
ss.ss_sp = 0;
- } else {
+ } else {
ret = -TARGET_ENOMEM;
if (ss.ss_size < minstacksize) {
goto out;
}
- }
+ }
target_sigaltstack_used.ss_sp = ss.ss_sp;
target_sigaltstack_used.ss_size = ss.ss_size;
for (arg_ptr_addr = arg2; ; arg_ptr_addr += sizeof(abi_ulong)) {
abi_ulong *arg_ptr, arg_addr;
- arg_ptr = lock_user(VERIFY_READ, arg_ptr_addr, sizeof(abi_ulong), 1);
+ arg_ptr = lock_user(VERIFY_READ, arg_ptr_addr, sizeof(abi_ulong), 1);
if (!arg_ptr)
return;
arg_addr = tswapal(*arg_ptr);
- unlock_user(arg_ptr, arg_ptr_addr, 0);
+ unlock_user(arg_ptr, arg_ptr_addr, 0);
if (!arg_addr)
break;
if ((s = lock_user_string(arg_addr))) {
if ((ghptr = lock_user(VERIFY_WRITE, gaddr, len, 0))) {
memcpy(ghptr, hptr, len);
- unlock_user(ghptr, gaddr, len);
+ unlock_user(ghptr, gaddr, len);
} else
ret = -TARGET_EFAULT;
#define CHECK_IF_IN_TRAP() \
if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
- newflags |= TF_MASK
+ newflags |= TF_MASK
#define VM86_FAULT_RETURN \
if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
uint16_t net_checksum_finish(uint32_t sum)
{
while (sum>>16)
- sum = (sum & 0xFFFF)+(sum >> 16);
+ sum = (sum & 0xFFFF)+(sum >> 16);
return ~sum;
}
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+ return;
}
if (irq_intercept_dev) {
} else {
qtest_send(chr, "OK\n");
}
- return;
+ return;
}
QLIST_FOREACH(ngl, &dev->gpios, node) {
static void gen_ieee_intcvt(DisasContext *ctx,
void (*helper)(TCGv, TCGv_ptr, TCGv),
- int rb, int rc, int fn11)
+ int rb, int rc, int fn11)
{
TCGv vb, vc;
/* Exception starts with dslot cleared. */
env->dslot = 0;
}
-
+
if (env->pregs[PR_CCS] & U_FLAG) {
/* Swap stack pointers. */
env->pregs[PR_USP] = env->regs[R_SP];
struct cris_mmu_result
{
- uint32_t phy;
- int prot;
- int bf_vec;
+ uint32_t phy;
+ int prot;
+ int bf_vec;
};
void cris_mmu_init(CPUCRISState *env);
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid);
int cris_mmu_translate(struct cris_mmu_result *res,
- CPUCRISState *env, uint32_t vaddr,
- int rw, int mmu_idx, int debug);
+ CPUCRISState *env, uint32_t vaddr,
+ int rw, int mmu_idx, int debug);
}
static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
- TCGv dd, TCGv ds, TCGv sd, TCGv ss)
+ TCGv dd, TCGv ds, TCGv sd, TCGv ss)
{
if (sext) {
t_gen_sext(dd, sd, size);
case 0x172:
case 0x173:
if (b1 >= 2) {
- goto unknown_op;
+ goto unknown_op;
}
val = x86_ldub_code(env, s);
if (is_xmm) {
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
tcg_gen_movi_i32(s->tmp2_i32, val);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
tcg_gen_movi_i32(s->tmp2_i32, val);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
gen_jmp_im(s, pc_start - s->cs_base);
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
gen_helper_rdtsc(cpu_env);
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
- }
+ }
gen_helper_mfc0_count(arg, cpu_env);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
- dc->mmuidx, memop);
+ dc->mmuidx, memop);
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
reg_names[srca], reg_names[srcb]);
tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
/* jmp *tb. */
tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
- (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
- + stack_addend);
+ (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ + stack_addend);
#else
# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64
if (guest_base) {
int test_##N (long a) \
{ \
int res = 1; \
- \
+ \
asm ("cmov"#N" %1,$31,%0" \
: "+r" (res) : "r" (a)); \
return !res; \
int test_##N (long a) \
{ \
int res = 1; \
- \
+ \
asm ("b"#N" %1,1f\n\t" \
"addq $31,$31,%0\n\t" \
"1: unop\n" \
#define __syscall_return(type, res) \
do { \
- return (type) (res); \
+ return (type) (res); \
} while (0)
#define _syscall0(type,name) \
"mov %0,r0" \
: "=r" (__res) \
: "r" ((long)(arg1)) \
- : "r0","lr"); \
+ : "r0","lr"); \
__syscall_return(type,__res); \
}
"mov\t%0,r0" \
: "=r" (__res) \
: "r" ((long)(arg1)),"r" ((long)(arg2)) \
- : "r0","r1","lr"); \
+ : "r0","r1","lr"); \
__syscall_return(type,__res); \
}
"mov\tr3,%4\n\t" \
__syscall(name) \
"mov\t%0,r0" \
- : "=r" (__res) \
- : "r" ((long)(arg1)),"r" ((long)(arg2)),"r" ((long)(arg3)),"r" ((long)(arg4)) \
- : "r0","r1","r2","r3","lr"); \
+ : "=r" (__res) \
+ : "r" ((long)(arg1)),"r" ((long)(arg2)),"r" ((long)(arg3)),"r" ((long)(arg4)) \
+ : "r0","r1","r2","r3","lr"); \
__syscall_return(type,__res); \
}
"mov\tr4,%5\n\t" \
__syscall(name) \
"mov\t%0,r0" \
- : "=r" (__res) \
- : "r" ((long)(arg1)),"r" ((long)(arg2)),"r" ((long)(arg3)),"r" ((long)(arg4)), \
- "r" ((long)(arg5)) \
- : "r0","r1","r2","r3","r4","lr"); \
+ : "=r" (__res) \
+ : "r" ((long)(arg1)),"r" ((long)(arg2)),"r" ((long)(arg3)),"r" ((long)(arg4)), \
+ "r" ((long)(arg5)) \
+ : "r0","r1","r2","r3","r4","lr"); \
__syscall_return(type,__res); \
}
if (parts < 3)
version <<= 8 * (3 - parts);
- if (version < __LINUX_KERNEL_VERSION)
- err();
- pass();
- exit(0);
+ if (version < __LINUX_KERNEL_VERSION)
+ err();
+ pass();
+ exit(0);
}
/* Check that we can map a non-multiple of a page and still get a full page. */
a = mmap (NULL, 0x4c, PROT_READ | PROT_WRITE | PROT_EXEC,
- MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
if (a == NULL || a == (unsigned char *) -1)
abort ();
{
fnam = malloc (strlen (argv[0]) + 2);
if (fnam == NULL)
- abort ();
+ abort ();
strcpy (fnam, "/");
strcat (fnam, argv[0]);
}
syscall (SYS_set_thread_area, old_tp);
if (tp != 0xeddeed00) {
- * (volatile int *) 0 = 0;
+ * (volatile int *) 0 = 0;
perror ("tls2");
abort ();
}
{
int __res;
__asm__ volatile ("movl %%ecx,%%ebx\n"\
- "int $0x80" \
- : "=a" (__res) : "0" (__NR_exit),"c" ((long)(status)));
+ "int $0x80" \
+ : "=a" (__res) : "0" (__NR_exit),"c" ((long)(status)));
}
static inline int write(int fd, const char * buf, int len)
{
int status;
__asm__ volatile ("pushl %%ebx\n"\
- "movl %%esi,%%ebx\n"\
- "int $0x80\n" \
- "popl %%ebx\n"\
- : "=a" (status) \
- : "0" (__NR_write),"S" ((long)(fd)),"c" ((long)(buf)),"d" ((long)(len)));
+ "movl %%esi,%%ebx\n"\
+ "int $0x80\n" \
+ "popl %%ebx\n"\
+ : "=a" (status) \
+ : "0" (__NR_write),"S" ((long)(fd)),"c" ((long)(buf)),"d" ((long)(len)));
return status;
}
" syscall \n"
" .set pop "
:
- : "i" (__NR_exit), "r" (__a0)
- : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
- "memory");
+ : "i" (__NR_exit), "r" (__a0)
+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
+ "memory");
}
static inline int write(int fd, const char *buf, int len)
" .set pop "
: "=r" (__v0), "=r" (__a3)
: "i" (__NR_write), "r" (__a0), "r" (__a1), "r" (__a2)
- : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
- "memory");
+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24",
+ "memory");
/* if (__a3 == 0) */
return (int) __v0;
j = context->count[0];
if ((context->count[0] += len << 3) < j)
- context->count[1]++;
+ context->count[1]++;
context->count[1] += (len>>29);
j = (j >> 3) & 63;
if ((j + len) > 63) {
for (i = 0; i < 2; i++)
{
- uint32_t t = context->count[i];
- int j;
+ uint32_t t = context->count[i];
+ int j;
- for (j = 0; j < 4; t >>= 8, j++)
- *--fcp = (unsigned char) t;
+ for (j = 0; j < 4; t >>= 8, j++)
+ *--fcp = (unsigned char) t;
}
#else
for (i = 0; i < 8; i++) {
c = 0200;
SHA1Update(context, &c, 1);
while ((context->count[0] & 504) != 448) {
- c = 0000;
+ c = 0000;
SHA1Update(context, &c, 1);
}
SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */
break;
case VHOST_USER_SET_FEATURES:
- g_assert_cmpint(msg.payload.u64 & (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES),
- !=, 0ULL);
+ g_assert_cmpint(msg.payload.u64 & (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES),
+ !=, 0ULL);
if (s->test_flags == TEST_FLAGS_DISCONNECT) {
qemu_chr_fe_disconnect(chr);
s->test_flags = TEST_FLAGS_BAD;
#include "qemu-common.h"
typedef struct {
- const char* name;
- int keysym;
+ const char* name;
+ int keysym;
} name2keysym_t;
/* scancode without modifiers */
pf.rshift = 0;
break;
case PIXMAN_TYPE_BGRA:
- pf.bshift = bpp - pf.bbits;
+ pf.bshift = bpp - pf.bbits;
pf.gshift = bpp - (pf.bbits + pf.gbits);
pf.rshift = bpp - (pf.bbits + pf.gbits + pf.rbits);
pf.ashift = 0;
/* Change Log:
V0.02 : 2008/02/04 : Fix mis encode/decode when width != scanline
- (Thanks Johannes Schindelin, author of LibVNC
- Server/Client)
+ (Thanks Johannes Schindelin, author of LibVNC
+ Server/Client)
V0.01 : 2007/02/06 : Initial release
*/
buffer_init(&vs->zrle.zlib, "vnc-zrle-zlib/%p", sioc);
if (skipauth) {
- vs->auth = VNC_AUTH_NONE;
- vs->subauth = VNC_AUTH_INVALID;
+ vs->auth = VNC_AUTH_NONE;
+ vs->subauth = VNC_AUTH_INVALID;
} else {
if (websocket) {
vs->auth = vd->ws_auth;
* Find the next set bit in a memory region.
*/
unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
- unsigned long offset)
+ unsigned long offset)
{
const unsigned long *p = addr + BIT_WORD(offset);
unsigned long result = offset & ~(BITS_PER_LONG-1);
* Linus' asm-alpha/bitops.h.
*/
unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size,
- unsigned long offset)
+ unsigned long offset)
{
const unsigned long *p = addr + BIT_WORD(offset);
unsigned long result = offset & ~(BITS_PER_LONG-1);
#ifdef _FIPS_DEBUG
fprintf(stderr, "FIPS mode %s (requested %s)\n",
- (fips_enabled ? "enabled" : "disabled"),
- (requested ? "enabled" : "disabled"));
+ (fips_enabled ? "enabled" : "disabled"),
+ (requested ? "enabled" : "disabled"));
#endif
}
/* create socket + bind/listen */
for (e = res; e != NULL; e = e->ai_next) {
getnameinfo((struct sockaddr*)e->ai_addr,e->ai_addrlen,
- uaddr,INET6_ADDRSTRLEN,uport,32,
- NI_NUMERICHOST | NI_NUMERICSERV);
+ uaddr,INET6_ADDRSTRLEN,uport,32,
+ NI_NUMERICHOST | NI_NUMERICSERV);
port_min = inet_getport(e);
port_max = saddr->has_to ? saddr->to + port_offset : port_min;
projects / mirror_qemu.git / commitdiff