[qemu.git] / hw / display / tcx.c

/*
 * QEMU TCX Frame buffer
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu-common.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
#include "hw/sysbus.h"

#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16
#define TCX_THC_NREGS_8  0x081c
#define TCX_THC_NREGS_24 0x1000
#define TCX_TEC_NREGS    0x1000

#define TYPE_TCX "SUNW,tcx"
#define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)

typedef struct TCXState {
    SysBusDevice parent_obj;

    QemuConsole *con;
    uint8_t *vram;
    uint32_t *vram24, *cplane;
    MemoryRegion vram_mem;
    MemoryRegion vram_8bit;
    MemoryRegion vram_24bit;
    MemoryRegion vram_cplane;
    MemoryRegion dac;
    MemoryRegion tec;
    MemoryRegion thc24;
    MemoryRegion thc8;
    ram_addr_t vram24_offset, cplane_offset;
    uint32_t vram_size;
    uint32_t palette[256];
    uint8_t r[256], g[256], b[256];
    uint16_t width, height, depth;
    uint8_t dac_index, dac_state;
} TCXState;

static void tcx_set_dirty(TCXState *s)
{
    memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
}

static void tcx24_set_dirty(TCXState *s)
{
    memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
    memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
}

static void update_palette_entries(TCXState *s, int start, int end)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int i;

    for (i = start; i < end; i++) {
        switch (surface_bits_per_pixel(surface)) {
        default:
        case 8:
            s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
            break;
        case 15:
            s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
            break;
        case 16:
            s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
            break;
        case 32:
            if (is_surface_bgr(surface)) {
                s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
            } else {
                s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
            }
            break;
        }
    }
    if (s->depth == 24) {
        tcx24_set_dirty(s);
    } else {
        tcx_set_dirty(s);
    }
}

static void tcx_draw_line32(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line16(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint16_t *p = (uint16_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line8(TCXState *s1, uint8_t *d,
                           const uint8_t *s, int width)
{
    int x;
    uint8_t val;

    for(x = 0; x < width; x++) {
        val = *s++;
        *d++ = s1->palette[val];
    }
}

/*
  XXX Could be much more optimal:
  * detect if line/page/whole screen is in 24 bit mode
  * if destination is also BGR, use memcpy
  */
static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
                                     const uint8_t *s, int width,
                                     const uint32_t *cplane,
                                     const uint32_t *s24)
{
    DisplaySurface *surface = qemu_console_surface(s1->con);
    int x, bgr, r, g, b;
    uint8_t val, *p8;
    uint32_t *p = (uint32_t *)d;
    uint32_t dval;

    bgr = is_surface_bgr(surface);
    for(x = 0; x < width; x++, s++, s24++) {
        if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
            // 24-bit direct, BGR order
            p8 = (uint8_t *)s24;
            p8++;
            b = *p8++;
            g = *p8++;
            r = *p8;
            if (bgr)
                dval = rgb_to_pixel32bgr(r, g, b);
            else
                dval = rgb_to_pixel32(r, g, b);
        } else {
            val = *s;
            dval = s1->palette[val];
        }
        *p++ = dval;
    }
}

static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
                              ram_addr_t cpage)
{
    int ret;

    ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
                                  DIRTY_MEMORY_VGA);
    ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
                                   DIRTY_MEMORY_VGA);
    ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
                                   DIRTY_MEMORY_VGA);
    return ret;
}

static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
                               ram_addr_t page_max, ram_addr_t page24,
                              ram_addr_t cpage)
{
    memory_region_reset_dirty(&ts->vram_mem,
                              page_min,
                              (page_max - page_min) + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
    memory_region_reset_dirty(&ts->vram_mem,
                              page24 + page_min * 4,
                              (page_max - page_min) * 4 + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
    memory_region_reset_dirty(&ts->vram_mem,
                              cpage + page_min * 4,
                              (page_max - page_min) * 4 + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
}

/* Fixed line length 1024 allows us to do nice tricks not possible on
   VGA... */
static void tcx_update_display(void *opaque)
{
    TCXState *ts = opaque;
    DisplaySurface *surface = qemu_console_surface(ts->con);
    ram_addr_t page, page_min, page_max;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);

    if (surface_bits_per_pixel(surface) == 0) {
        return;
    }

    page = 0;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = surface_data(surface);
    s = ts->vram;
    dd = surface_stride(surface);
    ds = 1024;

    switch (surface_bits_per_pixel(surface)) {
    case 32:
        f = tcx_draw_line32;
        break;
    case 15:
    case 16:
        f = tcx_draw_line16;
        break;
    default:
    case 8:
        f = tcx_draw_line8;
        break;
    case 0:
        return;
    }

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
        if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
                                    DIRTY_MEMORY_VGA)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_gfx_update(ts->con, 0, y_start,
                               ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_gfx_update(ts->con, 0, y_start,
                       ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        memory_region_reset_dirty(&ts->vram_mem,
                                  page_min,
                                  (page_max - page_min) + TARGET_PAGE_SIZE,
                                  DIRTY_MEMORY_VGA);
    }
}

static void tcx24_update_display(void *opaque)
{
    TCXState *ts = opaque;
    DisplaySurface *surface = qemu_console_surface(ts->con);
    ram_addr_t page, page_min, page_max, cpage, page24;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    uint32_t *cptr, *s24;

    if (surface_bits_per_pixel(surface) != 32) {
            return;
    }

    page = 0;
    page24 = ts->vram24_offset;
    cpage = ts->cplane_offset;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = surface_data(surface);
    s = ts->vram;
    s24 = ts->vram24;
    cptr = ts->cplane;
    dd = surface_stride(surface);
    ds = 1024;

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
            page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
        if (check_dirty(ts, page, page24, cpage)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_gfx_update(ts->con, 0, y_start,
                               ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
            cptr += ds * 4;
            s24 += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_gfx_update(ts->con, 0, y_start,
                       ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        reset_dirty(ts, page_min, page_max, page24, cpage);
    }
}

static void tcx_invalidate_display(void *opaque)
{
    TCXState *s = opaque;

    tcx_set_dirty(s);
    qemu_console_resize(s->con, s->width, s->height);
}

static void tcx24_invalidate_display(void *opaque)
{
    TCXState *s = opaque;

    tcx_set_dirty(s);
    tcx24_set_dirty(s);
    qemu_console_resize(s->con, s->width, s->height);
}

static int vmstate_tcx_post_load(void *opaque, int version_id)
{
    TCXState *s = opaque;

    update_palette_entries(s, 0, 256);
    if (s->depth == 24) {
        tcx24_set_dirty(s);
    } else {
        tcx_set_dirty(s);
    }

    return 0;
}

static const VMStateDescription vmstate_tcx = {
    .name ="tcx",
    .version_id = 4,
    .minimum_version_id = 4,
    .minimum_version_id_old = 4,
    .post_load = vmstate_tcx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINT16(height, TCXState),
        VMSTATE_UINT16(width, TCXState),
        VMSTATE_UINT16(depth, TCXState),
        VMSTATE_BUFFER(r, TCXState),
        VMSTATE_BUFFER(g, TCXState),
        VMSTATE_BUFFER(b, TCXState),
        VMSTATE_UINT8(dac_index, TCXState),
        VMSTATE_UINT8(dac_state, TCXState),
        VMSTATE_END_OF_LIST()
    }
};

static void tcx_reset(DeviceState *d)
{
    TCXState *s = TCX(d);

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);
    s->r[255] = s->g[255] = s->b[255] = 255;
    update_palette_entries(s, 0, 256);
    memset(s->vram, 0, MAXX*MAXY);
    memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
                              DIRTY_MEMORY_VGA);
    s->dac_index = 0;
    s->dac_state = 0;
}

static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
                              unsigned size)
{
    return 0;
}

static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
                           unsigned size)
{
    TCXState *s = opaque;

    switch (addr) {
    case 0:
        s->dac_index = val >> 24;
        s->dac_state = 0;
        break;
    case 4:
        switch (s->dac_state) {
        case 0:
            s->r[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 1:
            s->g[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 2:
            s->b[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
        default:
            s->dac_state = 0;
            break;
        }
        break;
    default:
        break;
    }
}

static const MemoryRegionOps tcx_dac_ops = {
    .read = tcx_dac_readl,
    .write = tcx_dac_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static uint64_t dummy_readl(void *opaque, hwaddr addr,
                            unsigned size)
{
    return 0;
}

static void dummy_writel(void *opaque, hwaddr addr,
                         uint64_t val, unsigned size)
{
}

static const MemoryRegionOps dummy_ops = {
    .read = dummy_readl,
    .write = dummy_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static const GraphicHwOps tcx_ops = {
    .invalidate = tcx_invalidate_display,
    .gfx_update = tcx_update_display,
};

static const GraphicHwOps tcx24_ops = {
    .invalidate = tcx24_invalidate_display,
    .gfx_update = tcx24_update_display,
};

static int tcx_init1(SysBusDevice *dev)
{
    TCXState *s = TCX(dev);
    ram_addr_t vram_offset = 0;
    int size;
    uint8_t *vram_base;

    memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
                           s->vram_size * (1 + 4 + 4));
    vmstate_register_ram_global(&s->vram_mem);
    vram_base = memory_region_get_ram_ptr(&s->vram_mem);

    /* 8-bit plane */
    s->vram = vram_base;
    size = s->vram_size;
    memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
                             &s->vram_mem, vram_offset, size);
    sysbus_init_mmio(dev, &s->vram_8bit);
    vram_offset += size;
    vram_base += size;

    /* DAC */
    memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s,
                          "tcx.dac", TCX_DAC_NREGS);
    sysbus_init_mmio(dev, &s->dac);

    /* TEC (dummy) */
    memory_region_init_io(&s->tec, OBJECT(s), &dummy_ops, s,
                          "tcx.tec", TCX_TEC_NREGS);
    sysbus_init_mmio(dev, &s->tec);
    /* THC: NetBSD writes here even with 8-bit display: dummy */
    memory_region_init_io(&s->thc24, OBJECT(s), &dummy_ops, s, "tcx.thc24",
                          TCX_THC_NREGS_24);
    sysbus_init_mmio(dev, &s->thc24);

    if (s->depth == 24) {
        /* 24-bit plane */
        size = s->vram_size * 4;
        s->vram24 = (uint32_t *)vram_base;
        s->vram24_offset = vram_offset;
        memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
                                 &s->vram_mem, vram_offset, size);
        sysbus_init_mmio(dev, &s->vram_24bit);
        vram_offset += size;
        vram_base += size;

        /* Control plane */
        size = s->vram_size * 4;
        s->cplane = (uint32_t *)vram_base;
        s->cplane_offset = vram_offset;
        memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
                                 &s->vram_mem, vram_offset, size);
        sysbus_init_mmio(dev, &s->vram_cplane);

        s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s);
    } else {
        /* THC 8 bit (dummy) */
        memory_region_init_io(&s->thc8, OBJECT(s), &dummy_ops, s, "tcx.thc8",
                              TCX_THC_NREGS_8);
        sysbus_init_mmio(dev, &s->thc8);

        s->con = graphic_console_init(DEVICE(dev), &tcx_ops, s);
    }

    qemu_console_resize(s->con, s->width, s->height);
    return 0;
}

static Property tcx_properties[] = {
    DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
    DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
    DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
    DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void tcx_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = tcx_init1;
    dc->reset = tcx_reset;
    dc->vmsd = &vmstate_tcx;
    dc->props = tcx_properties;
}

static const TypeInfo tcx_info = {
    .name          = TYPE_TCX,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(TCXState),
    .class_init    = tcx_class_init,
};

static void tcx_register_types(void)
{
    type_register_static(&tcx_info);
}

type_init(tcx_register_types)
Commit	Line	Data
420557e8	1	/*
6f7e9aec	2	* QEMU TCX Frame buffer
5fafdf24	3	*
6f7e9aec	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
f40070c3	24
077805fa	25	#include "qemu-common.h"
28ecbaee PB	26	#include "ui/console.h"
28ecbaee PB	27	#include "ui/pixel_ops.h"
83c9f4ca	28	#include "hw/sysbus.h"
420557e8	29
420557e8 FB	30	#define MAXX 1024
420557e8 FB	31	#define MAXY 768
6f7e9aec	32	#define TCX_DAC_NREGS 16
8508b89e BS	33	#define TCX_THC_NREGS_8 0x081c
	34	#define TCX_THC_NREGS_24 0x1000
	35	#define TCX_TEC_NREGS 0x1000
420557e8	36
01774ddb AF	37	#define TYPE_TCX "SUNW,tcx"
	38	#define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)
	39
420557e8	40	typedef struct TCXState {
01774ddb AF	41	SysBusDevice parent_obj;
01774ddb AF	42
c78f7137	43	QemuConsole *con;
8d5f07fa	44	uint8_t *vram;
eee0b836	45	uint32_t vram24, cplane;
d08151bf AK	46	MemoryRegion vram_mem;
	47	MemoryRegion vram_8bit;
	48	MemoryRegion vram_24bit;
	49	MemoryRegion vram_cplane;
	50	MemoryRegion dac;
	51	MemoryRegion tec;
	52	MemoryRegion thc24;
	53	MemoryRegion thc8;
	54	ram_addr_t vram24_offset, cplane_offset;
ee6847d1	55	uint32_t vram_size;
21206a10	56	uint32_t palette[256];
427a66c3 BS	57	uint8_t r[256], g[256], b[256];
427a66c3 BS	58	uint16_t width, height, depth;
6f7e9aec	59	uint8_t dac_index, dac_state;
420557e8 FB	60	} TCXState;
420557e8 FB	61
d3ffcafe BS	62	static void tcx_set_dirty(TCXState *s)
d3ffcafe BS	63	{
fd4aa979	64	memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
d3ffcafe BS	65	}
	66
	67	static void tcx24_set_dirty(TCXState *s)
	68	{
fd4aa979 BS	69	memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
fd4aa979 BS	70	memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
d3ffcafe	71	}
95219897	72
21206a10 FB	73	static void update_palette_entries(TCXState *s, int start, int end)
21206a10 FB	74	{
c78f7137	75	DisplaySurface *surface = qemu_console_surface(s->con);
21206a10	76	int i;
c78f7137 GH	77
	78	for (i = start; i < end; i++) {
	79	switch (surface_bits_per_pixel(surface)) {
21206a10 FB	80	default:
	81	case 8:
	82	s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
	83	break;
	84	case 15:
8927bcfd	85	s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
21206a10 FB	86	break;
21206a10 FB	87	case 16:
8927bcfd	88	s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
21206a10 FB	89	break;
21206a10 FB	90	case 32:
c78f7137	91	if (is_surface_bgr(surface)) {
7b5d76da	92	s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
c78f7137	93	} else {
7b5d76da	94	s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
c78f7137	95	}
21206a10 FB	96	break;
	97	}
	98	}
d3ffcafe BS	99	if (s->depth == 24) {
	100	tcx24_set_dirty(s);
	101	} else {
	102	tcx_set_dirty(s);
	103	}
21206a10 FB	104	}
21206a10 FB	105
5fafdf24	106	static void tcx_draw_line32(TCXState s1, uint8_t d,
f930d07e	107	const uint8_t *s, int width)
420557e8	108	{
e80cfcfc FB	109	int x;
e80cfcfc FB	110	uint8_t val;
8bdc2159	111	uint32_t p = (uint32_t )d;
e80cfcfc FB	112
e80cfcfc FB	113	for(x = 0; x < width; x++) {
f930d07e	114	val = *s++;
8bdc2159	115	*p++ = s1->palette[val];
e80cfcfc	116	}
420557e8 FB	117	}
420557e8 FB	118
5fafdf24	119	static void tcx_draw_line16(TCXState s1, uint8_t d,
f930d07e	120	const uint8_t *s, int width)
e80cfcfc FB	121	{
	122	int x;
	123	uint8_t val;
8bdc2159	124	uint16_t p = (uint16_t )d;
8d5f07fa	125
e80cfcfc	126	for(x = 0; x < width; x++) {
f930d07e	127	val = *s++;
8bdc2159	128	*p++ = s1->palette[val];
e80cfcfc FB	129	}
	130	}
	131
5fafdf24	132	static void tcx_draw_line8(TCXState s1, uint8_t d,
f930d07e	133	const uint8_t *s, int width)
420557e8	134	{
e80cfcfc FB	135	int x;
	136	uint8_t val;
	137
	138	for(x = 0; x < width; x++) {
f930d07e	139	val = *s++;
21206a10	140	*d++ = s1->palette[val];
420557e8	141	}
420557e8 FB	142	}
420557e8 FB	143
688ea2eb BS	144	/*
	145	XXX Could be much more optimal:
	146	* detect if line/page/whole screen is in 24 bit mode
	147	* if destination is also BGR, use memcpy
	148	*/
eee0b836 BS	149	static inline void tcx24_draw_line32(TCXState s1, uint8_t d,
	150	const uint8_t *s, int width,
	151	const uint32_t *cplane,
	152	const uint32_t *s24)
	153	{
c78f7137	154	DisplaySurface *surface = qemu_console_surface(s1->con);
7b5d76da	155	int x, bgr, r, g, b;
688ea2eb	156	uint8_t val, *p8;
eee0b836 BS	157	uint32_t p = (uint32_t )d;
	158	uint32_t dval;
	159
c78f7137	160	bgr = is_surface_bgr(surface);
eee0b836	161	for(x = 0; x < width; x++, s++, s24++) {
688ea2eb BS	162	if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
	163	// 24-bit direct, BGR order
	164	p8 = (uint8_t *)s24;
	165	p8++;
	166	b = *p8++;
	167	g = *p8++;
f7e683b8	168	r = *p8;
7b5d76da AL	169	if (bgr)
	170	dval = rgb_to_pixel32bgr(r, g, b);
	171	else
	172	dval = rgb_to_pixel32(r, g, b);
eee0b836 BS	173	} else {
	174	val = *s;
	175	dval = s1->palette[val];
	176	}
	177	*p++ = dval;
	178	}
	179	}
	180
d08151bf	181	static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
c227f099	182	ram_addr_t cpage)
eee0b836 BS	183	{
eee0b836 BS	184	int ret;
eee0b836	185
cd7a45c9 BS	186	ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
	187	DIRTY_MEMORY_VGA);
	188	ret \|= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
	189	DIRTY_MEMORY_VGA);
	190	ret \|= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
	191	DIRTY_MEMORY_VGA);
eee0b836 BS	192	return ret;
	193	}
	194
c227f099 AL	195	static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
	196	ram_addr_t page_max, ram_addr_t page24,
	197	ram_addr_t cpage)
eee0b836	198	{
d08151bf	199	memory_region_reset_dirty(&ts->vram_mem,
f10acc8b MCA	200	page_min,
f10acc8b MCA	201	(page_max - page_min) + TARGET_PAGE_SIZE,
d08151bf AK	202	DIRTY_MEMORY_VGA);
	203	memory_region_reset_dirty(&ts->vram_mem,
	204	page24 + page_min * 4,
f10acc8b	205	(page_max - page_min) * 4 + TARGET_PAGE_SIZE,
d08151bf AK	206	DIRTY_MEMORY_VGA);
	207	memory_region_reset_dirty(&ts->vram_mem,
	208	cpage + page_min * 4,
f10acc8b	209	(page_max - page_min) * 4 + TARGET_PAGE_SIZE,
d08151bf	210	DIRTY_MEMORY_VGA);
eee0b836 BS	211	}
eee0b836 BS	212
e80cfcfc FB	213	/* Fixed line length 1024 allows us to do nice tricks not possible on
e80cfcfc FB	214	VGA... */
95219897	215	static void tcx_update_display(void *opaque)
420557e8	216	{
e80cfcfc	217	TCXState *ts = opaque;
c78f7137	218	DisplaySurface *surface = qemu_console_surface(ts->con);
c227f099	219	ram_addr_t page, page_min, page_max;
550be127	220	int y, y_start, dd, ds;
e80cfcfc	221	uint8_t d, s;
b3ceef24	222	void (f)(TCXState s1, uint8_t dst, const uint8_t src, int width);
e80cfcfc	223
c78f7137	224	if (surface_bits_per_pixel(surface) == 0) {
f930d07e	225	return;
c78f7137 GH	226	}
c78f7137 GH	227
d08151bf	228	page = 0;
e80cfcfc	229	y_start = -1;
c0c440f3	230	page_min = -1;
550be127	231	page_max = 0;
c78f7137	232	d = surface_data(surface);
6f7e9aec	233	s = ts->vram;
c78f7137	234	dd = surface_stride(surface);
e80cfcfc FB	235	ds = 1024;
e80cfcfc FB	236
c78f7137	237	switch (surface_bits_per_pixel(surface)) {
e80cfcfc	238	case 32:
f930d07e BS	239	f = tcx_draw_line32;
f930d07e BS	240	break;
21206a10 FB	241	case 15:
21206a10 FB	242	case 16:
f930d07e BS	243	f = tcx_draw_line16;
f930d07e BS	244	break;
e80cfcfc FB	245	default:
e80cfcfc FB	246	case 8:
f930d07e BS	247	f = tcx_draw_line8;
f930d07e BS	248	break;
e80cfcfc	249	case 0:
f930d07e	250	return;
e80cfcfc	251	}
3b46e624	252
6f7e9aec	253	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
cd7a45c9 BS	254	if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
cd7a45c9 BS	255	DIRTY_MEMORY_VGA)) {
f930d07e	256	if (y_start < 0)
e80cfcfc FB	257	y_start = y;
	258	if (page < page_min)
	259	page_min = page;
	260	if (page > page_max)
	261	page_max = page;
f930d07e BS	262	f(ts, d, s, ts->width);
	263	d += dd;
	264	s += ds;
	265	f(ts, d, s, ts->width);
	266	d += dd;
	267	s += ds;
	268	f(ts, d, s, ts->width);
	269	d += dd;
	270	s += ds;
	271	f(ts, d, s, ts->width);
	272	d += dd;
	273	s += ds;
	274	} else {
e80cfcfc FB	275	if (y_start >= 0) {
e80cfcfc FB	276	/* flush to display */
c78f7137	277	dpy_gfx_update(ts->con, 0, y_start,
a93a4a22	278	ts->width, y - y_start);
e80cfcfc FB	279	y_start = -1;
e80cfcfc FB	280	}
f930d07e BS	281	d += dd * 4;
	282	s += ds * 4;
	283	}
e80cfcfc FB	284	}
e80cfcfc FB	285	if (y_start >= 0) {
f930d07e	286	/* flush to display */
c78f7137	287	dpy_gfx_update(ts->con, 0, y_start,
a93a4a22	288	ts->width, y - y_start);
e80cfcfc FB	289	}
e80cfcfc FB	290	/* reset modified pages */
c0c440f3	291	if (page_max >= page_min) {
d08151bf	292	memory_region_reset_dirty(&ts->vram_mem,
f10acc8b MCA	293	page_min,
f10acc8b MCA	294	(page_max - page_min) + TARGET_PAGE_SIZE,
d08151bf	295	DIRTY_MEMORY_VGA);
e80cfcfc	296	}
420557e8 FB	297	}
420557e8 FB	298
eee0b836 BS	299	static void tcx24_update_display(void *opaque)
	300	{
	301	TCXState *ts = opaque;
c78f7137	302	DisplaySurface *surface = qemu_console_surface(ts->con);
c227f099	303	ram_addr_t page, page_min, page_max, cpage, page24;
eee0b836 BS	304	int y, y_start, dd, ds;
	305	uint8_t d, s;
	306	uint32_t cptr, s24;
	307
c78f7137	308	if (surface_bits_per_pixel(surface) != 32) {
eee0b836	309	return;
c78f7137 GH	310	}
c78f7137 GH	311
d08151bf	312	page = 0;
eee0b836 BS	313	page24 = ts->vram24_offset;
	314	cpage = ts->cplane_offset;
	315	y_start = -1;
c0c440f3	316	page_min = -1;
eee0b836	317	page_max = 0;
c78f7137	318	d = surface_data(surface);
eee0b836 BS	319	s = ts->vram;
	320	s24 = ts->vram24;
	321	cptr = ts->cplane;
c78f7137	322	dd = surface_stride(surface);
eee0b836 BS	323	ds = 1024;
	324
	325	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
	326	page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
d08151bf	327	if (check_dirty(ts, page, page24, cpage)) {
eee0b836 BS	328	if (y_start < 0)
	329	y_start = y;
	330	if (page < page_min)
	331	page_min = page;
	332	if (page > page_max)
	333	page_max = page;
	334	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	335	d += dd;
	336	s += ds;
	337	cptr += ds;
	338	s24 += ds;
	339	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	340	d += dd;
	341	s += ds;
	342	cptr += ds;
	343	s24 += ds;
	344	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	345	d += dd;
	346	s += ds;
	347	cptr += ds;
	348	s24 += ds;
	349	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	350	d += dd;
	351	s += ds;
	352	cptr += ds;
	353	s24 += ds;
	354	} else {
	355	if (y_start >= 0) {
	356	/* flush to display */
c78f7137	357	dpy_gfx_update(ts->con, 0, y_start,
a93a4a22	358	ts->width, y - y_start);
eee0b836 BS	359	y_start = -1;
	360	}
	361	d += dd * 4;
	362	s += ds * 4;
	363	cptr += ds * 4;
	364	s24 += ds * 4;
	365	}
	366	}
	367	if (y_start >= 0) {
	368	/* flush to display */
c78f7137	369	dpy_gfx_update(ts->con, 0, y_start,
a93a4a22	370	ts->width, y - y_start);
eee0b836 BS	371	}
eee0b836 BS	372	/* reset modified pages */
c0c440f3	373	if (page_max >= page_min) {
eee0b836 BS	374	reset_dirty(ts, page_min, page_max, page24, cpage);
	375	}
	376	}
	377
95219897	378	static void tcx_invalidate_display(void *opaque)
420557e8	379	{
e80cfcfc	380	TCXState *s = opaque;
e80cfcfc	381
d3ffcafe	382	tcx_set_dirty(s);
c78f7137	383	qemu_console_resize(s->con, s->width, s->height);
420557e8 FB	384	}
420557e8 FB	385
eee0b836 BS	386	static void tcx24_invalidate_display(void *opaque)
	387	{
	388	TCXState *s = opaque;
eee0b836	389
d3ffcafe BS	390	tcx_set_dirty(s);
d3ffcafe BS	391	tcx24_set_dirty(s);
c78f7137	392	qemu_console_resize(s->con, s->width, s->height);
eee0b836 BS	393	}
eee0b836 BS	394
e59fb374	395	static int vmstate_tcx_post_load(void *opaque, int version_id)
420557e8 FB	396	{
420557e8 FB	397	TCXState *s = opaque;
3b46e624	398
21206a10	399	update_palette_entries(s, 0, 256);
d3ffcafe BS	400	if (s->depth == 24) {
	401	tcx24_set_dirty(s);
	402	} else {
	403	tcx_set_dirty(s);
	404	}
5425a216	405
e80cfcfc	406	return 0;
420557e8 FB	407	}
420557e8 FB	408
c0c41a4b BS	409	static const VMStateDescription vmstate_tcx = {
	410	.name ="tcx",
	411	.version_id = 4,
	412	.minimum_version_id = 4,
	413	.minimum_version_id_old = 4,
752ff2fa	414	.post_load = vmstate_tcx_post_load,
c0c41a4b BS	415	.fields = (VMStateField []) {
	416	VMSTATE_UINT16(height, TCXState),
	417	VMSTATE_UINT16(width, TCXState),
	418	VMSTATE_UINT16(depth, TCXState),
	419	VMSTATE_BUFFER(r, TCXState),
	420	VMSTATE_BUFFER(g, TCXState),
	421	VMSTATE_BUFFER(b, TCXState),
	422	VMSTATE_UINT8(dac_index, TCXState),
	423	VMSTATE_UINT8(dac_state, TCXState),
	424	VMSTATE_END_OF_LIST()
	425	}
	426	};
	427
7f23f812	428	static void tcx_reset(DeviceState *d)
420557e8	429	{
01774ddb	430	TCXState *s = TCX(d);
e80cfcfc FB	431
	432	/* Initialize palette */
	433	memset(s->r, 0, 256);
	434	memset(s->g, 0, 256);
	435	memset(s->b, 0, 256);
	436	s->r[255] = s->g[255] = s->b[255] = 255;
21206a10	437	update_palette_entries(s, 0, 256);
e80cfcfc	438	memset(s->vram, 0, MAXX*MAXY);
d08151bf AK	439	memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
d08151bf AK	440	DIRTY_MEMORY_VGA);
6f7e9aec FB	441	s->dac_index = 0;
	442	s->dac_state = 0;
	443	}
	444
a8170e5e	445	static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
d08151bf	446	unsigned size)
6f7e9aec FB	447	{
	448	return 0;
	449	}
	450
a8170e5e	451	static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
d08151bf	452	unsigned size)
6f7e9aec FB	453	{
6f7e9aec FB	454	TCXState *s = opaque;
6f7e9aec	455
e64d7d59	456	switch (addr) {
6f7e9aec	457	case 0:
f930d07e BS	458	s->dac_index = val >> 24;
	459	s->dac_state = 0;
	460	break;
e64d7d59	461	case 4:
f930d07e BS	462	switch (s->dac_state) {
	463	case 0:
	464	s->r[s->dac_index] = val >> 24;
21206a10	465	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	466	s->dac_state++;
	467	break;
	468	case 1:
	469	s->g[s->dac_index] = val >> 24;
21206a10	470	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	471	s->dac_state++;
	472	break;
	473	case 2:
	474	s->b[s->dac_index] = val >> 24;
21206a10	475	update_palette_entries(s, s->dac_index, s->dac_index + 1);
5c8cdbf8	476	s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
f930d07e BS	477	default:
	478	s->dac_state = 0;
	479	break;
	480	}
	481	break;
6f7e9aec	482	default:
f930d07e	483	break;
6f7e9aec	484	}
420557e8 FB	485	}
420557e8 FB	486
d08151bf AK	487	static const MemoryRegionOps tcx_dac_ops = {
	488	.read = tcx_dac_readl,
	489	.write = tcx_dac_writel,
	490	.endianness = DEVICE_NATIVE_ENDIAN,
	491	.valid = {
	492	.min_access_size = 4,
	493	.max_access_size = 4,
	494	},
6f7e9aec FB	495	};
6f7e9aec FB	496
a8170e5e	497	static uint64_t dummy_readl(void *opaque, hwaddr addr,
d08151bf	498	unsigned size)
8508b89e BS	499	{
	500	return 0;
	501	}
	502
a8170e5e	503	static void dummy_writel(void *opaque, hwaddr addr,
d08151bf	504	uint64_t val, unsigned size)
8508b89e BS	505	{
	506	}
	507
d08151bf AK	508	static const MemoryRegionOps dummy_ops = {
	509	.read = dummy_readl,
	510	.write = dummy_writel,
	511	.endianness = DEVICE_NATIVE_ENDIAN,
	512	.valid = {
	513	.min_access_size = 4,
	514	.max_access_size = 4,
	515	},
8508b89e BS	516	};
8508b89e BS	517
380cd056 GH	518	static const GraphicHwOps tcx_ops = {
	519	.invalidate = tcx_invalidate_display,
	520	.gfx_update = tcx_update_display,
	521	};
	522
	523	static const GraphicHwOps tcx24_ops = {
	524	.invalidate = tcx24_invalidate_display,
	525	.gfx_update = tcx24_update_display,
	526	};
	527
81a322d4	528	static int tcx_init1(SysBusDevice *dev)
f40070c3	529	{
01774ddb	530	TCXState *s = TCX(dev);
d08151bf	531	ram_addr_t vram_offset = 0;
ee6847d1	532	int size;
dc828ca1 PB	533	uint8_t *vram_base;
dc828ca1 PB	534
3eadad55	535	memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
d08151bf	536	s->vram_size * (1 + 4 + 4));
c5705a77	537	vmstate_register_ram_global(&s->vram_mem);
d08151bf	538	vram_base = memory_region_get_ram_ptr(&s->vram_mem);
eee0b836	539
f40070c3	540	/* 8-bit plane */
eee0b836	541	s->vram = vram_base;
ee6847d1	542	size = s->vram_size;
3eadad55	543	memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
d08151bf	544	&s->vram_mem, vram_offset, size);
750ecd44	545	sysbus_init_mmio(dev, &s->vram_8bit);
eee0b836 BS	546	vram_offset += size;
eee0b836 BS	547	vram_base += size;
e80cfcfc	548
f40070c3	549	/* DAC */
3eadad55 PB	550	memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s,
3eadad55 PB	551	"tcx.dac", TCX_DAC_NREGS);
750ecd44	552	sysbus_init_mmio(dev, &s->dac);
eee0b836	553
f40070c3	554	/* TEC (dummy) */
3eadad55 PB	555	memory_region_init_io(&s->tec, OBJECT(s), &dummy_ops, s,
3eadad55 PB	556	"tcx.tec", TCX_TEC_NREGS);
750ecd44	557	sysbus_init_mmio(dev, &s->tec);
f40070c3	558	/* THC: NetBSD writes here even with 8-bit display: dummy */
3eadad55	559	memory_region_init_io(&s->thc24, OBJECT(s), &dummy_ops, s, "tcx.thc24",
d08151bf	560	TCX_THC_NREGS_24);
750ecd44	561	sysbus_init_mmio(dev, &s->thc24);
f40070c3 BS	562
	563	if (s->depth == 24) {
	564	/* 24-bit plane */
ee6847d1	565	size = s->vram_size * 4;
eee0b836 BS	566	s->vram24 = (uint32_t *)vram_base;
eee0b836 BS	567	s->vram24_offset = vram_offset;
3eadad55	568	memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
d08151bf	569	&s->vram_mem, vram_offset, size);
750ecd44	570	sysbus_init_mmio(dev, &s->vram_24bit);
eee0b836 BS	571	vram_offset += size;
	572	vram_base += size;
	573
f40070c3	574	/* Control plane */
ee6847d1	575	size = s->vram_size * 4;
eee0b836 BS	576	s->cplane = (uint32_t *)vram_base;
eee0b836 BS	577	s->cplane_offset = vram_offset;
3eadad55	578	memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
d08151bf	579	&s->vram_mem, vram_offset, size);
750ecd44	580	sysbus_init_mmio(dev, &s->vram_cplane);
f40070c3	581
aa2beaa1	582	s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s);
eee0b836	583	} else {
f40070c3	584	/* THC 8 bit (dummy) */
3eadad55	585	memory_region_init_io(&s->thc8, OBJECT(s), &dummy_ops, s, "tcx.thc8",
d08151bf	586	TCX_THC_NREGS_8);
750ecd44	587	sysbus_init_mmio(dev, &s->thc8);
f40070c3	588
aa2beaa1	589	s->con = graphic_console_init(DEVICE(dev), &tcx_ops, s);
eee0b836	590	}
e80cfcfc	591
c78f7137	592	qemu_console_resize(s->con, s->width, s->height);
81a322d4	593	return 0;
420557e8 FB	594	}
420557e8 FB	595
999e12bb	596	static Property tcx_properties[] = {
999e12bb AL	597	DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
	598	DEFINE_PROP_UINT16("width", TCXState, width, -1),
	599	DEFINE_PROP_UINT16("height", TCXState, height, -1),
	600	DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
	601	DEFINE_PROP_END_OF_LIST(),
	602	};
	603
	604	static void tcx_class_init(ObjectClass klass, void data)
	605	{
39bffca2	606	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	607	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	608
	609	k->init = tcx_init1;
39bffca2 AL	610	dc->reset = tcx_reset;
	611	dc->vmsd = &vmstate_tcx;
	612	dc->props = tcx_properties;
999e12bb AL	613	}
999e12bb AL	614
8c43a6f0	615	static const TypeInfo tcx_info = {
01774ddb	616	.name = TYPE_TCX,
39bffca2 AL	617	.parent = TYPE_SYS_BUS_DEVICE,
	618	.instance_size = sizeof(TCXState),
	619	.class_init = tcx_class_init,
ee6847d1 GH	620	};
ee6847d1 GH	621
83f7d43a	622	static void tcx_register_types(void)
f40070c3	623	{
39bffca2	624	type_register_static(&tcx_info);
f40070c3 BS	625	}
f40070c3 BS	626
83f7d43a	627	type_init(tcx_register_types)