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Commit | Line | Data |
---|---|---|
e89f66ec | 1 | /* |
4fa0f5d2 | 2 | * QEMU VGA Emulator. |
5fafdf24 | 3 | * |
e89f66ec | 4 | * Copyright (c) 2003 Fabrice Bellard |
5fafdf24 | 5 | * |
e89f66ec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
47b43a1f | 25 | #include "vga.h" |
28ecbaee | 26 | #include "ui/console.h" |
0d09e41a | 27 | #include "hw/i386/pc.h" |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
47b43a1f | 29 | #include "vga_int.h" |
28ecbaee | 30 | #include "ui/pixel_ops.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
0d09e41a | 32 | #include "hw/xen/xen.h" |
72750018 | 33 | #include "trace.h" |
e89f66ec | 34 | |
e89f66ec | 35 | //#define DEBUG_VGA |
17b0018b | 36 | //#define DEBUG_VGA_MEM |
a41bc9af FB |
37 | //#define DEBUG_VGA_REG |
38 | ||
4fa0f5d2 FB |
39 | //#define DEBUG_BOCHS_VBE |
40 | ||
9aa0ff0b JK |
41 | /* 16 state changes per vertical frame @60 Hz */ |
42 | #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60) | |
43 | ||
47c012e2 BS |
44 | /* |
45 | * Video Graphics Array (VGA) | |
46 | * | |
47 | * Chipset docs for original IBM VGA: | |
48 | * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf | |
49 | * | |
50 | * FreeVGA site: | |
51 | * http://www.osdever.net/FreeVGA/home.htm | |
52 | * | |
53 | * Standard VGA features and Bochs VBE extensions are implemented. | |
54 | */ | |
55 | ||
e89f66ec | 56 | /* force some bits to zero */ |
798b0c25 | 57 | const uint8_t sr_mask[8] = { |
9e622b15 BS |
58 | 0x03, |
59 | 0x3d, | |
60 | 0x0f, | |
61 | 0x3f, | |
62 | 0x0e, | |
63 | 0x00, | |
64 | 0x00, | |
65 | 0xff, | |
e89f66ec FB |
66 | }; |
67 | ||
798b0c25 | 68 | const uint8_t gr_mask[16] = { |
9e622b15 BS |
69 | 0x0f, /* 0x00 */ |
70 | 0x0f, /* 0x01 */ | |
71 | 0x0f, /* 0x02 */ | |
72 | 0x1f, /* 0x03 */ | |
73 | 0x03, /* 0x04 */ | |
74 | 0x7b, /* 0x05 */ | |
75 | 0x0f, /* 0x06 */ | |
76 | 0x0f, /* 0x07 */ | |
77 | 0xff, /* 0x08 */ | |
78 | 0x00, /* 0x09 */ | |
79 | 0x00, /* 0x0a */ | |
80 | 0x00, /* 0x0b */ | |
81 | 0x00, /* 0x0c */ | |
82 | 0x00, /* 0x0d */ | |
83 | 0x00, /* 0x0e */ | |
84 | 0x00, /* 0x0f */ | |
e89f66ec FB |
85 | }; |
86 | ||
87 | #define cbswap_32(__x) \ | |
88 | ((uint32_t)( \ | |
89 | (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \ | |
90 | (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \ | |
91 | (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \ | |
92 | (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )) | |
93 | ||
e2542fe2 | 94 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
95 | #define PAT(x) cbswap_32(x) |
96 | #else | |
97 | #define PAT(x) (x) | |
98 | #endif | |
99 | ||
e2542fe2 | 100 | #ifdef HOST_WORDS_BIGENDIAN |
b8ed223b FB |
101 | #define BIG 1 |
102 | #else | |
103 | #define BIG 0 | |
104 | #endif | |
105 | ||
e2542fe2 | 106 | #ifdef HOST_WORDS_BIGENDIAN |
b8ed223b FB |
107 | #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff) |
108 | #else | |
109 | #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff) | |
110 | #endif | |
111 | ||
e89f66ec FB |
112 | static const uint32_t mask16[16] = { |
113 | PAT(0x00000000), | |
114 | PAT(0x000000ff), | |
115 | PAT(0x0000ff00), | |
116 | PAT(0x0000ffff), | |
117 | PAT(0x00ff0000), | |
118 | PAT(0x00ff00ff), | |
119 | PAT(0x00ffff00), | |
120 | PAT(0x00ffffff), | |
121 | PAT(0xff000000), | |
122 | PAT(0xff0000ff), | |
123 | PAT(0xff00ff00), | |
124 | PAT(0xff00ffff), | |
125 | PAT(0xffff0000), | |
126 | PAT(0xffff00ff), | |
127 | PAT(0xffffff00), | |
128 | PAT(0xffffffff), | |
129 | }; | |
130 | ||
131 | #undef PAT | |
132 | ||
e2542fe2 | 133 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
134 | #define PAT(x) (x) |
135 | #else | |
136 | #define PAT(x) cbswap_32(x) | |
137 | #endif | |
138 | ||
139 | static const uint32_t dmask16[16] = { | |
140 | PAT(0x00000000), | |
141 | PAT(0x000000ff), | |
142 | PAT(0x0000ff00), | |
143 | PAT(0x0000ffff), | |
144 | PAT(0x00ff0000), | |
145 | PAT(0x00ff00ff), | |
146 | PAT(0x00ffff00), | |
147 | PAT(0x00ffffff), | |
148 | PAT(0xff000000), | |
149 | PAT(0xff0000ff), | |
150 | PAT(0xff00ff00), | |
151 | PAT(0xff00ffff), | |
152 | PAT(0xffff0000), | |
153 | PAT(0xffff00ff), | |
154 | PAT(0xffffff00), | |
155 | PAT(0xffffffff), | |
156 | }; | |
157 | ||
158 | static const uint32_t dmask4[4] = { | |
159 | PAT(0x00000000), | |
160 | PAT(0x0000ffff), | |
161 | PAT(0xffff0000), | |
162 | PAT(0xffffffff), | |
163 | }; | |
164 | ||
165 | static uint32_t expand4[256]; | |
166 | static uint16_t expand2[256]; | |
17b0018b | 167 | static uint8_t expand4to8[16]; |
e89f66ec | 168 | |
80763888 JK |
169 | static void vga_update_memory_access(VGACommonState *s) |
170 | { | |
171 | MemoryRegion *region, *old_region = s->chain4_alias; | |
a8170e5e | 172 | hwaddr base, offset, size; |
80763888 JK |
173 | |
174 | s->chain4_alias = NULL; | |
175 | ||
5e55efc9 BS |
176 | if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) == |
177 | VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { | |
80763888 | 178 | offset = 0; |
5e55efc9 | 179 | switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) { |
80763888 JK |
180 | case 0: |
181 | base = 0xa0000; | |
182 | size = 0x20000; | |
183 | break; | |
184 | case 1: | |
185 | base = 0xa0000; | |
186 | size = 0x10000; | |
187 | offset = s->bank_offset; | |
188 | break; | |
189 | case 2: | |
190 | base = 0xb0000; | |
191 | size = 0x8000; | |
192 | break; | |
193 | case 3: | |
f065aa0a | 194 | default: |
80763888 JK |
195 | base = 0xb8000; |
196 | size = 0x8000; | |
197 | break; | |
198 | } | |
71579cae | 199 | base += isa_mem_base; |
80763888 | 200 | region = g_malloc(sizeof(*region)); |
2c9b15ca | 201 | memory_region_init_alias(region, NULL, "vga.chain4", &s->vram, offset, size); |
80763888 JK |
202 | memory_region_add_subregion_overlap(s->legacy_address_space, base, |
203 | region, 2); | |
204 | s->chain4_alias = region; | |
205 | } | |
206 | if (old_region) { | |
207 | memory_region_del_subregion(s->legacy_address_space, old_region); | |
208 | memory_region_destroy(old_region); | |
209 | g_free(old_region); | |
210 | s->plane_updated = 0xf; | |
211 | } | |
212 | } | |
213 | ||
cedd91d2 | 214 | static void vga_dumb_update_retrace_info(VGACommonState *s) |
cb5a7aa8 | 215 | { |
216 | (void) s; | |
217 | } | |
218 | ||
cedd91d2 | 219 | static void vga_precise_update_retrace_info(VGACommonState *s) |
cb5a7aa8 | 220 | { |
221 | int htotal_chars; | |
222 | int hretr_start_char; | |
223 | int hretr_skew_chars; | |
224 | int hretr_end_char; | |
225 | ||
226 | int vtotal_lines; | |
227 | int vretr_start_line; | |
228 | int vretr_end_line; | |
229 | ||
7f5b7d3e BS |
230 | int dots; |
231 | #if 0 | |
232 | int div2, sldiv2; | |
233 | #endif | |
cb5a7aa8 | 234 | int clocking_mode; |
235 | int clock_sel; | |
b0f74c87 | 236 | const int clk_hz[] = {25175000, 28322000, 25175000, 25175000}; |
cb5a7aa8 | 237 | int64_t chars_per_sec; |
238 | struct vga_precise_retrace *r = &s->retrace_info.precise; | |
239 | ||
5e55efc9 BS |
240 | htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5; |
241 | hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START]; | |
242 | hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3; | |
243 | hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f; | |
cb5a7aa8 | 244 | |
5e55efc9 BS |
245 | vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] | |
246 | (((s->cr[VGA_CRTC_OVERFLOW] & 1) | | |
247 | ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2; | |
248 | vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] | | |
249 | ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) | | |
250 | ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8); | |
251 | vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf; | |
cb5a7aa8 | 252 | |
5e55efc9 | 253 | clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1; |
cb5a7aa8 | 254 | clock_sel = (s->msr >> 2) & 3; |
f87fc09b | 255 | dots = (s->msr & 1) ? 8 : 9; |
cb5a7aa8 | 256 | |
b0f74c87 | 257 | chars_per_sec = clk_hz[clock_sel] / dots; |
cb5a7aa8 | 258 | |
259 | htotal_chars <<= clocking_mode; | |
260 | ||
261 | r->total_chars = vtotal_lines * htotal_chars; | |
cb5a7aa8 | 262 | if (r->freq) { |
6ee093c9 | 263 | r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq); |
cb5a7aa8 | 264 | } else { |
6ee093c9 | 265 | r->ticks_per_char = get_ticks_per_sec() / chars_per_sec; |
cb5a7aa8 | 266 | } |
267 | ||
268 | r->vstart = vretr_start_line; | |
269 | r->vend = r->vstart + vretr_end_line + 1; | |
270 | ||
271 | r->hstart = hretr_start_char + hretr_skew_chars; | |
272 | r->hend = r->hstart + hretr_end_char + 1; | |
273 | r->htotal = htotal_chars; | |
274 | ||
f87fc09b | 275 | #if 0 |
5e55efc9 BS |
276 | div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1; |
277 | sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1; | |
cb5a7aa8 | 278 | printf ( |
f87fc09b | 279 | "hz=%f\n" |
cb5a7aa8 | 280 | "htotal = %d\n" |
281 | "hretr_start = %d\n" | |
282 | "hretr_skew = %d\n" | |
283 | "hretr_end = %d\n" | |
284 | "vtotal = %d\n" | |
285 | "vretr_start = %d\n" | |
286 | "vretr_end = %d\n" | |
287 | "div2 = %d sldiv2 = %d\n" | |
288 | "clocking_mode = %d\n" | |
289 | "clock_sel = %d %d\n" | |
290 | "dots = %d\n" | |
0bfcd599 | 291 | "ticks/char = %" PRId64 "\n" |
cb5a7aa8 | 292 | "\n", |
6ee093c9 | 293 | (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars), |
cb5a7aa8 | 294 | htotal_chars, |
295 | hretr_start_char, | |
296 | hretr_skew_chars, | |
297 | hretr_end_char, | |
298 | vtotal_lines, | |
299 | vretr_start_line, | |
300 | vretr_end_line, | |
301 | div2, sldiv2, | |
302 | clocking_mode, | |
303 | clock_sel, | |
b0f74c87 | 304 | clk_hz[clock_sel], |
cb5a7aa8 | 305 | dots, |
306 | r->ticks_per_char | |
307 | ); | |
308 | #endif | |
309 | } | |
310 | ||
cedd91d2 | 311 | static uint8_t vga_precise_retrace(VGACommonState *s) |
cb5a7aa8 | 312 | { |
313 | struct vga_precise_retrace *r = &s->retrace_info.precise; | |
314 | uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE); | |
315 | ||
316 | if (r->total_chars) { | |
317 | int cur_line, cur_line_char, cur_char; | |
318 | int64_t cur_tick; | |
319 | ||
74475455 | 320 | cur_tick = qemu_get_clock_ns(vm_clock); |
cb5a7aa8 | 321 | |
322 | cur_char = (cur_tick / r->ticks_per_char) % r->total_chars; | |
323 | cur_line = cur_char / r->htotal; | |
324 | ||
325 | if (cur_line >= r->vstart && cur_line <= r->vend) { | |
326 | val |= ST01_V_RETRACE | ST01_DISP_ENABLE; | |
f87fc09b | 327 | } else { |
328 | cur_line_char = cur_char % r->htotal; | |
329 | if (cur_line_char >= r->hstart && cur_line_char <= r->hend) { | |
330 | val |= ST01_DISP_ENABLE; | |
331 | } | |
cb5a7aa8 | 332 | } |
333 | ||
334 | return val; | |
335 | } else { | |
336 | return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); | |
337 | } | |
338 | } | |
339 | ||
cedd91d2 | 340 | static uint8_t vga_dumb_retrace(VGACommonState *s) |
cb5a7aa8 | 341 | { |
342 | return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); | |
343 | } | |
344 | ||
25a18cbd JQ |
345 | int vga_ioport_invalid(VGACommonState *s, uint32_t addr) |
346 | { | |
5e55efc9 | 347 | if (s->msr & VGA_MIS_COLOR) { |
25a18cbd JQ |
348 | /* Color */ |
349 | return (addr >= 0x3b0 && addr <= 0x3bf); | |
350 | } else { | |
351 | /* Monochrome */ | |
352 | return (addr >= 0x3d0 && addr <= 0x3df); | |
353 | } | |
354 | } | |
355 | ||
43bf782b | 356 | uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
e89f66ec | 357 | { |
43bf782b | 358 | VGACommonState *s = opaque; |
e89f66ec FB |
359 | int val, index; |
360 | ||
bd8f2f5d JK |
361 | qemu_flush_coalesced_mmio_buffer(); |
362 | ||
25a18cbd | 363 | if (vga_ioport_invalid(s, addr)) { |
e89f66ec FB |
364 | val = 0xff; |
365 | } else { | |
366 | switch(addr) { | |
5e55efc9 | 367 | case VGA_ATT_W: |
e89f66ec FB |
368 | if (s->ar_flip_flop == 0) { |
369 | val = s->ar_index; | |
370 | } else { | |
371 | val = 0; | |
372 | } | |
373 | break; | |
5e55efc9 | 374 | case VGA_ATT_R: |
e89f66ec | 375 | index = s->ar_index & 0x1f; |
5e55efc9 | 376 | if (index < VGA_ATT_C) { |
e89f66ec | 377 | val = s->ar[index]; |
5e55efc9 | 378 | } else { |
e89f66ec | 379 | val = 0; |
5e55efc9 | 380 | } |
e89f66ec | 381 | break; |
5e55efc9 | 382 | case VGA_MIS_W: |
e89f66ec FB |
383 | val = s->st00; |
384 | break; | |
5e55efc9 | 385 | case VGA_SEQ_I: |
e89f66ec FB |
386 | val = s->sr_index; |
387 | break; | |
5e55efc9 | 388 | case VGA_SEQ_D: |
e89f66ec | 389 | val = s->sr[s->sr_index]; |
a41bc9af FB |
390 | #ifdef DEBUG_VGA_REG |
391 | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); | |
392 | #endif | |
e89f66ec | 393 | break; |
5e55efc9 | 394 | case VGA_PEL_IR: |
e89f66ec FB |
395 | val = s->dac_state; |
396 | break; | |
5e55efc9 | 397 | case VGA_PEL_IW: |
e9b43ea3 JQ |
398 | val = s->dac_write_index; |
399 | break; | |
5e55efc9 | 400 | case VGA_PEL_D: |
e89f66ec FB |
401 | val = s->palette[s->dac_read_index * 3 + s->dac_sub_index]; |
402 | if (++s->dac_sub_index == 3) { | |
403 | s->dac_sub_index = 0; | |
404 | s->dac_read_index++; | |
405 | } | |
406 | break; | |
5e55efc9 | 407 | case VGA_FTC_R: |
e89f66ec FB |
408 | val = s->fcr; |
409 | break; | |
5e55efc9 | 410 | case VGA_MIS_R: |
e89f66ec FB |
411 | val = s->msr; |
412 | break; | |
5e55efc9 | 413 | case VGA_GFX_I: |
e89f66ec FB |
414 | val = s->gr_index; |
415 | break; | |
5e55efc9 | 416 | case VGA_GFX_D: |
e89f66ec | 417 | val = s->gr[s->gr_index]; |
a41bc9af FB |
418 | #ifdef DEBUG_VGA_REG |
419 | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); | |
420 | #endif | |
e89f66ec | 421 | break; |
5e55efc9 BS |
422 | case VGA_CRT_IM: |
423 | case VGA_CRT_IC: | |
e89f66ec FB |
424 | val = s->cr_index; |
425 | break; | |
5e55efc9 BS |
426 | case VGA_CRT_DM: |
427 | case VGA_CRT_DC: | |
e89f66ec | 428 | val = s->cr[s->cr_index]; |
a41bc9af FB |
429 | #ifdef DEBUG_VGA_REG |
430 | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); | |
a41bc9af | 431 | #endif |
e89f66ec | 432 | break; |
5e55efc9 BS |
433 | case VGA_IS1_RM: |
434 | case VGA_IS1_RC: | |
e89f66ec | 435 | /* just toggle to fool polling */ |
cb5a7aa8 | 436 | val = s->st01 = s->retrace(s); |
e89f66ec FB |
437 | s->ar_flip_flop = 0; |
438 | break; | |
439 | default: | |
440 | val = 0x00; | |
441 | break; | |
442 | } | |
443 | } | |
4fa0f5d2 | 444 | #if defined(DEBUG_VGA) |
e89f66ec FB |
445 | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val); |
446 | #endif | |
447 | return val; | |
448 | } | |
449 | ||
43bf782b | 450 | void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
e89f66ec | 451 | { |
43bf782b | 452 | VGACommonState *s = opaque; |
5467a722 | 453 | int index; |
e89f66ec | 454 | |
bd8f2f5d JK |
455 | qemu_flush_coalesced_mmio_buffer(); |
456 | ||
e89f66ec | 457 | /* check port range access depending on color/monochrome mode */ |
25a18cbd | 458 | if (vga_ioport_invalid(s, addr)) { |
e89f66ec | 459 | return; |
25a18cbd | 460 | } |
e89f66ec FB |
461 | #ifdef DEBUG_VGA |
462 | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val); | |
463 | #endif | |
464 | ||
465 | switch(addr) { | |
5e55efc9 | 466 | case VGA_ATT_W: |
e89f66ec FB |
467 | if (s->ar_flip_flop == 0) { |
468 | val &= 0x3f; | |
469 | s->ar_index = val; | |
470 | } else { | |
471 | index = s->ar_index & 0x1f; | |
472 | switch(index) { | |
5e55efc9 | 473 | case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF: |
e89f66ec FB |
474 | s->ar[index] = val & 0x3f; |
475 | break; | |
5e55efc9 | 476 | case VGA_ATC_MODE: |
e89f66ec FB |
477 | s->ar[index] = val & ~0x10; |
478 | break; | |
5e55efc9 | 479 | case VGA_ATC_OVERSCAN: |
e89f66ec FB |
480 | s->ar[index] = val; |
481 | break; | |
5e55efc9 | 482 | case VGA_ATC_PLANE_ENABLE: |
e89f66ec FB |
483 | s->ar[index] = val & ~0xc0; |
484 | break; | |
5e55efc9 | 485 | case VGA_ATC_PEL: |
e89f66ec FB |
486 | s->ar[index] = val & ~0xf0; |
487 | break; | |
5e55efc9 | 488 | case VGA_ATC_COLOR_PAGE: |
e89f66ec FB |
489 | s->ar[index] = val & ~0xf0; |
490 | break; | |
491 | default: | |
492 | break; | |
493 | } | |
494 | } | |
495 | s->ar_flip_flop ^= 1; | |
496 | break; | |
5e55efc9 | 497 | case VGA_MIS_W: |
e89f66ec | 498 | s->msr = val & ~0x10; |
cb5a7aa8 | 499 | s->update_retrace_info(s); |
e89f66ec | 500 | break; |
5e55efc9 | 501 | case VGA_SEQ_I: |
e89f66ec FB |
502 | s->sr_index = val & 7; |
503 | break; | |
5e55efc9 | 504 | case VGA_SEQ_D: |
a41bc9af FB |
505 | #ifdef DEBUG_VGA_REG |
506 | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); | |
507 | #endif | |
e89f66ec | 508 | s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
5e55efc9 BS |
509 | if (s->sr_index == VGA_SEQ_CLOCK_MODE) { |
510 | s->update_retrace_info(s); | |
511 | } | |
80763888 | 512 | vga_update_memory_access(s); |
e89f66ec | 513 | break; |
5e55efc9 | 514 | case VGA_PEL_IR: |
e89f66ec FB |
515 | s->dac_read_index = val; |
516 | s->dac_sub_index = 0; | |
517 | s->dac_state = 3; | |
518 | break; | |
5e55efc9 | 519 | case VGA_PEL_IW: |
e89f66ec FB |
520 | s->dac_write_index = val; |
521 | s->dac_sub_index = 0; | |
522 | s->dac_state = 0; | |
523 | break; | |
5e55efc9 | 524 | case VGA_PEL_D: |
e89f66ec FB |
525 | s->dac_cache[s->dac_sub_index] = val; |
526 | if (++s->dac_sub_index == 3) { | |
527 | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); | |
528 | s->dac_sub_index = 0; | |
529 | s->dac_write_index++; | |
530 | } | |
531 | break; | |
5e55efc9 | 532 | case VGA_GFX_I: |
e89f66ec FB |
533 | s->gr_index = val & 0x0f; |
534 | break; | |
5e55efc9 | 535 | case VGA_GFX_D: |
a41bc9af FB |
536 | #ifdef DEBUG_VGA_REG |
537 | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); | |
538 | #endif | |
e89f66ec | 539 | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
80763888 | 540 | vga_update_memory_access(s); |
e89f66ec | 541 | break; |
5e55efc9 BS |
542 | case VGA_CRT_IM: |
543 | case VGA_CRT_IC: | |
e89f66ec FB |
544 | s->cr_index = val; |
545 | break; | |
5e55efc9 BS |
546 | case VGA_CRT_DM: |
547 | case VGA_CRT_DC: | |
a41bc9af FB |
548 | #ifdef DEBUG_VGA_REG |
549 | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val); | |
550 | #endif | |
e89f66ec | 551 | /* handle CR0-7 protection */ |
df800210 | 552 | if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) && |
553 | s->cr_index <= VGA_CRTC_OVERFLOW) { | |
554 | /* can always write bit 4 of CR7 */ | |
555 | if (s->cr_index == VGA_CRTC_OVERFLOW) { | |
556 | s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | | |
557 | (val & 0x10); | |
5e55efc9 | 558 | } |
df800210 | 559 | return; |
e89f66ec | 560 | } |
a46007a0 | 561 | s->cr[s->cr_index] = val; |
cb5a7aa8 | 562 | |
563 | switch(s->cr_index) { | |
5e55efc9 BS |
564 | case VGA_CRTC_H_TOTAL: |
565 | case VGA_CRTC_H_SYNC_START: | |
566 | case VGA_CRTC_H_SYNC_END: | |
567 | case VGA_CRTC_V_TOTAL: | |
568 | case VGA_CRTC_OVERFLOW: | |
569 | case VGA_CRTC_V_SYNC_END: | |
570 | case VGA_CRTC_MODE: | |
cb5a7aa8 | 571 | s->update_retrace_info(s); |
572 | break; | |
573 | } | |
e89f66ec | 574 | break; |
5e55efc9 BS |
575 | case VGA_IS1_RM: |
576 | case VGA_IS1_RC: | |
e89f66ec FB |
577 | s->fcr = val & 0x10; |
578 | break; | |
579 | } | |
580 | } | |
581 | ||
09a79b49 | 582 | static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr) |
4fa0f5d2 | 583 | { |
cedd91d2 | 584 | VGACommonState *s = opaque; |
4fa0f5d2 | 585 | uint32_t val; |
09a79b49 FB |
586 | val = s->vbe_index; |
587 | return val; | |
588 | } | |
4fa0f5d2 | 589 | |
803ff052 | 590 | uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr) |
09a79b49 | 591 | { |
cedd91d2 | 592 | VGACommonState *s = opaque; |
09a79b49 FB |
593 | uint32_t val; |
594 | ||
af92284b | 595 | if (s->vbe_index < VBE_DISPI_INDEX_NB) { |
8454df8b FB |
596 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) { |
597 | switch(s->vbe_index) { | |
598 | /* XXX: do not hardcode ? */ | |
599 | case VBE_DISPI_INDEX_XRES: | |
600 | val = VBE_DISPI_MAX_XRES; | |
601 | break; | |
602 | case VBE_DISPI_INDEX_YRES: | |
603 | val = VBE_DISPI_MAX_YRES; | |
604 | break; | |
605 | case VBE_DISPI_INDEX_BPP: | |
606 | val = VBE_DISPI_MAX_BPP; | |
607 | break; | |
608 | default: | |
5fafdf24 | 609 | val = s->vbe_regs[s->vbe_index]; |
8454df8b FB |
610 | break; |
611 | } | |
612 | } else { | |
5fafdf24 | 613 | val = s->vbe_regs[s->vbe_index]; |
8454df8b | 614 | } |
af92284b GH |
615 | } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) { |
616 | val = s->vram_size / (64 * 1024); | |
8454df8b | 617 | } else { |
09a79b49 | 618 | val = 0; |
8454df8b | 619 | } |
4fa0f5d2 | 620 | #ifdef DEBUG_BOCHS_VBE |
09a79b49 | 621 | printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val); |
4fa0f5d2 | 622 | #endif |
4fa0f5d2 FB |
623 | return val; |
624 | } | |
625 | ||
803ff052 | 626 | void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val) |
09a79b49 | 627 | { |
cedd91d2 | 628 | VGACommonState *s = opaque; |
09a79b49 FB |
629 | s->vbe_index = val; |
630 | } | |
631 | ||
803ff052 | 632 | void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) |
4fa0f5d2 | 633 | { |
cedd91d2 | 634 | VGACommonState *s = opaque; |
4fa0f5d2 | 635 | |
09a79b49 | 636 | if (s->vbe_index <= VBE_DISPI_INDEX_NB) { |
4fa0f5d2 FB |
637 | #ifdef DEBUG_BOCHS_VBE |
638 | printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val); | |
639 | #endif | |
640 | switch(s->vbe_index) { | |
641 | case VBE_DISPI_INDEX_ID: | |
cae61cef FB |
642 | if (val == VBE_DISPI_ID0 || |
643 | val == VBE_DISPI_ID1 || | |
37dd208d FB |
644 | val == VBE_DISPI_ID2 || |
645 | val == VBE_DISPI_ID3 || | |
646 | val == VBE_DISPI_ID4) { | |
cae61cef FB |
647 | s->vbe_regs[s->vbe_index] = val; |
648 | } | |
4fa0f5d2 FB |
649 | break; |
650 | case VBE_DISPI_INDEX_XRES: | |
cae61cef FB |
651 | if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) { |
652 | s->vbe_regs[s->vbe_index] = val; | |
653 | } | |
4fa0f5d2 FB |
654 | break; |
655 | case VBE_DISPI_INDEX_YRES: | |
cae61cef FB |
656 | if (val <= VBE_DISPI_MAX_YRES) { |
657 | s->vbe_regs[s->vbe_index] = val; | |
658 | } | |
4fa0f5d2 FB |
659 | break; |
660 | case VBE_DISPI_INDEX_BPP: | |
661 | if (val == 0) | |
662 | val = 8; | |
5fafdf24 | 663 | if (val == 4 || val == 8 || val == 15 || |
cae61cef FB |
664 | val == 16 || val == 24 || val == 32) { |
665 | s->vbe_regs[s->vbe_index] = val; | |
666 | } | |
4fa0f5d2 FB |
667 | break; |
668 | case VBE_DISPI_INDEX_BANK: | |
42fc925e FB |
669 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
670 | val &= (s->vbe_bank_mask >> 2); | |
671 | } else { | |
672 | val &= s->vbe_bank_mask; | |
673 | } | |
cae61cef | 674 | s->vbe_regs[s->vbe_index] = val; |
26aa7d72 | 675 | s->bank_offset = (val << 16); |
80763888 | 676 | vga_update_memory_access(s); |
4fa0f5d2 FB |
677 | break; |
678 | case VBE_DISPI_INDEX_ENABLE: | |
8454df8b FB |
679 | if ((val & VBE_DISPI_ENABLED) && |
680 | !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) { | |
4fa0f5d2 FB |
681 | int h, shift_control; |
682 | ||
5fafdf24 | 683 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = |
4fa0f5d2 | 684 | s->vbe_regs[VBE_DISPI_INDEX_XRES]; |
5fafdf24 | 685 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = |
4fa0f5d2 FB |
686 | s->vbe_regs[VBE_DISPI_INDEX_YRES]; |
687 | s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0; | |
688 | s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0; | |
3b46e624 | 689 | |
4fa0f5d2 FB |
690 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) |
691 | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1; | |
692 | else | |
5fafdf24 | 693 | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * |
4fa0f5d2 FB |
694 | ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); |
695 | s->vbe_start_addr = 0; | |
8454df8b | 696 | |
4fa0f5d2 FB |
697 | /* clear the screen (should be done in BIOS) */ |
698 | if (!(val & VBE_DISPI_NOCLEARMEM)) { | |
5fafdf24 | 699 | memset(s->vram_ptr, 0, |
4fa0f5d2 FB |
700 | s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset); |
701 | } | |
3b46e624 | 702 | |
cae61cef FB |
703 | /* we initialize the VGA graphic mode (should be done |
704 | in BIOS) */ | |
5e55efc9 BS |
705 | /* graphic mode + memory map 1 */ |
706 | s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 | | |
707 | VGA_GR06_GRAPHICS_MODE; | |
708 | s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */ | |
709 | s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3; | |
4fa0f5d2 | 710 | /* width */ |
5e55efc9 BS |
711 | s->cr[VGA_CRTC_H_DISP] = |
712 | (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; | |
8454df8b | 713 | /* height (only meaningful if < 1024) */ |
4fa0f5d2 | 714 | h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1; |
5e55efc9 BS |
715 | s->cr[VGA_CRTC_V_DISP_END] = h; |
716 | s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | | |
4fa0f5d2 FB |
717 | ((h >> 7) & 0x02) | ((h >> 3) & 0x40); |
718 | /* line compare to 1023 */ | |
5e55efc9 BS |
719 | s->cr[VGA_CRTC_LINE_COMPARE] = 0xff; |
720 | s->cr[VGA_CRTC_OVERFLOW] |= 0x10; | |
721 | s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; | |
3b46e624 | 722 | |
4fa0f5d2 FB |
723 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
724 | shift_control = 0; | |
5e55efc9 | 725 | s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */ |
4fa0f5d2 FB |
726 | } else { |
727 | shift_control = 2; | |
5e55efc9 BS |
728 | /* set chain 4 mode */ |
729 | s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M; | |
730 | /* activate all planes */ | |
731 | s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES; | |
4fa0f5d2 | 732 | } |
5e55efc9 BS |
733 | s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) | |
734 | (shift_control << 5); | |
735 | s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */ | |
cae61cef FB |
736 | } else { |
737 | /* XXX: the bios should do that */ | |
26aa7d72 | 738 | s->bank_offset = 0; |
cae61cef | 739 | } |
37dd208d | 740 | s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0; |
141253b2 | 741 | s->vbe_regs[s->vbe_index] = val; |
80763888 | 742 | vga_update_memory_access(s); |
cae61cef FB |
743 | break; |
744 | case VBE_DISPI_INDEX_VIRT_WIDTH: | |
745 | { | |
746 | int w, h, line_offset; | |
747 | ||
748 | if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES]) | |
749 | return; | |
750 | w = val; | |
751 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) | |
752 | line_offset = w >> 1; | |
753 | else | |
754 | line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); | |
755 | h = s->vram_size / line_offset; | |
756 | /* XXX: support weird bochs semantics ? */ | |
757 | if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES]) | |
758 | return; | |
759 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w; | |
760 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h; | |
761 | s->vbe_line_offset = line_offset; | |
762 | } | |
763 | break; | |
764 | case VBE_DISPI_INDEX_X_OFFSET: | |
765 | case VBE_DISPI_INDEX_Y_OFFSET: | |
766 | { | |
767 | int x; | |
768 | s->vbe_regs[s->vbe_index] = val; | |
769 | s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET]; | |
770 | x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET]; | |
771 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) | |
772 | s->vbe_start_addr += x >> 1; | |
773 | else | |
774 | s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); | |
775 | s->vbe_start_addr >>= 2; | |
4fa0f5d2 FB |
776 | } |
777 | break; | |
778 | default: | |
779 | break; | |
780 | } | |
4fa0f5d2 FB |
781 | } |
782 | } | |
4fa0f5d2 | 783 | |
e89f66ec | 784 | /* called for accesses between 0xa0000 and 0xc0000 */ |
a8170e5e | 785 | uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr) |
e89f66ec | 786 | { |
e89f66ec FB |
787 | int memory_map_mode, plane; |
788 | uint32_t ret; | |
3b46e624 | 789 | |
e89f66ec | 790 | /* convert to VGA memory offset */ |
5e55efc9 | 791 | memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; |
26aa7d72 | 792 | addr &= 0x1ffff; |
e89f66ec FB |
793 | switch(memory_map_mode) { |
794 | case 0: | |
e89f66ec FB |
795 | break; |
796 | case 1: | |
26aa7d72 | 797 | if (addr >= 0x10000) |
e89f66ec | 798 | return 0xff; |
cae61cef | 799 | addr += s->bank_offset; |
e89f66ec FB |
800 | break; |
801 | case 2: | |
26aa7d72 | 802 | addr -= 0x10000; |
e89f66ec FB |
803 | if (addr >= 0x8000) |
804 | return 0xff; | |
805 | break; | |
806 | default: | |
807 | case 3: | |
26aa7d72 | 808 | addr -= 0x18000; |
c92b2e84 FB |
809 | if (addr >= 0x8000) |
810 | return 0xff; | |
e89f66ec FB |
811 | break; |
812 | } | |
3b46e624 | 813 | |
5e55efc9 | 814 | if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { |
e89f66ec FB |
815 | /* chain 4 mode : simplest access */ |
816 | ret = s->vram_ptr[addr]; | |
5e55efc9 | 817 | } else if (s->gr[VGA_GFX_MODE] & 0x10) { |
e89f66ec | 818 | /* odd/even mode (aka text mode mapping) */ |
5e55efc9 | 819 | plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); |
e89f66ec FB |
820 | ret = s->vram_ptr[((addr & ~1) << 1) | plane]; |
821 | } else { | |
822 | /* standard VGA latched access */ | |
823 | s->latch = ((uint32_t *)s->vram_ptr)[addr]; | |
824 | ||
5e55efc9 | 825 | if (!(s->gr[VGA_GFX_MODE] & 0x08)) { |
e89f66ec | 826 | /* read mode 0 */ |
5e55efc9 | 827 | plane = s->gr[VGA_GFX_PLANE_READ]; |
b8ed223b | 828 | ret = GET_PLANE(s->latch, plane); |
e89f66ec FB |
829 | } else { |
830 | /* read mode 1 */ | |
5e55efc9 BS |
831 | ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) & |
832 | mask16[s->gr[VGA_GFX_COMPARE_MASK]]; | |
e89f66ec FB |
833 | ret |= ret >> 16; |
834 | ret |= ret >> 8; | |
835 | ret = (~ret) & 0xff; | |
836 | } | |
837 | } | |
838 | return ret; | |
839 | } | |
840 | ||
e89f66ec | 841 | /* called for accesses between 0xa0000 and 0xc0000 */ |
a8170e5e | 842 | void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) |
e89f66ec | 843 | { |
546fa6ab | 844 | int memory_map_mode, plane, write_mode, b, func_select, mask; |
e89f66ec FB |
845 | uint32_t write_mask, bit_mask, set_mask; |
846 | ||
17b0018b | 847 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 848 | printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val); |
e89f66ec FB |
849 | #endif |
850 | /* convert to VGA memory offset */ | |
5e55efc9 | 851 | memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; |
26aa7d72 | 852 | addr &= 0x1ffff; |
e89f66ec FB |
853 | switch(memory_map_mode) { |
854 | case 0: | |
e89f66ec FB |
855 | break; |
856 | case 1: | |
26aa7d72 | 857 | if (addr >= 0x10000) |
e89f66ec | 858 | return; |
cae61cef | 859 | addr += s->bank_offset; |
e89f66ec FB |
860 | break; |
861 | case 2: | |
26aa7d72 | 862 | addr -= 0x10000; |
e89f66ec FB |
863 | if (addr >= 0x8000) |
864 | return; | |
865 | break; | |
866 | default: | |
867 | case 3: | |
26aa7d72 | 868 | addr -= 0x18000; |
c92b2e84 FB |
869 | if (addr >= 0x8000) |
870 | return; | |
e89f66ec FB |
871 | break; |
872 | } | |
3b46e624 | 873 | |
5e55efc9 | 874 | if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { |
e89f66ec FB |
875 | /* chain 4 mode : simplest access */ |
876 | plane = addr & 3; | |
546fa6ab | 877 | mask = (1 << plane); |
5e55efc9 | 878 | if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) { |
e89f66ec | 879 | s->vram_ptr[addr] = val; |
17b0018b | 880 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 881 | printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr); |
e89f66ec | 882 | #endif |
546fa6ab | 883 | s->plane_updated |= mask; /* only used to detect font change */ |
fd4aa979 | 884 | memory_region_set_dirty(&s->vram, addr, 1); |
e89f66ec | 885 | } |
5e55efc9 | 886 | } else if (s->gr[VGA_GFX_MODE] & 0x10) { |
e89f66ec | 887 | /* odd/even mode (aka text mode mapping) */ |
5e55efc9 | 888 | plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); |
546fa6ab | 889 | mask = (1 << plane); |
5e55efc9 | 890 | if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) { |
e89f66ec FB |
891 | addr = ((addr & ~1) << 1) | plane; |
892 | s->vram_ptr[addr] = val; | |
17b0018b | 893 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 894 | printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr); |
e89f66ec | 895 | #endif |
546fa6ab | 896 | s->plane_updated |= mask; /* only used to detect font change */ |
fd4aa979 | 897 | memory_region_set_dirty(&s->vram, addr, 1); |
e89f66ec FB |
898 | } |
899 | } else { | |
900 | /* standard VGA latched access */ | |
5e55efc9 | 901 | write_mode = s->gr[VGA_GFX_MODE] & 3; |
e89f66ec FB |
902 | switch(write_mode) { |
903 | default: | |
904 | case 0: | |
905 | /* rotate */ | |
5e55efc9 | 906 | b = s->gr[VGA_GFX_DATA_ROTATE] & 7; |
e89f66ec FB |
907 | val = ((val >> b) | (val << (8 - b))) & 0xff; |
908 | val |= val << 8; | |
909 | val |= val << 16; | |
910 | ||
911 | /* apply set/reset mask */ | |
5e55efc9 BS |
912 | set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]]; |
913 | val = (val & ~set_mask) | | |
914 | (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask); | |
915 | bit_mask = s->gr[VGA_GFX_BIT_MASK]; | |
e89f66ec FB |
916 | break; |
917 | case 1: | |
918 | val = s->latch; | |
919 | goto do_write; | |
920 | case 2: | |
921 | val = mask16[val & 0x0f]; | |
5e55efc9 | 922 | bit_mask = s->gr[VGA_GFX_BIT_MASK]; |
e89f66ec FB |
923 | break; |
924 | case 3: | |
925 | /* rotate */ | |
5e55efc9 | 926 | b = s->gr[VGA_GFX_DATA_ROTATE] & 7; |
a41bc9af | 927 | val = (val >> b) | (val << (8 - b)); |
e89f66ec | 928 | |
5e55efc9 BS |
929 | bit_mask = s->gr[VGA_GFX_BIT_MASK] & val; |
930 | val = mask16[s->gr[VGA_GFX_SR_VALUE]]; | |
e89f66ec FB |
931 | break; |
932 | } | |
933 | ||
934 | /* apply logical operation */ | |
5e55efc9 | 935 | func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3; |
e89f66ec FB |
936 | switch(func_select) { |
937 | case 0: | |
938 | default: | |
939 | /* nothing to do */ | |
940 | break; | |
941 | case 1: | |
942 | /* and */ | |
943 | val &= s->latch; | |
944 | break; | |
945 | case 2: | |
946 | /* or */ | |
947 | val |= s->latch; | |
948 | break; | |
949 | case 3: | |
950 | /* xor */ | |
951 | val ^= s->latch; | |
952 | break; | |
953 | } | |
954 | ||
955 | /* apply bit mask */ | |
956 | bit_mask |= bit_mask << 8; | |
957 | bit_mask |= bit_mask << 16; | |
958 | val = (val & bit_mask) | (s->latch & ~bit_mask); | |
959 | ||
960 | do_write: | |
961 | /* mask data according to sr[2] */ | |
5e55efc9 | 962 | mask = s->sr[VGA_SEQ_PLANE_WRITE]; |
546fa6ab FB |
963 | s->plane_updated |= mask; /* only used to detect font change */ |
964 | write_mask = mask16[mask]; | |
5fafdf24 TS |
965 | ((uint32_t *)s->vram_ptr)[addr] = |
966 | (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | | |
e89f66ec | 967 | (val & write_mask); |
17b0018b | 968 | #ifdef DEBUG_VGA_MEM |
0bf9e31a BS |
969 | printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n", |
970 | addr * 4, write_mask, val); | |
e89f66ec | 971 | #endif |
fd4aa979 | 972 | memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); |
e89f66ec FB |
973 | } |
974 | } | |
975 | ||
e89f66ec FB |
976 | typedef void vga_draw_glyph8_func(uint8_t *d, int linesize, |
977 | const uint8_t *font_ptr, int h, | |
978 | uint32_t fgcol, uint32_t bgcol); | |
979 | typedef void vga_draw_glyph9_func(uint8_t *d, int linesize, | |
5fafdf24 | 980 | const uint8_t *font_ptr, int h, |
e89f66ec | 981 | uint32_t fgcol, uint32_t bgcol, int dup9); |
cedd91d2 | 982 | typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d, |
e89f66ec FB |
983 | const uint8_t *s, int width); |
984 | ||
e89f66ec | 985 | #define DEPTH 8 |
47b43a1f | 986 | #include "vga_template.h" |
e89f66ec FB |
987 | |
988 | #define DEPTH 15 | |
47b43a1f | 989 | #include "vga_template.h" |
e89f66ec | 990 | |
a2502b58 BS |
991 | #define BGR_FORMAT |
992 | #define DEPTH 15 | |
47b43a1f | 993 | #include "vga_template.h" |
a2502b58 BS |
994 | |
995 | #define DEPTH 16 | |
47b43a1f | 996 | #include "vga_template.h" |
a2502b58 BS |
997 | |
998 | #define BGR_FORMAT | |
e89f66ec | 999 | #define DEPTH 16 |
47b43a1f | 1000 | #include "vga_template.h" |
e89f66ec FB |
1001 | |
1002 | #define DEPTH 32 | |
47b43a1f | 1003 | #include "vga_template.h" |
e89f66ec | 1004 | |
d3079cd2 FB |
1005 | #define BGR_FORMAT |
1006 | #define DEPTH 32 | |
47b43a1f | 1007 | #include "vga_template.h" |
d3079cd2 | 1008 | |
17b0018b FB |
1009 | static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b) |
1010 | { | |
1011 | unsigned int col; | |
1012 | col = rgb_to_pixel8(r, g, b); | |
1013 | col |= col << 8; | |
1014 | col |= col << 16; | |
1015 | return col; | |
1016 | } | |
1017 | ||
1018 | static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b) | |
1019 | { | |
1020 | unsigned int col; | |
1021 | col = rgb_to_pixel15(r, g, b); | |
1022 | col |= col << 16; | |
1023 | return col; | |
1024 | } | |
1025 | ||
b29169d2 BS |
1026 | static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g, |
1027 | unsigned int b) | |
1028 | { | |
1029 | unsigned int col; | |
1030 | col = rgb_to_pixel15bgr(r, g, b); | |
1031 | col |= col << 16; | |
1032 | return col; | |
1033 | } | |
1034 | ||
17b0018b FB |
1035 | static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b) |
1036 | { | |
1037 | unsigned int col; | |
1038 | col = rgb_to_pixel16(r, g, b); | |
1039 | col |= col << 16; | |
1040 | return col; | |
1041 | } | |
1042 | ||
b29169d2 BS |
1043 | static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g, |
1044 | unsigned int b) | |
1045 | { | |
1046 | unsigned int col; | |
1047 | col = rgb_to_pixel16bgr(r, g, b); | |
1048 | col |= col << 16; | |
1049 | return col; | |
1050 | } | |
1051 | ||
17b0018b FB |
1052 | static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b) |
1053 | { | |
1054 | unsigned int col; | |
1055 | col = rgb_to_pixel32(r, g, b); | |
1056 | return col; | |
1057 | } | |
1058 | ||
d3079cd2 FB |
1059 | static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b) |
1060 | { | |
1061 | unsigned int col; | |
1062 | col = rgb_to_pixel32bgr(r, g, b); | |
1063 | return col; | |
1064 | } | |
1065 | ||
e89f66ec | 1066 | /* return true if the palette was modified */ |
cedd91d2 | 1067 | static int update_palette16(VGACommonState *s) |
e89f66ec | 1068 | { |
17b0018b | 1069 | int full_update, i; |
e89f66ec | 1070 | uint32_t v, col, *palette; |
e89f66ec FB |
1071 | |
1072 | full_update = 0; | |
1073 | palette = s->last_palette; | |
1074 | for(i = 0; i < 16; i++) { | |
1075 | v = s->ar[i]; | |
5e55efc9 BS |
1076 | if (s->ar[VGA_ATC_MODE] & 0x80) { |
1077 | v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf); | |
1078 | } else { | |
1079 | v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f); | |
1080 | } | |
e89f66ec | 1081 | v = v * 3; |
5fafdf24 TS |
1082 | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
1083 | c6_to_8(s->palette[v + 1]), | |
17b0018b FB |
1084 | c6_to_8(s->palette[v + 2])); |
1085 | if (col != palette[i]) { | |
1086 | full_update = 1; | |
1087 | palette[i] = col; | |
e89f66ec | 1088 | } |
17b0018b FB |
1089 | } |
1090 | return full_update; | |
1091 | } | |
1092 | ||
1093 | /* return true if the palette was modified */ | |
cedd91d2 | 1094 | static int update_palette256(VGACommonState *s) |
17b0018b FB |
1095 | { |
1096 | int full_update, i; | |
1097 | uint32_t v, col, *palette; | |
1098 | ||
1099 | full_update = 0; | |
1100 | palette = s->last_palette; | |
1101 | v = 0; | |
1102 | for(i = 0; i < 256; i++) { | |
37dd208d | 1103 | if (s->dac_8bit) { |
5fafdf24 TS |
1104 | col = s->rgb_to_pixel(s->palette[v], |
1105 | s->palette[v + 1], | |
37dd208d FB |
1106 | s->palette[v + 2]); |
1107 | } else { | |
5fafdf24 TS |
1108 | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
1109 | c6_to_8(s->palette[v + 1]), | |
37dd208d FB |
1110 | c6_to_8(s->palette[v + 2])); |
1111 | } | |
e89f66ec FB |
1112 | if (col != palette[i]) { |
1113 | full_update = 1; | |
1114 | palette[i] = col; | |
1115 | } | |
17b0018b | 1116 | v += 3; |
e89f66ec FB |
1117 | } |
1118 | return full_update; | |
1119 | } | |
1120 | ||
cedd91d2 | 1121 | static void vga_get_offsets(VGACommonState *s, |
5fafdf24 | 1122 | uint32_t *pline_offset, |
83acc96b FB |
1123 | uint32_t *pstart_addr, |
1124 | uint32_t *pline_compare) | |
e89f66ec | 1125 | { |
83acc96b | 1126 | uint32_t start_addr, line_offset, line_compare; |
a96d8bea | 1127 | |
4fa0f5d2 FB |
1128 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { |
1129 | line_offset = s->vbe_line_offset; | |
1130 | start_addr = s->vbe_start_addr; | |
83acc96b | 1131 | line_compare = 65535; |
a96d8bea | 1132 | } else { |
4fa0f5d2 | 1133 | /* compute line_offset in bytes */ |
5e55efc9 | 1134 | line_offset = s->cr[VGA_CRTC_OFFSET]; |
4fa0f5d2 | 1135 | line_offset <<= 3; |
08e48902 | 1136 | |
4fa0f5d2 | 1137 | /* starting address */ |
5e55efc9 BS |
1138 | start_addr = s->cr[VGA_CRTC_START_LO] | |
1139 | (s->cr[VGA_CRTC_START_HI] << 8); | |
83acc96b FB |
1140 | |
1141 | /* line compare */ | |
5e55efc9 BS |
1142 | line_compare = s->cr[VGA_CRTC_LINE_COMPARE] | |
1143 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) | | |
1144 | ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3); | |
4fa0f5d2 | 1145 | } |
798b0c25 FB |
1146 | *pline_offset = line_offset; |
1147 | *pstart_addr = start_addr; | |
83acc96b | 1148 | *pline_compare = line_compare; |
798b0c25 FB |
1149 | } |
1150 | ||
1151 | /* update start_addr and line_offset. Return TRUE if modified */ | |
cedd91d2 | 1152 | static int update_basic_params(VGACommonState *s) |
798b0c25 FB |
1153 | { |
1154 | int full_update; | |
1155 | uint32_t start_addr, line_offset, line_compare; | |
3b46e624 | 1156 | |
798b0c25 FB |
1157 | full_update = 0; |
1158 | ||
83acc96b | 1159 | s->get_offsets(s, &line_offset, &start_addr, &line_compare); |
e89f66ec FB |
1160 | |
1161 | if (line_offset != s->line_offset || | |
1162 | start_addr != s->start_addr || | |
1163 | line_compare != s->line_compare) { | |
1164 | s->line_offset = line_offset; | |
1165 | s->start_addr = start_addr; | |
1166 | s->line_compare = line_compare; | |
1167 | full_update = 1; | |
1168 | } | |
1169 | return full_update; | |
1170 | } | |
1171 | ||
b29169d2 | 1172 | #define NB_DEPTHS 7 |
d3079cd2 | 1173 | |
c78f7137 | 1174 | static inline int get_depth_index(DisplaySurface *s) |
e89f66ec | 1175 | { |
c78f7137 | 1176 | switch (surface_bits_per_pixel(s)) { |
e89f66ec FB |
1177 | default: |
1178 | case 8: | |
1179 | return 0; | |
1180 | case 15: | |
8927bcfd | 1181 | return 1; |
e89f66ec | 1182 | case 16: |
8927bcfd | 1183 | return 2; |
e89f66ec | 1184 | case 32: |
c78f7137 | 1185 | if (is_surface_bgr(s)) { |
7b5d76da | 1186 | return 4; |
c78f7137 | 1187 | } else { |
7b5d76da | 1188 | return 3; |
c78f7137 | 1189 | } |
e89f66ec FB |
1190 | } |
1191 | } | |
1192 | ||
68f04a3c | 1193 | static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = { |
e89f66ec FB |
1194 | vga_draw_glyph8_8, |
1195 | vga_draw_glyph8_16, | |
1196 | vga_draw_glyph8_16, | |
1197 | vga_draw_glyph8_32, | |
d3079cd2 | 1198 | vga_draw_glyph8_32, |
b29169d2 BS |
1199 | vga_draw_glyph8_16, |
1200 | vga_draw_glyph8_16, | |
e89f66ec FB |
1201 | }; |
1202 | ||
68f04a3c | 1203 | static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = { |
17b0018b FB |
1204 | vga_draw_glyph16_8, |
1205 | vga_draw_glyph16_16, | |
1206 | vga_draw_glyph16_16, | |
1207 | vga_draw_glyph16_32, | |
d3079cd2 | 1208 | vga_draw_glyph16_32, |
b29169d2 BS |
1209 | vga_draw_glyph16_16, |
1210 | vga_draw_glyph16_16, | |
17b0018b FB |
1211 | }; |
1212 | ||
68f04a3c | 1213 | static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = { |
e89f66ec FB |
1214 | vga_draw_glyph9_8, |
1215 | vga_draw_glyph9_16, | |
1216 | vga_draw_glyph9_16, | |
1217 | vga_draw_glyph9_32, | |
d3079cd2 | 1218 | vga_draw_glyph9_32, |
b29169d2 BS |
1219 | vga_draw_glyph9_16, |
1220 | vga_draw_glyph9_16, | |
e89f66ec | 1221 | }; |
3b46e624 | 1222 | |
e89f66ec FB |
1223 | static const uint8_t cursor_glyph[32 * 4] = { |
1224 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1225 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1226 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1227 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1228 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1229 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1230 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1231 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1232 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1233 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1234 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1235 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1236 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1237 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1238 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1239 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
3b46e624 | 1240 | }; |
e89f66ec | 1241 | |
cedd91d2 | 1242 | static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight, |
4c5e8c5c BS |
1243 | int *pcwidth, int *pcheight) |
1244 | { | |
1245 | int width, cwidth, height, cheight; | |
1246 | ||
1247 | /* total width & height */ | |
5e55efc9 | 1248 | cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; |
4c5e8c5c | 1249 | cwidth = 8; |
5e55efc9 | 1250 | if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) { |
4c5e8c5c | 1251 | cwidth = 9; |
5e55efc9 BS |
1252 | } |
1253 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) { | |
4c5e8c5c | 1254 | cwidth = 16; /* NOTE: no 18 pixel wide */ |
5e55efc9 BS |
1255 | } |
1256 | width = (s->cr[VGA_CRTC_H_DISP] + 1); | |
1257 | if (s->cr[VGA_CRTC_V_TOTAL] == 100) { | |
4c5e8c5c BS |
1258 | /* ugly hack for CGA 160x100x16 - explain me the logic */ |
1259 | height = 100; | |
1260 | } else { | |
5e55efc9 BS |
1261 | height = s->cr[VGA_CRTC_V_DISP_END] | |
1262 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
1263 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
4c5e8c5c BS |
1264 | height = (height + 1) / cheight; |
1265 | } | |
1266 | ||
1267 | *pwidth = width; | |
1268 | *pheight = height; | |
1269 | *pcwidth = cwidth; | |
1270 | *pcheight = cheight; | |
1271 | } | |
1272 | ||
7d957bd8 AL |
1273 | typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b); |
1274 | ||
68f04a3c | 1275 | static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = { |
bdb19571 AL |
1276 | rgb_to_pixel8_dup, |
1277 | rgb_to_pixel15_dup, | |
1278 | rgb_to_pixel16_dup, | |
1279 | rgb_to_pixel32_dup, | |
1280 | rgb_to_pixel32bgr_dup, | |
1281 | rgb_to_pixel15bgr_dup, | |
1282 | rgb_to_pixel16bgr_dup, | |
1283 | }; | |
7d957bd8 | 1284 | |
5fafdf24 TS |
1285 | /* |
1286 | * Text mode update | |
e89f66ec FB |
1287 | * Missing: |
1288 | * - double scan | |
5fafdf24 | 1289 | * - double width |
e89f66ec FB |
1290 | * - underline |
1291 | * - flashing | |
1292 | */ | |
cedd91d2 | 1293 | static void vga_draw_text(VGACommonState *s, int full_update) |
e89f66ec | 1294 | { |
c78f7137 | 1295 | DisplaySurface *surface = qemu_console_surface(s->con); |
e89f66ec | 1296 | int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr; |
cae334cd | 1297 | int cx_min, cx_max, linesize, x_incr, line, line1; |
e89f66ec | 1298 | uint32_t offset, fgcol, bgcol, v, cursor_offset; |
d1984194 | 1299 | uint8_t *d1, *d, *src, *dest, *cursor_ptr; |
e89f66ec FB |
1300 | const uint8_t *font_ptr, *font_base[2]; |
1301 | int dup9, line_offset, depth_index; | |
1302 | uint32_t *palette; | |
1303 | uint32_t *ch_attr_ptr; | |
1304 | vga_draw_glyph8_func *vga_draw_glyph8; | |
1305 | vga_draw_glyph9_func *vga_draw_glyph9; | |
9aa0ff0b | 1306 | int64_t now = qemu_get_clock_ms(vm_clock); |
e89f66ec | 1307 | |
e89f66ec | 1308 | /* compute font data address (in plane 2) */ |
5e55efc9 | 1309 | v = s->sr[VGA_SEQ_CHARACTER_MAP]; |
1078f663 | 1310 | offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2; |
e89f66ec FB |
1311 | if (offset != s->font_offsets[0]) { |
1312 | s->font_offsets[0] = offset; | |
1313 | full_update = 1; | |
1314 | } | |
1315 | font_base[0] = s->vram_ptr + offset; | |
1316 | ||
1078f663 | 1317 | offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2; |
e89f66ec FB |
1318 | font_base[1] = s->vram_ptr + offset; |
1319 | if (offset != s->font_offsets[1]) { | |
1320 | s->font_offsets[1] = offset; | |
1321 | full_update = 1; | |
1322 | } | |
80763888 | 1323 | if (s->plane_updated & (1 << 2) || s->chain4_alias) { |
546fa6ab FB |
1324 | /* if the plane 2 was modified since the last display, it |
1325 | indicates the font may have been modified */ | |
1326 | s->plane_updated = 0; | |
1327 | full_update = 1; | |
1328 | } | |
799e709b | 1329 | full_update |= update_basic_params(s); |
e89f66ec FB |
1330 | |
1331 | line_offset = s->line_offset; | |
e89f66ec | 1332 | |
4c5e8c5c | 1333 | vga_get_text_resolution(s, &width, &height, &cw, &cheight); |
1b296044 SW |
1334 | if ((height * width) <= 1) { |
1335 | /* better than nothing: exit if transient size is too small */ | |
1336 | return; | |
1337 | } | |
3294b949 FB |
1338 | if ((height * width) > CH_ATTR_SIZE) { |
1339 | /* better than nothing: exit if transient size is too big */ | |
1340 | return; | |
1341 | } | |
1342 | ||
799e709b AL |
1343 | if (width != s->last_width || height != s->last_height || |
1344 | cw != s->last_cw || cheight != s->last_ch || s->last_depth) { | |
1345 | s->last_scr_width = width * cw; | |
1346 | s->last_scr_height = height * cheight; | |
c78f7137 GH |
1347 | qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height); |
1348 | surface = qemu_console_surface(s->con); | |
1349 | dpy_text_resize(s->con, width, height); | |
799e709b AL |
1350 | s->last_depth = 0; |
1351 | s->last_width = width; | |
1352 | s->last_height = height; | |
1353 | s->last_ch = cheight; | |
1354 | s->last_cw = cw; | |
1355 | full_update = 1; | |
1356 | } | |
7d957bd8 | 1357 | s->rgb_to_pixel = |
c78f7137 | 1358 | rgb_to_pixel_dup_table[get_depth_index(surface)]; |
7d957bd8 AL |
1359 | full_update |= update_palette16(s); |
1360 | palette = s->last_palette; | |
c78f7137 | 1361 | x_incr = cw * surface_bytes_per_pixel(surface); |
7d957bd8 | 1362 | |
9678aedd GH |
1363 | if (full_update) { |
1364 | s->full_update_text = 1; | |
1365 | } | |
1366 | if (s->full_update_gfx) { | |
1367 | s->full_update_gfx = 0; | |
1368 | full_update |= 1; | |
1369 | } | |
1370 | ||
5e55efc9 BS |
1371 | cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | |
1372 | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; | |
e89f66ec | 1373 | if (cursor_offset != s->cursor_offset || |
5e55efc9 BS |
1374 | s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || |
1375 | s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) { | |
e89f66ec FB |
1376 | /* if the cursor position changed, we update the old and new |
1377 | chars */ | |
1378 | if (s->cursor_offset < CH_ATTR_SIZE) | |
1379 | s->last_ch_attr[s->cursor_offset] = -1; | |
1380 | if (cursor_offset < CH_ATTR_SIZE) | |
1381 | s->last_ch_attr[cursor_offset] = -1; | |
1382 | s->cursor_offset = cursor_offset; | |
5e55efc9 BS |
1383 | s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; |
1384 | s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; | |
e89f66ec | 1385 | } |
39cf7803 | 1386 | cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4; |
9aa0ff0b JK |
1387 | if (now >= s->cursor_blink_time) { |
1388 | s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2; | |
1389 | s->cursor_visible_phase = !s->cursor_visible_phase; | |
1390 | } | |
3b46e624 | 1391 | |
c78f7137 | 1392 | depth_index = get_depth_index(surface); |
17b0018b FB |
1393 | if (cw == 16) |
1394 | vga_draw_glyph8 = vga_draw_glyph16_table[depth_index]; | |
1395 | else | |
1396 | vga_draw_glyph8 = vga_draw_glyph8_table[depth_index]; | |
e89f66ec | 1397 | vga_draw_glyph9 = vga_draw_glyph9_table[depth_index]; |
3b46e624 | 1398 | |
c78f7137 GH |
1399 | dest = surface_data(surface); |
1400 | linesize = surface_stride(surface); | |
e89f66ec | 1401 | ch_attr_ptr = s->last_ch_attr; |
d1984194 | 1402 | line = 0; |
1403 | offset = s->start_addr * 4; | |
e89f66ec FB |
1404 | for(cy = 0; cy < height; cy++) { |
1405 | d1 = dest; | |
d1984194 | 1406 | src = s->vram_ptr + offset; |
e89f66ec FB |
1407 | cx_min = width; |
1408 | cx_max = -1; | |
1409 | for(cx = 0; cx < width; cx++) { | |
1410 | ch_attr = *(uint16_t *)src; | |
9aa0ff0b | 1411 | if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) { |
e89f66ec FB |
1412 | if (cx < cx_min) |
1413 | cx_min = cx; | |
1414 | if (cx > cx_max) | |
1415 | cx_max = cx; | |
1416 | *ch_attr_ptr = ch_attr; | |
e2542fe2 | 1417 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
1418 | ch = ch_attr >> 8; |
1419 | cattr = ch_attr & 0xff; | |
1420 | #else | |
1421 | ch = ch_attr & 0xff; | |
1422 | cattr = ch_attr >> 8; | |
1423 | #endif | |
1424 | font_ptr = font_base[(cattr >> 3) & 1]; | |
1425 | font_ptr += 32 * 4 * ch; | |
1426 | bgcol = palette[cattr >> 4]; | |
1427 | fgcol = palette[cattr & 0x0f]; | |
17b0018b | 1428 | if (cw != 9) { |
5fafdf24 | 1429 | vga_draw_glyph8(d1, linesize, |
e89f66ec FB |
1430 | font_ptr, cheight, fgcol, bgcol); |
1431 | } else { | |
1432 | dup9 = 0; | |
5e55efc9 BS |
1433 | if (ch >= 0xb0 && ch <= 0xdf && |
1434 | (s->ar[VGA_ATC_MODE] & 0x04)) { | |
e89f66ec | 1435 | dup9 = 1; |
5e55efc9 | 1436 | } |
5fafdf24 | 1437 | vga_draw_glyph9(d1, linesize, |
e89f66ec FB |
1438 | font_ptr, cheight, fgcol, bgcol, dup9); |
1439 | } | |
1440 | if (src == cursor_ptr && | |
9aa0ff0b JK |
1441 | !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) && |
1442 | s->cursor_visible_phase) { | |
e89f66ec FB |
1443 | int line_start, line_last, h; |
1444 | /* draw the cursor */ | |
5e55efc9 BS |
1445 | line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f; |
1446 | line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f; | |
e89f66ec FB |
1447 | /* XXX: check that */ |
1448 | if (line_last > cheight - 1) | |
1449 | line_last = cheight - 1; | |
1450 | if (line_last >= line_start && line_start < cheight) { | |
1451 | h = line_last - line_start + 1; | |
1452 | d = d1 + linesize * line_start; | |
17b0018b | 1453 | if (cw != 9) { |
5fafdf24 | 1454 | vga_draw_glyph8(d, linesize, |
e89f66ec FB |
1455 | cursor_glyph, h, fgcol, bgcol); |
1456 | } else { | |
5fafdf24 | 1457 | vga_draw_glyph9(d, linesize, |
e89f66ec FB |
1458 | cursor_glyph, h, fgcol, bgcol, 1); |
1459 | } | |
1460 | } | |
1461 | } | |
1462 | } | |
1463 | d1 += x_incr; | |
1464 | src += 4; | |
1465 | ch_attr_ptr++; | |
1466 | } | |
1467 | if (cx_max != -1) { | |
c78f7137 | 1468 | dpy_gfx_update(s->con, cx_min * cw, cy * cheight, |
a93a4a22 | 1469 | (cx_max - cx_min + 1) * cw, cheight); |
e89f66ec FB |
1470 | } |
1471 | dest += linesize * cheight; | |
cae334cd | 1472 | line1 = line + cheight; |
1473 | offset += line_offset; | |
1474 | if (line < s->line_compare && line1 >= s->line_compare) { | |
d1984194 | 1475 | offset = 0; |
1476 | } | |
cae334cd | 1477 | line = line1; |
e89f66ec FB |
1478 | } |
1479 | } | |
1480 | ||
17b0018b FB |
1481 | enum { |
1482 | VGA_DRAW_LINE2, | |
1483 | VGA_DRAW_LINE2D2, | |
1484 | VGA_DRAW_LINE4, | |
1485 | VGA_DRAW_LINE4D2, | |
1486 | VGA_DRAW_LINE8D2, | |
1487 | VGA_DRAW_LINE8, | |
1488 | VGA_DRAW_LINE15, | |
1489 | VGA_DRAW_LINE16, | |
4fa0f5d2 | 1490 | VGA_DRAW_LINE24, |
17b0018b FB |
1491 | VGA_DRAW_LINE32, |
1492 | VGA_DRAW_LINE_NB, | |
1493 | }; | |
1494 | ||
68f04a3c | 1495 | static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = { |
e89f66ec FB |
1496 | vga_draw_line2_8, |
1497 | vga_draw_line2_16, | |
1498 | vga_draw_line2_16, | |
1499 | vga_draw_line2_32, | |
d3079cd2 | 1500 | vga_draw_line2_32, |
b29169d2 BS |
1501 | vga_draw_line2_16, |
1502 | vga_draw_line2_16, | |
e89f66ec | 1503 | |
17b0018b FB |
1504 | vga_draw_line2d2_8, |
1505 | vga_draw_line2d2_16, | |
1506 | vga_draw_line2d2_16, | |
1507 | vga_draw_line2d2_32, | |
d3079cd2 | 1508 | vga_draw_line2d2_32, |
b29169d2 BS |
1509 | vga_draw_line2d2_16, |
1510 | vga_draw_line2d2_16, | |
17b0018b | 1511 | |
e89f66ec FB |
1512 | vga_draw_line4_8, |
1513 | vga_draw_line4_16, | |
1514 | vga_draw_line4_16, | |
1515 | vga_draw_line4_32, | |
d3079cd2 | 1516 | vga_draw_line4_32, |
b29169d2 BS |
1517 | vga_draw_line4_16, |
1518 | vga_draw_line4_16, | |
e89f66ec | 1519 | |
17b0018b FB |
1520 | vga_draw_line4d2_8, |
1521 | vga_draw_line4d2_16, | |
1522 | vga_draw_line4d2_16, | |
1523 | vga_draw_line4d2_32, | |
d3079cd2 | 1524 | vga_draw_line4d2_32, |
b29169d2 BS |
1525 | vga_draw_line4d2_16, |
1526 | vga_draw_line4d2_16, | |
17b0018b FB |
1527 | |
1528 | vga_draw_line8d2_8, | |
1529 | vga_draw_line8d2_16, | |
1530 | vga_draw_line8d2_16, | |
1531 | vga_draw_line8d2_32, | |
d3079cd2 | 1532 | vga_draw_line8d2_32, |
b29169d2 BS |
1533 | vga_draw_line8d2_16, |
1534 | vga_draw_line8d2_16, | |
17b0018b | 1535 | |
e89f66ec FB |
1536 | vga_draw_line8_8, |
1537 | vga_draw_line8_16, | |
1538 | vga_draw_line8_16, | |
1539 | vga_draw_line8_32, | |
d3079cd2 | 1540 | vga_draw_line8_32, |
b29169d2 BS |
1541 | vga_draw_line8_16, |
1542 | vga_draw_line8_16, | |
e89f66ec FB |
1543 | |
1544 | vga_draw_line15_8, | |
1545 | vga_draw_line15_15, | |
1546 | vga_draw_line15_16, | |
1547 | vga_draw_line15_32, | |
d3079cd2 | 1548 | vga_draw_line15_32bgr, |
b29169d2 BS |
1549 | vga_draw_line15_15bgr, |
1550 | vga_draw_line15_16bgr, | |
e89f66ec FB |
1551 | |
1552 | vga_draw_line16_8, | |
1553 | vga_draw_line16_15, | |
1554 | vga_draw_line16_16, | |
1555 | vga_draw_line16_32, | |
d3079cd2 | 1556 | vga_draw_line16_32bgr, |
b29169d2 BS |
1557 | vga_draw_line16_15bgr, |
1558 | vga_draw_line16_16bgr, | |
e89f66ec | 1559 | |
4fa0f5d2 FB |
1560 | vga_draw_line24_8, |
1561 | vga_draw_line24_15, | |
1562 | vga_draw_line24_16, | |
1563 | vga_draw_line24_32, | |
d3079cd2 | 1564 | vga_draw_line24_32bgr, |
b29169d2 BS |
1565 | vga_draw_line24_15bgr, |
1566 | vga_draw_line24_16bgr, | |
4fa0f5d2 | 1567 | |
e89f66ec FB |
1568 | vga_draw_line32_8, |
1569 | vga_draw_line32_15, | |
1570 | vga_draw_line32_16, | |
1571 | vga_draw_line32_32, | |
d3079cd2 | 1572 | vga_draw_line32_32bgr, |
b29169d2 BS |
1573 | vga_draw_line32_15bgr, |
1574 | vga_draw_line32_16bgr, | |
d3079cd2 FB |
1575 | }; |
1576 | ||
cedd91d2 | 1577 | static int vga_get_bpp(VGACommonState *s) |
798b0c25 FB |
1578 | { |
1579 | int ret; | |
a96d8bea | 1580 | |
798b0c25 FB |
1581 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { |
1582 | ret = s->vbe_regs[VBE_DISPI_INDEX_BPP]; | |
a96d8bea | 1583 | } else { |
798b0c25 FB |
1584 | ret = 0; |
1585 | } | |
1586 | return ret; | |
1587 | } | |
1588 | ||
cedd91d2 | 1589 | static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
a130a41e FB |
1590 | { |
1591 | int width, height; | |
3b46e624 | 1592 | |
8454df8b FB |
1593 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { |
1594 | width = s->vbe_regs[VBE_DISPI_INDEX_XRES]; | |
1595 | height = s->vbe_regs[VBE_DISPI_INDEX_YRES]; | |
a96d8bea | 1596 | } else { |
5e55efc9 BS |
1597 | width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8; |
1598 | height = s->cr[VGA_CRTC_V_DISP_END] | | |
1599 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
1600 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
8454df8b FB |
1601 | height = (height + 1); |
1602 | } | |
a130a41e FB |
1603 | *pwidth = width; |
1604 | *pheight = height; | |
1605 | } | |
1606 | ||
cedd91d2 | 1607 | void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2) |
a8aa669b FB |
1608 | { |
1609 | int y; | |
1610 | if (y1 >= VGA_MAX_HEIGHT) | |
1611 | return; | |
1612 | if (y2 >= VGA_MAX_HEIGHT) | |
1613 | y2 = VGA_MAX_HEIGHT; | |
1614 | for(y = y1; y < y2; y++) { | |
1615 | s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f); | |
1616 | } | |
1617 | } | |
1618 | ||
b51d7b2e | 1619 | void vga_sync_dirty_bitmap(VGACommonState *s) |
2bec46dc | 1620 | { |
b1950430 | 1621 | memory_region_sync_dirty_bitmap(&s->vram); |
2bec46dc AL |
1622 | } |
1623 | ||
50af3246 JQ |
1624 | void vga_dirty_log_start(VGACommonState *s) |
1625 | { | |
b1950430 | 1626 | memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA); |
b5cc6e32 AL |
1627 | } |
1628 | ||
1629 | void vga_dirty_log_stop(VGACommonState *s) | |
1630 | { | |
b1950430 | 1631 | memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA); |
b5cc6e32 AL |
1632 | } |
1633 | ||
799e709b AL |
1634 | /* |
1635 | * graphic modes | |
1636 | */ | |
cedd91d2 | 1637 | static void vga_draw_graphic(VGACommonState *s, int full_update) |
e89f66ec | 1638 | { |
c78f7137 | 1639 | DisplaySurface *surface = qemu_console_surface(s->con); |
12c7e75a AK |
1640 | int y1, y, update, linesize, y_start, double_scan, mask, depth; |
1641 | int width, height, shift_control, line_offset, bwidth, bits; | |
c227f099 | 1642 | ram_addr_t page0, page1, page_min, page_max; |
a07cf92a | 1643 | int disp_width, multi_scan, multi_run; |
799e709b AL |
1644 | uint8_t *d; |
1645 | uint32_t v, addr1, addr; | |
1646 | vga_draw_line_func *vga_draw_line; | |
b1424e03 GH |
1647 | #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) |
1648 | static const bool byteswap = false; | |
1649 | #else | |
1650 | static const bool byteswap = true; | |
1651 | #endif | |
799e709b AL |
1652 | |
1653 | full_update |= update_basic_params(s); | |
1654 | ||
1655 | if (!full_update) | |
1656 | vga_sync_dirty_bitmap(s); | |
2bec46dc | 1657 | |
a130a41e | 1658 | s->get_resolution(s, &width, &height); |
17b0018b | 1659 | disp_width = width; |
09a79b49 | 1660 | |
5e55efc9 BS |
1661 | shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3; |
1662 | double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7); | |
799e709b | 1663 | if (shift_control != 1) { |
5e55efc9 BS |
1664 | multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan) |
1665 | - 1; | |
799e709b AL |
1666 | } else { |
1667 | /* in CGA modes, multi_scan is ignored */ | |
1668 | /* XXX: is it correct ? */ | |
1669 | multi_scan = double_scan; | |
1670 | } | |
1671 | multi_run = multi_scan; | |
17b0018b FB |
1672 | if (shift_control != s->shift_control || |
1673 | double_scan != s->double_scan) { | |
799e709b | 1674 | full_update = 1; |
e89f66ec | 1675 | s->shift_control = shift_control; |
17b0018b | 1676 | s->double_scan = double_scan; |
e89f66ec | 1677 | } |
3b46e624 | 1678 | |
aba35a6c | 1679 | if (shift_control == 0) { |
5e55efc9 | 1680 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
aba35a6c | 1681 | disp_width <<= 1; |
1682 | } | |
1683 | } else if (shift_control == 1) { | |
5e55efc9 | 1684 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
aba35a6c | 1685 | disp_width <<= 1; |
1686 | } | |
1687 | } | |
1688 | ||
799e709b | 1689 | depth = s->get_bpp(s); |
e3697092 AJ |
1690 | if (s->line_offset != s->last_line_offset || |
1691 | disp_width != s->last_width || | |
1692 | height != s->last_height || | |
799e709b | 1693 | s->last_depth != depth) { |
b1424e03 | 1694 | if (depth == 32 || (depth == 16 && !byteswap)) { |
da229ef3 GH |
1695 | surface = qemu_create_displaysurface_from(disp_width, |
1696 | height, depth, s->line_offset, | |
b1424e03 | 1697 | s->vram_ptr + (s->start_addr * 4), byteswap); |
c78f7137 | 1698 | dpy_gfx_replace_surface(s->con, surface); |
e3697092 | 1699 | } else { |
c78f7137 GH |
1700 | qemu_console_resize(s->con, disp_width, height); |
1701 | surface = qemu_console_surface(s->con); | |
e3697092 AJ |
1702 | } |
1703 | s->last_scr_width = disp_width; | |
1704 | s->last_scr_height = height; | |
1705 | s->last_width = disp_width; | |
1706 | s->last_height = height; | |
1707 | s->last_line_offset = s->line_offset; | |
1708 | s->last_depth = depth; | |
799e709b | 1709 | full_update = 1; |
c78f7137 GH |
1710 | } else if (is_buffer_shared(surface) && |
1711 | (full_update || surface_data(surface) != s->vram_ptr | |
1fd2510a | 1712 | + (s->start_addr * 4))) { |
da229ef3 GH |
1713 | DisplaySurface *surface; |
1714 | surface = qemu_create_displaysurface_from(disp_width, | |
1715 | height, depth, s->line_offset, | |
b1424e03 | 1716 | s->vram_ptr + (s->start_addr * 4), byteswap); |
c78f7137 | 1717 | dpy_gfx_replace_surface(s->con, surface); |
e3697092 AJ |
1718 | } |
1719 | ||
1720 | s->rgb_to_pixel = | |
c78f7137 | 1721 | rgb_to_pixel_dup_table[get_depth_index(surface)]; |
e3697092 | 1722 | |
799e709b | 1723 | if (shift_control == 0) { |
17b0018b | 1724 | full_update |= update_palette16(s); |
5e55efc9 | 1725 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
17b0018b | 1726 | v = VGA_DRAW_LINE4D2; |
17b0018b FB |
1727 | } else { |
1728 | v = VGA_DRAW_LINE4; | |
1729 | } | |
15342721 | 1730 | bits = 4; |
799e709b | 1731 | } else if (shift_control == 1) { |
17b0018b | 1732 | full_update |= update_palette16(s); |
5e55efc9 | 1733 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
17b0018b | 1734 | v = VGA_DRAW_LINE2D2; |
17b0018b FB |
1735 | } else { |
1736 | v = VGA_DRAW_LINE2; | |
1737 | } | |
15342721 | 1738 | bits = 4; |
17b0018b | 1739 | } else { |
798b0c25 FB |
1740 | switch(s->get_bpp(s)) { |
1741 | default: | |
1742 | case 0: | |
4fa0f5d2 FB |
1743 | full_update |= update_palette256(s); |
1744 | v = VGA_DRAW_LINE8D2; | |
15342721 | 1745 | bits = 4; |
798b0c25 FB |
1746 | break; |
1747 | case 8: | |
1748 | full_update |= update_palette256(s); | |
1749 | v = VGA_DRAW_LINE8; | |
15342721 | 1750 | bits = 8; |
798b0c25 FB |
1751 | break; |
1752 | case 15: | |
1753 | v = VGA_DRAW_LINE15; | |
15342721 | 1754 | bits = 16; |
798b0c25 FB |
1755 | break; |
1756 | case 16: | |
1757 | v = VGA_DRAW_LINE16; | |
15342721 | 1758 | bits = 16; |
798b0c25 FB |
1759 | break; |
1760 | case 24: | |
1761 | v = VGA_DRAW_LINE24; | |
15342721 | 1762 | bits = 24; |
798b0c25 FB |
1763 | break; |
1764 | case 32: | |
1765 | v = VGA_DRAW_LINE32; | |
15342721 | 1766 | bits = 32; |
798b0c25 | 1767 | break; |
4fa0f5d2 | 1768 | } |
17b0018b | 1769 | } |
c78f7137 GH |
1770 | vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + |
1771 | get_depth_index(surface)]; | |
17b0018b | 1772 | |
c78f7137 | 1773 | if (!is_buffer_shared(surface) && s->cursor_invalidate) { |
a8aa669b | 1774 | s->cursor_invalidate(s); |
c78f7137 | 1775 | } |
3b46e624 | 1776 | |
e89f66ec | 1777 | line_offset = s->line_offset; |
17b0018b | 1778 | #if 0 |
f6c958c8 | 1779 | printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n", |
5e55efc9 BS |
1780 | width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE], |
1781 | s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]); | |
17b0018b | 1782 | #endif |
e89f66ec | 1783 | addr1 = (s->start_addr * 4); |
15342721 | 1784 | bwidth = (width * bits + 7) / 8; |
39cf7803 | 1785 | y_start = -1; |
12c7e75a AK |
1786 | page_min = -1; |
1787 | page_max = 0; | |
c78f7137 GH |
1788 | d = surface_data(surface); |
1789 | linesize = surface_stride(surface); | |
17b0018b | 1790 | y1 = 0; |
e89f66ec FB |
1791 | for(y = 0; y < height; y++) { |
1792 | addr = addr1; | |
5e55efc9 | 1793 | if (!(s->cr[VGA_CRTC_MODE] & 1)) { |
17b0018b | 1794 | int shift; |
e89f66ec | 1795 | /* CGA compatibility handling */ |
5e55efc9 | 1796 | shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1); |
17b0018b | 1797 | addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift); |
e89f66ec | 1798 | } |
5e55efc9 | 1799 | if (!(s->cr[VGA_CRTC_MODE] & 2)) { |
17b0018b | 1800 | addr = (addr & ~0x8000) | ((y1 & 2) << 14); |
e89f66ec | 1801 | } |
734781c9 | 1802 | update = full_update; |
cd7a45c9 BS |
1803 | page0 = addr; |
1804 | page1 = addr + bwidth - 1; | |
734781c9 JK |
1805 | update |= memory_region_get_dirty(&s->vram, page0, page1 - page0, |
1806 | DIRTY_MEMORY_VGA); | |
a8aa669b FB |
1807 | /* explicit invalidation for the hardware cursor */ |
1808 | update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1; | |
e89f66ec | 1809 | if (update) { |
39cf7803 FB |
1810 | if (y_start < 0) |
1811 | y_start = y; | |
e89f66ec FB |
1812 | if (page0 < page_min) |
1813 | page_min = page0; | |
1814 | if (page1 > page_max) | |
1815 | page_max = page1; | |
c78f7137 | 1816 | if (!(is_buffer_shared(surface))) { |
7d957bd8 AL |
1817 | vga_draw_line(s, d, s->vram_ptr + addr, width); |
1818 | if (s->cursor_draw_line) | |
1819 | s->cursor_draw_line(s, d, y); | |
1820 | } | |
39cf7803 FB |
1821 | } else { |
1822 | if (y_start >= 0) { | |
1823 | /* flush to display */ | |
c78f7137 | 1824 | dpy_gfx_update(s->con, 0, y_start, |
a93a4a22 | 1825 | disp_width, y - y_start); |
39cf7803 FB |
1826 | y_start = -1; |
1827 | } | |
e89f66ec | 1828 | } |
a07cf92a | 1829 | if (!multi_run) { |
5e55efc9 | 1830 | mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3; |
f6c958c8 FB |
1831 | if ((y1 & mask) == mask) |
1832 | addr1 += line_offset; | |
1833 | y1++; | |
799e709b | 1834 | multi_run = multi_scan; |
a07cf92a FB |
1835 | } else { |
1836 | multi_run--; | |
e89f66ec | 1837 | } |
f6c958c8 FB |
1838 | /* line compare acts on the displayed lines */ |
1839 | if (y == s->line_compare) | |
1840 | addr1 = 0; | |
e89f66ec FB |
1841 | d += linesize; |
1842 | } | |
39cf7803 FB |
1843 | if (y_start >= 0) { |
1844 | /* flush to display */ | |
c78f7137 | 1845 | dpy_gfx_update(s->con, 0, y_start, |
a93a4a22 | 1846 | disp_width, y - y_start); |
39cf7803 | 1847 | } |
e89f66ec | 1848 | /* reset modified pages */ |
12c7e75a | 1849 | if (page_max >= page_min) { |
b1950430 AK |
1850 | memory_region_reset_dirty(&s->vram, |
1851 | page_min, | |
cd7a45c9 | 1852 | page_max - page_min, |
b1950430 | 1853 | DIRTY_MEMORY_VGA); |
e89f66ec | 1854 | } |
a8aa669b | 1855 | memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4); |
e89f66ec FB |
1856 | } |
1857 | ||
cedd91d2 | 1858 | static void vga_draw_blank(VGACommonState *s, int full_update) |
2aebb3eb | 1859 | { |
c78f7137 | 1860 | DisplaySurface *surface = qemu_console_surface(s->con); |
2aebb3eb FB |
1861 | int i, w, val; |
1862 | uint8_t *d; | |
1863 | ||
1864 | if (!full_update) | |
1865 | return; | |
1866 | if (s->last_scr_width <= 0 || s->last_scr_height <= 0) | |
1867 | return; | |
2bec46dc | 1868 | |
7d957bd8 | 1869 | s->rgb_to_pixel = |
c78f7137 GH |
1870 | rgb_to_pixel_dup_table[get_depth_index(surface)]; |
1871 | if (surface_bits_per_pixel(surface) == 8) { | |
2aebb3eb | 1872 | val = s->rgb_to_pixel(0, 0, 0); |
c78f7137 | 1873 | } else { |
2aebb3eb | 1874 | val = 0; |
c78f7137 GH |
1875 | } |
1876 | w = s->last_scr_width * surface_bytes_per_pixel(surface); | |
1877 | d = surface_data(surface); | |
2aebb3eb FB |
1878 | for(i = 0; i < s->last_scr_height; i++) { |
1879 | memset(d, val, w); | |
c78f7137 | 1880 | d += surface_stride(surface); |
2aebb3eb | 1881 | } |
c78f7137 | 1882 | dpy_gfx_update(s->con, 0, 0, |
a93a4a22 | 1883 | s->last_scr_width, s->last_scr_height); |
2aebb3eb FB |
1884 | } |
1885 | ||
799e709b AL |
1886 | #define GMODE_TEXT 0 |
1887 | #define GMODE_GRAPH 1 | |
1888 | #define GMODE_BLANK 2 | |
1889 | ||
95219897 | 1890 | static void vga_update_display(void *opaque) |
e89f66ec | 1891 | { |
cedd91d2 | 1892 | VGACommonState *s = opaque; |
c78f7137 | 1893 | DisplaySurface *surface = qemu_console_surface(s->con); |
799e709b | 1894 | int full_update, graphic_mode; |
e89f66ec | 1895 | |
e9a07334 JK |
1896 | qemu_flush_coalesced_mmio_buffer(); |
1897 | ||
c78f7137 | 1898 | if (surface_bits_per_pixel(surface) == 0) { |
0f35920c | 1899 | /* nothing to do */ |
59a983b9 | 1900 | } else { |
3098b9fd | 1901 | full_update = 0; |
df800210 | 1902 | if (!(s->ar_index & 0x20)) { |
799e709b AL |
1903 | graphic_mode = GMODE_BLANK; |
1904 | } else { | |
5e55efc9 | 1905 | graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; |
799e709b AL |
1906 | } |
1907 | if (graphic_mode != s->graphic_mode) { | |
1908 | s->graphic_mode = graphic_mode; | |
9aa0ff0b | 1909 | s->cursor_blink_time = qemu_get_clock_ms(vm_clock); |
799e709b AL |
1910 | full_update = 1; |
1911 | } | |
1912 | switch(graphic_mode) { | |
2aebb3eb | 1913 | case GMODE_TEXT: |
e89f66ec | 1914 | vga_draw_text(s, full_update); |
2aebb3eb FB |
1915 | break; |
1916 | case GMODE_GRAPH: | |
1917 | vga_draw_graphic(s, full_update); | |
1918 | break; | |
1919 | case GMODE_BLANK: | |
1920 | default: | |
1921 | vga_draw_blank(s, full_update); | |
1922 | break; | |
1923 | } | |
e89f66ec FB |
1924 | } |
1925 | } | |
1926 | ||
a130a41e | 1927 | /* force a full display refresh */ |
95219897 | 1928 | static void vga_invalidate_display(void *opaque) |
a130a41e | 1929 | { |
cedd91d2 | 1930 | VGACommonState *s = opaque; |
3b46e624 | 1931 | |
3098b9fd AJ |
1932 | s->last_width = -1; |
1933 | s->last_height = -1; | |
a130a41e FB |
1934 | } |
1935 | ||
03a3e7ba | 1936 | void vga_common_reset(VGACommonState *s) |
e89f66ec | 1937 | { |
6e6b7363 BS |
1938 | s->sr_index = 0; |
1939 | memset(s->sr, '\0', sizeof(s->sr)); | |
1940 | s->gr_index = 0; | |
1941 | memset(s->gr, '\0', sizeof(s->gr)); | |
1942 | s->ar_index = 0; | |
1943 | memset(s->ar, '\0', sizeof(s->ar)); | |
1944 | s->ar_flip_flop = 0; | |
1945 | s->cr_index = 0; | |
1946 | memset(s->cr, '\0', sizeof(s->cr)); | |
1947 | s->msr = 0; | |
1948 | s->fcr = 0; | |
1949 | s->st00 = 0; | |
1950 | s->st01 = 0; | |
1951 | s->dac_state = 0; | |
1952 | s->dac_sub_index = 0; | |
1953 | s->dac_read_index = 0; | |
1954 | s->dac_write_index = 0; | |
1955 | memset(s->dac_cache, '\0', sizeof(s->dac_cache)); | |
1956 | s->dac_8bit = 0; | |
1957 | memset(s->palette, '\0', sizeof(s->palette)); | |
1958 | s->bank_offset = 0; | |
6e6b7363 BS |
1959 | s->vbe_index = 0; |
1960 | memset(s->vbe_regs, '\0', sizeof(s->vbe_regs)); | |
af92284b | 1961 | s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5; |
6e6b7363 BS |
1962 | s->vbe_start_addr = 0; |
1963 | s->vbe_line_offset = 0; | |
1964 | s->vbe_bank_mask = (s->vram_size >> 16) - 1; | |
6e6b7363 | 1965 | memset(s->font_offsets, '\0', sizeof(s->font_offsets)); |
799e709b | 1966 | s->graphic_mode = -1; /* force full update */ |
6e6b7363 BS |
1967 | s->shift_control = 0; |
1968 | s->double_scan = 0; | |
1969 | s->line_offset = 0; | |
1970 | s->line_compare = 0; | |
1971 | s->start_addr = 0; | |
1972 | s->plane_updated = 0; | |
1973 | s->last_cw = 0; | |
1974 | s->last_ch = 0; | |
1975 | s->last_width = 0; | |
1976 | s->last_height = 0; | |
1977 | s->last_scr_width = 0; | |
1978 | s->last_scr_height = 0; | |
1979 | s->cursor_start = 0; | |
1980 | s->cursor_end = 0; | |
1981 | s->cursor_offset = 0; | |
1982 | memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table)); | |
1983 | memset(s->last_palette, '\0', sizeof(s->last_palette)); | |
1984 | memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr)); | |
1985 | switch (vga_retrace_method) { | |
1986 | case VGA_RETRACE_DUMB: | |
1987 | break; | |
1988 | case VGA_RETRACE_PRECISE: | |
1989 | memset(&s->retrace_info, 0, sizeof (s->retrace_info)); | |
1990 | break; | |
1991 | } | |
80763888 | 1992 | vga_update_memory_access(s); |
e89f66ec FB |
1993 | } |
1994 | ||
03a3e7ba JQ |
1995 | static void vga_reset(void *opaque) |
1996 | { | |
cedd91d2 | 1997 | VGACommonState *s = opaque; |
03a3e7ba JQ |
1998 | vga_common_reset(s); |
1999 | } | |
2000 | ||
4d3b6f6e AZ |
2001 | #define TEXTMODE_X(x) ((x) % width) |
2002 | #define TEXTMODE_Y(x) ((x) / width) | |
2003 | #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \ | |
2004 | ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1)) | |
2005 | /* relay text rendering to the display driver | |
2006 | * instead of doing a full vga_update_display() */ | |
c227f099 | 2007 | static void vga_update_text(void *opaque, console_ch_t *chardata) |
4d3b6f6e | 2008 | { |
cedd91d2 | 2009 | VGACommonState *s = opaque; |
799e709b | 2010 | int graphic_mode, i, cursor_offset, cursor_visible; |
4d3b6f6e AZ |
2011 | int cw, cheight, width, height, size, c_min, c_max; |
2012 | uint32_t *src; | |
c227f099 | 2013 | console_ch_t *dst, val; |
4d3b6f6e | 2014 | char msg_buffer[80]; |
799e709b AL |
2015 | int full_update = 0; |
2016 | ||
e9a07334 JK |
2017 | qemu_flush_coalesced_mmio_buffer(); |
2018 | ||
799e709b AL |
2019 | if (!(s->ar_index & 0x20)) { |
2020 | graphic_mode = GMODE_BLANK; | |
2021 | } else { | |
5e55efc9 | 2022 | graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; |
799e709b AL |
2023 | } |
2024 | if (graphic_mode != s->graphic_mode) { | |
2025 | s->graphic_mode = graphic_mode; | |
2026 | full_update = 1; | |
2027 | } | |
2028 | if (s->last_width == -1) { | |
2029 | s->last_width = 0; | |
2030 | full_update = 1; | |
2031 | } | |
4d3b6f6e | 2032 | |
799e709b | 2033 | switch (graphic_mode) { |
4d3b6f6e AZ |
2034 | case GMODE_TEXT: |
2035 | /* TODO: update palette */ | |
799e709b | 2036 | full_update |= update_basic_params(s); |
4d3b6f6e | 2037 | |
799e709b | 2038 | /* total width & height */ |
5e55efc9 | 2039 | cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; |
799e709b | 2040 | cw = 8; |
5e55efc9 | 2041 | if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) { |
799e709b | 2042 | cw = 9; |
5e55efc9 BS |
2043 | } |
2044 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) { | |
799e709b | 2045 | cw = 16; /* NOTE: no 18 pixel wide */ |
5e55efc9 BS |
2046 | } |
2047 | width = (s->cr[VGA_CRTC_H_DISP] + 1); | |
2048 | if (s->cr[VGA_CRTC_V_TOTAL] == 100) { | |
799e709b AL |
2049 | /* ugly hack for CGA 160x100x16 - explain me the logic */ |
2050 | height = 100; | |
2051 | } else { | |
5e55efc9 BS |
2052 | height = s->cr[VGA_CRTC_V_DISP_END] | |
2053 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
2054 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
799e709b | 2055 | height = (height + 1) / cheight; |
4d3b6f6e AZ |
2056 | } |
2057 | ||
2058 | size = (height * width); | |
2059 | if (size > CH_ATTR_SIZE) { | |
2060 | if (!full_update) | |
2061 | return; | |
2062 | ||
363a37d5 BS |
2063 | snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode", |
2064 | width, height); | |
4d3b6f6e AZ |
2065 | break; |
2066 | } | |
2067 | ||
799e709b AL |
2068 | if (width != s->last_width || height != s->last_height || |
2069 | cw != s->last_cw || cheight != s->last_ch) { | |
2070 | s->last_scr_width = width * cw; | |
2071 | s->last_scr_height = height * cheight; | |
c78f7137 GH |
2072 | qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height); |
2073 | dpy_text_resize(s->con, width, height); | |
9678aedd | 2074 | s->last_depth = 0; |
799e709b AL |
2075 | s->last_width = width; |
2076 | s->last_height = height; | |
2077 | s->last_ch = cheight; | |
2078 | s->last_cw = cw; | |
2079 | full_update = 1; | |
2080 | } | |
2081 | ||
9678aedd GH |
2082 | if (full_update) { |
2083 | s->full_update_gfx = 1; | |
2084 | } | |
2085 | if (s->full_update_text) { | |
2086 | s->full_update_text = 0; | |
2087 | full_update |= 1; | |
2088 | } | |
2089 | ||
4d3b6f6e | 2090 | /* Update "hardware" cursor */ |
5e55efc9 BS |
2091 | cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | |
2092 | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; | |
4d3b6f6e | 2093 | if (cursor_offset != s->cursor_offset || |
5e55efc9 BS |
2094 | s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || |
2095 | s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) { | |
2096 | cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20); | |
4d3b6f6e | 2097 | if (cursor_visible && cursor_offset < size && cursor_offset >= 0) |
c78f7137 | 2098 | dpy_text_cursor(s->con, |
bf2fde70 GH |
2099 | TEXTMODE_X(cursor_offset), |
2100 | TEXTMODE_Y(cursor_offset)); | |
4d3b6f6e | 2101 | else |
c78f7137 | 2102 | dpy_text_cursor(s->con, -1, -1); |
4d3b6f6e | 2103 | s->cursor_offset = cursor_offset; |
5e55efc9 BS |
2104 | s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; |
2105 | s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; | |
4d3b6f6e AZ |
2106 | } |
2107 | ||
2108 | src = (uint32_t *) s->vram_ptr + s->start_addr; | |
2109 | dst = chardata; | |
2110 | ||
2111 | if (full_update) { | |
2112 | for (i = 0; i < size; src ++, dst ++, i ++) | |
9ae19b65 | 2113 | console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e | 2114 | |
c78f7137 | 2115 | dpy_text_update(s->con, 0, 0, width, height); |
4d3b6f6e AZ |
2116 | } else { |
2117 | c_max = 0; | |
2118 | ||
2119 | for (i = 0; i < size; src ++, dst ++, i ++) { | |
9ae19b65 | 2120 | console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e AZ |
2121 | if (*dst != val) { |
2122 | *dst = val; | |
2123 | c_max = i; | |
2124 | break; | |
2125 | } | |
2126 | } | |
2127 | c_min = i; | |
2128 | for (; i < size; src ++, dst ++, i ++) { | |
9ae19b65 | 2129 | console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e AZ |
2130 | if (*dst != val) { |
2131 | *dst = val; | |
2132 | c_max = i; | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | if (c_min <= c_max) { | |
2137 | i = TEXTMODE_Y(c_min); | |
c78f7137 | 2138 | dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1); |
4d3b6f6e AZ |
2139 | } |
2140 | } | |
2141 | ||
2142 | return; | |
2143 | case GMODE_GRAPH: | |
2144 | if (!full_update) | |
2145 | return; | |
2146 | ||
2147 | s->get_resolution(s, &width, &height); | |
363a37d5 BS |
2148 | snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode", |
2149 | width, height); | |
4d3b6f6e AZ |
2150 | break; |
2151 | case GMODE_BLANK: | |
2152 | default: | |
2153 | if (!full_update) | |
2154 | return; | |
2155 | ||
363a37d5 | 2156 | snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode"); |
4d3b6f6e AZ |
2157 | break; |
2158 | } | |
2159 | ||
2160 | /* Display a message */ | |
5228c2d3 AZ |
2161 | s->last_width = 60; |
2162 | s->last_height = height = 3; | |
c78f7137 GH |
2163 | dpy_text_cursor(s->con, -1, -1); |
2164 | dpy_text_resize(s->con, s->last_width, height); | |
4d3b6f6e | 2165 | |
5228c2d3 | 2166 | for (dst = chardata, i = 0; i < s->last_width * height; i ++) |
4d3b6f6e AZ |
2167 | console_write_ch(dst ++, ' '); |
2168 | ||
2169 | size = strlen(msg_buffer); | |
5228c2d3 AZ |
2170 | width = (s->last_width - size) / 2; |
2171 | dst = chardata + s->last_width + width; | |
4d3b6f6e AZ |
2172 | for (i = 0; i < size; i ++) |
2173 | console_write_ch(dst ++, 0x00200100 | msg_buffer[i]); | |
2174 | ||
c78f7137 | 2175 | dpy_text_update(s->con, 0, 0, s->last_width, height); |
4d3b6f6e AZ |
2176 | } |
2177 | ||
a8170e5e | 2178 | static uint64_t vga_mem_read(void *opaque, hwaddr addr, |
b1950430 AK |
2179 | unsigned size) |
2180 | { | |
2181 | VGACommonState *s = opaque; | |
2182 | ||
b2a5e761 | 2183 | return vga_mem_readb(s, addr); |
b1950430 | 2184 | } |
e89f66ec | 2185 | |
a8170e5e | 2186 | static void vga_mem_write(void *opaque, hwaddr addr, |
b1950430 AK |
2187 | uint64_t data, unsigned size) |
2188 | { | |
2189 | VGACommonState *s = opaque; | |
2190 | ||
b2a5e761 | 2191 | return vga_mem_writeb(s, addr, data); |
b1950430 AK |
2192 | } |
2193 | ||
2194 | const MemoryRegionOps vga_mem_ops = { | |
2195 | .read = vga_mem_read, | |
2196 | .write = vga_mem_write, | |
2197 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2a5e761 AK |
2198 | .impl = { |
2199 | .min_access_size = 1, | |
2200 | .max_access_size = 1, | |
2201 | }, | |
e89f66ec FB |
2202 | }; |
2203 | ||
11b6b345 | 2204 | static int vga_common_post_load(void *opaque, int version_id) |
b0a21b53 | 2205 | { |
0d65ddc3 | 2206 | VGACommonState *s = opaque; |
11b6b345 JQ |
2207 | |
2208 | /* force refresh */ | |
2209 | s->graphic_mode = -1; | |
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | const VMStateDescription vmstate_vga_common = { | |
2214 | .name = "vga", | |
2215 | .version_id = 2, | |
2216 | .minimum_version_id = 2, | |
2217 | .minimum_version_id_old = 2, | |
2218 | .post_load = vga_common_post_load, | |
2219 | .fields = (VMStateField []) { | |
2220 | VMSTATE_UINT32(latch, VGACommonState), | |
2221 | VMSTATE_UINT8(sr_index, VGACommonState), | |
2222 | VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8), | |
2223 | VMSTATE_UINT8(gr_index, VGACommonState), | |
2224 | VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16), | |
2225 | VMSTATE_UINT8(ar_index, VGACommonState), | |
2226 | VMSTATE_BUFFER(ar, VGACommonState), | |
2227 | VMSTATE_INT32(ar_flip_flop, VGACommonState), | |
2228 | VMSTATE_UINT8(cr_index, VGACommonState), | |
2229 | VMSTATE_BUFFER(cr, VGACommonState), | |
2230 | VMSTATE_UINT8(msr, VGACommonState), | |
2231 | VMSTATE_UINT8(fcr, VGACommonState), | |
2232 | VMSTATE_UINT8(st00, VGACommonState), | |
2233 | VMSTATE_UINT8(st01, VGACommonState), | |
2234 | ||
2235 | VMSTATE_UINT8(dac_state, VGACommonState), | |
2236 | VMSTATE_UINT8(dac_sub_index, VGACommonState), | |
2237 | VMSTATE_UINT8(dac_read_index, VGACommonState), | |
2238 | VMSTATE_UINT8(dac_write_index, VGACommonState), | |
2239 | VMSTATE_BUFFER(dac_cache, VGACommonState), | |
2240 | VMSTATE_BUFFER(palette, VGACommonState), | |
2241 | ||
2242 | VMSTATE_INT32(bank_offset, VGACommonState), | |
2243 | VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState), | |
11b6b345 JQ |
2244 | VMSTATE_UINT16(vbe_index, VGACommonState), |
2245 | VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB), | |
2246 | VMSTATE_UINT32(vbe_start_addr, VGACommonState), | |
2247 | VMSTATE_UINT32(vbe_line_offset, VGACommonState), | |
2248 | VMSTATE_UINT32(vbe_bank_mask, VGACommonState), | |
11b6b345 JQ |
2249 | VMSTATE_END_OF_LIST() |
2250 | } | |
2251 | }; | |
2252 | ||
380cd056 GH |
2253 | static const GraphicHwOps vga_ops = { |
2254 | .invalidate = vga_invalidate_display, | |
2255 | .gfx_update = vga_update_display, | |
2256 | .text_update = vga_update_text, | |
2257 | }; | |
2258 | ||
4a1e244e | 2259 | void vga_common_init(VGACommonState *s) |
e89f66ec | 2260 | { |
17b0018b | 2261 | int i, j, v, b; |
e89f66ec FB |
2262 | |
2263 | for(i = 0;i < 256; i++) { | |
2264 | v = 0; | |
2265 | for(j = 0; j < 8; j++) { | |
2266 | v |= ((i >> j) & 1) << (j * 4); | |
2267 | } | |
2268 | expand4[i] = v; | |
2269 | ||
2270 | v = 0; | |
2271 | for(j = 0; j < 4; j++) { | |
2272 | v |= ((i >> (2 * j)) & 3) << (j * 4); | |
2273 | } | |
2274 | expand2[i] = v; | |
2275 | } | |
17b0018b FB |
2276 | for(i = 0; i < 16; i++) { |
2277 | v = 0; | |
2278 | for(j = 0; j < 4; j++) { | |
2279 | b = ((i >> j) & 1); | |
2280 | v |= b << (2 * j); | |
2281 | v |= b << (2 * j + 1); | |
2282 | } | |
2283 | expand4to8[i] = v; | |
2284 | } | |
e89f66ec | 2285 | |
4a1e244e GH |
2286 | /* valid range: 1 MB -> 256 MB */ |
2287 | s->vram_size = 1024 * 1024; | |
2288 | while (s->vram_size < (s->vram_size_mb << 20) && | |
2289 | s->vram_size < (256 << 20)) { | |
2290 | s->vram_size <<= 1; | |
2291 | } | |
2292 | s->vram_size_mb = s->vram_size >> 20; | |
2293 | ||
2a3138ab | 2294 | s->is_vbe_vmstate = 1; |
2c9b15ca | 2295 | memory_region_init_ram(&s->vram, NULL, "vga.vram", s->vram_size); |
c5705a77 | 2296 | vmstate_register_ram_global(&s->vram); |
c65adf9b | 2297 | xen_register_framebuffer(&s->vram); |
b1950430 | 2298 | s->vram_ptr = memory_region_get_ram_ptr(&s->vram); |
798b0c25 FB |
2299 | s->get_bpp = vga_get_bpp; |
2300 | s->get_offsets = vga_get_offsets; | |
a130a41e | 2301 | s->get_resolution = vga_get_resolution; |
380cd056 | 2302 | s->hw_ops = &vga_ops; |
cb5a7aa8 | 2303 | switch (vga_retrace_method) { |
2304 | case VGA_RETRACE_DUMB: | |
2305 | s->retrace = vga_dumb_retrace; | |
2306 | s->update_retrace_info = vga_dumb_update_retrace_info; | |
2307 | break; | |
2308 | ||
2309 | case VGA_RETRACE_PRECISE: | |
2310 | s->retrace = vga_precise_retrace; | |
2311 | s->update_retrace_info = vga_precise_update_retrace_info; | |
cb5a7aa8 | 2312 | break; |
2313 | } | |
b1950430 | 2314 | vga_dirty_log_start(s); |
798b0c25 FB |
2315 | } |
2316 | ||
0a039dc7 RH |
2317 | static const MemoryRegionPortio vga_portio_list[] = { |
2318 | { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */ | |
2319 | { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */ | |
2320 | { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */ | |
2321 | { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */ | |
2322 | { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */ | |
2323 | PORTIO_END_OF_LIST(), | |
2324 | }; | |
e89f66ec | 2325 | |
0a039dc7 RH |
2326 | static const MemoryRegionPortio vbe_portio_list[] = { |
2327 | { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index }, | |
2328 | # ifdef TARGET_I386 | |
2329 | { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, | |
0a039dc7 | 2330 | # endif |
df9ffb72 | 2331 | { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, |
0a039dc7 RH |
2332 | PORTIO_END_OF_LIST(), |
2333 | }; | |
4fa0f5d2 | 2334 | |
0a039dc7 RH |
2335 | /* Used by both ISA and PCI */ |
2336 | MemoryRegion *vga_init_io(VGACommonState *s, | |
2337 | const MemoryRegionPortio **vga_ports, | |
2338 | const MemoryRegionPortio **vbe_ports) | |
2339 | { | |
2340 | MemoryRegion *vga_mem; | |
09a79b49 | 2341 | |
0a039dc7 | 2342 | *vga_ports = vga_portio_list; |
0a039dc7 | 2343 | *vbe_ports = vbe_portio_list; |
4fa0f5d2 | 2344 | |
7267c094 | 2345 | vga_mem = g_malloc(sizeof(*vga_mem)); |
2c9b15ca | 2346 | memory_region_init_io(vga_mem, NULL, &vga_mem_ops, s, |
b1950430 | 2347 | "vga-lowmem", 0x20000); |
bd8f2f5d | 2348 | memory_region_set_flush_coalesced(vga_mem); |
b1950430 AK |
2349 | |
2350 | return vga_mem; | |
7435b791 BS |
2351 | } |
2352 | ||
0a039dc7 RH |
2353 | void vga_init(VGACommonState *s, MemoryRegion *address_space, |
2354 | MemoryRegion *address_space_io, bool init_vga_ports) | |
7435b791 | 2355 | { |
b1950430 | 2356 | MemoryRegion *vga_io_memory; |
0a039dc7 RH |
2357 | const MemoryRegionPortio *vga_ports, *vbe_ports; |
2358 | PortioList *vga_port_list = g_new(PortioList, 1); | |
2359 | PortioList *vbe_port_list = g_new(PortioList, 1); | |
7435b791 BS |
2360 | |
2361 | qemu_register_reset(vga_reset, s); | |
2362 | ||
2363 | s->bank_offset = 0; | |
2364 | ||
80763888 JK |
2365 | s->legacy_address_space = address_space; |
2366 | ||
0a039dc7 | 2367 | vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports); |
be20f9e9 | 2368 | memory_region_add_subregion_overlap(address_space, |
b1950430 AK |
2369 | isa_mem_base + 0x000a0000, |
2370 | vga_io_memory, | |
2371 | 1); | |
2372 | memory_region_set_coalescing(vga_io_memory); | |
0a039dc7 RH |
2373 | if (init_vga_ports) { |
2374 | portio_list_init(vga_port_list, vga_ports, s, "vga"); | |
2375 | portio_list_add(vga_port_list, address_space_io, 0x3b0); | |
2376 | } | |
2377 | if (vbe_ports) { | |
2378 | portio_list_init(vbe_port_list, vbe_ports, s, "vbe"); | |
2379 | portio_list_add(vbe_port_list, address_space_io, 0x1ce); | |
2380 | } | |
d2269f6f FB |
2381 | } |
2382 | ||
be20f9e9 | 2383 | void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) |
f0138a63 | 2384 | { |
8294a64d AK |
2385 | /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region, |
2386 | * so use an alias to avoid double-mapping the same region. | |
2387 | */ | |
2c9b15ca | 2388 | memory_region_init_alias(&s->vram_vbe, NULL, "vram.vbe", |
8294a64d | 2389 | &s->vram, 0, memory_region_size(&s->vram)); |
f0138a63 | 2390 | /* XXX: use optimized standard vga accesses */ |
be20f9e9 | 2391 | memory_region_add_subregion(system_memory, |
b1950430 | 2392 | VBE_DISPI_LFB_PHYSICAL_ADDRESS, |
8294a64d | 2393 | &s->vram_vbe); |
f0138a63 | 2394 | s->vbe_mapped = 1; |
f0138a63 | 2395 | } |