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798b0c25
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1/*
2 * QEMU internal VGA defines.
5fafdf24 3 *
798b0c25 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
798b0c25
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
175de524 24
cb9c377f 25#ifndef HW_VGA_INT_H
175de524 26#define HW_VGA_INT_H
11b6b345 27
e07b1589 28#include "exec/ioport.h"
022c62cb 29#include "exec/memory.h"
11b6b345 30
a3ee49f0 31#include "hw/display/bochs-vbe.h"
cfead313 32#include "hw/acpi/acpi_aml_interface.h"
a3ee49f0 33
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34#define ST01_V_RETRACE 0x08
35#define ST01_DISP_ENABLE 0x01
36
798b0c25 37#define CH_ATTR_SIZE (160 * 100)
8454df8b 38#define VGA_MAX_HEIGHT 2048
4e3e9d0b 39
cb5a7aa8 40struct vga_precise_retrace {
41 int64_t ticks_per_char;
42 int64_t total_chars;
43 int htotal;
44 int hstart;
45 int hend;
46 int vstart;
47 int vend;
48 int freq;
49};
50
51union vga_retrace {
52 struct vga_precise_retrace precise;
53};
54
4e12cd94
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55struct VGACommonState;
56typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
57typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
58
f9b925fd
PB
59typedef struct VGADisplayParams {
60 uint32_t line_offset;
61 uint32_t start_addr;
62 uint32_t line_compare;
973a724e
PB
63 uint8_t hpel;
64 bool hpel_split;
f9b925fd
PB
65} VGADisplayParams;
66
4e12cd94 67typedef struct VGACommonState {
80763888 68 MemoryRegion *legacy_address_space;
4e12cd94 69 uint8_t *vram_ptr;
b1950430 70 MemoryRegion vram;
a19cbfb3 71 uint32_t vram_size;
4a1e244e 72 uint32_t vram_size_mb; /* property */
54a85d46 73 uint32_t vbe_size;
3d90c625 74 uint32_t vbe_size_mask;
4e12cd94 75 uint32_t latch;
ad37168c
PB
76 bool has_chain4_alias;
77 MemoryRegion chain4_alias;
4e12cd94
AK
78 uint8_t sr_index;
79 uint8_t sr[256];
94ef4f33 80 uint8_t sr_vbe[256];
4e12cd94
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81 uint8_t gr_index;
82 uint8_t gr[256];
83 uint8_t ar_index;
84 uint8_t ar[21];
85 int ar_flip_flop;
86 uint8_t cr_index;
87 uint8_t cr[256]; /* CRT registers */
88 uint8_t msr; /* Misc Output Register */
89 uint8_t fcr; /* Feature Control Register */
90 uint8_t st00; /* status 0 */
91 uint8_t st01; /* status 1 */
92 uint8_t dac_state;
93 uint8_t dac_sub_index;
94 uint8_t dac_read_index;
95 uint8_t dac_write_index;
96 uint8_t dac_cache[3]; /* used when writing */
97 int dac_8bit;
98 uint8_t palette[768];
99 int32_t bank_offset;
4e12cd94 100 int (*get_bpp)(struct VGACommonState *s);
f9b925fd 101 void (*get_params)(struct VGACommonState *s, VGADisplayParams *params);
4e12cd94
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102 void (*get_resolution)(struct VGACommonState *s,
103 int *pwidth,
104 int *pheight);
848696bf
KB
105 PortioList vga_port_list;
106 PortioList vbe_port_list;
a96d8bea
GH
107 /* bochs vbe state */
108 uint16_t vbe_index;
109 uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
110 uint32_t vbe_start_addr;
111 uint32_t vbe_line_offset;
112 uint32_t vbe_bank_mask;
4e12cd94 113 /* display refresh support */
c78f7137 114 QemuConsole *con;
4e12cd94 115 uint32_t font_offsets[2];
973a724e 116 uint8_t *panning_buf;
4e12cd94
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117 int graphic_mode;
118 uint8_t shift_control;
119 uint8_t double_scan;
f9b925fd 120 VGADisplayParams params;
4e12cd94
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121 uint32_t plane_updated;
122 uint32_t last_line_offset;
123 uint8_t last_cw, last_ch;
124 uint32_t last_width, last_height; /* in chars or pixels */
125 uint32_t last_scr_width, last_scr_height; /* in pixels */
126 uint32_t last_depth; /* in bits */
c3b10605 127 bool last_byteswap;
55080993 128 bool force_shadow;
4e12cd94 129 uint8_t cursor_start, cursor_end;
9aa0ff0b
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130 bool cursor_visible_phase;
131 int64_t cursor_blink_time;
4e12cd94 132 uint32_t cursor_offset;
380cd056 133 const GraphicHwOps *hw_ops;
9678aedd
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134 bool full_update_text;
135 bool full_update_gfx;
2c7d8736 136 bool big_endian_fb;
c3b10605 137 bool default_endian_fb;
1fcfdc43 138 bool global_vmstate;
4e12cd94
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139 /* hardware mouse cursor support */
140 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
22382bb9
GH
141 uint32_t hw_cursor_x;
142 uint32_t hw_cursor_y;
4e12cd94
AK
143 void (*cursor_invalidate)(struct VGACommonState *s);
144 void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
145 /* tell for each page if it has been updated since the last time */
146 uint32_t last_palette[256];
147 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
148 /* retrace */
149 vga_retrace_fn retrace;
150 vga_update_retrace_info_fn update_retrace_info;
cb5a7aa8 151 union vga_retrace retrace_info;
2a3138ab 152 uint8_t is_vbe_vmstate;
4e12cd94 153} VGACommonState;
4e3e9d0b 154
a8aa669b
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155static inline int c6_to_8(int v)
156{
157 int b;
158 v &= 0x3f;
159 b = v & 1;
160 return (v << 2) | (b << 1) | b;
161}
162
6832deb8 163bool vga_common_init(VGACommonState *s, Object *obj, Error **errp);
712f0cc7 164void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
0a039dc7 165 MemoryRegion *address_space_io, bool init_vga_ports);
c84b28ee 166MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
0a039dc7
RH
167 const MemoryRegionPortio **vga_ports,
168 const MemoryRegionPortio **vbe_ports);
03a3e7ba 169void vga_common_reset(VGACommonState *s);
2bec46dc 170
a4a2f59c 171void vga_dirty_log_start(VGACommonState *s);
b5cc6e32 172void vga_dirty_log_stop(VGACommonState *s);
2bec46dc 173
11b6b345 174extern const VMStateDescription vmstate_vga_common;
43bf782b
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175uint32_t vga_ioport_read(void *opaque, uint32_t addr);
176void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
a8170e5e
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177uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
178void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
a4a2f59c 179void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
a8aa669b 180
25a18cbd 181int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
803ff052 182
803ff052
GH
183uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
184void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
185void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
25a18cbd 186
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187extern const uint8_t sr_mask[8];
188extern const uint8_t gr_mask[16];
fbe1b595 189
5245d57a
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190#define VGABIOS_FILENAME "vgabios.bin"
191#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
fbe1b595 192
b1950430 193extern const MemoryRegionOps vga_mem_ops;
cb9c377f 194
c5d4dac8
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195/* vga-pci.c */
196void pci_std_vga_mmio_region_init(VGACommonState *s,
93abfc88 197 Object *owner,
c5d4dac8
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198 MemoryRegion *parent,
199 MemoryRegion *subs,
d46b40fc 200 bool qext, bool edid);
c5d4dac8 201
cfead313 202void build_vga_aml(AcpiDevAmlIf *adev, Aml *scope);
cb9c377f 203#endif