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Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
[qemu.git] / hw / dma / etraxfs_dma.c
CommitLineData
1ba13a5d
EI		 1/*
2 * QEMU ETRAX DMA Controller.
3 *
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include <stdio.h>
25#include <sys/time.h>
83c9f4ca 26#include "hw/hw.h"
022c62cb 27#include "exec/address-spaces.h"
492c30af 28#include "qemu-common.h"
9c17d615 29#include "sysemu/sysemu.h"
1ba13a5d 30
0d09e41a 31#include "hw/cris/etraxfs_dma.h"
1ba13a5d
EI		 32
33#define D(x)
34
c01c07bb
EI		 35#define RW_DATA (0x0 / 4)
36#define RW_SAVED_DATA (0x58 / 4)
37#define RW_SAVED_DATA_BUF (0x5c / 4)
38#define RW_GROUP (0x60 / 4)
39#define RW_GROUP_DOWN (0x7c / 4)
40#define RW_CMD (0x80 / 4)
41#define RW_CFG (0x84 / 4)
42#define RW_STAT (0x88 / 4)
43#define RW_INTR_MASK (0x8c / 4)
44#define RW_ACK_INTR (0x90 / 4)
45#define R_INTR (0x94 / 4)
46#define R_MASKED_INTR (0x98 / 4)
47#define RW_STREAM_CMD (0x9c / 4)
48
49#define DMA_REG_MAX (0x100 / 4)
1ba13a5d
EI		 50
51/* descriptors */
52
53// ------------------------------------------------------------ dma_descr_group
54typedef struct dma_descr_group {
41107bcb 55 uint32_t next;
1ba13a5d
EI		 56 unsigned eol : 1;
57 unsigned tol : 1;
58 unsigned bol : 1;
59 unsigned : 1;
60 unsigned intr : 1;
61 unsigned : 2;
62 unsigned en : 1;
63 unsigned : 7;
64 unsigned dis : 1;
65 unsigned md : 16;
66 struct dma_descr_group *up;
67 union {
68 struct dma_descr_context *context;
69 struct dma_descr_group *group;
70 } down;
71} dma_descr_group;
72
73// ---------------------------------------------------------- dma_descr_context
74typedef struct dma_descr_context {
41107bcb 75 uint32_t next;
1ba13a5d
EI		 76 unsigned eol : 1;
77 unsigned : 3;
78 unsigned intr : 1;
79 unsigned : 1;
80 unsigned store_mode : 1;
81 unsigned en : 1;
82 unsigned : 7;
83 unsigned dis : 1;
84 unsigned md0 : 16;
85 unsigned md1;
86 unsigned md2;
87 unsigned md3;
88 unsigned md4;
41107bcb
EI		 89 uint32_t saved_data;
90 uint32_t saved_data_buf;
1ba13a5d
EI		 91} dma_descr_context;
92
93// ------------------------------------------------------------- dma_descr_data
94typedef struct dma_descr_data {
41107bcb
EI		 95 uint32_t next;
96 uint32_t buf;
1ba13a5d
EI		 97 unsigned eol : 1;
98 unsigned : 2;
99 unsigned out_eop : 1;
100 unsigned intr : 1;
101 unsigned wait : 1;
102 unsigned : 2;
103 unsigned : 3;
104 unsigned in_eop : 1;
105 unsigned : 4;
106 unsigned md : 16;
41107bcb 107 uint32_t after;
1ba13a5d
EI		 108} dma_descr_data;
109
110/* Constants */
111enum {
112 regk_dma_ack_pkt = 0x00000100,
113 regk_dma_anytime = 0x00000001,
114 regk_dma_array = 0x00000008,
115 regk_dma_burst = 0x00000020,
116 regk_dma_client = 0x00000002,
117 regk_dma_copy_next = 0x00000010,
118 regk_dma_copy_up = 0x00000020,
119 regk_dma_data_at_eol = 0x00000001,
120 regk_dma_dis_c = 0x00000010,
121 regk_dma_dis_g = 0x00000020,
122 regk_dma_idle = 0x00000001,
123 regk_dma_intern = 0x00000004,
124 regk_dma_load_c = 0x00000200,
125 regk_dma_load_c_n = 0x00000280,
126 regk_dma_load_c_next = 0x00000240,
127 regk_dma_load_d = 0x00000140,
128 regk_dma_load_g = 0x00000300,
129 regk_dma_load_g_down = 0x000003c0,
130 regk_dma_load_g_next = 0x00000340,
131 regk_dma_load_g_up = 0x00000380,
132 regk_dma_next_en = 0x00000010,
133 regk_dma_next_pkt = 0x00000010,
134 regk_dma_no = 0x00000000,
135 regk_dma_only_at_wait = 0x00000000,
136 regk_dma_restore = 0x00000020,
137 regk_dma_rst = 0x00000001,
138 regk_dma_running = 0x00000004,
139 regk_dma_rw_cfg_default = 0x00000000,
140 regk_dma_rw_cmd_default = 0x00000000,
141 regk_dma_rw_intr_mask_default = 0x00000000,
142 regk_dma_rw_stat_default = 0x00000101,
143 regk_dma_rw_stream_cmd_default = 0x00000000,
144 regk_dma_save_down = 0x00000020,
145 regk_dma_save_up = 0x00000020,
146 regk_dma_set_reg = 0x00000050,
147 regk_dma_set_w_size1 = 0x00000190,
148 regk_dma_set_w_size2 = 0x000001a0,
149 regk_dma_set_w_size4 = 0x000001c0,
150 regk_dma_stopped = 0x00000002,
151 regk_dma_store_c = 0x00000002,
152 regk_dma_store_descr = 0x00000000,
153 regk_dma_store_g = 0x00000004,
154 regk_dma_store_md = 0x00000001,
155 regk_dma_sw = 0x00000008,
156 regk_dma_update_down = 0x00000020,
157 regk_dma_yes = 0x00000001
158};
159
160enum dma_ch_state
161{
4487fd34 162 RST = 1,
1ba13a5d
EI		 163 STOPPED = 2,
164 RUNNING = 4
165};
166
167struct fs_dma_channel
168{
96d7ddde 169 qemu_irq irq;
1ba13a5d
EI		 170 struct etraxfs_dma_client *client;
171
1ba13a5d
EI		 172 /* Internal status. */
173 int stream_cmd_src;
174 enum dma_ch_state state;
175
176 unsigned int input : 1;
177 unsigned int eol : 1;
178
179 struct dma_descr_group current_g;
180 struct dma_descr_context current_c;
181 struct dma_descr_data current_d;
182
66a0a2cb 183 /* Control registers. */
1ba13a5d
EI		 184 uint32_t regs[DMA_REG_MAX];
185};
186
187struct fs_dma_ctrl
188{
9dcb06ce 189 MemoryRegion mmio;
1ba13a5d
EI		 190 int nr_channels;
191 struct fs_dma_channel *channels;
492c30af
AL		 192
193 QEMUBH *bh;
1ba13a5d
EI		 194};
195
c01c07bb
EI		 196static void DMA_run(void *opaque);
197static int channel_out_run(struct fs_dma_ctrl *ctrl, int c);
198
1ba13a5d
EI		 199static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
200{
201 return ctrl->channels[c].regs[reg];
202}
203
204static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
205{
206 return channel_reg(ctrl, c, RW_CFG) & 2;
207}
208
209static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
210{
211 return (channel_reg(ctrl, c, RW_CFG) & 1)
212 && ctrl->channels[c].client;
213}
214
a8170e5e 215static inline int fs_channel(hwaddr addr)
1ba13a5d
EI		 216{
217 /* Every channel has a 0x2000 ctrl register map. */
8da3ff18 218 return addr >> 13;
1ba13a5d
EI		 219}
220
d297f464 221#ifdef USE_THIS_DEAD_CODE
1ba13a5d
EI		 222static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
223{
a8170e5e 224 hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
1ba13a5d
EI		 225
226 /* Load and decode. FIXME: handle endianness. */
227 cpu_physical_memory_read (addr,
228 (void *) &ctrl->channels[c].current_g,
229 sizeof ctrl->channels[c].current_g);
230}
231
232static void dump_c(int ch, struct dma_descr_context *c)
233{
234 printf("%s ch=%d\n", __func__, ch);
41107bcb
EI		 235 printf("next=%x\n", c->next);
236 printf("saved_data=%x\n", c->saved_data);
237 printf("saved_data_buf=%x\n", c->saved_data_buf);
1ba13a5d
EI		 238 printf("eol=%x\n", (uint32_t) c->eol);
239}
240
241static void dump_d(int ch, struct dma_descr_data *d)
242{
243 printf("%s ch=%d\n", __func__, ch);
41107bcb
EI		 244 printf("next=%x\n", d->next);
245 printf("buf=%x\n", d->buf);
246 printf("after=%x\n", d->after);
1ba13a5d
EI		 247 printf("intr=%x\n", (uint32_t) d->intr);
248 printf("out_eop=%x\n", (uint32_t) d->out_eop);
249 printf("in_eop=%x\n", (uint32_t) d->in_eop);
250 printf("eol=%x\n", (uint32_t) d->eol);
251}
d297f464 252#endif
1ba13a5d
EI		 253
254static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
255{
a8170e5e 256 hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
1ba13a5d
EI		 257
258 /* Load and decode. FIXME: handle endianness. */
259 cpu_physical_memory_read (addr,
260 (void *) &ctrl->channels[c].current_c,
261 sizeof ctrl->channels[c].current_c);
262
263 D(dump_c(c, &ctrl->channels[c].current_c));
264 /* I guess this should update the current pos. */
d297f464
EI		 265 ctrl->channels[c].regs[RW_SAVED_DATA] =
266 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
1ba13a5d 267 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
d297f464 268 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
1ba13a5d
EI		 269}
270
271static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
272{
a8170e5e 273 hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
1ba13a5d
EI		 274
275 /* Load and decode. FIXME: handle endianness. */
41107bcb 276 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
1ba13a5d
EI		 277 cpu_physical_memory_read (addr,
278 (void *) &ctrl->channels[c].current_d,
279 sizeof ctrl->channels[c].current_d);
280
281 D(dump_d(c, &ctrl->channels[c].current_d));
fa1bdde4 282 ctrl->channels[c].regs[RW_DATA] = addr;
a8303d18
EI		 283}
284
285static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
286{
a8170e5e 287 hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
a8303d18
EI		 288
289 /* Encode and store. FIXME: handle endianness. */
41107bcb 290 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
a8303d18
EI		 291 D(dump_d(c, &ctrl->channels[c].current_d));
292 cpu_physical_memory_write (addr,
293 (void *) &ctrl->channels[c].current_c,
294 sizeof ctrl->channels[c].current_c);
1ba13a5d
EI		 295}
296
297static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
298{
a8170e5e 299 hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
1ba13a5d 300
a8303d18 301 /* Encode and store. FIXME: handle endianness. */
41107bcb 302 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
1ba13a5d
EI		 303 cpu_physical_memory_write (addr,
304 (void *) &ctrl->channels[c].current_d,
305 sizeof ctrl->channels[c].current_d);
306}
307
308static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
309{
310 /* FIXME: */
311}
312
313static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
314{
315 if (ctrl->channels[c].client)
316 {
317 ctrl->channels[c].eol = 0;
318 ctrl->channels[c].state = RUNNING;
c01c07bb
EI		 319 if (!ctrl->channels[c].input)
320 channel_out_run(ctrl, c);
1ba13a5d
EI		 321 } else
322 printf("WARNING: starting DMA ch %d with no client\n", c);
1ab5f75c
EI		 323
324 qemu_bh_schedule_idle(ctrl->bh);
1ba13a5d
EI		 325}
326
327static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
328{
329 if (!channel_en(ctrl, c)
330 || channel_stopped(ctrl, c)
331 || ctrl->channels[c].state != RUNNING
332 /* Only reload the current data descriptor if it has eol set. */
333 || !ctrl->channels[c].current_d.eol) {
334 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
335 c, ctrl->channels[c].state,
336 channel_stopped(ctrl, c),
337 channel_en(ctrl,c),
338 ctrl->channels[c].eol));
339 D(dump_d(c, &ctrl->channels[c].current_d));
340 return;
341 }
342
343 /* Reload the current descriptor. */
344 channel_load_d(ctrl, c);
345
346 /* If the current descriptor cleared the eol flag and we had already
347 reached eol state, do the continue. */
348 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
41107bcb 349 D(printf("continue %d ok %x\n", c,
1ba13a5d
EI		 350 ctrl->channels[c].current_d.next));
351 ctrl->channels[c].regs[RW_SAVED_DATA] =
d297f464 352 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
1ba13a5d 353 channel_load_d(ctrl, c);
c01c07bb
EI		 354 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
355 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
356
1ba13a5d
EI		 357 channel_start(ctrl, c);
358 }
a8303d18 359 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
d297f464 360 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
1ba13a5d
EI		 361}
362
363static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
364{
365 unsigned int cmd = v & ((1 << 10) - 1);
366
d27b2e50
EI		 367 D(printf("%s ch=%d cmd=%x\n",
368 __func__, c, cmd));
1ba13a5d
EI		 369 if (cmd & regk_dma_load_d) {
370 channel_load_d(ctrl, c);
371 if (cmd & regk_dma_burst)
372 channel_start(ctrl, c);
373 }
374
375 if (cmd & regk_dma_load_c) {
376 channel_load_c(ctrl, c);
377 }
378}
379
380static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
381{
382 D(printf("%s %d\n", __func__, c));
383 ctrl->channels[c].regs[R_INTR] &=
384 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
385
386 ctrl->channels[c].regs[R_MASKED_INTR] =
387 ctrl->channels[c].regs[R_INTR]
388 & ctrl->channels[c].regs[RW_INTR_MASK];
389
390 D(printf("%s: chan=%d masked_intr=%x\n", __func__,
391 c,
392 ctrl->channels[c].regs[R_MASKED_INTR]));
393
96d7ddde 394 qemu_set_irq(ctrl->channels[c].irq,
7a3161ba 395 !!ctrl->channels[c].regs[R_MASKED_INTR]);
1ba13a5d
EI		 396}
397
1ab5f75c 398static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
1ba13a5d
EI		 399{
400 uint32_t len;
401 uint32_t saved_data_buf;
402 unsigned char buf[2 * 1024];
403
73a511de
LP		 404 struct dma_context_metadata meta;
405 bool send_context = true;
406
1ab5f75c
EI		 407 if (ctrl->channels[c].eol)
408 return 0;
409
410 do {
73a511de 411 bool out_eop;
41107bcb 412 D(printf("ch=%d buf=%x after=%x\n",
c968ef8d
EI		 413 c,
414 (uint32_t)ctrl->channels[c].current_d.buf,
41107bcb 415 (uint32_t)ctrl->channels[c].current_d.after));
c968ef8d 416
73a511de
LP		 417 if (send_context) {
418 if (ctrl->channels[c].client->client.metadata_push) {
419 meta.metadata = ctrl->channels[c].current_d.md;
420 ctrl->channels[c].client->client.metadata_push(
421 ctrl->channels[c].client->client.opaque,
422 &meta);
423 }
424 send_context = false;
425 }
426
c01c07bb
EI		 427 channel_load_d(ctrl, c);
428 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
ea0f49a7
EI		 429 len = (uint32_t)(unsigned long)
430 ctrl->channels[c].current_d.after;
c968ef8d
EI		 431 len -= saved_data_buf;
432
433 if (len > sizeof buf)
434 len = sizeof buf;
435 cpu_physical_memory_read (saved_data_buf, buf, len);
436
73a511de
LP		 437 out_eop = ((saved_data_buf + len) ==
438 ctrl->channels[c].current_d.after) &&
439 ctrl->channels[c].current_d.out_eop;
440
441 D(printf("channel %d pushes %x %u bytes eop=%u\n", c,
442 saved_data_buf, len, out_eop));
c968ef8d
EI		 443
444 if (ctrl->channels[c].client->client.push)
445 ctrl->channels[c].client->client.push(
446 ctrl->channels[c].client->client.opaque,
73a511de 447 buf, len, out_eop);
c968ef8d
EI		 448 else
449 printf("WARNING: DMA ch%d dataloss,"
450 " no attached client.\n", c);
451
452 saved_data_buf += len;
453
ea0f49a7
EI		 454 if (saved_data_buf == (uint32_t)(unsigned long)
455 ctrl->channels[c].current_d.after) {
c968ef8d
EI		 456 /* Done. Step to next. */
457 if (ctrl->channels[c].current_d.out_eop) {
73a511de 458 send_context = true;
c968ef8d
EI		 459 }
460 if (ctrl->channels[c].current_d.intr) {
c968ef8d 461 /* data intr. */
c01c07bb
EI		 462 D(printf("signal intr %d eol=%d\n",
463 len, ctrl->channels[c].current_d.eol));
c968ef8d
EI		 464 ctrl->channels[c].regs[R_INTR] |= (1 << 2);
465 channel_update_irq(ctrl, c);
466 }
c01c07bb 467 channel_store_d(ctrl, c);
c968ef8d
EI		 468 if (ctrl->channels[c].current_d.eol) {
469 D(printf("channel %d EOL\n", c));
470 ctrl->channels[c].eol = 1;
471
472 /* Mark the context as disabled. */
473 ctrl->channels[c].current_c.dis = 1;
474 channel_store_c(ctrl, c);
475
476 channel_stop(ctrl, c);
477 } else {
478 ctrl->channels[c].regs[RW_SAVED_DATA] =
ea0f49a7
EI		 479 (uint32_t)(unsigned long)ctrl->
480 channels[c].current_d.next;
c968ef8d
EI		 481 /* Load new descriptor. */
482 channel_load_d(ctrl, c);
483 saved_data_buf = (uint32_t)(unsigned long)
484 ctrl->channels[c].current_d.buf;
485 }
486
c968ef8d
EI		 487 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
488 saved_data_buf;
489 D(dump_d(c, &ctrl->channels[c].current_d));
1ba13a5d 490 }
a8303d18 491 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
1ab5f75c
EI		 492 } while (!ctrl->channels[c].eol);
493 return 1;
1ba13a5d
EI		 494}
495
496static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
497 unsigned char *buf, int buflen, int eop)
498{
499 uint32_t len;
500 uint32_t saved_data_buf;
501
502 if (ctrl->channels[c].eol == 1)
503 return 0;
504
c01c07bb 505 channel_load_d(ctrl, c);
1ba13a5d 506 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
ea0f49a7 507 len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
1ba13a5d
EI		 508 len -= saved_data_buf;
509
510 if (len > buflen)
511 len = buflen;
512
513 cpu_physical_memory_write (saved_data_buf, buf, len);
514 saved_data_buf += len;
515
d297f464 516 if (saved_data_buf ==
ea0f49a7 517 (uint32_t)(unsigned long)ctrl->channels[c].current_d.after
1ba13a5d
EI		 518 || eop) {
519 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
520
521 D(printf("in dscr end len=%d\n",
522 ctrl->channels[c].current_d.after
523 - ctrl->channels[c].current_d.buf));
41107bcb 524 ctrl->channels[c].current_d.after = saved_data_buf;
1ba13a5d
EI		 525
526 /* Done. Step to next. */
527 if (ctrl->channels[c].current_d.intr) {
528 /* TODO: signal eop to the client. */
529 /* data intr. */
530 ctrl->channels[c].regs[R_INTR] |= 3;
531 }
532 if (eop) {
533 ctrl->channels[c].current_d.in_eop = 1;
534 ctrl->channels[c].regs[R_INTR] |= 8;
535 }
536 if (r_intr != ctrl->channels[c].regs[R_INTR])
537 channel_update_irq(ctrl, c);
538
539 channel_store_d(ctrl, c);
540 D(dump_d(c, &ctrl->channels[c].current_d));
541
542 if (ctrl->channels[c].current_d.eol) {
543 D(printf("channel %d EOL\n", c));
544 ctrl->channels[c].eol = 1;
a8303d18
EI		 545
546 /* Mark the context as disabled. */
547 ctrl->channels[c].current_c.dis = 1;
548 channel_store_c(ctrl, c);
549
1ba13a5d
EI		 550 channel_stop(ctrl, c);
551 } else {
552 ctrl->channels[c].regs[RW_SAVED_DATA] =
ea0f49a7
EI		 553 (uint32_t)(unsigned long)ctrl->
554 channels[c].current_d.next;
1ba13a5d
EI		 555 /* Load new descriptor. */
556 channel_load_d(ctrl, c);
ea0f49a7 557 saved_data_buf = (uint32_t)(unsigned long)
a8303d18 558 ctrl->channels[c].current_d.buf;
1ba13a5d
EI		 559 }
560 }
561
562 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
563 return len;
564}
565
1ab5f75c 566static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
1ba13a5d 567{
1ab5f75c 568 if (ctrl->channels[c].client->client.pull) {
1ba13a5d
EI		 569 ctrl->channels[c].client->client.pull(
570 ctrl->channels[c].client->client.opaque);
1ab5f75c
EI		 571 return 1;
572 } else
573 return 0;
1ba13a5d
EI		 574}
575
a8170e5e 576static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
1ba13a5d 577{
41107bcb 578 hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
1ba13a5d
EI		 579 return 0;
580}
581
9dcb06ce 582static uint64_t
a8170e5e 583dma_read(void *opaque, hwaddr addr, unsigned int size)
1ba13a5d
EI		 584{
585 struct fs_dma_ctrl *ctrl = opaque;
586 int c;
587 uint32_t r = 0;
588
9dcb06ce
EI		 589 if (size != 4) {
590 dma_rinvalid(opaque, addr);
591 }
592
e6320485 593 /* Make addr relative to this channel and bounded to nr regs. */
8da3ff18 594 c = fs_channel(addr);
e6320485 595 addr &= 0xff;
c01c07bb 596 addr >>= 2;
1ba13a5d 597 switch (addr)
a8303d18 598 {
1ba13a5d
EI		 599 case RW_STAT:
600 r = ctrl->channels[c].state & 7;
601 r |= ctrl->channels[c].eol << 5;
602 r |= ctrl->channels[c].stream_cmd_src << 8;
603 break;
604
a8303d18 605 default:
1ba13a5d 606 r = ctrl->channels[c].regs[addr];
41107bcb 607 D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
d27b2e50 608 __func__, c, addr));
a8303d18
EI		 609 break;
610 }
1ba13a5d
EI		 611 return r;
612}
613
614static void
a8170e5e 615dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
1ba13a5d 616{
41107bcb 617 hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
1ba13a5d
EI		 618}
619
4487fd34
EI		 620static void
621dma_update_state(struct fs_dma_ctrl *ctrl, int c)
622{
d11cf8cc
EI		 623 if (ctrl->channels[c].regs[RW_CFG] & 2)
624 ctrl->channels[c].state = STOPPED;
625 if (!(ctrl->channels[c].regs[RW_CFG] & 1))
626 ctrl->channels[c].state = RST;
4487fd34
EI		 627}
628
1ba13a5d 629static void
a8170e5e 630dma_write(void *opaque, hwaddr addr,
9dcb06ce 631 uint64_t val64, unsigned int size)
1ba13a5d
EI		 632{
633 struct fs_dma_ctrl *ctrl = opaque;
9dcb06ce 634 uint32_t value = val64;
1ba13a5d
EI		 635 int c;
636
9dcb06ce
EI		 637 if (size != 4) {
638 dma_winvalid(opaque, addr, value);
639 }
640
e6320485 641 /* Make addr relative to this channel and bounded to nr regs. */
8da3ff18 642 c = fs_channel(addr);
e6320485 643 addr &= 0xff;
c01c07bb 644 addr >>= 2;
1ba13a5d 645 switch (addr)
a8303d18 646 {
1ba13a5d 647 case RW_DATA:
fa1bdde4 648 ctrl->channels[c].regs[addr] = value;
1ba13a5d
EI		 649 break;
650
651 case RW_CFG:
652 ctrl->channels[c].regs[addr] = value;
4487fd34 653 dma_update_state(ctrl, c);
1ba13a5d
EI		 654 break;
655 case RW_CMD:
656 /* continue. */
4487fd34
EI		 657 if (value & ~1)
658 printf("Invalid store to ch=%d RW_CMD %x\n",
659 c, value);
1ba13a5d
EI		 660 ctrl->channels[c].regs[addr] = value;
661 channel_continue(ctrl, c);
662 break;
663
664 case RW_SAVED_DATA:
665 case RW_SAVED_DATA_BUF:
666 case RW_GROUP:
667 case RW_GROUP_DOWN:
668 ctrl->channels[c].regs[addr] = value;
669 break;
670
671 case RW_ACK_INTR:
672 case RW_INTR_MASK:
673 ctrl->channels[c].regs[addr] = value;
674 channel_update_irq(ctrl, c);
675 if (addr == RW_ACK_INTR)
676 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
677 break;
678
679 case RW_STREAM_CMD:
4487fd34
EI		 680 if (value & ~1023)
681 printf("Invalid store to ch=%d "
682 "RW_STREAMCMD %x\n",
683 c, value);
1ba13a5d 684 ctrl->channels[c].regs[addr] = value;
d27b2e50 685 D(printf("stream_cmd ch=%d\n", c));
1ba13a5d
EI		 686 channel_stream_cmd(ctrl, c, value);
687 break;
688
a8303d18 689 default:
41107bcb
EI		 690 D(printf ("%s c=%d " TARGET_FMT_plx "\n",
691 __func__, c, addr));
a8303d18 692 break;
1ba13a5d
EI		 693 }
694}
695
9dcb06ce
EI		 696static const MemoryRegionOps dma_ops = {
697 .read = dma_read,
698 .write = dma_write,
699 .endianness = DEVICE_NATIVE_ENDIAN,
700 .valid = {
701 .min_access_size = 1,
702 .max_access_size = 4
703 }
1ba13a5d
EI		 704};
705
1ab5f75c 706static int etraxfs_dmac_run(void *opaque)
1ba13a5d
EI		 707{
708 struct fs_dma_ctrl *ctrl = opaque;
709 int i;
710 int p = 0;
711
712 for (i = 0;
713 i < ctrl->nr_channels;
714 i++)
715 {
716 if (ctrl->channels[i].state == RUNNING)
717 {
1ab5f75c
EI		 718 if (ctrl->channels[i].input) {
719 p += channel_in_run(ctrl, i);
720 } else {
721 p += channel_out_run(ctrl, i);
722 }
1ba13a5d
EI		 723 }
724 }
1ab5f75c 725 return p;
1ba13a5d
EI		 726}
727
728int etraxfs_dmac_input(struct etraxfs_dma_client *client,
729 void *buf, int len, int eop)
730{
731 return channel_in_process(client->ctrl, client->channel,
732 buf, len, eop);
733}
734
735/* Connect an IRQ line with a channel. */
736void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
737{
738 struct fs_dma_ctrl *ctrl = opaque;
96d7ddde 739 ctrl->channels[c].irq = *line;
1ba13a5d
EI		 740 ctrl->channels[c].input = input;
741}
742
743void etraxfs_dmac_connect_client(void *opaque, int c,
744 struct etraxfs_dma_client *cl)
745{
746 struct fs_dma_ctrl *ctrl = opaque;
747 cl->ctrl = ctrl;
748 cl->channel = c;
749 ctrl->channels[c].client = cl;
750}
751
752
492c30af 753static void DMA_run(void *opaque)
fa1bdde4 754{
492c30af 755 struct fs_dma_ctrl *etraxfs_dmac = opaque;
1ab5f75c
EI		 756 int p = 1;
757
1354869c 758 if (runstate_is_running())
1ab5f75c
EI		 759 p = etraxfs_dmac_run(etraxfs_dmac);
760
761 if (p)
762 qemu_bh_schedule_idle(etraxfs_dmac->bh);
fa1bdde4
EI		 763}
764
a8170e5e 765void *etraxfs_dmac_init(hwaddr base, int nr_channels)
1ba13a5d
EI		 766{
767 struct fs_dma_ctrl *ctrl = NULL;
1ba13a5d 768
7267c094 769 ctrl = g_malloc0(sizeof *ctrl);
1ba13a5d 770
492c30af 771 ctrl->bh = qemu_bh_new(DMA_run, ctrl);
492c30af 772
1ba13a5d 773 ctrl->nr_channels = nr_channels;
7267c094 774 ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels);
1ba13a5d 775
2c9b15ca 776 memory_region_init_io(&ctrl->mmio, NULL, &dma_ops, ctrl, "etraxfs-dma",
9dcb06ce
EI		 777 nr_channels * 0x2000);
778 memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio);
779
1ba13a5d 780 return ctrl;
1ba13a5d 781}
Qemu copy for testing