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06a1cea5 PC |
1 | /* |
2 | * ARM PrimeCell PL330 DMA Controller | |
3 | * | |
4 | * Copyright (c) 2009 Samsung Electronics. | |
5 | * Contributed by Kirill Batuzov <batuzovk@ispras.ru> | |
6 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) | |
7 | * Copyright (c) 2012 PetaLogix Pty Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 or later. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along | |
14 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
8ef94f0b | 17 | #include "qemu/osdep.h" |
a8d25326 | 18 | #include "qemu-common.h" |
64552b6b | 19 | #include "hw/irq.h" |
a27bd6c7 | 20 | #include "hw/qdev-properties.h" |
0d09e41a | 21 | #include "hw/sysbus.h" |
d6454270 | 22 | #include "migration/vmstate.h" |
da34e65c | 23 | #include "qapi/error.h" |
06a1cea5 PC |
24 | #include "qemu/timer.h" |
25 | #include "sysemu/dma.h" | |
03dd024f | 26 | #include "qemu/log.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
db1e7afa | 28 | #include "trace.h" |
db1015e9 | 29 | #include "qom/object.h" |
06a1cea5 PC |
30 | |
31 | #ifndef PL330_ERR_DEBUG | |
32 | #define PL330_ERR_DEBUG 0 | |
33 | #endif | |
34 | ||
06a1cea5 PC |
35 | #define PL330_PERIPH_NUM 32 |
36 | #define PL330_MAX_BURST_LEN 128 | |
37 | #define PL330_INSN_MAXSIZE 6 | |
38 | ||
39 | #define PL330_FIFO_OK 0 | |
40 | #define PL330_FIFO_STALL 1 | |
41 | #define PL330_FIFO_ERR (-1) | |
42 | ||
43 | #define PL330_FAULT_UNDEF_INSTR (1 << 0) | |
44 | #define PL330_FAULT_OPERAND_INVALID (1 << 1) | |
45 | #define PL330_FAULT_DMAGO_ERR (1 << 4) | |
46 | #define PL330_FAULT_EVENT_ERR (1 << 5) | |
47 | #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) | |
48 | #define PL330_FAULT_CH_RDWR_ERR (1 << 7) | |
49 | #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) | |
50 | #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) | |
51 | #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) | |
52 | #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) | |
53 | #define PL330_FAULT_DATA_READ_ERR (1 << 18) | |
54 | #define PL330_FAULT_DBG_INSTR (1 << 30) | |
55 | #define PL330_FAULT_LOCKUP_ERR (1 << 31) | |
56 | ||
57 | #define PL330_UNTAGGED 0xff | |
58 | ||
59 | #define PL330_SINGLE 0x0 | |
60 | #define PL330_BURST 0x1 | |
61 | ||
62 | #define PL330_WATCHDOG_LIMIT 1024 | |
63 | ||
64 | /* IOMEM mapped registers */ | |
65 | #define PL330_REG_DSR 0x000 | |
66 | #define PL330_REG_DPC 0x004 | |
67 | #define PL330_REG_INTEN 0x020 | |
68 | #define PL330_REG_INT_EVENT_RIS 0x024 | |
69 | #define PL330_REG_INTMIS 0x028 | |
70 | #define PL330_REG_INTCLR 0x02C | |
71 | #define PL330_REG_FSRD 0x030 | |
72 | #define PL330_REG_FSRC 0x034 | |
73 | #define PL330_REG_FTRD 0x038 | |
74 | #define PL330_REG_FTR_BASE 0x040 | |
75 | #define PL330_REG_CSR_BASE 0x100 | |
76 | #define PL330_REG_CPC_BASE 0x104 | |
77 | #define PL330_REG_CHANCTRL 0x400 | |
78 | #define PL330_REG_DBGSTATUS 0xD00 | |
79 | #define PL330_REG_DBGCMD 0xD04 | |
80 | #define PL330_REG_DBGINST0 0xD08 | |
81 | #define PL330_REG_DBGINST1 0xD0C | |
82 | #define PL330_REG_CR0_BASE 0xE00 | |
83 | #define PL330_REG_PERIPH_ID 0xFE0 | |
84 | ||
85 | #define PL330_IOMEM_SIZE 0x1000 | |
86 | ||
87 | #define CFG_BOOT_ADDR 2 | |
88 | #define CFG_INS 3 | |
89 | #define CFG_PNS 4 | |
90 | #define CFG_CRD 5 | |
91 | ||
92 | static const uint32_t pl330_id[] = { | |
93 | 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 | |
94 | }; | |
95 | ||
96 | /* DMA channel states as they are described in PL330 Technical Reference Manual | |
97 | * Most of them will not be used in emulation. | |
98 | */ | |
99 | typedef enum { | |
100 | pl330_chan_stopped = 0, | |
101 | pl330_chan_executing = 1, | |
102 | pl330_chan_cache_miss = 2, | |
103 | pl330_chan_updating_pc = 3, | |
104 | pl330_chan_waiting_event = 4, | |
105 | pl330_chan_at_barrier = 5, | |
106 | pl330_chan_queue_busy = 6, | |
107 | pl330_chan_waiting_periph = 7, | |
108 | pl330_chan_killing = 8, | |
109 | pl330_chan_completing = 9, | |
110 | pl330_chan_fault_completing = 14, | |
111 | pl330_chan_fault = 15, | |
112 | } PL330ChanState; | |
113 | ||
114 | typedef struct PL330State PL330State; | |
115 | ||
116 | typedef struct PL330Chan { | |
117 | uint32_t src; | |
118 | uint32_t dst; | |
119 | uint32_t pc; | |
120 | uint32_t control; | |
121 | uint32_t status; | |
122 | uint32_t lc[2]; | |
123 | uint32_t fault_type; | |
124 | uint32_t watchdog_timer; | |
125 | ||
126 | bool ns; | |
127 | uint8_t request_flag; | |
128 | uint8_t wakeup; | |
129 | uint8_t wfp_sbp; | |
130 | ||
131 | uint8_t state; | |
132 | uint8_t stall; | |
133 | ||
134 | bool is_manager; | |
135 | PL330State *parent; | |
136 | uint8_t tag; | |
137 | } PL330Chan; | |
138 | ||
139 | static const VMStateDescription vmstate_pl330_chan = { | |
140 | .name = "pl330_chan", | |
141 | .version_id = 1, | |
142 | .minimum_version_id = 1, | |
06a1cea5 PC |
143 | .fields = (VMStateField[]) { |
144 | VMSTATE_UINT32(src, PL330Chan), | |
145 | VMSTATE_UINT32(dst, PL330Chan), | |
146 | VMSTATE_UINT32(pc, PL330Chan), | |
147 | VMSTATE_UINT32(control, PL330Chan), | |
148 | VMSTATE_UINT32(status, PL330Chan), | |
149 | VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2), | |
150 | VMSTATE_UINT32(fault_type, PL330Chan), | |
151 | VMSTATE_UINT32(watchdog_timer, PL330Chan), | |
152 | VMSTATE_BOOL(ns, PL330Chan), | |
153 | VMSTATE_UINT8(request_flag, PL330Chan), | |
154 | VMSTATE_UINT8(wakeup, PL330Chan), | |
155 | VMSTATE_UINT8(wfp_sbp, PL330Chan), | |
156 | VMSTATE_UINT8(state, PL330Chan), | |
157 | VMSTATE_UINT8(stall, PL330Chan), | |
158 | VMSTATE_END_OF_LIST() | |
159 | } | |
160 | }; | |
161 | ||
162 | typedef struct PL330Fifo { | |
163 | uint8_t *buf; | |
164 | uint8_t *tag; | |
165 | uint32_t head; | |
166 | uint32_t num; | |
167 | uint32_t buf_size; | |
168 | } PL330Fifo; | |
169 | ||
170 | static const VMStateDescription vmstate_pl330_fifo = { | |
171 | .name = "pl330_chan", | |
172 | .version_id = 1, | |
173 | .minimum_version_id = 1, | |
06a1cea5 | 174 | .fields = (VMStateField[]) { |
59046ec2 HP |
175 | VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size), |
176 | VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size), | |
06a1cea5 PC |
177 | VMSTATE_UINT32(head, PL330Fifo), |
178 | VMSTATE_UINT32(num, PL330Fifo), | |
179 | VMSTATE_UINT32(buf_size, PL330Fifo), | |
180 | VMSTATE_END_OF_LIST() | |
181 | } | |
182 | }; | |
183 | ||
184 | typedef struct PL330QueueEntry { | |
185 | uint32_t addr; | |
186 | uint32_t len; | |
187 | uint8_t n; | |
188 | bool inc; | |
189 | bool z; | |
190 | uint8_t tag; | |
191 | uint8_t seqn; | |
192 | } PL330QueueEntry; | |
193 | ||
194 | static const VMStateDescription vmstate_pl330_queue_entry = { | |
195 | .name = "pl330_queue_entry", | |
196 | .version_id = 1, | |
197 | .minimum_version_id = 1, | |
06a1cea5 PC |
198 | .fields = (VMStateField[]) { |
199 | VMSTATE_UINT32(addr, PL330QueueEntry), | |
200 | VMSTATE_UINT32(len, PL330QueueEntry), | |
201 | VMSTATE_UINT8(n, PL330QueueEntry), | |
202 | VMSTATE_BOOL(inc, PL330QueueEntry), | |
203 | VMSTATE_BOOL(z, PL330QueueEntry), | |
204 | VMSTATE_UINT8(tag, PL330QueueEntry), | |
205 | VMSTATE_UINT8(seqn, PL330QueueEntry), | |
206 | VMSTATE_END_OF_LIST() | |
207 | } | |
208 | }; | |
209 | ||
210 | typedef struct PL330Queue { | |
211 | PL330State *parent; | |
212 | PL330QueueEntry *queue; | |
213 | uint32_t queue_size; | |
214 | } PL330Queue; | |
215 | ||
216 | static const VMStateDescription vmstate_pl330_queue = { | |
217 | .name = "pl330_queue", | |
830fc739 DH |
218 | .version_id = 2, |
219 | .minimum_version_id = 2, | |
06a1cea5 | 220 | .fields = (VMStateField[]) { |
830fc739 DH |
221 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size, |
222 | vmstate_pl330_queue_entry, | |
223 | PL330QueueEntry), | |
06a1cea5 PC |
224 | VMSTATE_END_OF_LIST() |
225 | } | |
226 | }; | |
227 | ||
228 | struct PL330State { | |
1c8be73d PC |
229 | SysBusDevice parent_obj; |
230 | ||
06a1cea5 PC |
231 | MemoryRegion iomem; |
232 | qemu_irq irq_abort; | |
233 | qemu_irq *irq; | |
234 | ||
235 | /* Config registers. cfg[5] = CfgDn. */ | |
236 | uint32_t cfg[6]; | |
237 | #define EVENT_SEC_STATE 3 | |
238 | #define PERIPH_SEC_STATE 4 | |
239 | /* cfg 0 bits and pieces */ | |
240 | uint32_t num_chnls; | |
241 | uint8_t num_periph_req; | |
242 | uint8_t num_events; | |
243 | uint8_t mgr_ns_at_rst; | |
244 | /* cfg 1 bits and pieces */ | |
245 | uint8_t i_cache_len; | |
246 | uint8_t num_i_cache_lines; | |
247 | /* CRD bits and pieces */ | |
248 | uint8_t data_width; | |
249 | uint8_t wr_cap; | |
250 | uint8_t wr_q_dep; | |
251 | uint8_t rd_cap; | |
252 | uint8_t rd_q_dep; | |
253 | uint16_t data_buffer_dep; | |
254 | ||
255 | PL330Chan manager; | |
256 | PL330Chan *chan; | |
257 | PL330Fifo fifo; | |
258 | PL330Queue read_queue; | |
259 | PL330Queue write_queue; | |
260 | uint8_t *lo_seqn; | |
261 | uint8_t *hi_seqn; | |
262 | QEMUTimer *timer; /* is used for restore dma. */ | |
263 | ||
264 | uint32_t inten; | |
265 | uint32_t int_status; | |
266 | uint32_t ev_status; | |
267 | uint32_t dbg[2]; | |
268 | uint8_t debug_status; | |
269 | uint8_t num_faulting; | |
270 | uint8_t periph_busy[PL330_PERIPH_NUM]; | |
271 | ||
272 | }; | |
273 | ||
274 | #define TYPE_PL330 "pl330" | |
8063396b | 275 | OBJECT_DECLARE_SIMPLE_TYPE(PL330State, PL330) |
06a1cea5 PC |
276 | |
277 | static const VMStateDescription vmstate_pl330 = { | |
278 | .name = "pl330", | |
830fc739 DH |
279 | .version_id = 2, |
280 | .minimum_version_id = 2, | |
06a1cea5 PC |
281 | .fields = (VMStateField[]) { |
282 | VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), | |
830fc739 DH |
283 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls, |
284 | vmstate_pl330_chan, PL330Chan), | |
59046ec2 HP |
285 | VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls), |
286 | VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls), | |
06a1cea5 PC |
287 | VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), |
288 | VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue, | |
289 | PL330Queue), | |
290 | VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue, | |
291 | PL330Queue), | |
e720677e | 292 | VMSTATE_TIMER_PTR(timer, PL330State), |
06a1cea5 PC |
293 | VMSTATE_UINT32(inten, PL330State), |
294 | VMSTATE_UINT32(int_status, PL330State), | |
295 | VMSTATE_UINT32(ev_status, PL330State), | |
296 | VMSTATE_UINT32_ARRAY(dbg, PL330State, 2), | |
297 | VMSTATE_UINT8(debug_status, PL330State), | |
298 | VMSTATE_UINT8(num_faulting, PL330State), | |
299 | VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), | |
300 | VMSTATE_END_OF_LIST() | |
301 | } | |
302 | }; | |
303 | ||
304 | typedef struct PL330InsnDesc { | |
305 | /* OPCODE of the instruction */ | |
306 | uint8_t opcode; | |
307 | /* Mask so we can select several sibling instructions, such as | |
308 | DMALD, DMALDS and DMALDB */ | |
309 | uint8_t opmask; | |
310 | /* Size of instruction in bytes */ | |
311 | uint8_t size; | |
312 | /* Interpreter */ | |
313 | void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); | |
314 | } PL330InsnDesc; | |
315 | ||
db1e7afa GR |
316 | static void pl330_hexdump(uint8_t *buf, size_t size) |
317 | { | |
318 | unsigned int b, i, len; | |
319 | char tmpbuf[80]; | |
320 | ||
321 | for (b = 0; b < size; b += 16) { | |
322 | len = size - b; | |
323 | if (len > 16) { | |
324 | len = 16; | |
325 | } | |
326 | tmpbuf[0] = '\0'; | |
327 | for (i = 0; i < len; i++) { | |
328 | if ((i % 4) == 0) { | |
329 | strcat(tmpbuf, " "); | |
330 | } | |
331 | sprintf(tmpbuf + strlen(tmpbuf), " %02x", buf[b + i]); | |
332 | } | |
333 | trace_pl330_hexdump(b, tmpbuf); | |
334 | } | |
335 | } | |
06a1cea5 PC |
336 | |
337 | /* MFIFO Implementation | |
338 | * | |
339 | * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are | |
340 | * stored in this buffer. Data is stored in BUF field, tags - in the | |
341 | * corresponding array elements of TAG field. | |
342 | */ | |
343 | ||
344 | /* Initialize queue. */ | |
345 | ||
346 | static void pl330_fifo_init(PL330Fifo *s, uint32_t size) | |
347 | { | |
348 | s->buf = g_malloc0(size); | |
349 | s->tag = g_malloc0(size); | |
350 | s->buf_size = size; | |
351 | } | |
352 | ||
353 | /* Cyclic increment */ | |
354 | ||
355 | static inline int pl330_fifo_inc(PL330Fifo *s, int x) | |
356 | { | |
357 | return (x + 1) % s->buf_size; | |
358 | } | |
359 | ||
360 | /* Number of empty bytes in MFIFO */ | |
361 | ||
362 | static inline int pl330_fifo_num_free(PL330Fifo *s) | |
363 | { | |
364 | return s->buf_size - s->num; | |
365 | } | |
366 | ||
367 | /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG. | |
368 | * Zero returned on success, PL330_FIFO_STALL if there is no enough free | |
369 | * space in MFIFO to store requested amount of data. If push was unsuccessful | |
370 | * no data is stored to MFIFO. | |
371 | */ | |
372 | ||
373 | static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) | |
374 | { | |
375 | int i; | |
376 | ||
377 | if (s->buf_size - s->num < len) { | |
378 | return PL330_FIFO_STALL; | |
379 | } | |
380 | for (i = 0; i < len; i++) { | |
381 | int push_idx = (s->head + s->num + i) % s->buf_size; | |
382 | s->buf[push_idx] = buf[i]; | |
383 | s->tag[push_idx] = tag; | |
384 | } | |
385 | s->num += len; | |
386 | return PL330_FIFO_OK; | |
387 | } | |
388 | ||
389 | /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each | |
390 | * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch | |
391 | * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was | |
392 | * unsuccessful no data is removed from MFIFO. | |
393 | */ | |
394 | ||
395 | static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) | |
396 | { | |
397 | int i; | |
398 | ||
399 | if (s->num < len) { | |
400 | return PL330_FIFO_STALL; | |
401 | } | |
402 | for (i = 0; i < len; i++) { | |
403 | if (s->tag[s->head] == tag) { | |
404 | int get_idx = (s->head + i) % s->buf_size; | |
405 | buf[i] = s->buf[get_idx]; | |
406 | } else { /* Tag mismatch - Rollback transaction */ | |
407 | return PL330_FIFO_ERR; | |
408 | } | |
409 | } | |
410 | s->head = (s->head + len) % s->buf_size; | |
411 | s->num -= len; | |
412 | return PL330_FIFO_OK; | |
413 | } | |
414 | ||
415 | /* Reset MFIFO. This completely erases all data in it. */ | |
416 | ||
417 | static inline void pl330_fifo_reset(PL330Fifo *s) | |
418 | { | |
419 | s->head = 0; | |
420 | s->num = 0; | |
421 | } | |
422 | ||
423 | /* Return tag of the first byte stored in MFIFO. If MFIFO is empty | |
424 | * PL330_UNTAGGED is returned. | |
425 | */ | |
426 | ||
427 | static inline uint8_t pl330_fifo_tag(PL330Fifo *s) | |
428 | { | |
429 | return (!s->num) ? PL330_UNTAGGED : s->tag[s->head]; | |
430 | } | |
431 | ||
432 | /* Returns non-zero if tag TAG is present in fifo or zero otherwise */ | |
433 | ||
434 | static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) | |
435 | { | |
436 | int i, n; | |
437 | ||
438 | i = s->head; | |
439 | for (n = 0; n < s->num; n++) { | |
440 | if (s->tag[i] == tag) { | |
441 | return 1; | |
442 | } | |
443 | i = pl330_fifo_inc(s, i); | |
444 | } | |
445 | return 0; | |
446 | } | |
447 | ||
448 | /* Remove all entry tagged with TAG from MFIFO */ | |
449 | ||
450 | static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) | |
451 | { | |
452 | int i, t, n; | |
453 | ||
454 | t = i = s->head; | |
455 | for (n = 0; n < s->num; n++) { | |
456 | if (s->tag[i] != tag) { | |
457 | s->buf[t] = s->buf[i]; | |
458 | s->tag[t] = s->tag[i]; | |
459 | t = pl330_fifo_inc(s, t); | |
460 | } else { | |
461 | s->num = s->num - 1; | |
462 | } | |
463 | i = pl330_fifo_inc(s, i); | |
464 | } | |
465 | } | |
466 | ||
467 | /* Read-Write Queue implementation | |
468 | * | |
469 | * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores). | |
470 | * Each instruction is described by source (for loads) or destination (for | |
471 | * stores) address ADDR, width of data to be loaded/stored LEN, number of | |
472 | * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel | |
473 | * this instruction belongs to. Queue does not store any information about | |
474 | * nature of the instruction: is it load or store. PL330 has different queues | |
475 | * for loads and stores so this is already known at the top level where it | |
476 | * matters. | |
477 | * | |
478 | * Queue works as FIFO for instructions with equivalent tags, but can issue | |
479 | * instructions with different tags in arbitrary order. SEQN field attached to | |
480 | * each instruction helps to achieve this. For each TAG queue contains | |
481 | * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to | |
482 | * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is | |
483 | * followed by SEQN=0. | |
484 | * | |
485 | * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed | |
486 | * in this case. | |
487 | */ | |
488 | ||
489 | static void pl330_queue_reset(PL330Queue *s) | |
490 | { | |
491 | int i; | |
492 | ||
493 | for (i = 0; i < s->queue_size; i++) { | |
494 | s->queue[i].tag = PL330_UNTAGGED; | |
495 | } | |
496 | } | |
497 | ||
498 | /* Initialize queue */ | |
499 | static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) | |
500 | { | |
501 | s->parent = parent; | |
502 | s->queue = g_new0(PL330QueueEntry, size); | |
503 | s->queue_size = size; | |
504 | } | |
505 | ||
506 | /* Returns pointer to an empty slot or NULL if queue is full */ | |
507 | static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s) | |
508 | { | |
509 | int i; | |
510 | ||
511 | for (i = 0; i < s->queue_size; i++) { | |
512 | if (s->queue[i].tag == PL330_UNTAGGED) { | |
513 | return &s->queue[i]; | |
514 | } | |
515 | } | |
516 | return NULL; | |
517 | } | |
518 | ||
519 | /* Put instruction in queue. | |
520 | * Return value: | |
521 | * - zero - OK | |
522 | * - non-zero - queue is full | |
523 | */ | |
524 | ||
525 | static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, | |
526 | int len, int n, bool inc, bool z, uint8_t tag) | |
527 | { | |
528 | PL330QueueEntry *entry = pl330_queue_find_empty(s); | |
529 | ||
530 | if (!entry) { | |
531 | return 1; | |
532 | } | |
533 | entry->tag = tag; | |
534 | entry->addr = addr; | |
535 | entry->len = len; | |
536 | entry->n = n; | |
537 | entry->z = z; | |
538 | entry->inc = inc; | |
539 | entry->seqn = s->parent->hi_seqn[tag]; | |
540 | s->parent->hi_seqn[tag]++; | |
541 | return 0; | |
542 | } | |
543 | ||
544 | /* Returns a pointer to queue slot containing instruction which satisfies | |
545 | * following conditions: | |
546 | * - it has valid tag value (not PL330_UNTAGGED) | |
547 | * - if enforce_seq is set it has to be issuable without violating queue | |
548 | * logic (see above) | |
549 | * - if TAG argument is not PL330_UNTAGGED this instruction has tag value | |
550 | * equivalent to the argument TAG value. | |
551 | * If such instruction cannot be found NULL is returned. | |
552 | */ | |
553 | ||
554 | static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag, | |
555 | bool enforce_seq) | |
556 | { | |
557 | int i; | |
558 | ||
559 | for (i = 0; i < s->queue_size; i++) { | |
560 | if (s->queue[i].tag != PL330_UNTAGGED) { | |
561 | if ((!enforce_seq || | |
562 | s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && | |
563 | (s->queue[i].tag == tag || tag == PL330_UNTAGGED || | |
564 | s->queue[i].z)) { | |
565 | return &s->queue[i]; | |
566 | } | |
567 | } | |
568 | } | |
569 | return NULL; | |
570 | } | |
571 | ||
572 | /* Removes instruction from queue. */ | |
573 | ||
574 | static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) | |
575 | { | |
576 | s->parent->lo_seqn[e->tag]++; | |
577 | e->tag = PL330_UNTAGGED; | |
578 | } | |
579 | ||
580 | /* Removes all instructions tagged with TAG from queue. */ | |
581 | ||
582 | static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) | |
583 | { | |
584 | int i; | |
585 | ||
586 | for (i = 0; i < s->queue_size; i++) { | |
587 | if (s->queue[i].tag == tag) { | |
588 | s->queue[i].tag = PL330_UNTAGGED; | |
589 | } | |
590 | } | |
591 | } | |
592 | ||
593 | /* DMA instruction execution engine */ | |
594 | ||
595 | /* Moves DMA channel to the FAULT state and updates it's status. */ | |
596 | ||
597 | static inline void pl330_fault(PL330Chan *ch, uint32_t flags) | |
598 | { | |
db1e7afa | 599 | trace_pl330_fault(ch, flags); |
06a1cea5 PC |
600 | ch->fault_type |= flags; |
601 | if (ch->state == pl330_chan_fault) { | |
602 | return; | |
603 | } | |
604 | ch->state = pl330_chan_fault; | |
605 | ch->parent->num_faulting++; | |
606 | if (ch->parent->num_faulting == 1) { | |
db1e7afa | 607 | trace_pl330_fault_abort(); |
06a1cea5 PC |
608 | qemu_irq_raise(ch->parent->irq_abort); |
609 | } | |
610 | } | |
611 | ||
612 | /* | |
613 | * For information about instructions see PL330 Technical Reference Manual. | |
614 | * | |
615 | * Arguments: | |
616 | * CH - channel executing the instruction | |
617 | * OPCODE - opcode | |
618 | * ARGS - array of 8-bit arguments | |
619 | * LEN - number of elements in ARGS array | |
620 | */ | |
621 | ||
c04018e9 | 622 | static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg) |
06a1cea5 | 623 | { |
c04018e9 PC |
624 | uint32_t im = (args[1] << 8) | args[0]; |
625 | if (neg) { | |
626 | im |= 0xffffu << 16; | |
627 | } | |
06a1cea5 PC |
628 | |
629 | if (ch->is_manager) { | |
630 | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); | |
631 | return; | |
632 | } | |
633 | if (ra) { | |
634 | ch->dst += im; | |
635 | } else { | |
636 | ch->src += im; | |
637 | } | |
638 | } | |
639 | ||
c04018e9 PC |
640 | static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
641 | { | |
642 | pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false); | |
643 | } | |
644 | ||
645 | static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
646 | { | |
647 | pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true); | |
648 | } | |
649 | ||
06a1cea5 PC |
650 | static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, |
651 | uint8_t *args, int len) | |
652 | { | |
653 | PL330State *s = ch->parent; | |
654 | ||
655 | if (ch->state == pl330_chan_executing && !ch->is_manager) { | |
656 | /* Wait for all transfers to complete */ | |
657 | if (pl330_fifo_has_tag(&s->fifo, ch->tag) || | |
658 | pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || | |
659 | pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { | |
660 | ||
661 | ch->stall = 1; | |
662 | return; | |
663 | } | |
664 | } | |
db1e7afa | 665 | trace_pl330_dmaend(); |
06a1cea5 PC |
666 | pl330_fifo_tagged_remove(&s->fifo, ch->tag); |
667 | pl330_queue_remove_tagged(&s->read_queue, ch->tag); | |
668 | pl330_queue_remove_tagged(&s->write_queue, ch->tag); | |
669 | ch->state = pl330_chan_stopped; | |
670 | } | |
671 | ||
672 | static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, | |
673 | uint8_t *args, int len) | |
674 | { | |
675 | uint8_t periph_id; | |
676 | ||
677 | if (args[0] & 7) { | |
678 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
679 | return; | |
680 | } | |
681 | periph_id = (args[0] >> 3) & 0x1f; | |
682 | if (periph_id >= ch->parent->num_periph_req) { | |
683 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
684 | return; | |
685 | } | |
686 | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { | |
687 | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); | |
688 | return; | |
689 | } | |
690 | /* Do nothing */ | |
691 | } | |
692 | ||
693 | static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
694 | { | |
695 | uint8_t chan_id; | |
696 | uint8_t ns; | |
697 | uint32_t pc; | |
698 | PL330Chan *s; | |
699 | ||
db1e7afa | 700 | trace_pl330_dmago(); |
06a1cea5 PC |
701 | |
702 | if (!ch->is_manager) { | |
703 | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); | |
704 | return; | |
705 | } | |
706 | ns = !!(opcode & 2); | |
707 | chan_id = args[0] & 7; | |
708 | if ((args[0] >> 3)) { | |
709 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
710 | return; | |
711 | } | |
712 | if (chan_id >= ch->parent->num_chnls) { | |
713 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
714 | return; | |
715 | } | |
716 | pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | | |
717 | (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); | |
718 | if (ch->parent->chan[chan_id].state != pl330_chan_stopped) { | |
719 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
720 | return; | |
721 | } | |
722 | if (ch->ns && !ns) { | |
723 | pl330_fault(ch, PL330_FAULT_DMAGO_ERR); | |
724 | return; | |
725 | } | |
726 | s = &ch->parent->chan[chan_id]; | |
727 | s->ns = ns; | |
728 | s->pc = pc; | |
729 | s->state = pl330_chan_executing; | |
730 | } | |
731 | ||
732 | static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
733 | { | |
734 | uint8_t bs = opcode & 3; | |
735 | uint32_t size, num; | |
736 | bool inc; | |
737 | ||
738 | if (bs == 2) { | |
739 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
740 | return; | |
741 | } | |
742 | if ((bs == 1 && ch->request_flag == PL330_BURST) || | |
743 | (bs == 3 && ch->request_flag == PL330_SINGLE)) { | |
744 | /* Perform NOP */ | |
745 | return; | |
746 | } | |
747 | if (bs == 1 && ch->request_flag == PL330_SINGLE) { | |
748 | num = 1; | |
749 | } else { | |
750 | num = ((ch->control >> 4) & 0xf) + 1; | |
751 | } | |
752 | size = (uint32_t)1 << ((ch->control >> 1) & 0x7); | |
753 | inc = !!(ch->control & 1); | |
754 | ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, | |
755 | size, num, inc, 0, ch->tag); | |
756 | if (!ch->stall) { | |
db1e7afa | 757 | trace_pl330_dmald(ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); |
06a1cea5 PC |
758 | ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; |
759 | } | |
760 | } | |
761 | ||
762 | static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
763 | { | |
764 | uint8_t periph_id; | |
765 | ||
766 | if (args[0] & 7) { | |
767 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
768 | return; | |
769 | } | |
770 | periph_id = (args[0] >> 3) & 0x1f; | |
771 | if (periph_id >= ch->parent->num_periph_req) { | |
772 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
773 | return; | |
774 | } | |
775 | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { | |
776 | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); | |
777 | return; | |
778 | } | |
779 | pl330_dmald(ch, opcode, args, len); | |
780 | } | |
781 | ||
782 | static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
783 | { | |
784 | uint8_t lc = (opcode & 2) >> 1; | |
785 | ||
786 | ch->lc[lc] = args[0]; | |
787 | } | |
788 | ||
789 | static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
790 | { | |
791 | if (ch->state == pl330_chan_fault || | |
792 | ch->state == pl330_chan_fault_completing) { | |
793 | /* This is the only way for a channel to leave the faulting state */ | |
794 | ch->fault_type = 0; | |
795 | ch->parent->num_faulting--; | |
796 | if (ch->parent->num_faulting == 0) { | |
db1e7afa | 797 | trace_pl330_dmakill(); |
06a1cea5 PC |
798 | qemu_irq_lower(ch->parent->irq_abort); |
799 | } | |
800 | } | |
801 | ch->state = pl330_chan_killing; | |
802 | pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); | |
803 | pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); | |
804 | pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); | |
805 | ch->state = pl330_chan_stopped; | |
806 | } | |
807 | ||
808 | static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, | |
809 | uint8_t *args, int len) | |
810 | { | |
811 | uint8_t nf = (opcode & 0x10) >> 4; | |
812 | uint8_t bs = opcode & 3; | |
813 | uint8_t lc = (opcode & 4) >> 2; | |
814 | ||
db1e7afa GR |
815 | trace_pl330_dmalpend(nf, bs, lc, ch->lc[lc], ch->request_flag); |
816 | ||
06a1cea5 PC |
817 | if (bs == 2) { |
818 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
819 | return; | |
820 | } | |
821 | if ((bs == 1 && ch->request_flag == PL330_BURST) || | |
822 | (bs == 3 && ch->request_flag == PL330_SINGLE)) { | |
823 | /* Perform NOP */ | |
824 | return; | |
825 | } | |
826 | if (!nf || ch->lc[lc]) { | |
827 | if (nf) { | |
828 | ch->lc[lc]--; | |
829 | } | |
db1e7afa | 830 | trace_pl330_dmalpiter(); |
06a1cea5 PC |
831 | ch->pc -= args[0]; |
832 | ch->pc -= len + 1; | |
833 | /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */ | |
834 | } else { | |
db1e7afa | 835 | trace_pl330_dmalpfallthrough(); |
06a1cea5 PC |
836 | } |
837 | } | |
838 | ||
839 | ||
840 | static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
841 | { | |
842 | uint8_t rd = args[0] & 7; | |
843 | uint32_t im; | |
844 | ||
845 | if ((args[0] >> 3)) { | |
846 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
847 | return; | |
848 | } | |
849 | im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | | |
850 | (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); | |
851 | switch (rd) { | |
852 | case 0: | |
853 | ch->src = im; | |
854 | break; | |
855 | case 1: | |
856 | ch->control = im; | |
857 | break; | |
858 | case 2: | |
859 | ch->dst = im; | |
860 | break; | |
861 | default: | |
862 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
863 | return; | |
864 | } | |
865 | } | |
866 | ||
867 | static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, | |
868 | uint8_t *args, int len) | |
869 | { | |
870 | /* NOP is NOP. */ | |
871 | } | |
872 | ||
873 | static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
874 | { | |
875 | if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { | |
876 | ch->state = pl330_chan_at_barrier; | |
877 | ch->stall = 1; | |
878 | return; | |
879 | } else { | |
880 | ch->state = pl330_chan_executing; | |
881 | } | |
882 | } | |
883 | ||
884 | static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
885 | { | |
886 | uint8_t ev_id; | |
887 | ||
888 | if (args[0] & 7) { | |
889 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
890 | return; | |
891 | } | |
892 | ev_id = (args[0] >> 3) & 0x1f; | |
893 | if (ev_id >= ch->parent->num_events) { | |
894 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
895 | return; | |
896 | } | |
897 | if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { | |
898 | pl330_fault(ch, PL330_FAULT_EVENT_ERR); | |
899 | return; | |
900 | } | |
901 | if (ch->parent->inten & (1 << ev_id)) { | |
902 | ch->parent->int_status |= (1 << ev_id); | |
db1e7afa | 903 | trace_pl330_dmasev_evirq(ev_id); |
06a1cea5 | 904 | qemu_irq_raise(ch->parent->irq[ev_id]); |
06a1cea5 | 905 | } |
db1e7afa | 906 | trace_pl330_dmasev_event(ev_id); |
fd7f8a99 | 907 | ch->parent->ev_status |= (1 << ev_id); |
06a1cea5 PC |
908 | } |
909 | ||
910 | static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) | |
911 | { | |
912 | uint8_t bs = opcode & 3; | |
913 | uint32_t size, num; | |
914 | bool inc; | |
915 | ||
916 | if (bs == 2) { | |
917 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
918 | return; | |
919 | } | |
920 | if ((bs == 1 && ch->request_flag == PL330_BURST) || | |
921 | (bs == 3 && ch->request_flag == PL330_SINGLE)) { | |
922 | /* Perform NOP */ | |
923 | return; | |
924 | } | |
925 | num = ((ch->control >> 18) & 0xf) + 1; | |
926 | size = (uint32_t)1 << ((ch->control >> 15) & 0x7); | |
927 | inc = !!((ch->control >> 14) & 1); | |
928 | ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, | |
929 | size, num, inc, 0, ch->tag); | |
930 | if (!ch->stall) { | |
db1e7afa | 931 | trace_pl330_dmast(ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); |
06a1cea5 PC |
932 | ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; |
933 | } | |
934 | } | |
935 | ||
936 | static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, | |
937 | uint8_t *args, int len) | |
938 | { | |
939 | uint8_t periph_id; | |
940 | ||
941 | if (args[0] & 7) { | |
942 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
943 | return; | |
944 | } | |
945 | periph_id = (args[0] >> 3) & 0x1f; | |
946 | if (periph_id >= ch->parent->num_periph_req) { | |
947 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
948 | return; | |
949 | } | |
950 | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { | |
951 | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); | |
952 | return; | |
953 | } | |
954 | pl330_dmast(ch, opcode, args, len); | |
955 | } | |
956 | ||
957 | static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, | |
958 | uint8_t *args, int len) | |
959 | { | |
960 | uint32_t size, num; | |
961 | bool inc; | |
962 | ||
963 | num = ((ch->control >> 18) & 0xf) + 1; | |
964 | size = (uint32_t)1 << ((ch->control >> 15) & 0x7); | |
965 | inc = !!((ch->control >> 14) & 1); | |
966 | ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, | |
967 | size, num, inc, 1, ch->tag); | |
968 | if (inc) { | |
969 | ch->dst += size * num; | |
970 | } | |
971 | } | |
972 | ||
973 | static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, | |
974 | uint8_t *args, int len) | |
975 | { | |
976 | uint8_t ev_id; | |
977 | int i; | |
978 | ||
979 | if (args[0] & 5) { | |
980 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
981 | return; | |
982 | } | |
983 | ev_id = (args[0] >> 3) & 0x1f; | |
984 | if (ev_id >= ch->parent->num_events) { | |
985 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
986 | return; | |
987 | } | |
988 | if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { | |
989 | pl330_fault(ch, PL330_FAULT_EVENT_ERR); | |
990 | return; | |
991 | } | |
992 | ch->wakeup = ev_id; | |
993 | ch->state = pl330_chan_waiting_event; | |
994 | if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { | |
995 | ch->state = pl330_chan_executing; | |
996 | /* If anyone else is currently waiting on the same event, let them | |
997 | * clear the ev_status so they pick up event as well | |
998 | */ | |
999 | for (i = 0; i < ch->parent->num_chnls; ++i) { | |
1000 | PL330Chan *peer = &ch->parent->chan[i]; | |
1001 | if (peer->state == pl330_chan_waiting_event && | |
1002 | peer->wakeup == ev_id) { | |
1003 | return; | |
1004 | } | |
1005 | } | |
1006 | ch->parent->ev_status &= ~(1 << ev_id); | |
db1e7afa | 1007 | trace_pl330_dmawfe(ev_id); |
06a1cea5 PC |
1008 | } else { |
1009 | ch->stall = 1; | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, | |
1014 | uint8_t *args, int len) | |
1015 | { | |
1016 | uint8_t bs = opcode & 3; | |
1017 | uint8_t periph_id; | |
1018 | ||
1019 | if (args[0] & 7) { | |
1020 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
1021 | return; | |
1022 | } | |
1023 | periph_id = (args[0] >> 3) & 0x1f; | |
1024 | if (periph_id >= ch->parent->num_periph_req) { | |
1025 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
1026 | return; | |
1027 | } | |
1028 | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { | |
1029 | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); | |
1030 | return; | |
1031 | } | |
1032 | switch (bs) { | |
1033 | case 0: /* S */ | |
1034 | ch->request_flag = PL330_SINGLE; | |
1035 | ch->wfp_sbp = 0; | |
1036 | break; | |
1037 | case 1: /* P */ | |
1038 | ch->request_flag = PL330_BURST; | |
1039 | ch->wfp_sbp = 2; | |
1040 | break; | |
1041 | case 2: /* B */ | |
1042 | ch->request_flag = PL330_BURST; | |
1043 | ch->wfp_sbp = 1; | |
1044 | break; | |
1045 | default: | |
1046 | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); | |
1047 | return; | |
1048 | } | |
1049 | ||
1050 | if (ch->parent->periph_busy[periph_id]) { | |
1051 | ch->state = pl330_chan_waiting_periph; | |
1052 | ch->stall = 1; | |
1053 | } else if (ch->state == pl330_chan_waiting_periph) { | |
1054 | ch->state = pl330_chan_executing; | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, | |
1059 | uint8_t *args, int len) | |
1060 | { | |
1061 | if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { | |
1062 | ch->state = pl330_chan_at_barrier; | |
1063 | ch->stall = 1; | |
1064 | return; | |
1065 | } else { | |
1066 | ch->state = pl330_chan_executing; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /* NULL terminated array of the instruction descriptions. */ | |
1071 | static const PL330InsnDesc insn_desc[] = { | |
1072 | { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, | |
c04018e9 | 1073 | { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, }, |
06a1cea5 PC |
1074 | { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, |
1075 | { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, | |
1076 | { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, | |
1077 | { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, | |
1078 | { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, | |
1079 | { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, | |
1080 | /* dmastp must be before dmalpend in this list, because their maps | |
1081 | * are overlapping | |
1082 | */ | |
1083 | { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, | |
1084 | { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, | |
1085 | { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, | |
1086 | { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, | |
1087 | { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, | |
1088 | { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, | |
1089 | { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, | |
1090 | { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, | |
1091 | { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, | |
1092 | { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, | |
1093 | { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, | |
1094 | { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, | |
1095 | { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } | |
1096 | }; | |
1097 | ||
1098 | /* Instructions which can be issued via debug registers. */ | |
1099 | static const PL330InsnDesc debug_insn_desc[] = { | |
1100 | { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, | |
1101 | { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, | |
1102 | { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, | |
1103 | { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } | |
1104 | }; | |
1105 | ||
1106 | static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) | |
1107 | { | |
1108 | uint8_t opcode; | |
1109 | int i; | |
1110 | ||
df32fd1c | 1111 | dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); |
06a1cea5 PC |
1112 | for (i = 0; insn_desc[i].size; i++) { |
1113 | if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { | |
1114 | return &insn_desc[i]; | |
1115 | } | |
1116 | } | |
1117 | return NULL; | |
1118 | } | |
1119 | ||
1120 | static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) | |
1121 | { | |
1122 | uint8_t buf[PL330_INSN_MAXSIZE]; | |
1123 | ||
1124 | assert(insn->size <= PL330_INSN_MAXSIZE); | |
df32fd1c | 1125 | dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); |
06a1cea5 PC |
1126 | insn->exec(ch, buf[0], &buf[1], insn->size - 1); |
1127 | } | |
1128 | ||
1129 | static inline void pl330_update_pc(PL330Chan *ch, | |
1130 | const PL330InsnDesc *insn) | |
1131 | { | |
1132 | ch->pc += insn->size; | |
1133 | } | |
1134 | ||
1135 | /* Try to execute current instruction in channel CH. Number of executed | |
1136 | instructions is returned (0 or 1). */ | |
1137 | static int pl330_chan_exec(PL330Chan *ch) | |
1138 | { | |
1139 | const PL330InsnDesc *insn; | |
1140 | ||
1141 | if (ch->state != pl330_chan_executing && | |
1142 | ch->state != pl330_chan_waiting_periph && | |
1143 | ch->state != pl330_chan_at_barrier && | |
1144 | ch->state != pl330_chan_waiting_event) { | |
06a1cea5 PC |
1145 | return 0; |
1146 | } | |
1147 | ch->stall = 0; | |
1148 | insn = pl330_fetch_insn(ch); | |
1149 | if (!insn) { | |
db1e7afa | 1150 | trace_pl330_chan_exec_undef(); |
06a1cea5 PC |
1151 | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); |
1152 | return 0; | |
1153 | } | |
1154 | pl330_exec_insn(ch, insn); | |
1155 | if (!ch->stall) { | |
1156 | pl330_update_pc(ch, insn); | |
1157 | ch->watchdog_timer = 0; | |
1158 | return 1; | |
1159 | /* WDT only active in exec state */ | |
1160 | } else if (ch->state == pl330_chan_executing) { | |
1161 | ch->watchdog_timer++; | |
1162 | if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) { | |
1163 | pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); | |
1164 | } | |
1165 | } | |
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | /* Try to execute 1 instruction in each channel, one instruction from read | |
1170 | queue and one instruction from write queue. Number of successfully executed | |
1171 | instructions is returned. */ | |
1172 | static int pl330_exec_cycle(PL330Chan *channel) | |
1173 | { | |
1174 | PL330State *s = channel->parent; | |
1175 | PL330QueueEntry *q; | |
1176 | int i; | |
1177 | int num_exec = 0; | |
1178 | int fifo_res = 0; | |
1179 | uint8_t buf[PL330_MAX_BURST_LEN]; | |
1180 | ||
1181 | /* Execute one instruction in each channel */ | |
1182 | num_exec += pl330_chan_exec(channel); | |
1183 | ||
1184 | /* Execute one instruction from read queue */ | |
1185 | q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true); | |
1186 | if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { | |
1187 | int len = q->len - (q->addr & (q->len - 1)); | |
1188 | ||
df32fd1c | 1189 | dma_memory_read(&address_space_memory, q->addr, buf, len); |
db1e7afa GR |
1190 | trace_pl330_exec_cycle(q->addr, len); |
1191 | if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { | |
1192 | pl330_hexdump(buf, len); | |
06a1cea5 PC |
1193 | } |
1194 | fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); | |
1195 | if (fifo_res == PL330_FIFO_OK) { | |
1196 | if (q->inc) { | |
1197 | q->addr += len; | |
1198 | } | |
1199 | q->n--; | |
1200 | if (!q->n) { | |
1201 | pl330_queue_remove_insn(&s->read_queue, q); | |
1202 | } | |
1203 | num_exec++; | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | /* Execute one instruction from write queue. */ | |
1208 | q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true); | |
1209 | if (q != NULL) { | |
1210 | int len = q->len - (q->addr & (q->len - 1)); | |
1211 | ||
1212 | if (q->z) { | |
1213 | for (i = 0; i < len; i++) { | |
1214 | buf[i] = 0; | |
1215 | } | |
1216 | } else { | |
1217 | fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); | |
1218 | } | |
1219 | if (fifo_res == PL330_FIFO_OK || q->z) { | |
df32fd1c | 1220 | dma_memory_write(&address_space_memory, q->addr, buf, len); |
db1e7afa GR |
1221 | trace_pl330_exec_cycle(q->addr, len); |
1222 | if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { | |
1223 | pl330_hexdump(buf, len); | |
06a1cea5 PC |
1224 | } |
1225 | if (q->inc) { | |
1226 | q->addr += len; | |
1227 | } | |
1228 | num_exec++; | |
1229 | } else if (fifo_res == PL330_FIFO_STALL) { | |
1230 | pl330_fault(&channel->parent->chan[q->tag], | |
1231 | PL330_FAULT_FIFOEMPTY_ERR); | |
1232 | } | |
1233 | q->n--; | |
1234 | if (!q->n) { | |
1235 | pl330_queue_remove_insn(&s->write_queue, q); | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | return num_exec; | |
1240 | } | |
1241 | ||
1242 | static int pl330_exec_channel(PL330Chan *channel) | |
1243 | { | |
1244 | int insr_exec = 0; | |
1245 | ||
1246 | /* TODO: Is it all right to execute everything or should we do per-cycle | |
1247 | simulation? */ | |
1248 | while (pl330_exec_cycle(channel)) { | |
1249 | insr_exec++; | |
1250 | } | |
1251 | ||
1252 | /* Detect deadlock */ | |
1253 | if (channel->state == pl330_chan_executing) { | |
1254 | pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); | |
1255 | } | |
1256 | /* Situation when one of the queues has deadlocked but all channels | |
1257 | * have finished their programs should be impossible. | |
1258 | */ | |
1259 | ||
1260 | return insr_exec; | |
1261 | } | |
1262 | ||
1263 | static inline void pl330_exec(PL330State *s) | |
1264 | { | |
06a1cea5 | 1265 | int i, insr_exec; |
db1e7afa | 1266 | trace_pl330_exec(); |
06a1cea5 PC |
1267 | do { |
1268 | insr_exec = pl330_exec_channel(&s->manager); | |
1269 | ||
1270 | for (i = 0; i < s->num_chnls; i++) { | |
1271 | insr_exec += pl330_exec_channel(&s->chan[i]); | |
1272 | } | |
1273 | } while (insr_exec); | |
1274 | } | |
1275 | ||
1276 | static void pl330_exec_cycle_timer(void *opaque) | |
1277 | { | |
1278 | PL330State *s = (PL330State *)opaque; | |
1279 | pl330_exec(s); | |
1280 | } | |
1281 | ||
1282 | /* Stop or restore dma operations */ | |
1283 | ||
1284 | static void pl330_dma_stop_irq(void *opaque, int irq, int level) | |
1285 | { | |
1286 | PL330State *s = (PL330State *)opaque; | |
1287 | ||
1288 | if (s->periph_busy[irq] != level) { | |
1289 | s->periph_busy[irq] = level; | |
bc72ad67 | 1290 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
06a1cea5 PC |
1291 | } |
1292 | } | |
1293 | ||
1294 | static void pl330_debug_exec(PL330State *s) | |
1295 | { | |
1296 | uint8_t args[5]; | |
1297 | uint8_t opcode; | |
1298 | uint8_t chan_id; | |
1299 | int i; | |
1300 | PL330Chan *ch; | |
1301 | const PL330InsnDesc *insn; | |
1302 | ||
1303 | s->debug_status = 1; | |
1304 | chan_id = (s->dbg[0] >> 8) & 0x07; | |
1305 | opcode = (s->dbg[0] >> 16) & 0xff; | |
1306 | args[0] = (s->dbg[0] >> 24) & 0xff; | |
1307 | args[1] = (s->dbg[1] >> 0) & 0xff; | |
1308 | args[2] = (s->dbg[1] >> 8) & 0xff; | |
1309 | args[3] = (s->dbg[1] >> 16) & 0xff; | |
1310 | args[4] = (s->dbg[1] >> 24) & 0xff; | |
db1e7afa | 1311 | trace_pl330_debug_exec(chan_id); |
06a1cea5 PC |
1312 | if (s->dbg[0] & 1) { |
1313 | ch = &s->chan[chan_id]; | |
1314 | } else { | |
1315 | ch = &s->manager; | |
1316 | } | |
1317 | insn = NULL; | |
1318 | for (i = 0; debug_insn_desc[i].size; i++) { | |
1319 | if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) { | |
1320 | insn = &debug_insn_desc[i]; | |
1321 | } | |
1322 | } | |
1323 | if (!insn) { | |
1324 | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); | |
1325 | return ; | |
1326 | } | |
1327 | ch->stall = 0; | |
1328 | insn->exec(ch, opcode, args, insn->size - 1); | |
1329 | if (ch->fault_type) { | |
1330 | ch->fault_type |= PL330_FAULT_DBG_INSTR; | |
1331 | } | |
1332 | if (ch->stall) { | |
db1e7afa | 1333 | trace_pl330_debug_exec_stall(); |
06a1cea5 PC |
1334 | qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " |
1335 | "implemented\n"); | |
1336 | } | |
1337 | s->debug_status = 0; | |
1338 | } | |
1339 | ||
1340 | /* IOMEM mapped registers */ | |
1341 | ||
1342 | static void pl330_iomem_write(void *opaque, hwaddr offset, | |
1343 | uint64_t value, unsigned size) | |
1344 | { | |
1345 | PL330State *s = (PL330State *) opaque; | |
024c6e2e | 1346 | int i; |
06a1cea5 | 1347 | |
db1e7afa | 1348 | trace_pl330_iomem_write((unsigned)offset, (unsigned)value); |
06a1cea5 PC |
1349 | |
1350 | switch (offset) { | |
1351 | case PL330_REG_INTEN: | |
1352 | s->inten = value; | |
1353 | break; | |
1354 | case PL330_REG_INTCLR: | |
1355 | for (i = 0; i < s->num_events; i++) { | |
1356 | if (s->int_status & s->inten & value & (1 << i)) { | |
db1e7afa | 1357 | trace_pl330_iomem_write_clr(i); |
06a1cea5 PC |
1358 | qemu_irq_lower(s->irq[i]); |
1359 | } | |
1360 | } | |
1361 | s->ev_status &= ~(value & s->inten); | |
1362 | s->int_status &= ~(value & s->inten); | |
1363 | break; | |
1364 | case PL330_REG_DBGCMD: | |
1365 | if ((value & 3) == 0) { | |
1366 | pl330_debug_exec(s); | |
1367 | pl330_exec(s); | |
1368 | } else { | |
1369 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " | |
1370 | "for offset " TARGET_FMT_plx "\n", (unsigned)value, | |
1371 | offset); | |
1372 | } | |
1373 | break; | |
1374 | case PL330_REG_DBGINST0: | |
06a1cea5 PC |
1375 | s->dbg[0] = value; |
1376 | break; | |
1377 | case PL330_REG_DBGINST1: | |
06a1cea5 PC |
1378 | s->dbg[1] = value; |
1379 | break; | |
1380 | default: | |
1381 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx | |
1382 | "\n", offset); | |
1383 | break; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | static inline uint32_t pl330_iomem_read_imp(void *opaque, | |
1388 | hwaddr offset) | |
1389 | { | |
1390 | PL330State *s = (PL330State *)opaque; | |
1391 | int chan_id; | |
1392 | int i; | |
1393 | uint32_t res; | |
1394 | ||
1395 | if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { | |
1396 | return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; | |
1397 | } | |
1398 | if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { | |
1399 | return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; | |
1400 | } | |
1401 | if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) { | |
1402 | offset -= PL330_REG_CHANCTRL; | |
1403 | chan_id = offset >> 5; | |
1404 | if (chan_id >= s->num_chnls) { | |
1405 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " | |
1406 | TARGET_FMT_plx "\n", offset); | |
1407 | return 0; | |
1408 | } | |
1409 | switch (offset & 0x1f) { | |
1410 | case 0x00: | |
1411 | return s->chan[chan_id].src; | |
1412 | case 0x04: | |
1413 | return s->chan[chan_id].dst; | |
1414 | case 0x08: | |
1415 | return s->chan[chan_id].control; | |
1416 | case 0x0C: | |
1417 | return s->chan[chan_id].lc[0]; | |
1418 | case 0x10: | |
1419 | return s->chan[chan_id].lc[1]; | |
1420 | default: | |
1421 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " | |
1422 | TARGET_FMT_plx "\n", offset); | |
1423 | return 0; | |
1424 | } | |
1425 | } | |
1426 | if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { | |
1427 | offset -= PL330_REG_CSR_BASE; | |
1428 | chan_id = offset >> 3; | |
1429 | if (chan_id >= s->num_chnls) { | |
1430 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " | |
1431 | TARGET_FMT_plx "\n", offset); | |
1432 | return 0; | |
1433 | } | |
1434 | switch ((offset >> 2) & 1) { | |
1435 | case 0x0: | |
1436 | res = (s->chan[chan_id].ns << 21) | | |
1437 | (s->chan[chan_id].wakeup << 4) | | |
1438 | (s->chan[chan_id].state) | | |
1439 | (s->chan[chan_id].wfp_sbp << 14); | |
1440 | return res; | |
1441 | case 0x1: | |
1442 | return s->chan[chan_id].pc; | |
1443 | default: | |
1444 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); | |
1445 | return 0; | |
1446 | } | |
1447 | } | |
1448 | if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { | |
1449 | offset -= PL330_REG_FTR_BASE; | |
1450 | chan_id = offset >> 2; | |
1451 | if (chan_id >= s->num_chnls) { | |
1452 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " | |
1453 | TARGET_FMT_plx "\n", offset); | |
1454 | return 0; | |
1455 | } | |
1456 | return s->chan[chan_id].fault_type; | |
1457 | } | |
1458 | switch (offset) { | |
1459 | case PL330_REG_DSR: | |
1460 | return (s->manager.ns << 9) | (s->manager.wakeup << 4) | | |
1461 | (s->manager.state & 0xf); | |
1462 | case PL330_REG_DPC: | |
1463 | return s->manager.pc; | |
1464 | case PL330_REG_INTEN: | |
1465 | return s->inten; | |
1466 | case PL330_REG_INT_EVENT_RIS: | |
1467 | return s->ev_status; | |
1468 | case PL330_REG_INTMIS: | |
1469 | return s->int_status; | |
1470 | case PL330_REG_INTCLR: | |
1471 | /* Documentation says that we can't read this register | |
1472 | * but linux kernel does it | |
1473 | */ | |
1474 | return 0; | |
1475 | case PL330_REG_FSRD: | |
1476 | return s->manager.state ? 1 : 0; | |
1477 | case PL330_REG_FSRC: | |
1478 | res = 0; | |
1479 | for (i = 0; i < s->num_chnls; i++) { | |
1480 | if (s->chan[i].state == pl330_chan_fault || | |
1481 | s->chan[i].state == pl330_chan_fault_completing) { | |
1482 | res |= 1 << i; | |
1483 | } | |
1484 | } | |
1485 | return res; | |
1486 | case PL330_REG_FTRD: | |
1487 | return s->manager.fault_type; | |
1488 | case PL330_REG_DBGSTATUS: | |
1489 | return s->debug_status; | |
1490 | default: | |
1491 | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " | |
1492 | TARGET_FMT_plx "\n", offset); | |
1493 | } | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, | |
1498 | unsigned size) | |
1499 | { | |
c3143ba8 | 1500 | uint32_t ret = pl330_iomem_read_imp(opaque, offset); |
db1e7afa | 1501 | trace_pl330_iomem_read((uint32_t)offset, ret); |
06a1cea5 PC |
1502 | return ret; |
1503 | } | |
1504 | ||
1505 | static const MemoryRegionOps pl330_ops = { | |
1506 | .read = pl330_iomem_read, | |
1507 | .write = pl330_iomem_write, | |
1508 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1509 | .impl = { | |
1510 | .min_access_size = 4, | |
1511 | .max_access_size = 4, | |
1512 | } | |
1513 | }; | |
1514 | ||
1515 | /* Controller logic and initialization */ | |
1516 | ||
1517 | static void pl330_chan_reset(PL330Chan *ch) | |
1518 | { | |
1519 | ch->src = 0; | |
1520 | ch->dst = 0; | |
1521 | ch->pc = 0; | |
1522 | ch->state = pl330_chan_stopped; | |
1523 | ch->watchdog_timer = 0; | |
1524 | ch->stall = 0; | |
1525 | ch->control = 0; | |
1526 | ch->status = 0; | |
1527 | ch->fault_type = 0; | |
1528 | } | |
1529 | ||
1530 | static void pl330_reset(DeviceState *d) | |
1531 | { | |
1532 | int i; | |
1533 | PL330State *s = PL330(d); | |
1534 | ||
1535 | s->inten = 0; | |
1536 | s->int_status = 0; | |
1537 | s->ev_status = 0; | |
1538 | s->debug_status = 0; | |
1539 | s->num_faulting = 0; | |
1540 | s->manager.ns = s->mgr_ns_at_rst; | |
1541 | pl330_fifo_reset(&s->fifo); | |
1542 | pl330_queue_reset(&s->read_queue); | |
1543 | pl330_queue_reset(&s->write_queue); | |
1544 | ||
1545 | for (i = 0; i < s->num_chnls; i++) { | |
1546 | pl330_chan_reset(&s->chan[i]); | |
1547 | } | |
1548 | for (i = 0; i < s->num_periph_req; i++) { | |
1549 | s->periph_busy[i] = 0; | |
1550 | } | |
1551 | ||
bc72ad67 | 1552 | timer_del(s->timer); |
06a1cea5 PC |
1553 | } |
1554 | ||
1555 | static void pl330_realize(DeviceState *dev, Error **errp) | |
1556 | { | |
1557 | int i; | |
1558 | PL330State *s = PL330(dev); | |
1559 | ||
1560 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); | |
3eadad55 PB |
1561 | memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s, |
1562 | "dma", PL330_IOMEM_SIZE); | |
06a1cea5 PC |
1563 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
1564 | ||
bc72ad67 | 1565 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s); |
06a1cea5 PC |
1566 | |
1567 | s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | | |
1568 | (s->num_periph_req > 0 ? 1 : 0) | | |
1569 | ((s->num_chnls - 1) & 0x7) << 4 | | |
1570 | ((s->num_periph_req - 1) & 0x1f) << 12 | | |
1571 | ((s->num_events - 1) & 0x1f) << 17; | |
1572 | ||
1573 | switch (s->i_cache_len) { | |
1574 | case (4): | |
1575 | s->cfg[1] |= 2; | |
1576 | break; | |
1577 | case (8): | |
1578 | s->cfg[1] |= 3; | |
1579 | break; | |
1580 | case (16): | |
1581 | s->cfg[1] |= 4; | |
1582 | break; | |
1583 | case (32): | |
1584 | s->cfg[1] |= 5; | |
1585 | break; | |
1586 | default: | |
0c267a6b | 1587 | error_setg(errp, "Bad value for i-cache_len property: %" PRIx8, |
06a1cea5 PC |
1588 | s->i_cache_len); |
1589 | return; | |
1590 | } | |
1591 | s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; | |
1592 | ||
1593 | s->chan = g_new0(PL330Chan, s->num_chnls); | |
1594 | s->hi_seqn = g_new0(uint8_t, s->num_chnls); | |
1595 | s->lo_seqn = g_new0(uint8_t, s->num_chnls); | |
1596 | for (i = 0; i < s->num_chnls; i++) { | |
1597 | s->chan[i].parent = s; | |
1598 | s->chan[i].tag = (uint8_t)i; | |
1599 | } | |
1600 | s->manager.parent = s; | |
1601 | s->manager.tag = s->num_chnls; | |
1602 | s->manager.is_manager = true; | |
1603 | ||
1604 | s->irq = g_new0(qemu_irq, s->num_events); | |
1605 | for (i = 0; i < s->num_events; i++) { | |
1606 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); | |
1607 | } | |
1608 | ||
1609 | qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); | |
1610 | ||
1611 | switch (s->data_width) { | |
1612 | case (32): | |
1613 | s->cfg[CFG_CRD] |= 0x2; | |
1614 | break; | |
1615 | case (64): | |
1616 | s->cfg[CFG_CRD] |= 0x3; | |
1617 | break; | |
1618 | case (128): | |
1619 | s->cfg[CFG_CRD] |= 0x4; | |
1620 | break; | |
1621 | default: | |
0c267a6b | 1622 | error_setg(errp, "Bad value for data_width property: %" PRIx8, |
06a1cea5 PC |
1623 | s->data_width); |
1624 | return; | |
1625 | } | |
1626 | ||
1627 | s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | | |
1628 | ((s->wr_q_dep - 1) & 0xf) << 8 | | |
1629 | ((s->rd_cap - 1) & 0x7) << 12 | | |
1630 | ((s->rd_q_dep - 1) & 0xf) << 16 | | |
1631 | ((s->data_buffer_dep - 1) & 0x1ff) << 20; | |
1632 | ||
1633 | pl330_queue_init(&s->read_queue, s->rd_q_dep, s); | |
1634 | pl330_queue_init(&s->write_queue, s->wr_q_dep, s); | |
a5ae7e39 | 1635 | pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); |
06a1cea5 PC |
1636 | } |
1637 | ||
1638 | static Property pl330_properties[] = { | |
1639 | /* CR0 */ | |
1640 | DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), | |
1641 | DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), | |
1642 | DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), | |
1643 | DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), | |
1644 | /* CR1 */ | |
1645 | DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), | |
1646 | DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), | |
1647 | /* CR2-4 */ | |
1648 | DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), | |
1649 | DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), | |
1650 | DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), | |
1651 | /* CRD */ | |
1652 | DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), | |
1653 | DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), | |
1654 | DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), | |
1655 | DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), | |
1656 | DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), | |
1657 | DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), | |
1658 | ||
1659 | DEFINE_PROP_END_OF_LIST(), | |
1660 | }; | |
1661 | ||
1662 | static void pl330_class_init(ObjectClass *klass, void *data) | |
1663 | { | |
1664 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1665 | ||
1666 | dc->realize = pl330_realize; | |
1667 | dc->reset = pl330_reset; | |
4f67d30b | 1668 | device_class_set_props(dc, pl330_properties); |
06a1cea5 PC |
1669 | dc->vmsd = &vmstate_pl330; |
1670 | } | |
1671 | ||
1672 | static const TypeInfo pl330_type_info = { | |
1673 | .name = TYPE_PL330, | |
1674 | .parent = TYPE_SYS_BUS_DEVICE, | |
1675 | .instance_size = sizeof(PL330State), | |
1676 | .class_init = pl330_class_init, | |
1677 | }; | |
1678 | ||
1679 | static void pl330_register_types(void) | |
1680 | { | |
1681 | type_register_static(&pl330_type_info); | |
1682 | } | |
1683 | ||
1684 | type_init(pl330_register_types) |