]> git.proxmox.com Git - qemu.git/blame - hw/e1000.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-arm/neon_helper.c: Use make_float32/float32_val macros
[qemu.git] / hw / e1000.c
CommitLineData
7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
1ca4d09a 33#include "sysemu.h"
7c23b892 34
7c23b892
AZ		 35#include "e1000_hw.h"
36
27124888 37#define E1000_DEBUG
7c23b892 38
27124888 39#ifdef E1000_DEBUG
7c23b892
AZ		 40enum {
41 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
42 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
43 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
44 DEBUG_RXFILTER, DEBUG_NOTYET,
45};
46#define DBGBIT(x) (1<<DEBUG_##x)
47static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
48
6c7f4b47 49#define DBGOUT(what, fmt, ...) do { \
7c23b892 50 if (debugflags & DBGBIT(what)) \
6c7f4b47 51 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 52 } while (0)
53#else
6c7f4b47 54#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 55#endif
56
57#define IOPORT_SIZE 0x40
e94bbefe 58#define PNPMMIO_SIZE 0x20000
78aeb23e 59#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
7c23b892
AZ		 60
61/*
62 * HW models:
63 * E1000_DEV_ID_82540EM works with Windows and Linux
64 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
65 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
66 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
67 * Others never tested
68 */
69enum { E1000_DEVID = E1000_DEV_ID_82540EM };
70
71/*
72 * May need to specify additional MAC-to-PHY entries --
73 * Intel's Windows driver refuses to initialize unless they match
74 */
75enum {
76 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
77 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
78 /* default to E1000_DEV_ID_82540EM */ 0xc20
79};
80
81typedef struct E1000State_st {
82 PCIDevice dev;
a03e2aec 83 NICState *nic;
fbdaa002 84 NICConf conf;
7c23b892
AZ		 85 int mmio_index;
86
87 uint32_t mac_reg[0x8000];
88 uint16_t phy_reg[0x20];
89 uint16_t eeprom_data[64];
90
91 uint32_t rxbuf_size;
92 uint32_t rxbuf_min_shift;
93 int check_rxov;
94 struct e1000_tx {
95 unsigned char header[256];
8f2e8d1f 96 unsigned char vlan_header[4];
b10fec9b 97 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 98 unsigned char vlan[4];
7c23b892
AZ		 99 unsigned char data[0x10000];
100 uint16_t size;
101 unsigned char sum_needed;
8f2e8d1f 102 unsigned char vlan_needed;
7c23b892
AZ		 103 uint8_t ipcss;
104 uint8_t ipcso;
105 uint16_t ipcse;
106 uint8_t tucss;
107 uint8_t tucso;
108 uint16_t tucse;
109 uint8_t hdr_len;
110 uint16_t mss;
111 uint32_t paylen;
112 uint16_t tso_frames;
113 char tse;
b6c4f71f
BS		 114 int8_t ip;
115 int8_t tcp;
1b0009db 116 char cptse; // current packet tse bit
7c23b892
AZ		 117 } tx;
118
119 struct {
120 uint32_t val_in; // shifted in from guest driver
121 uint16_t bitnum_in;
122 uint16_t bitnum_out;
123 uint16_t reading;
124 uint32_t old_eecd;
125 } eecd_state;
126} E1000State;
127
128#define defreg(x) x = (E1000_##x>>2)
129enum {
130 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
131 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
132 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
133 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
134 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
135 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
136 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
137 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
138 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 139 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
140 defreg(VET),
7c23b892
AZ		 141};
142
143enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 144static const char phy_regcap[0x20] = {
7c23b892
AZ		 145 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
146 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
147 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
148 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
149 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 150 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 151};
152
153static void
6e355d90
IY		 154ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
155 pcibus_t size, int type)
7c23b892 156{
89e8b13c
IY		 157 DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
158 " size=0x%08"FMT_PCIBUS"\n", addr, size);
7c23b892
AZ		 159}
160
161static void
162set_interrupt_cause(E1000State *s, int index, uint32_t val)
163{
164 if (val)
165 val |= E1000_ICR_INT_ASSERTED;
166 s->mac_reg[ICR] = val;
b1332393 167 s->mac_reg[ICS] = val;
bc26e55a 168 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 169}
170
171static void
172set_ics(E1000State *s, int index, uint32_t val)
173{
174 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
175 s->mac_reg[IMS]);
176 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
177}
178
179static int
180rxbufsize(uint32_t v)
181{
182 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
183 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
184 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
185 switch (v) {
186 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
187 return 16384;
188 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
189 return 8192;
190 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
191 return 4096;
192 case E1000_RCTL_SZ_1024:
193 return 1024;
194 case E1000_RCTL_SZ_512:
195 return 512;
196 case E1000_RCTL_SZ_256:
197 return 256;
198 }
199 return 2048;
200}
201
cab3c825
KW		 202static void
203set_ctrl(E1000State *s, int index, uint32_t val)
204{
205 /* RST is self clearing */
206 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
207}
208
7c23b892
AZ		 209static void
210set_rx_control(E1000State *s, int index, uint32_t val)
211{
212 s->mac_reg[RCTL] = val;
213 s->rxbuf_size = rxbufsize(val);
214 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
215 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
216 s->mac_reg[RCTL]);
217}
218
219static void
220set_mdic(E1000State *s, int index, uint32_t val)
221{
222 uint32_t data = val & E1000_MDIC_DATA_MASK;
223 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
224
225 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
226 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
227 else if (val & E1000_MDIC_OP_READ) {
228 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
229 if (!(phy_regcap[addr] & PHY_R)) {
230 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
231 val |= E1000_MDIC_ERROR;
232 } else
233 val = (val ^ data) | s->phy_reg[addr];
234 } else if (val & E1000_MDIC_OP_WRITE) {
235 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
236 if (!(phy_regcap[addr] & PHY_W)) {
237 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
238 val |= E1000_MDIC_ERROR;
239 } else
240 s->phy_reg[addr] = data;
241 }
242 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
243 set_ics(s, 0, E1000_ICR_MDAC);
244}
245
246static uint32_t
247get_eecd(E1000State *s, int index)
248{
249 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
250
251 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
252 s->eecd_state.bitnum_out, s->eecd_state.reading);
253 if (!s->eecd_state.reading ||
254 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
255 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
256 ret |= E1000_EECD_DO;
257 return ret;
258}
259
260static void
261set_eecd(E1000State *s, int index, uint32_t val)
262{
263 uint32_t oldval = s->eecd_state.old_eecd;
264
265 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
266 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 267 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
268 return;
269 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
270 s->eecd_state.val_in = 0;
271 s->eecd_state.bitnum_in = 0;
272 s->eecd_state.bitnum_out = 0;
273 s->eecd_state.reading = 0;
274 }
7c23b892
AZ		 275 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
276 return;
277 if (!(E1000_EECD_SK & val)) { // falling edge
278 s->eecd_state.bitnum_out++;
279 return;
280 }
7c23b892
AZ		 281 s->eecd_state.val_in <<= 1;
282 if (val & E1000_EECD_DI)
283 s->eecd_state.val_in |= 1;
284 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
285 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
286 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
287 EEPROM_READ_OPCODE_MICROWIRE);
288 }
289 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
290 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
291 s->eecd_state.reading);
292}
293
294static uint32_t
295flash_eerd_read(E1000State *s, int x)
296{
297 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
298
b1332393
BP		 299 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
300 return (s->mac_reg[EERD]);
301
7c23b892 302 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 303 return (E1000_EEPROM_RW_REG_DONE | r);
304
305 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
306 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 307}
308
7c23b892
AZ		 309static void
310putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
311{
c6a6a5e3
AL		 312 uint32_t sum;
313
7c23b892
AZ		 314 if (cse && cse < n)
315 n = cse + 1;
c6a6a5e3
AL		 316 if (sloc < n-1) {
317 sum = net_checksum_add(n-css, data+css);
7c23b892 318 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 319 net_checksum_finish(sum));
320 }
7c23b892
AZ		 321}
322
8f2e8d1f
AL		 323static inline int
324vlan_enabled(E1000State *s)
325{
326 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
327}
328
329static inline int
330vlan_rx_filter_enabled(E1000State *s)
331{
332 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
333}
334
335static inline int
336is_vlan_packet(E1000State *s, const uint8_t *buf)
337{
338 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
339 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
340}
341
342static inline int
343is_vlan_txd(uint32_t txd_lower)
344{
345 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
346}
347
55e8d1ce
MT		 348/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
349 * fill it in, just pad descriptor length by 4 bytes unless guest
a05e8a6e 350 * told us to strip it off the packet. */
55e8d1ce
MT		 351static inline int
352fcs_len(E1000State *s)
353{
354 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
355}
356
7c23b892
AZ		 357static void
358xmit_seg(E1000State *s)
359{
360 uint16_t len, *sp;
361 unsigned int frames = s->tx.tso_frames, css, sofar, n;
362 struct e1000_tx *tp = &s->tx;
363
1b0009db 364 if (tp->tse && tp->cptse) {
7c23b892
AZ		 365 css = tp->ipcss;
366 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
367 frames, tp->size, css);
368 if (tp->ip) { // IPv4
369 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
370 tp->size - css);
371 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
372 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
373 } else // IPv6
374 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
375 tp->size - css);
376 css = tp->tucss;
377 len = tp->size - css;
378 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
379 if (tp->tcp) {
380 sofar = frames * tp->mss;
381 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 382 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 383 if (tp->paylen - sofar > tp->mss)
384 tp->data[css + 13] &= ~9; // PSH, FIN
385 } else // UDP
386 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
387 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
e685b4eb 388 unsigned int phsum;
7c23b892
AZ		 389 // add pseudo-header length before checksum calculation
390 sp = (uint16_t *)(tp->data + tp->tucso);
e685b4eb
AW		 391 phsum = be16_to_cpup(sp) + len;
392 phsum = (phsum >> 16) + (phsum & 0xffff);
393 cpu_to_be16wu(sp, phsum);
7c23b892
AZ		 394 }
395 tp->tso_frames++;
396 }
397
398 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
399 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
400 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
401 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 402 if (tp->vlan_needed) {
b10fec9b
SW		 403 memmove(tp->vlan, tp->data, 4);
404 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 405 memcpy(tp->data + 8, tp->vlan_header, 4);
a03e2aec 406 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
8f2e8d1f 407 } else
a03e2aec 408 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
7c23b892
AZ		 409 s->mac_reg[TPT]++;
410 s->mac_reg[GPTC]++;
411 n = s->mac_reg[TOTL];
412 if ((s->mac_reg[TOTL] += s->tx.size) < n)
413 s->mac_reg[TOTH]++;
414}
415
416static void
417process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
418{
419 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
420 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
421 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
422 unsigned int msh = 0xfffff, hdr = 0;
423 uint64_t addr;
424 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
425 struct e1000_tx *tp = &s->tx;
426
427 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
428 op = le32_to_cpu(xp->cmd_and_length);
429 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
430 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
431 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
432 tp->tucss = xp->upper_setup.tcp_fields.tucss;
433 tp->tucso = xp->upper_setup.tcp_fields.tucso;
434 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
435 tp->paylen = op & 0xfffff;
436 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
437 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
438 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
439 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
440 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
441 tp->tso_frames = 0;
442 if (tp->tucso == 0) { // this is probably wrong
443 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
444 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
445 }
446 return;
1b0009db
AZ		 447 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
448 // data descriptor
735e77ec
SH		 449 if (tp->size == 0) {
450 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
451 }
1b0009db 452 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
43ad7e3e 453 } else {
1b0009db
AZ		 454 // legacy descriptor
455 tp->cptse = 0;
43ad7e3e 456 }
7c23b892 457
8f2e8d1f
AL		 458 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
459 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
460 tp->vlan_needed = 1;
461 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
462 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
463 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
464 le16_to_cpu(dp->upper.fields.special));
465 }
466
7c23b892 467 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 468 if (tp->tse && tp->cptse) {
7c23b892
AZ		 469 hdr = tp->hdr_len;
470 msh = hdr + tp->mss;
1b0009db
AZ		 471 do {
472 bytes = split_size;
473 if (tp->size + bytes > msh)
474 bytes = msh - tp->size;
475 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
476 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
477 memmove(tp->header, tp->data, hdr);
478 tp->size = sz;
479 addr += bytes;
480 if (sz == msh) {
481 xmit_seg(s);
482 memmove(tp->data, tp->header, hdr);
483 tp->size = hdr;
484 }
485 } while (split_size -= bytes);
486 } else if (!tp->tse && tp->cptse) {
487 // context descriptor TSE is not set, while data descriptor TSE is set
488 DBGOUT(TXERR, "TCP segmentaion Error\n");
489 } else {
490 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
491 tp->size += split_size;
7c23b892 492 }
7c23b892
AZ		 493
494 if (!(txd_lower & E1000_TXD_CMD_EOP))
495 return;
1b0009db 496 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 497 xmit_seg(s);
498 tp->tso_frames = 0;
499 tp->sum_needed = 0;
8f2e8d1f 500 tp->vlan_needed = 0;
7c23b892 501 tp->size = 0;
1b0009db 502 tp->cptse = 0;
7c23b892
AZ		 503}
504
505static uint32_t
c227f099 506txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 507{
508 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
509
510 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
511 return 0;
512 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
513 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
514 dp->upper.data = cpu_to_le32(txd_upper);
515 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
516 (void *)&dp->upper, sizeof(dp->upper));
517 return E1000_ICR_TXDW;
518}
519
520static void
521start_xmit(E1000State *s)
522{
c227f099 523 target_phys_addr_t base;
7c23b892
AZ		 524 struct e1000_tx_desc desc;
525 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
526
527 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
528 DBGOUT(TX, "tx disabled\n");
529 return;
530 }
531
532 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
533 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
534 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
535 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
536
537 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 538 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 539 desc.upper.data);
540
541 process_tx_desc(s, &desc);
542 cause |= txdesc_writeback(base, &desc);
543
544 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
545 s->mac_reg[TDH] = 0;
546 /*
547 * the following could happen only if guest sw assigns
548 * bogus values to TDT/TDLEN.
549 * there's nothing too intelligent we could do about this.
550 */
551 if (s->mac_reg[TDH] == tdh_start) {
552 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
553 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
554 break;
555 }
556 }
557 set_ics(s, 0, cause);
558}
559
560static int
561receive_filter(E1000State *s, const uint8_t *buf, int size)
562{
af2960f9
BS		 563 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
564 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 565 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
566
8f2e8d1f
AL		 567 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
568 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
569 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
570 ((vid >> 5) & 0x7f));
571 if ((vfta & (1 << (vid & 0x1f))) == 0)
572 return 0;
573 }
574
7c23b892
AZ		 575 if (rctl & E1000_RCTL_UPE) // promiscuous
576 return 1;
577
578 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
579 return 1;
580
581 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
582 return 1;
583
584 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
585 if (!(rp[1] & E1000_RAH_AV))
586 continue;
587 ra[0] = cpu_to_le32(rp[0]);
588 ra[1] = cpu_to_le32(rp[1]);
589 if (!memcmp(buf, (uint8_t *)ra, 6)) {
590 DBGOUT(RXFILTER,
591 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
592 (int)(rp - s->mac_reg - RA)/2,
593 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
594 return 1;
595 }
596 }
597 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
598 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
599
600 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
601 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
602 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
603 return 1;
604 DBGOUT(RXFILTER,
605 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
606 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
607 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
608 s->mac_reg[MTA + (f >> 5)]);
609
610 return 0;
611}
612
99ed7e30 613static void
a03e2aec 614e1000_set_link_status(VLANClientState *nc)
99ed7e30 615{
a03e2aec 616 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 617 uint32_t old_status = s->mac_reg[STATUS];
618
a03e2aec 619 if (nc->link_down)
99ed7e30
AL		 620 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
621 else
622 s->mac_reg[STATUS] |= E1000_STATUS_LU;
623
624 if (s->mac_reg[STATUS] != old_status)
625 set_ics(s, 0, E1000_ICR_LSC);
626}
627
322fd48a
MT		 628static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
629{
630 int bufs;
631 /* Fast-path short packets */
632 if (total_size <= s->rxbuf_size) {
633 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
634 }
635 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
636 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
637 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
638 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
639 s->mac_reg[RDT] - s->mac_reg[RDH];
640 } else {
641 return false;
642 }
643 return total_size <= bufs * s->rxbuf_size;
644}
645
6cdfab28
MT		 646static int
647e1000_can_receive(VLANClientState *nc)
648{
649 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
650
651 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
652}
653
4f1c942b 654static ssize_t
a03e2aec 655e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 656{
a03e2aec 657 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 658 struct e1000_rx_desc desc;
c227f099 659 target_phys_addr_t base;
7c23b892
AZ		 660 unsigned int n, rdt;
661 uint32_t rdh_start;
8f2e8d1f
AL		 662 uint16_t vlan_special = 0;
663 uint8_t vlan_status = 0, vlan_offset = 0;
78aeb23e 664 uint8_t min_buf[MIN_BUF_SIZE];
b19487e2
MT		 665 size_t desc_offset;
666 size_t desc_size;
667 size_t total_size;
7c23b892
AZ		 668
669 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 670 return -1;
7c23b892 671
78aeb23e
SH		 672 /* Pad to minimum Ethernet frame length */
673 if (size < sizeof(min_buf)) {
674 memcpy(min_buf, buf, size);
675 memset(&min_buf[size], 0, sizeof(min_buf) - size);
676 buf = min_buf;
677 size = sizeof(min_buf);
678 }
679
7c23b892 680 if (!receive_filter(s, buf, size))
4f1c942b 681 return size;
7c23b892 682
8f2e8d1f
AL		 683 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
684 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 685 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 686 vlan_status = E1000_RXD_STAT_VP;
687 vlan_offset = 4;
688 size -= 4;
689 }
690
7c23b892 691 rdh_start = s->mac_reg[RDH];
b19487e2
MT		 692 desc_offset = 0;
693 total_size = size + fcs_len(s);
322fd48a
MT		 694 if (!e1000_has_rxbufs(s, total_size)) {
695 set_ics(s, 0, E1000_ICS_RXO);
696 return -1;
697 }
7c23b892 698 do {
b19487e2
MT		 699 desc_size = total_size - desc_offset;
700 if (desc_size > s->rxbuf_size) {
701 desc_size = s->rxbuf_size;
702 }
7c23b892
AZ		 703 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
704 sizeof(desc) * s->mac_reg[RDH];
705 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 706 desc.special = vlan_special;
707 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892 708 if (desc.buffer_addr) {
b19487e2
MT		 709 if (desc_offset < size) {
710 size_t copy_size = size - desc_offset;
711 if (copy_size > s->rxbuf_size) {
712 copy_size = s->rxbuf_size;
713 }
714 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
715 (void *)(buf + desc_offset + vlan_offset),
716 copy_size);
717 }
718 desc_offset += desc_size;
ee912ccf 719 desc.length = cpu_to_le16(desc_size);
b19487e2 720 if (desc_offset >= total_size) {
b19487e2
MT		 721 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
722 } else {
ee912ccf
MT		 723 /* Guest zeroing out status is not a hardware requirement.
724 Clear EOP in case guest didn't do it. */
725 desc.status &= ~E1000_RXD_STAT_EOP;
b19487e2 726 }
43ad7e3e 727 } else { // as per intel docs; skip descriptors with null buf addr
7c23b892 728 DBGOUT(RX, "Null RX descriptor!!\n");
43ad7e3e 729 }
7c23b892
AZ		 730 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
731
732 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
733 s->mac_reg[RDH] = 0;
734 s->check_rxov = 1;
735 /* see comment in start_xmit; same here */
736 if (s->mac_reg[RDH] == rdh_start) {
737 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
738 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
739 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 740 return -1;
7c23b892 741 }
b19487e2 742 } while (desc_offset < total_size);
7c23b892
AZ		 743
744 s->mac_reg[GPRC]++;
745 s->mac_reg[TPR]++;
a05e8a6e
MT		 746 /* TOR - Total Octets Received:
747 * This register includes bytes received in a packet from the <Destination
748 * Address> field through the <CRC> field, inclusively.
749 */
750 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
751 if (n < s->mac_reg[TORL])
7c23b892 752 s->mac_reg[TORH]++;
a05e8a6e 753 s->mac_reg[TORL] = n;
7c23b892
AZ		 754
755 n = E1000_ICS_RXT0;
756 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
757 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 758 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
759 s->rxbuf_min_shift)
7c23b892
AZ		 760 n |= E1000_ICS_RXDMT0;
761
762 set_ics(s, 0, n);
4f1c942b
MM		 763
764 return size;
7c23b892
AZ		 765}
766
767static uint32_t
768mac_readreg(E1000State *s, int index)
769{
770 return s->mac_reg[index];
771}
772
773static uint32_t
774mac_icr_read(E1000State *s, int index)
775{
776 uint32_t ret = s->mac_reg[ICR];
777
778 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
779 set_interrupt_cause(s, 0, 0);
780 return ret;
781}
782
783static uint32_t
784mac_read_clr4(E1000State *s, int index)
785{
786 uint32_t ret = s->mac_reg[index];
787
788 s->mac_reg[index] = 0;
789 return ret;
790}
791
792static uint32_t
793mac_read_clr8(E1000State *s, int index)
794{
795 uint32_t ret = s->mac_reg[index];
796
797 s->mac_reg[index] = 0;
798 s->mac_reg[index-1] = 0;
799 return ret;
800}
801
802static void
803mac_writereg(E1000State *s, int index, uint32_t val)
804{
805 s->mac_reg[index] = val;
806}
807
808static void
809set_rdt(E1000State *s, int index, uint32_t val)
810{
811 s->check_rxov = 0;
812 s->mac_reg[index] = val & 0xffff;
813}
814
815static void
816set_16bit(E1000State *s, int index, uint32_t val)
817{
818 s->mac_reg[index] = val & 0xffff;
819}
820
821static void
822set_dlen(E1000State *s, int index, uint32_t val)
823{
824 s->mac_reg[index] = val & 0xfff80;
825}
826
827static void
828set_tctl(E1000State *s, int index, uint32_t val)
829{
830 s->mac_reg[index] = val;
831 s->mac_reg[TDT] &= 0xffff;
832 start_xmit(s);
833}
834
835static void
836set_icr(E1000State *s, int index, uint32_t val)
837{
838 DBGOUT(INTERRUPT, "set_icr %x\n", val);
839 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
840}
841
842static void
843set_imc(E1000State *s, int index, uint32_t val)
844{
845 s->mac_reg[IMS] &= ~val;
846 set_ics(s, 0, 0);
847}
848
849static void
850set_ims(E1000State *s, int index, uint32_t val)
851{
852 s->mac_reg[IMS] |= val;
853 set_ics(s, 0, 0);
854}
855
856#define getreg(x) [x] = mac_readreg
857static uint32_t (*macreg_readops[])(E1000State *, int) = {
858 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
859 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
860 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
861 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 862 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 863 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
864 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 865
866 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
867 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
868 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
869 [CRCERRS ... MPC] = &mac_readreg,
870 [RA ... RA+31] = &mac_readreg,
871 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 872 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 873};
b1503cda 874enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 875
876#define putreg(x) [x] = mac_writereg
877static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
878 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
879 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 880 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 881 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
882 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
883 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
884 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 885 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 886 [RA ... RA+31] = &mac_writereg,
887 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 888 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 889};
b1503cda 890enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 891
892static void
c227f099 893e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 894{
895 E1000State *s = opaque;
8da3ff18 896 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 897
43ad7e3e 898 if (index < NWRITEOPS && macreg_writeops[index]) {
6b59fc74 899 macreg_writeops[index](s, index, val);
43ad7e3e 900 } else if (index < NREADOPS && macreg_readops[index]) {
7c23b892 901 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
43ad7e3e 902 } else {
7c23b892
AZ		 903 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
904 index<<2, val);
43ad7e3e 905 }
7c23b892
AZ		 906}
907
908static void
c227f099 909e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 910{
911 // emulate hw without byte enables: no RMW
912 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 913 (val & 0xffff) << (8*(addr & 3)));
7c23b892
AZ		 914}
915
916static void
c227f099 917e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 918{
919 // emulate hw without byte enables: no RMW
920 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 921 (val & 0xff) << (8*(addr & 3)));
7c23b892
AZ		 922}
923
924static uint32_t
c227f099 925e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
7c23b892
AZ		 926{
927 E1000State *s = opaque;
8da3ff18 928 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 929
930 if (index < NREADOPS && macreg_readops[index])
6b59fc74 931 {
32600a30 932 return macreg_readops[index](s, index);
6b59fc74 933 }
7c23b892
AZ		 934 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
935 return 0;
936}
937
938static uint32_t
c227f099 939e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
7c23b892 940{
6b59fc74 941 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
7c23b892
AZ		 942 (8 * (addr & 3))) & 0xff;
943}
944
945static uint32_t
c227f099 946e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
7c23b892 947{
6b59fc74
AJ		 948 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
949 (8 * (addr & 3))) & 0xffff;
7c23b892
AZ		 950}
951
e482dc3e 952static bool is_version_1(void *opaque, int version_id)
7c23b892 953{
e482dc3e 954 return version_id == 1;
7c23b892
AZ		 955}
956
e482dc3e
JQ		 957static const VMStateDescription vmstate_e1000 = {
958 .name = "e1000",
959 .version_id = 2,
960 .minimum_version_id = 1,
961 .minimum_version_id_old = 1,
962 .fields = (VMStateField []) {
963 VMSTATE_PCI_DEVICE(dev, E1000State),
964 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
965 VMSTATE_UNUSED(4), /* Was mmio_base. */
966 VMSTATE_UINT32(rxbuf_size, E1000State),
967 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
968 VMSTATE_UINT32(eecd_state.val_in, E1000State),
969 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
970 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
971 VMSTATE_UINT16(eecd_state.reading, E1000State),
972 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
973 VMSTATE_UINT8(tx.ipcss, E1000State),
974 VMSTATE_UINT8(tx.ipcso, E1000State),
975 VMSTATE_UINT16(tx.ipcse, E1000State),
976 VMSTATE_UINT8(tx.tucss, E1000State),
977 VMSTATE_UINT8(tx.tucso, E1000State),
978 VMSTATE_UINT16(tx.tucse, E1000State),
979 VMSTATE_UINT32(tx.paylen, E1000State),
980 VMSTATE_UINT8(tx.hdr_len, E1000State),
981 VMSTATE_UINT16(tx.mss, E1000State),
982 VMSTATE_UINT16(tx.size, E1000State),
983 VMSTATE_UINT16(tx.tso_frames, E1000State),
984 VMSTATE_UINT8(tx.sum_needed, E1000State),
985 VMSTATE_INT8(tx.ip, E1000State),
986 VMSTATE_INT8(tx.tcp, E1000State),
987 VMSTATE_BUFFER(tx.header, E1000State),
988 VMSTATE_BUFFER(tx.data, E1000State),
989 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
990 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
991 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
992 VMSTATE_UINT32(mac_reg[EECD], E1000State),
993 VMSTATE_UINT32(mac_reg[EERD], E1000State),
994 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
995 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
996 VMSTATE_UINT32(mac_reg[ICR], E1000State),
997 VMSTATE_UINT32(mac_reg[ICS], E1000State),
998 VMSTATE_UINT32(mac_reg[IMC], E1000State),
999 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1000 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1001 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1002 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1003 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1004 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1005 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1006 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1007 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1008 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1009 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1010 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1011 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1012 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1013 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1014 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1015 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1016 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1017 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1018 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1019 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1020 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1021 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1022 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1023 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1024 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1025 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1026 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1027 VMSTATE_UINT32(mac_reg[VET], E1000State),
1028 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1029 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1030 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1031 VMSTATE_END_OF_LIST()
1032 }
1033};
7c23b892 1034
88b4e9db 1035static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 1036 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1037 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1038 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1039 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1040 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1041 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1042 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1043 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1044};
1045
88b4e9db 1046static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 1047 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1048 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1049 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1050 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1051 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 1052 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 1053};
1054
88b4e9db 1055static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 1056 [PBA] = 0x00100030,
1057 [LEDCTL] = 0x602,
1058 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1059 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1060 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1061 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1062 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1063 E1000_STATUS_LU,
1064 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1065 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1066 E1000_MANC_RMCP_EN,
1067};
1068
1069/* PCI interface */
1070
d60efc6b 1071static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
7c23b892
AZ		 1072 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1073};
1074
d60efc6b 1075static CPUReadMemoryFunc * const e1000_mmio_read[] = {
7c23b892
AZ		 1076 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1077};
1078
1079static void
1080e1000_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 1081 pcibus_t addr, pcibus_t size, int type)
7c23b892 1082{
7d9e52bd 1083 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
f65ed4c1
AL		 1084 int i;
1085 const uint32_t excluded_regs[] = {
1086 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1087 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1088 };
1089
7c23b892 1090
89e8b13c
IY		 1091 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
1092 addr, size);
7c23b892 1093
7c23b892 1094 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
f65ed4c1
AL		 1095 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1096
1097 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1098 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1099 excluded_regs[i + 1] -
1100 excluded_regs[i] - 4);
7c23b892
AZ		 1101}
1102
b946a153 1103static void
a03e2aec 1104e1000_cleanup(VLANClientState *nc)
b946a153 1105{
a03e2aec 1106 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1107
a03e2aec 1108 s->nic = NULL;
b946a153
AL		 1109}
1110
4b09be85
AL		 1111static int
1112pci_e1000_uninit(PCIDevice *dev)
1113{
7d9e52bd 1114 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85
AL		 1115
1116 cpu_unregister_io_memory(d->mmio_index);
a03e2aec 1117 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1118 return 0;
1119}
1120
32c86e95
BS		 1121static void e1000_reset(void *opaque)
1122{
1123 E1000State *d = opaque;
1124
1125 memset(d->phy_reg, 0, sizeof d->phy_reg);
1126 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1127 memset(d->mac_reg, 0, sizeof d->mac_reg);
1128 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1129 d->rxbuf_min_shift = 1;
1130 memset(&d->tx, 0, sizeof d->tx);
1131}
1132
a03e2aec
MM		 1133static NetClientInfo net_e1000_info = {
1134 .type = NET_CLIENT_TYPE_NIC,
1135 .size = sizeof(NICState),
1136 .can_receive = e1000_can_receive,
1137 .receive = e1000_receive,
1138 .cleanup = e1000_cleanup,
1139 .link_status_changed = e1000_set_link_status,
1140};
1141
81a322d4 1142static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1143{
7d9e52bd 1144 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1145 uint8_t *pci_conf;
7c23b892 1146 uint16_t checksum = 0;
7c23b892 1147 int i;
fbdaa002 1148 uint8_t *macaddr;
aff427a1 1149
7c23b892 1150 pci_conf = d->dev.config;
7c23b892 1151
deb54399
AL		 1152 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1153 pci_config_set_device_id(pci_conf, E1000_DEVID);
a9cbacb0
MT		 1154 /* TODO: we have no capabilities, so why is this bit set? */
1155 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
1156 pci_conf[PCI_REVISION_ID] = 0x03;
173a543b 1157 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
a9cbacb0
MT		 1158 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1159 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1160
a9cbacb0
MT		 1161 /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */
1162 pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
7c23b892 1163
1eed09cb 1164 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
32600a30 1165 e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
7c23b892 1166
b90c73cf 1167 pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
0392a017 1168 PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
7c23b892 1169
b90c73cf 1170 pci_register_bar(&d->dev, 1, IOPORT_SIZE,
0392a017 1171 PCI_BASE_ADDRESS_SPACE_IO, ioport_map);
7c23b892 1172
7c23b892
AZ		 1173 memmove(d->eeprom_data, e1000_eeprom_template,
1174 sizeof e1000_eeprom_template);
fbdaa002
GH		 1175 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1176 macaddr = d->conf.macaddr.a;
7c23b892 1177 for (i = 0; i < 3; i++)
9d07d757 1178 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1179 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1180 checksum += d->eeprom_data[i];
1181 checksum = (uint16_t) EEPROM_SUM - checksum;
1182 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1183
a03e2aec
MM		 1184 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1185 d->dev.qdev.info->name, d->dev.qdev.id, d);
7c23b892 1186
a03e2aec 1187 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1ca4d09a
GN		 1188
1189 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1190
81a322d4 1191 return 0;
9d07d757 1192}
72da4208 1193
fbdaa002
GH		 1194static void qdev_e1000_reset(DeviceState *dev)
1195{
1196 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1197 e1000_reset(d);
1198}
1199
0aab0d3a 1200static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1201 .qdev.name = "e1000",
1202 .qdev.desc = "Intel Gigabit Ethernet",
1203 .qdev.size = sizeof(E1000State),
1204 .qdev.reset = qdev_e1000_reset,
be73cfe2 1205 .qdev.vmsd = &vmstate_e1000,
fbdaa002
GH		 1206 .init = pci_e1000_init,
1207 .exit = pci_e1000_uninit,
8c52c8f3 1208 .romfile = "pxe-e1000.bin",
fbdaa002
GH		 1209 .qdev.props = (Property[]) {
1210 DEFINE_NIC_PROPERTIES(E1000State, conf),
1211 DEFINE_PROP_END_OF_LIST(),
1212 }
0aab0d3a
GH		 1213};
1214
9d07d757
PB		 1215static void e1000_register_devices(void)
1216{
0aab0d3a 1217 pci_qdev_register(&e1000_info);
7c23b892 1218}
9d07d757
PB		 1219
1220device_init(e1000_register_devices)
Qemu copy for testing