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[qemu.git] / hw / e1000.c
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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
1ca4d09a 33#include "sysemu.h"
62ecbd35 34#include "dma.h"
7c23b892 35
7c23b892
AZ		 36#include "e1000_hw.h"
37
27124888 38#define E1000_DEBUG
7c23b892 39
27124888 40#ifdef E1000_DEBUG
7c23b892
AZ		 41enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_NOTYET,
46};
47#define DBGBIT(x) (1<<DEBUG_##x)
48static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
6c7f4b47 50#define DBGOUT(what, fmt, ...) do { \
7c23b892 51 if (debugflags & DBGBIT(what)) \
6c7f4b47 52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 53 } while (0)
54#else
6c7f4b47 55#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 56#endif
57
58#define IOPORT_SIZE 0x40
e94bbefe 59#define PNPMMIO_SIZE 0x20000
78aeb23e 60#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
7c23b892
AZ		 61
62/*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72/*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80};
81
82typedef struct E1000State_st {
83 PCIDevice dev;
a03e2aec 84 NICState *nic;
fbdaa002 85 NICConf conf;
ad00a9b9
AK		 86 MemoryRegion mmio;
87 MemoryRegion io;
7c23b892
AZ		 88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 int check_rxov;
96 struct e1000_tx {
97 unsigned char header[256];
8f2e8d1f 98 unsigned char vlan_header[4];
b10fec9b 99 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 100 unsigned char vlan[4];
7c23b892
AZ		 101 unsigned char data[0x10000];
102 uint16_t size;
103 unsigned char sum_needed;
8f2e8d1f 104 unsigned char vlan_needed;
7c23b892
AZ		 105 uint8_t ipcss;
106 uint8_t ipcso;
107 uint16_t ipcse;
108 uint8_t tucss;
109 uint8_t tucso;
110 uint16_t tucse;
111 uint8_t hdr_len;
112 uint16_t mss;
113 uint32_t paylen;
114 uint16_t tso_frames;
115 char tse;
b6c4f71f
BS		 116 int8_t ip;
117 int8_t tcp;
1b0009db 118 char cptse; // current packet tse bit
7c23b892
AZ		 119 } tx;
120
121 struct {
122 uint32_t val_in; // shifted in from guest driver
123 uint16_t bitnum_in;
124 uint16_t bitnum_out;
125 uint16_t reading;
126 uint32_t old_eecd;
127 } eecd_state;
128} E1000State;
129
130#define defreg(x) x = (E1000_##x>>2)
131enum {
132 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
133 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
134 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
135 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
136 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
137 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
138 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
139 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
140 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 141 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
142 defreg(VET),
7c23b892
AZ		 143};
144
145enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 146static const char phy_regcap[0x20] = {
7c23b892
AZ		 147 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
148 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
149 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
150 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
151 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 152 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 153};
154
7c23b892
AZ		 155static void
156set_interrupt_cause(E1000State *s, int index, uint32_t val)
157{
158 if (val)
159 val |= E1000_ICR_INT_ASSERTED;
160 s->mac_reg[ICR] = val;
b1332393 161 s->mac_reg[ICS] = val;
bc26e55a 162 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 163}
164
165static void
166set_ics(E1000State *s, int index, uint32_t val)
167{
168 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
169 s->mac_reg[IMS]);
170 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
171}
172
173static int
174rxbufsize(uint32_t v)
175{
176 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
177 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
178 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
179 switch (v) {
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
181 return 16384;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
183 return 8192;
184 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
185 return 4096;
186 case E1000_RCTL_SZ_1024:
187 return 1024;
188 case E1000_RCTL_SZ_512:
189 return 512;
190 case E1000_RCTL_SZ_256:
191 return 256;
192 }
193 return 2048;
194}
195
cab3c825
KW		 196static void
197set_ctrl(E1000State *s, int index, uint32_t val)
198{
199 /* RST is self clearing */
200 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
201}
202
7c23b892
AZ		 203static void
204set_rx_control(E1000State *s, int index, uint32_t val)
205{
206 s->mac_reg[RCTL] = val;
207 s->rxbuf_size = rxbufsize(val);
208 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
209 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
210 s->mac_reg[RCTL]);
211}
212
213static void
214set_mdic(E1000State *s, int index, uint32_t val)
215{
216 uint32_t data = val & E1000_MDIC_DATA_MASK;
217 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
218
219 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
220 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
221 else if (val & E1000_MDIC_OP_READ) {
222 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
223 if (!(phy_regcap[addr] & PHY_R)) {
224 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
225 val |= E1000_MDIC_ERROR;
226 } else
227 val = (val ^ data) | s->phy_reg[addr];
228 } else if (val & E1000_MDIC_OP_WRITE) {
229 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
230 if (!(phy_regcap[addr] & PHY_W)) {
231 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
232 val |= E1000_MDIC_ERROR;
233 } else
234 s->phy_reg[addr] = data;
235 }
236 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
237 set_ics(s, 0, E1000_ICR_MDAC);
238}
239
240static uint32_t
241get_eecd(E1000State *s, int index)
242{
243 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
244
245 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
246 s->eecd_state.bitnum_out, s->eecd_state.reading);
247 if (!s->eecd_state.reading ||
248 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
249 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
250 ret |= E1000_EECD_DO;
251 return ret;
252}
253
254static void
255set_eecd(E1000State *s, int index, uint32_t val)
256{
257 uint32_t oldval = s->eecd_state.old_eecd;
258
259 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
260 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 261 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
262 return;
263 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
264 s->eecd_state.val_in = 0;
265 s->eecd_state.bitnum_in = 0;
266 s->eecd_state.bitnum_out = 0;
267 s->eecd_state.reading = 0;
268 }
7c23b892
AZ		 269 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
270 return;
271 if (!(E1000_EECD_SK & val)) { // falling edge
272 s->eecd_state.bitnum_out++;
273 return;
274 }
7c23b892
AZ		 275 s->eecd_state.val_in <<= 1;
276 if (val & E1000_EECD_DI)
277 s->eecd_state.val_in |= 1;
278 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
279 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
280 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
281 EEPROM_READ_OPCODE_MICROWIRE);
282 }
283 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
284 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
285 s->eecd_state.reading);
286}
287
288static uint32_t
289flash_eerd_read(E1000State *s, int x)
290{
291 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
292
b1332393
BP		 293 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
294 return (s->mac_reg[EERD]);
295
7c23b892 296 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 297 return (E1000_EEPROM_RW_REG_DONE | r);
298
299 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
300 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 301}
302
7c23b892
AZ		 303static void
304putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
305{
c6a6a5e3
AL		 306 uint32_t sum;
307
7c23b892
AZ		 308 if (cse && cse < n)
309 n = cse + 1;
c6a6a5e3
AL		 310 if (sloc < n-1) {
311 sum = net_checksum_add(n-css, data+css);
7c23b892 312 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 313 net_checksum_finish(sum));
314 }
7c23b892
AZ		 315}
316
8f2e8d1f
AL		 317static inline int
318vlan_enabled(E1000State *s)
319{
320 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
321}
322
323static inline int
324vlan_rx_filter_enabled(E1000State *s)
325{
326 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
327}
328
329static inline int
330is_vlan_packet(E1000State *s, const uint8_t *buf)
331{
332 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
333 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
334}
335
336static inline int
337is_vlan_txd(uint32_t txd_lower)
338{
339 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
340}
341
55e8d1ce
MT		 342/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
343 * fill it in, just pad descriptor length by 4 bytes unless guest
a05e8a6e 344 * told us to strip it off the packet. */
55e8d1ce
MT		 345static inline int
346fcs_len(E1000State *s)
347{
348 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
349}
350
7c23b892
AZ		 351static void
352xmit_seg(E1000State *s)
353{
354 uint16_t len, *sp;
355 unsigned int frames = s->tx.tso_frames, css, sofar, n;
356 struct e1000_tx *tp = &s->tx;
357
1b0009db 358 if (tp->tse && tp->cptse) {
7c23b892
AZ		 359 css = tp->ipcss;
360 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
361 frames, tp->size, css);
362 if (tp->ip) { // IPv4
363 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
364 tp->size - css);
365 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
366 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
367 } else // IPv6
368 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
369 tp->size - css);
370 css = tp->tucss;
371 len = tp->size - css;
372 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
373 if (tp->tcp) {
374 sofar = frames * tp->mss;
375 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 376 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 377 if (tp->paylen - sofar > tp->mss)
378 tp->data[css + 13] &= ~9; // PSH, FIN
379 } else // UDP
380 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
381 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
e685b4eb 382 unsigned int phsum;
7c23b892
AZ		 383 // add pseudo-header length before checksum calculation
384 sp = (uint16_t *)(tp->data + tp->tucso);
e685b4eb
AW		 385 phsum = be16_to_cpup(sp) + len;
386 phsum = (phsum >> 16) + (phsum & 0xffff);
387 cpu_to_be16wu(sp, phsum);
7c23b892
AZ		 388 }
389 tp->tso_frames++;
390 }
391
392 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
393 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
394 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
395 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 396 if (tp->vlan_needed) {
b10fec9b
SW		 397 memmove(tp->vlan, tp->data, 4);
398 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 399 memcpy(tp->data + 8, tp->vlan_header, 4);
a03e2aec 400 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
8f2e8d1f 401 } else
a03e2aec 402 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
7c23b892
AZ		 403 s->mac_reg[TPT]++;
404 s->mac_reg[GPTC]++;
405 n = s->mac_reg[TOTL];
406 if ((s->mac_reg[TOTL] += s->tx.size) < n)
407 s->mac_reg[TOTH]++;
408}
409
410static void
411process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
412{
413 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
414 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
415 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
416 unsigned int msh = 0xfffff, hdr = 0;
417 uint64_t addr;
418 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
419 struct e1000_tx *tp = &s->tx;
420
421 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
422 op = le32_to_cpu(xp->cmd_and_length);
423 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
424 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
425 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
426 tp->tucss = xp->upper_setup.tcp_fields.tucss;
427 tp->tucso = xp->upper_setup.tcp_fields.tucso;
428 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
429 tp->paylen = op & 0xfffff;
430 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
431 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
432 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
433 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
434 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
435 tp->tso_frames = 0;
436 if (tp->tucso == 0) { // this is probably wrong
437 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
438 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
439 }
440 return;
1b0009db
AZ		 441 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
442 // data descriptor
735e77ec
SH		 443 if (tp->size == 0) {
444 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
445 }
1b0009db 446 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
43ad7e3e 447 } else {
1b0009db
AZ		 448 // legacy descriptor
449 tp->cptse = 0;
43ad7e3e 450 }
7c23b892 451
8f2e8d1f
AL		 452 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
453 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
454 tp->vlan_needed = 1;
455 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
456 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
457 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
458 le16_to_cpu(dp->upper.fields.special));
459 }
460
7c23b892 461 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 462 if (tp->tse && tp->cptse) {
7c23b892
AZ		 463 hdr = tp->hdr_len;
464 msh = hdr + tp->mss;
1b0009db
AZ		 465 do {
466 bytes = split_size;
467 if (tp->size + bytes > msh)
468 bytes = msh - tp->size;
62ecbd35 469 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
1b0009db
AZ		 470 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
471 memmove(tp->header, tp->data, hdr);
472 tp->size = sz;
473 addr += bytes;
474 if (sz == msh) {
475 xmit_seg(s);
476 memmove(tp->data, tp->header, hdr);
477 tp->size = hdr;
478 }
479 } while (split_size -= bytes);
480 } else if (!tp->tse && tp->cptse) {
481 // context descriptor TSE is not set, while data descriptor TSE is set
482 DBGOUT(TXERR, "TCP segmentaion Error\n");
483 } else {
62ecbd35 484 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
1b0009db 485 tp->size += split_size;
7c23b892 486 }
7c23b892
AZ		 487
488 if (!(txd_lower & E1000_TXD_CMD_EOP))
489 return;
1b0009db 490 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 491 xmit_seg(s);
492 tp->tso_frames = 0;
493 tp->sum_needed = 0;
8f2e8d1f 494 tp->vlan_needed = 0;
7c23b892 495 tp->size = 0;
1b0009db 496 tp->cptse = 0;
7c23b892
AZ		 497}
498
499static uint32_t
62ecbd35 500txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 501{
502 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
503
504 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
505 return 0;
506 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
507 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
508 dp->upper.data = cpu_to_le32(txd_upper);
62ecbd35
EGM		 509 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
510 (void *)&dp->upper, sizeof(dp->upper));
7c23b892
AZ		 511 return E1000_ICR_TXDW;
512}
513
d17161f6
KW		 514static uint64_t tx_desc_base(E1000State *s)
515{
516 uint64_t bah = s->mac_reg[TDBAH];
517 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
518
519 return (bah << 32) + bal;
520}
521
7c23b892
AZ		 522static void
523start_xmit(E1000State *s)
524{
62ecbd35 525 dma_addr_t base;
7c23b892
AZ		 526 struct e1000_tx_desc desc;
527 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
528
529 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
530 DBGOUT(TX, "tx disabled\n");
531 return;
532 }
533
534 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
d17161f6 535 base = tx_desc_base(s) +
7c23b892 536 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
62ecbd35 537 pci_dma_read(&s->dev, base, (void *)&desc, sizeof(desc));
7c23b892
AZ		 538
539 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 540 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 541 desc.upper.data);
542
543 process_tx_desc(s, &desc);
62ecbd35 544 cause |= txdesc_writeback(s, base, &desc);
7c23b892
AZ		 545
546 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
547 s->mac_reg[TDH] = 0;
548 /*
549 * the following could happen only if guest sw assigns
550 * bogus values to TDT/TDLEN.
551 * there's nothing too intelligent we could do about this.
552 */
553 if (s->mac_reg[TDH] == tdh_start) {
554 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
555 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
556 break;
557 }
558 }
559 set_ics(s, 0, cause);
560}
561
562static int
563receive_filter(E1000State *s, const uint8_t *buf, int size)
564{
af2960f9
BS		 565 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
566 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 567 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
568
8f2e8d1f
AL		 569 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
570 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
571 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
572 ((vid >> 5) & 0x7f));
573 if ((vfta & (1 << (vid & 0x1f))) == 0)
574 return 0;
575 }
576
7c23b892
AZ		 577 if (rctl & E1000_RCTL_UPE) // promiscuous
578 return 1;
579
580 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
581 return 1;
582
583 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
584 return 1;
585
586 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
587 if (!(rp[1] & E1000_RAH_AV))
588 continue;
589 ra[0] = cpu_to_le32(rp[0]);
590 ra[1] = cpu_to_le32(rp[1]);
591 if (!memcmp(buf, (uint8_t *)ra, 6)) {
592 DBGOUT(RXFILTER,
593 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
594 (int)(rp - s->mac_reg - RA)/2,
595 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
596 return 1;
597 }
598 }
599 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
600 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
601
602 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
603 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
604 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
605 return 1;
606 DBGOUT(RXFILTER,
607 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
608 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
609 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
610 s->mac_reg[MTA + (f >> 5)]);
611
612 return 0;
613}
614
99ed7e30 615static void
a03e2aec 616e1000_set_link_status(VLANClientState *nc)
99ed7e30 617{
a03e2aec 618 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 619 uint32_t old_status = s->mac_reg[STATUS];
620
d4044c2a 621 if (nc->link_down) {
99ed7e30 622 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
d4044c2a
BM		 623 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
624 } else {
99ed7e30 625 s->mac_reg[STATUS] |= E1000_STATUS_LU;
d4044c2a
BM		 626 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
627 }
99ed7e30
AL		 628
629 if (s->mac_reg[STATUS] != old_status)
630 set_ics(s, 0, E1000_ICR_LSC);
631}
632
322fd48a
MT		 633static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
634{
635 int bufs;
636 /* Fast-path short packets */
637 if (total_size <= s->rxbuf_size) {
638 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
639 }
640 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
641 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
642 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
643 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
644 s->mac_reg[RDT] - s->mac_reg[RDH];
645 } else {
646 return false;
647 }
648 return total_size <= bufs * s->rxbuf_size;
649}
650
6cdfab28
MT		 651static int
652e1000_can_receive(VLANClientState *nc)
653{
654 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
655
656 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
657}
658
d17161f6
KW		 659static uint64_t rx_desc_base(E1000State *s)
660{
661 uint64_t bah = s->mac_reg[RDBAH];
662 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
663
664 return (bah << 32) + bal;
665}
666
4f1c942b 667static ssize_t
a03e2aec 668e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 669{
a03e2aec 670 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 671 struct e1000_rx_desc desc;
62ecbd35 672 dma_addr_t base;
7c23b892
AZ		 673 unsigned int n, rdt;
674 uint32_t rdh_start;
8f2e8d1f
AL		 675 uint16_t vlan_special = 0;
676 uint8_t vlan_status = 0, vlan_offset = 0;
78aeb23e 677 uint8_t min_buf[MIN_BUF_SIZE];
b19487e2
MT		 678 size_t desc_offset;
679 size_t desc_size;
680 size_t total_size;
7c23b892
AZ		 681
682 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 683 return -1;
7c23b892 684
78aeb23e
SH		 685 /* Pad to minimum Ethernet frame length */
686 if (size < sizeof(min_buf)) {
687 memcpy(min_buf, buf, size);
688 memset(&min_buf[size], 0, sizeof(min_buf) - size);
689 buf = min_buf;
690 size = sizeof(min_buf);
691 }
692
7c23b892 693 if (!receive_filter(s, buf, size))
4f1c942b 694 return size;
7c23b892 695
8f2e8d1f
AL		 696 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
697 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 698 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 699 vlan_status = E1000_RXD_STAT_VP;
700 vlan_offset = 4;
701 size -= 4;
702 }
703
7c23b892 704 rdh_start = s->mac_reg[RDH];
b19487e2
MT		 705 desc_offset = 0;
706 total_size = size + fcs_len(s);
322fd48a
MT		 707 if (!e1000_has_rxbufs(s, total_size)) {
708 set_ics(s, 0, E1000_ICS_RXO);
709 return -1;
710 }
7c23b892 711 do {
b19487e2
MT		 712 desc_size = total_size - desc_offset;
713 if (desc_size > s->rxbuf_size) {
714 desc_size = s->rxbuf_size;
715 }
d17161f6 716 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
62ecbd35 717 pci_dma_read(&s->dev, base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 718 desc.special = vlan_special;
719 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892 720 if (desc.buffer_addr) {
b19487e2
MT		 721 if (desc_offset < size) {
722 size_t copy_size = size - desc_offset;
723 if (copy_size > s->rxbuf_size) {
724 copy_size = s->rxbuf_size;
725 }
62ecbd35
EGM		 726 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
727 (void *)(buf + desc_offset + vlan_offset),
728 copy_size);
b19487e2
MT		 729 }
730 desc_offset += desc_size;
ee912ccf 731 desc.length = cpu_to_le16(desc_size);
b19487e2 732 if (desc_offset >= total_size) {
b19487e2
MT		 733 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
734 } else {
ee912ccf
MT		 735 /* Guest zeroing out status is not a hardware requirement.
736 Clear EOP in case guest didn't do it. */
737 desc.status &= ~E1000_RXD_STAT_EOP;
b19487e2 738 }
43ad7e3e 739 } else { // as per intel docs; skip descriptors with null buf addr
7c23b892 740 DBGOUT(RX, "Null RX descriptor!!\n");
43ad7e3e 741 }
62ecbd35 742 pci_dma_write(&s->dev, base, (void *)&desc, sizeof(desc));
7c23b892
AZ		 743
744 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
745 s->mac_reg[RDH] = 0;
746 s->check_rxov = 1;
747 /* see comment in start_xmit; same here */
748 if (s->mac_reg[RDH] == rdh_start) {
749 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
750 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
751 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 752 return -1;
7c23b892 753 }
b19487e2 754 } while (desc_offset < total_size);
7c23b892
AZ		 755
756 s->mac_reg[GPRC]++;
757 s->mac_reg[TPR]++;
a05e8a6e
MT		 758 /* TOR - Total Octets Received:
759 * This register includes bytes received in a packet from the <Destination
760 * Address> field through the <CRC> field, inclusively.
761 */
762 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
763 if (n < s->mac_reg[TORL])
7c23b892 764 s->mac_reg[TORH]++;
a05e8a6e 765 s->mac_reg[TORL] = n;
7c23b892
AZ		 766
767 n = E1000_ICS_RXT0;
768 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
769 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 770 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
771 s->rxbuf_min_shift)
7c23b892
AZ		 772 n |= E1000_ICS_RXDMT0;
773
774 set_ics(s, 0, n);
4f1c942b
MM		 775
776 return size;
7c23b892
AZ		 777}
778
779static uint32_t
780mac_readreg(E1000State *s, int index)
781{
782 return s->mac_reg[index];
783}
784
785static uint32_t
786mac_icr_read(E1000State *s, int index)
787{
788 uint32_t ret = s->mac_reg[ICR];
789
790 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
791 set_interrupt_cause(s, 0, 0);
792 return ret;
793}
794
795static uint32_t
796mac_read_clr4(E1000State *s, int index)
797{
798 uint32_t ret = s->mac_reg[index];
799
800 s->mac_reg[index] = 0;
801 return ret;
802}
803
804static uint32_t
805mac_read_clr8(E1000State *s, int index)
806{
807 uint32_t ret = s->mac_reg[index];
808
809 s->mac_reg[index] = 0;
810 s->mac_reg[index-1] = 0;
811 return ret;
812}
813
814static void
815mac_writereg(E1000State *s, int index, uint32_t val)
816{
817 s->mac_reg[index] = val;
818}
819
820static void
821set_rdt(E1000State *s, int index, uint32_t val)
822{
823 s->check_rxov = 0;
824 s->mac_reg[index] = val & 0xffff;
825}
826
827static void
828set_16bit(E1000State *s, int index, uint32_t val)
829{
830 s->mac_reg[index] = val & 0xffff;
831}
832
833static void
834set_dlen(E1000State *s, int index, uint32_t val)
835{
836 s->mac_reg[index] = val & 0xfff80;
837}
838
839static void
840set_tctl(E1000State *s, int index, uint32_t val)
841{
842 s->mac_reg[index] = val;
843 s->mac_reg[TDT] &= 0xffff;
844 start_xmit(s);
845}
846
847static void
848set_icr(E1000State *s, int index, uint32_t val)
849{
850 DBGOUT(INTERRUPT, "set_icr %x\n", val);
851 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
852}
853
854static void
855set_imc(E1000State *s, int index, uint32_t val)
856{
857 s->mac_reg[IMS] &= ~val;
858 set_ics(s, 0, 0);
859}
860
861static void
862set_ims(E1000State *s, int index, uint32_t val)
863{
864 s->mac_reg[IMS] |= val;
865 set_ics(s, 0, 0);
866}
867
868#define getreg(x) [x] = mac_readreg
869static uint32_t (*macreg_readops[])(E1000State *, int) = {
870 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
871 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
872 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
873 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 874 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 875 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
876 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 877
878 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
879 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
880 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
881 [CRCERRS ... MPC] = &mac_readreg,
882 [RA ... RA+31] = &mac_readreg,
883 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 884 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 885};
b1503cda 886enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 887
888#define putreg(x) [x] = mac_writereg
889static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
890 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
891 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 892 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 893 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
894 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
895 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
896 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 897 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 898 [RA ... RA+31] = &mac_writereg,
899 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 900 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 901};
b1503cda 902enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 903
904static void
ad00a9b9
AK		 905e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
906 unsigned size)
7c23b892
AZ		 907{
908 E1000State *s = opaque;
8da3ff18 909 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 910
43ad7e3e 911 if (index < NWRITEOPS && macreg_writeops[index]) {
6b59fc74 912 macreg_writeops[index](s, index, val);
43ad7e3e 913 } else if (index < NREADOPS && macreg_readops[index]) {
ad00a9b9 914 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
43ad7e3e 915 } else {
ad00a9b9 916 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
7c23b892 917 index<<2, val);
43ad7e3e 918 }
7c23b892
AZ		 919}
920
ad00a9b9
AK		 921static uint64_t
922e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
7c23b892
AZ		 923{
924 E1000State *s = opaque;
8da3ff18 925 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 926
927 if (index < NREADOPS && macreg_readops[index])
6b59fc74 928 {
32600a30 929 return macreg_readops[index](s, index);
6b59fc74 930 }
7c23b892
AZ		 931 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
932 return 0;
933}
934
ad00a9b9
AK		 935static const MemoryRegionOps e1000_mmio_ops = {
936 .read = e1000_mmio_read,
937 .write = e1000_mmio_write,
938 .endianness = DEVICE_LITTLE_ENDIAN,
939 .impl = {
940 .min_access_size = 4,
941 .max_access_size = 4,
942 },
943};
944
945static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
946 unsigned size)
7c23b892 947{
ad00a9b9
AK		 948 E1000State *s = opaque;
949
950 (void)s;
951 return 0;
7c23b892
AZ		 952}
953
ad00a9b9
AK		 954static void e1000_io_write(void *opaque, target_phys_addr_t addr,
955 uint64_t val, unsigned size)
7c23b892 956{
ad00a9b9
AK		 957 E1000State *s = opaque;
958
959 (void)s;
7c23b892
AZ		 960}
961
ad00a9b9
AK		 962static const MemoryRegionOps e1000_io_ops = {
963 .read = e1000_io_read,
964 .write = e1000_io_write,
965 .endianness = DEVICE_LITTLE_ENDIAN,
966};
967
e482dc3e 968static bool is_version_1(void *opaque, int version_id)
7c23b892 969{
e482dc3e 970 return version_id == 1;
7c23b892
AZ		 971}
972
e482dc3e
JQ		 973static const VMStateDescription vmstate_e1000 = {
974 .name = "e1000",
975 .version_id = 2,
976 .minimum_version_id = 1,
977 .minimum_version_id_old = 1,
978 .fields = (VMStateField []) {
979 VMSTATE_PCI_DEVICE(dev, E1000State),
980 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
981 VMSTATE_UNUSED(4), /* Was mmio_base. */
982 VMSTATE_UINT32(rxbuf_size, E1000State),
983 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
984 VMSTATE_UINT32(eecd_state.val_in, E1000State),
985 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
986 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
987 VMSTATE_UINT16(eecd_state.reading, E1000State),
988 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
989 VMSTATE_UINT8(tx.ipcss, E1000State),
990 VMSTATE_UINT8(tx.ipcso, E1000State),
991 VMSTATE_UINT16(tx.ipcse, E1000State),
992 VMSTATE_UINT8(tx.tucss, E1000State),
993 VMSTATE_UINT8(tx.tucso, E1000State),
994 VMSTATE_UINT16(tx.tucse, E1000State),
995 VMSTATE_UINT32(tx.paylen, E1000State),
996 VMSTATE_UINT8(tx.hdr_len, E1000State),
997 VMSTATE_UINT16(tx.mss, E1000State),
998 VMSTATE_UINT16(tx.size, E1000State),
999 VMSTATE_UINT16(tx.tso_frames, E1000State),
1000 VMSTATE_UINT8(tx.sum_needed, E1000State),
1001 VMSTATE_INT8(tx.ip, E1000State),
1002 VMSTATE_INT8(tx.tcp, E1000State),
1003 VMSTATE_BUFFER(tx.header, E1000State),
1004 VMSTATE_BUFFER(tx.data, E1000State),
1005 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1006 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1007 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1008 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1009 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1010 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1011 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1012 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1013 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1014 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1015 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1016 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1017 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1018 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1019 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1020 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1021 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1022 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1023 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1024 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1025 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1026 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1027 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1028 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1029 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1030 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1031 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1032 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1033 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1034 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1035 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1036 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1037 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1038 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1039 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1040 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1041 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1042 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1043 VMSTATE_UINT32(mac_reg[VET], E1000State),
1044 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1045 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1046 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1047 VMSTATE_END_OF_LIST()
1048 }
1049};
7c23b892 1050
88b4e9db 1051static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 1052 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1053 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1054 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1055 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1056 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1057 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1058 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1059 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1060};
1061
88b4e9db 1062static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 1063 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1064 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1065 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1066 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1067 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 1068 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 1069};
1070
88b4e9db 1071static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 1072 [PBA] = 0x00100030,
1073 [LEDCTL] = 0x602,
1074 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1075 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1076 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1077 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1078 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1079 E1000_STATUS_LU,
1080 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1081 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1082 E1000_MANC_RMCP_EN,
1083};
1084
1085/* PCI interface */
1086
7c23b892 1087static void
ad00a9b9 1088e1000_mmio_setup(E1000State *d)
7c23b892 1089{
f65ed4c1
AL		 1090 int i;
1091 const uint32_t excluded_regs[] = {
1092 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1093 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1094 };
1095
ad00a9b9
AK		 1096 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1097 PNPMMIO_SIZE);
1098 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
f65ed4c1 1099 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
ad00a9b9
AK		 1100 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1101 excluded_regs[i+1] - excluded_regs[i] - 4);
1102 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
7c23b892
AZ		 1103}
1104
b946a153 1105static void
a03e2aec 1106e1000_cleanup(VLANClientState *nc)
b946a153 1107{
a03e2aec 1108 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1109
a03e2aec 1110 s->nic = NULL;
b946a153
AL		 1111}
1112
4b09be85
AL		 1113static int
1114pci_e1000_uninit(PCIDevice *dev)
1115{
7d9e52bd 1116 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85 1117
ad00a9b9
AK		 1118 memory_region_destroy(&d->mmio);
1119 memory_region_destroy(&d->io);
a03e2aec 1120 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1121 return 0;
1122}
1123
32c86e95
BS		 1124static void e1000_reset(void *opaque)
1125{
1126 E1000State *d = opaque;
1127
1128 memset(d->phy_reg, 0, sizeof d->phy_reg);
1129 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1130 memset(d->mac_reg, 0, sizeof d->mac_reg);
1131 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1132 d->rxbuf_min_shift = 1;
1133 memset(&d->tx, 0, sizeof d->tx);
1134}
1135
a03e2aec
MM		 1136static NetClientInfo net_e1000_info = {
1137 .type = NET_CLIENT_TYPE_NIC,
1138 .size = sizeof(NICState),
1139 .can_receive = e1000_can_receive,
1140 .receive = e1000_receive,
1141 .cleanup = e1000_cleanup,
1142 .link_status_changed = e1000_set_link_status,
1143};
1144
81a322d4 1145static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1146{
7d9e52bd 1147 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1148 uint8_t *pci_conf;
7c23b892 1149 uint16_t checksum = 0;
7c23b892 1150 int i;
fbdaa002 1151 uint8_t *macaddr;
aff427a1 1152
7c23b892 1153 pci_conf = d->dev.config;
7c23b892 1154
a9cbacb0
MT		 1155 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1156 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1157
817e0b6f 1158 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
7c23b892 1159
ad00a9b9 1160 e1000_mmio_setup(d);
7c23b892 1161
e824b2cc 1162 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
7c23b892 1163
e824b2cc 1164 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
7c23b892 1165
7c23b892
AZ		 1166 memmove(d->eeprom_data, e1000_eeprom_template,
1167 sizeof e1000_eeprom_template);
fbdaa002
GH		 1168 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1169 macaddr = d->conf.macaddr.a;
7c23b892 1170 for (i = 0; i < 3; i++)
9d07d757 1171 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1172 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1173 checksum += d->eeprom_data[i];
1174 checksum = (uint16_t) EEPROM_SUM - checksum;
1175 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1176
a03e2aec
MM		 1177 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1178 d->dev.qdev.info->name, d->dev.qdev.id, d);
7c23b892 1179
a03e2aec 1180 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1ca4d09a
GN		 1181
1182 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1183
81a322d4 1184 return 0;
9d07d757 1185}
72da4208 1186
fbdaa002
GH		 1187static void qdev_e1000_reset(DeviceState *dev)
1188{
1189 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1190 e1000_reset(d);
1191}
1192
0aab0d3a 1193static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1194 .qdev.name = "e1000",
1195 .qdev.desc = "Intel Gigabit Ethernet",
1196 .qdev.size = sizeof(E1000State),
1197 .qdev.reset = qdev_e1000_reset,
be73cfe2 1198 .qdev.vmsd = &vmstate_e1000,
fbdaa002
GH		 1199 .init = pci_e1000_init,
1200 .exit = pci_e1000_uninit,
5ee8ad71 1201 .romfile = "pxe-e1000.rom",
e72d5c9d
IY		 1202 .vendor_id = PCI_VENDOR_ID_INTEL,
1203 .device_id = E1000_DEVID,
1204 .revision = 0x03,
1205 .class_id = PCI_CLASS_NETWORK_ETHERNET,
fbdaa002
GH		 1206 .qdev.props = (Property[]) {
1207 DEFINE_NIC_PROPERTIES(E1000State, conf),
1208 DEFINE_PROP_END_OF_LIST(),
1209 }
0aab0d3a
GH		 1210};
1211
9d07d757
PB		 1212static void e1000_register_devices(void)
1213{
0aab0d3a 1214 pci_qdev_register(&e1000_info);
7c23b892 1215}
9d07d757
PB		 1216
1217device_init(e1000_register_devices)
Qemu copy for testing