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mips: more fixes to the MIPS interrupt glue logic
[qemu.git] / hw / e1000.c
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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
7c23b892 33
7c23b892
AZ		 34#include "e1000_hw.h"
35
27124888 36#define E1000_DEBUG
7c23b892 37
27124888 38#ifdef E1000_DEBUG
7c23b892
AZ		 39enum {
40 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
41 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
42 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
43 DEBUG_RXFILTER, DEBUG_NOTYET,
44};
45#define DBGBIT(x) (1<<DEBUG_##x)
46static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
47
6c7f4b47 48#define DBGOUT(what, fmt, ...) do { \
7c23b892 49 if (debugflags & DBGBIT(what)) \
6c7f4b47 50 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 51 } while (0)
52#else
6c7f4b47 53#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 54#endif
55
56#define IOPORT_SIZE 0x40
e94bbefe 57#define PNPMMIO_SIZE 0x20000
7c23b892
AZ		 58
59/*
60 * HW models:
61 * E1000_DEV_ID_82540EM works with Windows and Linux
62 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
63 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
64 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
65 * Others never tested
66 */
67enum { E1000_DEVID = E1000_DEV_ID_82540EM };
68
69/*
70 * May need to specify additional MAC-to-PHY entries --
71 * Intel's Windows driver refuses to initialize unless they match
72 */
73enum {
74 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
75 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
76 /* default to E1000_DEV_ID_82540EM */ 0xc20
77};
78
79typedef struct E1000State_st {
80 PCIDevice dev;
a03e2aec 81 NICState *nic;
fbdaa002 82 NICConf conf;
7c23b892
AZ		 83 int mmio_index;
84
85 uint32_t mac_reg[0x8000];
86 uint16_t phy_reg[0x20];
87 uint16_t eeprom_data[64];
88
89 uint32_t rxbuf_size;
90 uint32_t rxbuf_min_shift;
91 int check_rxov;
92 struct e1000_tx {
93 unsigned char header[256];
8f2e8d1f 94 unsigned char vlan_header[4];
b10fec9b 95 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 96 unsigned char vlan[4];
7c23b892
AZ		 97 unsigned char data[0x10000];
98 uint16_t size;
99 unsigned char sum_needed;
8f2e8d1f 100 unsigned char vlan_needed;
7c23b892
AZ		 101 uint8_t ipcss;
102 uint8_t ipcso;
103 uint16_t ipcse;
104 uint8_t tucss;
105 uint8_t tucso;
106 uint16_t tucse;
107 uint8_t hdr_len;
108 uint16_t mss;
109 uint32_t paylen;
110 uint16_t tso_frames;
111 char tse;
b6c4f71f
BS		 112 int8_t ip;
113 int8_t tcp;
1b0009db 114 char cptse; // current packet tse bit
7c23b892
AZ		 115 } tx;
116
117 struct {
118 uint32_t val_in; // shifted in from guest driver
119 uint16_t bitnum_in;
120 uint16_t bitnum_out;
121 uint16_t reading;
122 uint32_t old_eecd;
123 } eecd_state;
124} E1000State;
125
126#define defreg(x) x = (E1000_##x>>2)
127enum {
128 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
129 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
130 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
131 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
132 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
133 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
134 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
135 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
136 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 137 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
138 defreg(VET),
7c23b892
AZ		 139};
140
141enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 142static const char phy_regcap[0x20] = {
7c23b892
AZ		 143 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
144 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
145 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
146 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
147 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 148 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 149};
150
151static void
6e355d90
IY		 152ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
153 pcibus_t size, int type)
7c23b892 154{
89e8b13c
IY		 155 DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
156 " size=0x%08"FMT_PCIBUS"\n", addr, size);
7c23b892
AZ		 157}
158
159static void
160set_interrupt_cause(E1000State *s, int index, uint32_t val)
161{
162 if (val)
163 val |= E1000_ICR_INT_ASSERTED;
164 s->mac_reg[ICR] = val;
b1332393 165 s->mac_reg[ICS] = val;
bc26e55a 166 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 167}
168
169static void
170set_ics(E1000State *s, int index, uint32_t val)
171{
172 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
173 s->mac_reg[IMS]);
174 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
175}
176
177static int
178rxbufsize(uint32_t v)
179{
180 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
181 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
182 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
183 switch (v) {
184 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
185 return 16384;
186 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
187 return 8192;
188 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
189 return 4096;
190 case E1000_RCTL_SZ_1024:
191 return 1024;
192 case E1000_RCTL_SZ_512:
193 return 512;
194 case E1000_RCTL_SZ_256:
195 return 256;
196 }
197 return 2048;
198}
199
cab3c825
KW		 200static void
201set_ctrl(E1000State *s, int index, uint32_t val)
202{
203 /* RST is self clearing */
204 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
205}
206
7c23b892
AZ		 207static void
208set_rx_control(E1000State *s, int index, uint32_t val)
209{
210 s->mac_reg[RCTL] = val;
211 s->rxbuf_size = rxbufsize(val);
212 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
213 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
214 s->mac_reg[RCTL]);
215}
216
217static void
218set_mdic(E1000State *s, int index, uint32_t val)
219{
220 uint32_t data = val & E1000_MDIC_DATA_MASK;
221 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
222
223 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
224 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
225 else if (val & E1000_MDIC_OP_READ) {
226 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
227 if (!(phy_regcap[addr] & PHY_R)) {
228 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
229 val |= E1000_MDIC_ERROR;
230 } else
231 val = (val ^ data) | s->phy_reg[addr];
232 } else if (val & E1000_MDIC_OP_WRITE) {
233 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
234 if (!(phy_regcap[addr] & PHY_W)) {
235 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
236 val |= E1000_MDIC_ERROR;
237 } else
238 s->phy_reg[addr] = data;
239 }
240 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
241 set_ics(s, 0, E1000_ICR_MDAC);
242}
243
244static uint32_t
245get_eecd(E1000State *s, int index)
246{
247 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
248
249 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
250 s->eecd_state.bitnum_out, s->eecd_state.reading);
251 if (!s->eecd_state.reading ||
252 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
253 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
254 ret |= E1000_EECD_DO;
255 return ret;
256}
257
258static void
259set_eecd(E1000State *s, int index, uint32_t val)
260{
261 uint32_t oldval = s->eecd_state.old_eecd;
262
263 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
264 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 265 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
266 return;
267 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
268 s->eecd_state.val_in = 0;
269 s->eecd_state.bitnum_in = 0;
270 s->eecd_state.bitnum_out = 0;
271 s->eecd_state.reading = 0;
272 }
7c23b892
AZ		 273 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
274 return;
275 if (!(E1000_EECD_SK & val)) { // falling edge
276 s->eecd_state.bitnum_out++;
277 return;
278 }
7c23b892
AZ		 279 s->eecd_state.val_in <<= 1;
280 if (val & E1000_EECD_DI)
281 s->eecd_state.val_in |= 1;
282 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
283 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
284 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
285 EEPROM_READ_OPCODE_MICROWIRE);
286 }
287 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
288 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
289 s->eecd_state.reading);
290}
291
292static uint32_t
293flash_eerd_read(E1000State *s, int x)
294{
295 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
296
b1332393
BP		 297 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
298 return (s->mac_reg[EERD]);
299
7c23b892 300 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 301 return (E1000_EEPROM_RW_REG_DONE | r);
302
303 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
304 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 305}
306
7c23b892
AZ		 307static void
308putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
309{
c6a6a5e3
AL		 310 uint32_t sum;
311
7c23b892
AZ		 312 if (cse && cse < n)
313 n = cse + 1;
c6a6a5e3
AL		 314 if (sloc < n-1) {
315 sum = net_checksum_add(n-css, data+css);
7c23b892 316 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 317 net_checksum_finish(sum));
318 }
7c23b892
AZ		 319}
320
8f2e8d1f
AL		 321static inline int
322vlan_enabled(E1000State *s)
323{
324 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
325}
326
327static inline int
328vlan_rx_filter_enabled(E1000State *s)
329{
330 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
331}
332
333static inline int
334is_vlan_packet(E1000State *s, const uint8_t *buf)
335{
336 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
337 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
338}
339
340static inline int
341is_vlan_txd(uint32_t txd_lower)
342{
343 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
344}
345
7c23b892
AZ		 346static void
347xmit_seg(E1000State *s)
348{
349 uint16_t len, *sp;
350 unsigned int frames = s->tx.tso_frames, css, sofar, n;
351 struct e1000_tx *tp = &s->tx;
352
1b0009db 353 if (tp->tse && tp->cptse) {
7c23b892
AZ		 354 css = tp->ipcss;
355 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
356 frames, tp->size, css);
357 if (tp->ip) { // IPv4
358 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
359 tp->size - css);
360 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
361 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
362 } else // IPv6
363 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
364 tp->size - css);
365 css = tp->tucss;
366 len = tp->size - css;
367 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
368 if (tp->tcp) {
369 sofar = frames * tp->mss;
370 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 371 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 372 if (tp->paylen - sofar > tp->mss)
373 tp->data[css + 13] &= ~9; // PSH, FIN
374 } else // UDP
375 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
376 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
377 // add pseudo-header length before checksum calculation
378 sp = (uint16_t *)(tp->data + tp->tucso);
379 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
380 }
381 tp->tso_frames++;
382 }
383
384 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
385 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
386 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
387 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 388 if (tp->vlan_needed) {
b10fec9b
SW		 389 memmove(tp->vlan, tp->data, 4);
390 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 391 memcpy(tp->data + 8, tp->vlan_header, 4);
a03e2aec 392 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
8f2e8d1f 393 } else
a03e2aec 394 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
7c23b892
AZ		 395 s->mac_reg[TPT]++;
396 s->mac_reg[GPTC]++;
397 n = s->mac_reg[TOTL];
398 if ((s->mac_reg[TOTL] += s->tx.size) < n)
399 s->mac_reg[TOTH]++;
400}
401
402static void
403process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
404{
405 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
406 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
407 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
408 unsigned int msh = 0xfffff, hdr = 0;
409 uint64_t addr;
410 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
411 struct e1000_tx *tp = &s->tx;
412
413 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
414 op = le32_to_cpu(xp->cmd_and_length);
415 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
416 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
417 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
418 tp->tucss = xp->upper_setup.tcp_fields.tucss;
419 tp->tucso = xp->upper_setup.tcp_fields.tucso;
420 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
421 tp->paylen = op & 0xfffff;
422 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
423 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
424 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
425 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
426 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
427 tp->tso_frames = 0;
428 if (tp->tucso == 0) { // this is probably wrong
429 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
430 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
431 }
432 return;
1b0009db
AZ		 433 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
434 // data descriptor
7c23b892 435 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
1b0009db
AZ		 436 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
437 } else
438 // legacy descriptor
439 tp->cptse = 0;
7c23b892 440
8f2e8d1f
AL		 441 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
442 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
443 tp->vlan_needed = 1;
444 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
445 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
446 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
447 le16_to_cpu(dp->upper.fields.special));
448 }
449
7c23b892 450 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 451 if (tp->tse && tp->cptse) {
7c23b892
AZ		 452 hdr = tp->hdr_len;
453 msh = hdr + tp->mss;
1b0009db
AZ		 454 do {
455 bytes = split_size;
456 if (tp->size + bytes > msh)
457 bytes = msh - tp->size;
458 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
459 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
460 memmove(tp->header, tp->data, hdr);
461 tp->size = sz;
462 addr += bytes;
463 if (sz == msh) {
464 xmit_seg(s);
465 memmove(tp->data, tp->header, hdr);
466 tp->size = hdr;
467 }
468 } while (split_size -= bytes);
469 } else if (!tp->tse && tp->cptse) {
470 // context descriptor TSE is not set, while data descriptor TSE is set
471 DBGOUT(TXERR, "TCP segmentaion Error\n");
472 } else {
473 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
474 tp->size += split_size;
7c23b892 475 }
7c23b892
AZ		 476
477 if (!(txd_lower & E1000_TXD_CMD_EOP))
478 return;
1b0009db 479 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 480 xmit_seg(s);
481 tp->tso_frames = 0;
482 tp->sum_needed = 0;
8f2e8d1f 483 tp->vlan_needed = 0;
7c23b892 484 tp->size = 0;
1b0009db 485 tp->cptse = 0;
7c23b892
AZ		 486}
487
488static uint32_t
c227f099 489txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 490{
491 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
492
493 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
494 return 0;
495 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
496 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
497 dp->upper.data = cpu_to_le32(txd_upper);
498 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
499 (void *)&dp->upper, sizeof(dp->upper));
500 return E1000_ICR_TXDW;
501}
502
503static void
504start_xmit(E1000State *s)
505{
c227f099 506 target_phys_addr_t base;
7c23b892
AZ		 507 struct e1000_tx_desc desc;
508 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
509
510 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
511 DBGOUT(TX, "tx disabled\n");
512 return;
513 }
514
515 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
516 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
517 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
518 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
519
520 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 521 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 522 desc.upper.data);
523
524 process_tx_desc(s, &desc);
525 cause |= txdesc_writeback(base, &desc);
526
527 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
528 s->mac_reg[TDH] = 0;
529 /*
530 * the following could happen only if guest sw assigns
531 * bogus values to TDT/TDLEN.
532 * there's nothing too intelligent we could do about this.
533 */
534 if (s->mac_reg[TDH] == tdh_start) {
535 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
536 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
537 break;
538 }
539 }
540 set_ics(s, 0, cause);
541}
542
543static int
544receive_filter(E1000State *s, const uint8_t *buf, int size)
545{
af2960f9
BS		 546 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
547 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 548 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
549
8f2e8d1f
AL		 550 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
551 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
552 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
553 ((vid >> 5) & 0x7f));
554 if ((vfta & (1 << (vid & 0x1f))) == 0)
555 return 0;
556 }
557
7c23b892
AZ		 558 if (rctl & E1000_RCTL_UPE) // promiscuous
559 return 1;
560
561 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
562 return 1;
563
564 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
565 return 1;
566
567 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
568 if (!(rp[1] & E1000_RAH_AV))
569 continue;
570 ra[0] = cpu_to_le32(rp[0]);
571 ra[1] = cpu_to_le32(rp[1]);
572 if (!memcmp(buf, (uint8_t *)ra, 6)) {
573 DBGOUT(RXFILTER,
574 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
575 (int)(rp - s->mac_reg - RA)/2,
576 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
577 return 1;
578 }
579 }
580 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
581 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
582
583 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
584 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
585 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
586 return 1;
587 DBGOUT(RXFILTER,
588 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
589 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
590 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
591 s->mac_reg[MTA + (f >> 5)]);
592
593 return 0;
594}
595
99ed7e30 596static void
a03e2aec 597e1000_set_link_status(VLANClientState *nc)
99ed7e30 598{
a03e2aec 599 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 600 uint32_t old_status = s->mac_reg[STATUS];
601
a03e2aec 602 if (nc->link_down)
99ed7e30
AL		 603 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
604 else
605 s->mac_reg[STATUS] |= E1000_STATUS_LU;
606
607 if (s->mac_reg[STATUS] != old_status)
608 set_ics(s, 0, E1000_ICR_LSC);
609}
610
7c23b892 611static int
a03e2aec 612e1000_can_receive(VLANClientState *nc)
7c23b892 613{
a03e2aec 614 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 615
4105de67 616 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
7c23b892
AZ		 617}
618
4f1c942b 619static ssize_t
a03e2aec 620e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 621{
a03e2aec 622 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 623 struct e1000_rx_desc desc;
c227f099 624 target_phys_addr_t base;
7c23b892
AZ		 625 unsigned int n, rdt;
626 uint32_t rdh_start;
8f2e8d1f
AL		 627 uint16_t vlan_special = 0;
628 uint8_t vlan_status = 0, vlan_offset = 0;
7c23b892
AZ		 629
630 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 631 return -1;
7c23b892
AZ		 632
633 if (size > s->rxbuf_size) {
cda9046b
MM		 634 DBGOUT(RX, "packet too large for buffers (%lu > %d)\n",
635 (unsigned long)size, s->rxbuf_size);
4f1c942b 636 return -1;
7c23b892
AZ		 637 }
638
639 if (!receive_filter(s, buf, size))
4f1c942b 640 return size;
7c23b892 641
8f2e8d1f
AL		 642 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
643 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 644 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 645 vlan_status = E1000_RXD_STAT_VP;
646 vlan_offset = 4;
647 size -= 4;
648 }
649
7c23b892
AZ		 650 rdh_start = s->mac_reg[RDH];
651 size += 4; // for the header
652 do {
653 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
654 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 655 return -1;
7c23b892
AZ		 656 }
657 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
658 sizeof(desc) * s->mac_reg[RDH];
659 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 660 desc.special = vlan_special;
661 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892
AZ		 662 if (desc.buffer_addr) {
663 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
8f2e8d1f 664 (void *)(buf + vlan_offset), size);
7c23b892
AZ		 665 desc.length = cpu_to_le16(size);
666 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
667 } else // as per intel docs; skip descriptors with null buf addr
668 DBGOUT(RX, "Null RX descriptor!!\n");
669 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
670
671 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
672 s->mac_reg[RDH] = 0;
673 s->check_rxov = 1;
674 /* see comment in start_xmit; same here */
675 if (s->mac_reg[RDH] == rdh_start) {
676 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
677 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
678 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 679 return -1;
7c23b892
AZ		 680 }
681 } while (desc.buffer_addr == 0);
682
683 s->mac_reg[GPRC]++;
684 s->mac_reg[TPR]++;
685 n = s->mac_reg[TORL];
686 if ((s->mac_reg[TORL] += size) < n)
687 s->mac_reg[TORH]++;
688
689 n = E1000_ICS_RXT0;
690 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
691 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 692 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
693 s->rxbuf_min_shift)
7c23b892
AZ		 694 n |= E1000_ICS_RXDMT0;
695
696 set_ics(s, 0, n);
4f1c942b
MM		 697
698 return size;
7c23b892
AZ		 699}
700
701static uint32_t
702mac_readreg(E1000State *s, int index)
703{
704 return s->mac_reg[index];
705}
706
707static uint32_t
708mac_icr_read(E1000State *s, int index)
709{
710 uint32_t ret = s->mac_reg[ICR];
711
712 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
713 set_interrupt_cause(s, 0, 0);
714 return ret;
715}
716
717static uint32_t
718mac_read_clr4(E1000State *s, int index)
719{
720 uint32_t ret = s->mac_reg[index];
721
722 s->mac_reg[index] = 0;
723 return ret;
724}
725
726static uint32_t
727mac_read_clr8(E1000State *s, int index)
728{
729 uint32_t ret = s->mac_reg[index];
730
731 s->mac_reg[index] = 0;
732 s->mac_reg[index-1] = 0;
733 return ret;
734}
735
736static void
737mac_writereg(E1000State *s, int index, uint32_t val)
738{
739 s->mac_reg[index] = val;
740}
741
742static void
743set_rdt(E1000State *s, int index, uint32_t val)
744{
745 s->check_rxov = 0;
746 s->mac_reg[index] = val & 0xffff;
747}
748
749static void
750set_16bit(E1000State *s, int index, uint32_t val)
751{
752 s->mac_reg[index] = val & 0xffff;
753}
754
755static void
756set_dlen(E1000State *s, int index, uint32_t val)
757{
758 s->mac_reg[index] = val & 0xfff80;
759}
760
761static void
762set_tctl(E1000State *s, int index, uint32_t val)
763{
764 s->mac_reg[index] = val;
765 s->mac_reg[TDT] &= 0xffff;
766 start_xmit(s);
767}
768
769static void
770set_icr(E1000State *s, int index, uint32_t val)
771{
772 DBGOUT(INTERRUPT, "set_icr %x\n", val);
773 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
774}
775
776static void
777set_imc(E1000State *s, int index, uint32_t val)
778{
779 s->mac_reg[IMS] &= ~val;
780 set_ics(s, 0, 0);
781}
782
783static void
784set_ims(E1000State *s, int index, uint32_t val)
785{
786 s->mac_reg[IMS] |= val;
787 set_ics(s, 0, 0);
788}
789
790#define getreg(x) [x] = mac_readreg
791static uint32_t (*macreg_readops[])(E1000State *, int) = {
792 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
793 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
794 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
795 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 796 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 797 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
798 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 799
800 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
801 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
802 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
803 [CRCERRS ... MPC] = &mac_readreg,
804 [RA ... RA+31] = &mac_readreg,
805 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 806 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 807};
b1503cda 808enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 809
810#define putreg(x) [x] = mac_writereg
811static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
812 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
813 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 814 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 815 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
816 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
817 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
818 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 819 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 820 [RA ... RA+31] = &mac_writereg,
821 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 822 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 823};
b1503cda 824enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 825
826static void
c227f099 827e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 828{
829 E1000State *s = opaque;
8da3ff18 830 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 831
6b59fc74
AJ		 832#ifdef TARGET_WORDS_BIGENDIAN
833 val = bswap32(val);
834#endif
7c23b892 835 if (index < NWRITEOPS && macreg_writeops[index])
6b59fc74 836 macreg_writeops[index](s, index, val);
7c23b892
AZ		 837 else if (index < NREADOPS && macreg_readops[index])
838 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
839 else
840 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
841 index<<2, val);
842}
843
844static void
c227f099 845e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 846{
847 // emulate hw without byte enables: no RMW
848 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 849 (val & 0xffff) << (8*(addr & 3)));
7c23b892
AZ		 850}
851
852static void
c227f099 853e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 854{
855 // emulate hw without byte enables: no RMW
856 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 857 (val & 0xff) << (8*(addr & 3)));
7c23b892
AZ		 858}
859
860static uint32_t
c227f099 861e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
7c23b892
AZ		 862{
863 E1000State *s = opaque;
8da3ff18 864 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 865
866 if (index < NREADOPS && macreg_readops[index])
6b59fc74
AJ		 867 {
868 uint32_t val = macreg_readops[index](s, index);
869#ifdef TARGET_WORDS_BIGENDIAN
870 val = bswap32(val);
871#endif
872 return val;
873 }
7c23b892
AZ		 874 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
875 return 0;
876}
877
878static uint32_t
c227f099 879e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
7c23b892 880{
6b59fc74 881 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
7c23b892
AZ		 882 (8 * (addr & 3))) & 0xff;
883}
884
885static uint32_t
c227f099 886e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
7c23b892 887{
6b59fc74
AJ		 888 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
889 (8 * (addr & 3))) & 0xffff;
7c23b892
AZ		 890}
891
e482dc3e 892static bool is_version_1(void *opaque, int version_id)
7c23b892 893{
e482dc3e 894 return version_id == 1;
7c23b892
AZ		 895}
896
e482dc3e
JQ		 897static const VMStateDescription vmstate_e1000 = {
898 .name = "e1000",
899 .version_id = 2,
900 .minimum_version_id = 1,
901 .minimum_version_id_old = 1,
902 .fields = (VMStateField []) {
903 VMSTATE_PCI_DEVICE(dev, E1000State),
904 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
905 VMSTATE_UNUSED(4), /* Was mmio_base. */
906 VMSTATE_UINT32(rxbuf_size, E1000State),
907 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
908 VMSTATE_UINT32(eecd_state.val_in, E1000State),
909 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
910 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
911 VMSTATE_UINT16(eecd_state.reading, E1000State),
912 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
913 VMSTATE_UINT8(tx.ipcss, E1000State),
914 VMSTATE_UINT8(tx.ipcso, E1000State),
915 VMSTATE_UINT16(tx.ipcse, E1000State),
916 VMSTATE_UINT8(tx.tucss, E1000State),
917 VMSTATE_UINT8(tx.tucso, E1000State),
918 VMSTATE_UINT16(tx.tucse, E1000State),
919 VMSTATE_UINT32(tx.paylen, E1000State),
920 VMSTATE_UINT8(tx.hdr_len, E1000State),
921 VMSTATE_UINT16(tx.mss, E1000State),
922 VMSTATE_UINT16(tx.size, E1000State),
923 VMSTATE_UINT16(tx.tso_frames, E1000State),
924 VMSTATE_UINT8(tx.sum_needed, E1000State),
925 VMSTATE_INT8(tx.ip, E1000State),
926 VMSTATE_INT8(tx.tcp, E1000State),
927 VMSTATE_BUFFER(tx.header, E1000State),
928 VMSTATE_BUFFER(tx.data, E1000State),
929 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
930 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
931 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
932 VMSTATE_UINT32(mac_reg[EECD], E1000State),
933 VMSTATE_UINT32(mac_reg[EERD], E1000State),
934 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
935 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
936 VMSTATE_UINT32(mac_reg[ICR], E1000State),
937 VMSTATE_UINT32(mac_reg[ICS], E1000State),
938 VMSTATE_UINT32(mac_reg[IMC], E1000State),
939 VMSTATE_UINT32(mac_reg[IMS], E1000State),
940 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
941 VMSTATE_UINT32(mac_reg[MANC], E1000State),
942 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
943 VMSTATE_UINT32(mac_reg[MPC], E1000State),
944 VMSTATE_UINT32(mac_reg[PBA], E1000State),
945 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
946 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
947 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
948 VMSTATE_UINT32(mac_reg[RDH], E1000State),
949 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
950 VMSTATE_UINT32(mac_reg[RDT], E1000State),
951 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
952 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
953 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
954 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
955 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
956 VMSTATE_UINT32(mac_reg[TDH], E1000State),
957 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
958 VMSTATE_UINT32(mac_reg[TDT], E1000State),
959 VMSTATE_UINT32(mac_reg[TORH], E1000State),
960 VMSTATE_UINT32(mac_reg[TORL], E1000State),
961 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
962 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
963 VMSTATE_UINT32(mac_reg[TPR], E1000State),
964 VMSTATE_UINT32(mac_reg[TPT], E1000State),
965 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
966 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
967 VMSTATE_UINT32(mac_reg[VET], E1000State),
968 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
969 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
970 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
971 VMSTATE_END_OF_LIST()
972 }
973};
7c23b892 974
88b4e9db 975static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 976 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
977 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
978 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
979 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
980 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
981 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
982 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
983 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
984};
985
88b4e9db 986static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 987 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
988 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
989 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
990 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
991 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 992 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 993};
994
88b4e9db 995static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 996 [PBA] = 0x00100030,
997 [LEDCTL] = 0x602,
998 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
999 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1000 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1001 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1002 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1003 E1000_STATUS_LU,
1004 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1005 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1006 E1000_MANC_RMCP_EN,
1007};
1008
1009/* PCI interface */
1010
d60efc6b 1011static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
7c23b892
AZ		 1012 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1013};
1014
d60efc6b 1015static CPUReadMemoryFunc * const e1000_mmio_read[] = {
7c23b892
AZ		 1016 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1017};
1018
1019static void
1020e1000_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 1021 pcibus_t addr, pcibus_t size, int type)
7c23b892 1022{
7d9e52bd 1023 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
f65ed4c1
AL		 1024 int i;
1025 const uint32_t excluded_regs[] = {
1026 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1027 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1028 };
1029
7c23b892 1030
89e8b13c
IY		 1031 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
1032 addr, size);
7c23b892 1033
7c23b892 1034 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
f65ed4c1
AL		 1035 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1036
1037 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1038 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1039 excluded_regs[i + 1] -
1040 excluded_regs[i] - 4);
7c23b892
AZ		 1041}
1042
b946a153 1043static void
a03e2aec 1044e1000_cleanup(VLANClientState *nc)
b946a153 1045{
a03e2aec 1046 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1047
a03e2aec 1048 s->nic = NULL;
b946a153
AL		 1049}
1050
4b09be85
AL		 1051static int
1052pci_e1000_uninit(PCIDevice *dev)
1053{
7d9e52bd 1054 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85
AL		 1055
1056 cpu_unregister_io_memory(d->mmio_index);
a03e2aec 1057 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1058 return 0;
1059}
1060
32c86e95
BS		 1061static void e1000_reset(void *opaque)
1062{
1063 E1000State *d = opaque;
1064
1065 memset(d->phy_reg, 0, sizeof d->phy_reg);
1066 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1067 memset(d->mac_reg, 0, sizeof d->mac_reg);
1068 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1069 d->rxbuf_min_shift = 1;
1070 memset(&d->tx, 0, sizeof d->tx);
1071}
1072
a03e2aec
MM		 1073static NetClientInfo net_e1000_info = {
1074 .type = NET_CLIENT_TYPE_NIC,
1075 .size = sizeof(NICState),
1076 .can_receive = e1000_can_receive,
1077 .receive = e1000_receive,
1078 .cleanup = e1000_cleanup,
1079 .link_status_changed = e1000_set_link_status,
1080};
1081
81a322d4 1082static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1083{
7d9e52bd 1084 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1085 uint8_t *pci_conf;
7c23b892 1086 uint16_t checksum = 0;
7c23b892 1087 int i;
fbdaa002 1088 uint8_t *macaddr;
aff427a1 1089
7c23b892 1090 pci_conf = d->dev.config;
7c23b892 1091
deb54399
AL		 1092 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1093 pci_config_set_device_id(pci_conf, E1000_DEVID);
a9cbacb0
MT		 1094 /* TODO: we have no capabilities, so why is this bit set? */
1095 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
1096 pci_conf[PCI_REVISION_ID] = 0x03;
173a543b 1097 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
a9cbacb0
MT		 1098 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1099 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1100
a9cbacb0
MT		 1101 /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */
1102 pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
7c23b892 1103
1eed09cb 1104 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
7c23b892
AZ		 1105 e1000_mmio_write, d);
1106
28c2c264 1107 pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
0392a017 1108 PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
7c23b892 1109
28c2c264 1110 pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE,
0392a017 1111 PCI_BASE_ADDRESS_SPACE_IO, ioport_map);
7c23b892 1112
7c23b892
AZ		 1113 memmove(d->eeprom_data, e1000_eeprom_template,
1114 sizeof e1000_eeprom_template);
fbdaa002
GH		 1115 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1116 macaddr = d->conf.macaddr.a;
7c23b892 1117 for (i = 0; i < 3; i++)
9d07d757 1118 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1119 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1120 checksum += d->eeprom_data[i];
1121 checksum = (uint16_t) EEPROM_SUM - checksum;
1122 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1123
a03e2aec
MM		 1124 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1125 d->dev.qdev.info->name, d->dev.qdev.id, d);
7c23b892 1126
a03e2aec 1127 qemu_format_nic_info_str(&d->nic->nc, macaddr);
81a322d4 1128 return 0;
9d07d757 1129}
72da4208 1130
fbdaa002
GH		 1131static void qdev_e1000_reset(DeviceState *dev)
1132{
1133 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1134 e1000_reset(d);
1135}
1136
0aab0d3a 1137static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1138 .qdev.name = "e1000",
1139 .qdev.desc = "Intel Gigabit Ethernet",
1140 .qdev.size = sizeof(E1000State),
1141 .qdev.reset = qdev_e1000_reset,
be73cfe2 1142 .qdev.vmsd = &vmstate_e1000,
fbdaa002
GH		 1143 .init = pci_e1000_init,
1144 .exit = pci_e1000_uninit,
8c52c8f3 1145 .romfile = "pxe-e1000.bin",
fbdaa002
GH		 1146 .qdev.props = (Property[]) {
1147 DEFINE_NIC_PROPERTIES(E1000State, conf),
1148 DEFINE_PROP_END_OF_LIST(),
1149 }
0aab0d3a
GH		 1150};
1151
9d07d757
PB		 1152static void e1000_register_devices(void)
1153{
0aab0d3a 1154 pci_qdev_register(&e1000_info);
7c23b892 1155}
9d07d757
PB		 1156
1157device_init(e1000_register_devices)
Qemu copy for testing