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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
4 | * Copyright (c) 2006-2007 Stefan Weil | |
5 | * | |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
23 | * PXE boot (i386) no valid link | |
24 | * Linux networking (i386) ok | |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
34 | */ | |
35 | ||
36 | #if defined(TARGET_I386) | |
37 | # warning "PXE boot still not working!" | |
38 | #endif | |
39 | ||
663e8e51 | 40 | #include <stddef.h> /* offsetof */ |
b84a5c6f | 41 | #include <stdbool.h> |
87ecb68b PB |
42 | #include "hw.h" |
43 | #include "pci.h" | |
44 | #include "net.h" | |
663e8e51 TS |
45 | #include "eeprom93xx.h" |
46 | ||
47 | /* Common declarations for all PCI devices. */ | |
48 | ||
663e8e51 TS |
49 | #define PCI_CONFIG_8(offset, value) \ |
50 | (pci_conf[offset] = (value)) | |
51 | #define PCI_CONFIG_16(offset, value) \ | |
52 | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) | |
53 | #define PCI_CONFIG_32(offset, value) \ | |
54 | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) | |
55 | ||
56 | #define KiB 1024 | |
57 | ||
aac443e6 | 58 | /* Debug EEPRO100 card. */ |
663e8e51 TS |
59 | //~ #define DEBUG_EEPRO100 |
60 | ||
61 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 62 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 63 | #else |
001faf32 | 64 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
65 | #endif |
66 | ||
67 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
68 | #define INT 1 /* interrupt related actions */ |
69 | #define MDI 1 /* mdi related actions */ | |
70 | #define OTHER 1 | |
71 | #define RXTX 1 | |
72 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
73 | |
74 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
75 | ||
7f1e9d4e | 76 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
77 | |
78 | #define MAX_ETH_FRAME_SIZE 1514 | |
79 | ||
80 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 81 | #define i82550 0x82550 |
663e8e51 | 82 | #define i82551 0x82551 |
c4c270e2 | 83 | #define i82557A 0x82557a |
663e8e51 TS |
84 | #define i82557B 0x82557b |
85 | #define i82557C 0x82557c | |
c4c270e2 | 86 | #define i82558A 0x82558a |
663e8e51 | 87 | #define i82558B 0x82558b |
c4c270e2 SW |
88 | #define i82559A 0x82559a |
89 | #define i82559B 0x82559b | |
663e8e51 TS |
90 | #define i82559C 0x82559c |
91 | #define i82559ER 0x82559e | |
92 | #define i82562 0x82562 | |
93 | ||
aac443e6 | 94 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
95 | #define EEPROM_SIZE 64 |
96 | ||
97 | #define PCI_MEM_SIZE (4 * KiB) | |
98 | #define PCI_IO_SIZE 64 | |
99 | #define PCI_FLASH_SIZE (128 * KiB) | |
100 | ||
101 | #define BIT(n) (1 << (n)) | |
102 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
103 | ||
104 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
105 | #define CU_NOP 0x0000 /* No operation. */ | |
106 | #define CU_START 0x0010 /* CU start. */ | |
107 | #define CU_RESUME 0x0020 /* CU resume. */ | |
108 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
109 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
110 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
111 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
112 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
113 | ||
114 | #define RU_NOP 0x0000 | |
115 | #define RX_START 0x0001 | |
116 | #define RX_RESUME 0x0002 | |
117 | #define RX_ABORT 0x0004 | |
118 | #define RX_ADDR_LOAD 0x0006 | |
119 | #define RX_RESUMENR 0x0007 | |
120 | #define INT_MASK 0x0100 | |
121 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
122 | ||
663e8e51 TS |
123 | /* Offsets to the various registers. |
124 | All accesses need not be longword aligned. */ | |
125 | enum speedo_offsets { | |
126 | SCBStatus = 0, | |
127 | SCBAck = 1, | |
128 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
129 | SCBIntmask = 3, | |
130 | SCBPointer = 4, /* General purpose pointer. */ | |
131 | SCBPort = 8, /* Misc. commands and operands. */ | |
132 | SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ | |
133 | SCBCtrlMDI = 16, /* MDI interface control. */ | |
134 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
3257d2b6 | 135 | SCBFlow = 24, |
663e8e51 TS |
136 | }; |
137 | ||
138 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
139 | typedef struct { | |
140 | uint16_t status; | |
141 | uint16_t command; | |
142 | uint32_t link; /* void * */ | |
143 | uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */ | |
144 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ | |
145 | uint8_t tx_threshold; /* transmit threshold */ | |
146 | uint8_t tbd_count; /* TBD number */ | |
147 | //~ /* This constitutes two "TBD" entries: hdr and data */ | |
148 | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
149 | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
150 | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
151 | //~ int32_t tx_buf_size1; /* Length of Tx data. */ | |
c227f099 | 152 | } eepro100_tx_t; |
663e8e51 TS |
153 | |
154 | /* Receive frame descriptor. */ | |
155 | typedef struct { | |
156 | int16_t status; | |
157 | uint16_t command; | |
158 | uint32_t link; /* struct RxFD * */ | |
159 | uint32_t rx_buf_addr; /* void * */ | |
160 | uint16_t count; | |
161 | uint16_t size; | |
162 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 163 | } eepro100_rx_t; |
663e8e51 TS |
164 | |
165 | typedef struct { | |
166 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
167 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, | |
168 | tx_multiple_collisions, tx_total_collisions; | |
169 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, | |
170 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, | |
171 | rx_short_frame_errors; | |
172 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; | |
173 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
174 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
175 | uint32_t reserved[4]; | |
c227f099 | 176 | } eepro100_stats_t; |
663e8e51 TS |
177 | |
178 | typedef enum { | |
179 | cu_idle = 0, | |
180 | cu_suspended = 1, | |
181 | cu_active = 2, | |
182 | cu_lpq_active = 2, | |
183 | cu_hqp_active = 3 | |
c227f099 | 184 | } cu_state_t; |
663e8e51 TS |
185 | |
186 | typedef enum { | |
187 | ru_idle = 0, | |
188 | ru_suspended = 1, | |
189 | ru_no_resources = 2, | |
190 | ru_ready = 4 | |
c227f099 | 191 | } ru_state_t; |
663e8e51 | 192 | |
663e8e51 | 193 | typedef struct { |
273a2142 | 194 | PCIDevice dev; |
663e8e51 TS |
195 | uint8_t mult[8]; /* multicast mask array */ |
196 | int mmio_index; | |
e00e365e | 197 | NICState *nic; |
508ef936 | 198 | NICConf conf; |
663e8e51 TS |
199 | uint8_t scb_stat; /* SCB stat/ack byte */ |
200 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 201 | /* region must not be saved by nic_save. */ |
663e8e51 | 202 | uint32_t region[3]; /* PCI region addresses */ |
663e8e51 | 203 | uint16_t mdimem[32]; |
c227f099 | 204 | eeprom_t *eeprom; |
663e8e51 TS |
205 | uint32_t device; /* device variant */ |
206 | uint32_t pointer; | |
207 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
208 | uint32_t cu_base; /* CU base address */ | |
209 | uint32_t cu_offset; /* CU address offset */ | |
210 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
211 | uint32_t ru_base; /* RU base address */ | |
212 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 213 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 SW |
214 | |
215 | /* Statistical counters. Also used for wake-up packet (i82559). */ | |
216 | eepro100_stats_t statistics; | |
217 | ||
663e8e51 TS |
218 | #if 0 |
219 | uint16_t status; | |
220 | #endif | |
221 | ||
222 | /* Configuration bytes. */ | |
223 | uint8_t configuration[22]; | |
224 | ||
225 | /* Data in mem is always in the byte order of the controller (le). */ | |
226 | uint8_t mem[PCI_MEM_SIZE]; | |
151b2986 JQ |
227 | /* vmstate for each particular nic */ |
228 | VMStateDescription *vmstate; | |
ba42b646 SW |
229 | |
230 | /* Quasi static device properties (no need to save them). */ | |
231 | uint16_t stats_size; | |
232 | bool has_extended_tcb_support; | |
663e8e51 TS |
233 | } EEPRO100State; |
234 | ||
235 | /* Default values for MDI (PHY) registers */ | |
236 | static const uint16_t eepro100_mdi_default[] = { | |
237 | /* MDI Registers 0 - 6, 7 */ | |
238 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
239 | /* MDI Registers 8 - 15 */ | |
240 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
241 | /* MDI Registers 16 - 31 */ | |
242 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
243 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
244 | }; | |
245 | ||
246 | /* Readonly mask for MDI (PHY) registers */ | |
247 | static const uint16_t eepro100_mdi_mask[] = { | |
248 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
249 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
250 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
251 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
252 | }; | |
253 | ||
ba42b646 SW |
254 | /* XXX: optimize */ |
255 | static void stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
256 | { | |
257 | val = cpu_to_le32(val); | |
258 | cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); | |
259 | } | |
260 | ||
663e8e51 TS |
261 | #define POLYNOMIAL 0x04c11db6 |
262 | ||
263 | /* From FreeBSD */ | |
264 | /* XXX: optimize */ | |
265 | static int compute_mcast_idx(const uint8_t * ep) | |
266 | { | |
267 | uint32_t crc; | |
268 | int carry, i, j; | |
269 | uint8_t b; | |
270 | ||
271 | crc = 0xffffffff; | |
272 | for (i = 0; i < 6; i++) { | |
273 | b = *ep++; | |
274 | for (j = 0; j < 8; j++) { | |
275 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
276 | crc <<= 1; | |
277 | b >>= 1; | |
aac443e6 | 278 | if (carry) { |
663e8e51 | 279 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 280 | } |
663e8e51 TS |
281 | } |
282 | } | |
283 | return (crc >> 26); | |
284 | } | |
285 | ||
286 | #if defined(DEBUG_EEPRO100) | |
287 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
288 | { | |
289 | static char dump[3 * 16 + 1]; | |
290 | char *p = &dump[0]; | |
aac443e6 | 291 | if (size > 16) { |
663e8e51 | 292 | size = 16; |
aac443e6 | 293 | } |
663e8e51 TS |
294 | while (size-- > 0) { |
295 | p += sprintf(p, " %02x", *buf++); | |
296 | } | |
297 | return dump; | |
298 | } | |
299 | #endif /* DEBUG_EEPRO100 */ | |
300 | ||
301 | enum scb_stat_ack { | |
302 | stat_ack_not_ours = 0x00, | |
303 | stat_ack_sw_gen = 0x04, | |
304 | stat_ack_rnr = 0x10, | |
305 | stat_ack_cu_idle = 0x20, | |
306 | stat_ack_frame_rx = 0x40, | |
307 | stat_ack_cu_cmd_done = 0x80, | |
308 | stat_ack_not_present = 0xFF, | |
309 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
310 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
311 | }; | |
312 | ||
313 | static void disable_interrupt(EEPRO100State * s) | |
314 | { | |
315 | if (s->int_stat) { | |
aac443e6 | 316 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 317 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
318 | s->int_stat = 0; |
319 | } | |
320 | } | |
321 | ||
322 | static void enable_interrupt(EEPRO100State * s) | |
323 | { | |
324 | if (!s->int_stat) { | |
aac443e6 | 325 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 326 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
327 | s->int_stat = 1; |
328 | } | |
329 | } | |
330 | ||
331 | static void eepro100_acknowledge(EEPRO100State * s) | |
332 | { | |
333 | s->scb_stat &= ~s->mem[SCBAck]; | |
334 | s->mem[SCBAck] = s->scb_stat; | |
335 | if (s->scb_stat == 0) { | |
336 | disable_interrupt(s); | |
337 | } | |
338 | } | |
339 | ||
340 | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) | |
341 | { | |
342 | uint8_t mask = ~s->mem[SCBIntmask]; | |
343 | s->mem[SCBAck] |= stat; | |
344 | stat = s->scb_stat = s->mem[SCBAck]; | |
345 | stat &= (mask | 0x0f); | |
346 | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf); | |
347 | if (stat && (mask & 0x01)) { | |
348 | /* SCB mask and SCB Bit M do not disable interrupt. */ | |
349 | enable_interrupt(s); | |
350 | } else if (s->int_stat) { | |
351 | disable_interrupt(s); | |
352 | } | |
353 | } | |
354 | ||
355 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
356 | { | |
357 | /* CU completed action command. */ | |
358 | /* Transmit not ok (82557 only, not in emulation). */ | |
359 | eepro100_interrupt(s, 0x80); | |
360 | } | |
361 | ||
362 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
363 | { | |
364 | /* CU left the active state. */ | |
365 | eepro100_interrupt(s, 0x20); | |
366 | } | |
367 | ||
368 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
369 | { | |
370 | /* RU received a complete frame. */ | |
371 | eepro100_interrupt(s, 0x40); | |
372 | } | |
373 | ||
374 | #if 0 | |
375 | static void eepro100_rnr_interrupt(EEPRO100State * s) | |
376 | { | |
377 | /* RU is not ready. */ | |
378 | eepro100_interrupt(s, 0x10); | |
379 | } | |
380 | #endif | |
381 | ||
382 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
383 | { | |
384 | /* MDI completed read or write cycle. */ | |
385 | eepro100_interrupt(s, 0x08); | |
386 | } | |
387 | ||
388 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
389 | { | |
390 | /* Software has requested an interrupt. */ | |
391 | eepro100_interrupt(s, 0x04); | |
392 | } | |
393 | ||
394 | #if 0 | |
395 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
396 | { | |
397 | /* Flow control pause interrupt (82558 and later). */ | |
398 | eepro100_interrupt(s, 0x01); | |
399 | } | |
400 | #endif | |
401 | ||
402 | static void pci_reset(EEPRO100State * s) | |
403 | { | |
404 | uint32_t device = s->device; | |
273a2142 | 405 | uint8_t *pci_conf = s->dev.config; |
ba42b646 | 406 | bool power_management = 1; |
663e8e51 | 407 | |
aac443e6 | 408 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
409 | |
410 | /* PCI Vendor ID */ | |
deb54399 | 411 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
d6fd1e66 | 412 | /* PCI Device ID depends on device and is set below. */ |
663e8e51 | 413 | /* PCI Command */ |
508cc6b4 | 414 | /* TODO: this is the default, do not override. */ |
663e8e51 TS |
415 | PCI_CONFIG_16(PCI_COMMAND, 0x0000); |
416 | /* PCI Status */ | |
508cc6b4 | 417 | /* TODO: Value at RST# should be 0. */ |
61702408 | 418 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); |
663e8e51 TS |
419 | /* PCI Revision ID */ |
420 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
508cc6b4 | 421 | /* TODO: this is the default, do not override. */ |
663e8e51 | 422 | /* PCI Class Code */ |
508cc6b4 | 423 | PCI_CONFIG_8(PCI_CLASS_PROG, 0x00); |
173a543b | 424 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 TS |
425 | /* PCI Cache Line Size */ |
426 | /* check cache line size!!! */ | |
427 | //~ PCI_CONFIG_8(0x0c, 0x00); | |
428 | /* PCI Latency Timer */ | |
508cc6b4 | 429 | PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks |
663e8e51 TS |
430 | /* PCI Header Type */ |
431 | /* BIST (built-in self test) */ | |
432 | #if defined(TARGET_I386) | |
433 | // !!! workaround for buggy bios | |
0392a017 | 434 | //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0 |
663e8e51 TS |
435 | #endif |
436 | #if 0 | |
437 | /* PCI Base Address Registers */ | |
438 | /* CSR Memory Mapped Base Address */ | |
439 | PCI_CONFIG_32(PCI_BASE_ADDRESS_0, | |
0392a017 IY |
440 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
441 | PCI_BASE_ADDRESS_MEM_PREFETCH); | |
663e8e51 | 442 | /* CSR I/O Mapped Base Address */ |
0392a017 | 443 | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO); |
663e8e51 TS |
444 | #if 0 |
445 | /* Flash Memory Mapped Base Address */ | |
0392a017 IY |
446 | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, |
447 | 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY); | |
663e8e51 TS |
448 | #endif |
449 | #endif | |
450 | /* Expansion ROM Base Address (depends on boot disable!!!) */ | |
508cc6b4 MT |
451 | /* TODO: not needed, set when BAR is registered */ |
452 | PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
663e8e51 | 453 | /* Capability Pointer */ |
508cc6b4 MT |
454 | /* TODO: revisions with power_management 1 use this but |
455 | * do not set new capability list bit in status register. */ | |
456 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc); | |
aac443e6 | 457 | /* Interrupt Line */ |
663e8e51 | 458 | /* Interrupt Pin */ |
508cc6b4 MT |
459 | /* TODO: RST# value should be 0 */ |
460 | PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0 | |
663e8e51 | 461 | /* Minimum Grant */ |
508cc6b4 | 462 | PCI_CONFIG_8(PCI_MIN_GNT, 0x08); |
663e8e51 | 463 | /* Maximum Latency */ |
508cc6b4 | 464 | PCI_CONFIG_8(PCI_MAX_LAT, 0x18); |
663e8e51 TS |
465 | |
466 | switch (device) { | |
ba42b646 SW |
467 | case i82550: |
468 | // TODO: check device id. | |
469 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
470 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ | |
471 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
472 | // TODO: check size of statistical counters. | |
473 | s->stats_size = 80; | |
474 | // TODO: check extended tcb support. | |
475 | s->has_extended_tcb_support = 1; | |
476 | break; | |
663e8e51 | 477 | case i82551: |
d6fd1e66 | 478 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
ba42b646 | 479 | /* Revision ID: 0x0f, 0x10. */ |
663e8e51 | 480 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
ba42b646 SW |
481 | // TODO: check size of statistical counters. |
482 | s->stats_size = 80; | |
483 | s->has_extended_tcb_support = 1; | |
484 | break; | |
485 | case i82557A: | |
486 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
487 | PCI_CONFIG_8(PCI_REVISION_ID, 0x01); | |
508cc6b4 | 488 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 | 489 | power_management = 0; |
663e8e51 TS |
490 | break; |
491 | case i82557B: | |
d6fd1e66 | 492 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 493 | PCI_CONFIG_8(PCI_REVISION_ID, 0x02); |
508cc6b4 | 494 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 | 495 | power_management = 0; |
663e8e51 TS |
496 | break; |
497 | case i82557C: | |
d6fd1e66 | 498 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 499 | PCI_CONFIG_8(PCI_REVISION_ID, 0x03); |
508cc6b4 | 500 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 SW |
501 | power_management = 0; |
502 | break; | |
503 | case i82558A: | |
504 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
505 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
506 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
507 | PCI_CONFIG_8(PCI_REVISION_ID, 0x04); |
508 | s->stats_size = 76; | |
509 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
510 | break; |
511 | case i82558B: | |
d6fd1e66 | 512 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
508cc6b4 MT |
513 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
514 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
663e8e51 | 515 | PCI_CONFIG_8(PCI_REVISION_ID, 0x05); |
ba42b646 SW |
516 | s->stats_size = 76; |
517 | s->has_extended_tcb_support = 1; | |
518 | break; | |
519 | case i82559A: | |
520 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
521 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
522 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
523 | PCI_CONFIG_8(PCI_REVISION_ID, 0x06); |
524 | s->stats_size = 80; | |
525 | s->has_extended_tcb_support = 1; | |
526 | break; | |
527 | case i82559B: | |
528 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
529 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
530 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
531 | PCI_CONFIG_8(PCI_REVISION_ID, 0x07); |
532 | s->stats_size = 80; | |
533 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
534 | break; |
535 | case i82559C: | |
d6fd1e66 | 536 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
508cc6b4 MT |
537 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
538 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
539 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); |
540 | // TODO: Windows wants revision id 0x0c. | |
541 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0c); | |
542 | #if EEPROM_SIZE > 0 | |
543 | PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086); | |
544 | PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040); | |
545 | #endif | |
546 | s->stats_size = 80; | |
547 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
548 | break; |
549 | case i82559ER: | |
d6fd1e66 | 550 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
508cc6b4 MT |
551 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
552 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
663e8e51 | 553 | PCI_CONFIG_8(PCI_REVISION_ID, 0x09); |
ba42b646 SW |
554 | s->stats_size = 80; |
555 | s->has_extended_tcb_support = 1; | |
556 | break; | |
557 | case i82562: | |
558 | // TODO: check device id. | |
559 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
560 | /* TODO: wrong revision id. */ | |
561 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
562 | s->stats_size = 80; | |
563 | s->has_extended_tcb_support = 1; | |
663e8e51 | 564 | break; |
663e8e51 TS |
565 | default: |
566 | logout("Device %X is undefined!\n", device); | |
567 | } | |
568 | ||
ba42b646 SW |
569 | s->configuration[6] |= BIT(5); |
570 | ||
571 | if (s->stats_size == 80) { | |
572 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
573 | if (s->configuration[6] & BIT(2)) { | |
574 | /* TCO statistical counters. */ | |
575 | assert(s->configuration[6] & BIT(5)); | |
576 | } else { | |
577 | if (s->configuration[6] & BIT(5)) { | |
578 | /* No extended statistical counters, i82557 compatible. */ | |
579 | s->stats_size = 64; | |
580 | } else { | |
581 | /* i82558 compatible. */ | |
582 | s->stats_size = 76; | |
583 | } | |
584 | } | |
585 | } else { | |
586 | if (s->configuration[6] & BIT(5)) { | |
587 | /* No extended statistical counters. */ | |
588 | s->stats_size = 64; | |
589 | } | |
590 | } | |
591 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
592 | ||
593 | if (power_management) { | |
594 | /* Power Management Capabilities */ | |
595 | PCI_CONFIG_8(0xdc, 0x01); | |
596 | /* Next Item Pointer */ | |
597 | /* Capability ID */ | |
598 | PCI_CONFIG_16(0xde, 0x7e21); | |
599 | /* TODO: Power Management Control / Status. */ | |
600 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
601 | } | |
602 | ||
603 | #if EEPROM_SIZE > 0 | |
663e8e51 | 604 | if (device == i82557C || device == i82558B || device == i82559C) { |
ba42b646 SW |
605 | // TODO: get vendor id from EEPROM for i82557C or later. |
606 | // TODO: get device id from EEPROM for i82557C or later. | |
607 | // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
608 | // TODO: header type is determined by EEPROM for i82559. | |
609 | // TODO: get subsystem id from EEPROM for i82557C or later. | |
610 | // TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
611 | // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
612 | // TODO: capability pointer depends on EEPROM for i82558. | |
663e8e51 TS |
613 | logout("Get device id and revision from EEPROM!!!\n"); |
614 | } | |
ba42b646 | 615 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
616 | } |
617 | ||
618 | static void nic_selective_reset(EEPRO100State * s) | |
619 | { | |
620 | size_t i; | |
621 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
622 | //~ eeprom93xx_reset(s->eeprom); | |
508ef936 | 623 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
663e8e51 | 624 | eeprom_contents[0xa] = 0x4000; |
f4e94dfe URCB |
625 | if (s->device == i82557B || s->device == i82557C) |
626 | eeprom_contents[5] = 0x0100; | |
663e8e51 TS |
627 | uint16_t sum = 0; |
628 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
629 | sum += eeprom_contents[i]; | |
630 | } | |
631 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 632 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
633 | |
634 | memset(s->mem, 0, sizeof(s->mem)); | |
635 | uint32_t val = BIT(21); | |
636 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
637 | ||
638 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
639 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
640 | } | |
641 | ||
642 | static void nic_reset(void *opaque) | |
643 | { | |
769cf7a5 | 644 | EEPRO100State *s = opaque; |
aac443e6 | 645 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
646 | nic_selective_reset(s); |
647 | } | |
648 | ||
649 | #if defined(DEBUG_EEPRO100) | |
b8f6ba0d | 650 | static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
651 | "Command/Status", |
652 | "General Pointer", | |
653 | "Port", | |
654 | "EEPROM/Flash Control", | |
655 | "MDI Control", | |
656 | "Receive DMA Byte Count", | |
b8f6ba0d | 657 | "Flow Control", |
663e8e51 TS |
658 | "General Status/Control" |
659 | }; | |
660 | ||
661 | static char *regname(uint32_t addr) | |
662 | { | |
ec169288 | 663 | static char buf[32]; |
663e8e51 | 664 | if (addr < PCI_IO_SIZE) { |
b8f6ba0d | 665 | const char *r = e100_reg[addr / 4]; |
663e8e51 | 666 | if (r != 0) { |
41cbc23c | 667 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 668 | } else { |
41cbc23c | 669 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
670 | } |
671 | } else { | |
41cbc23c | 672 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
673 | } |
674 | return buf; | |
675 | } | |
676 | #endif /* DEBUG_EEPRO100 */ | |
677 | ||
678 | #if 0 | |
679 | static uint16_t eepro100_read_status(EEPRO100State * s) | |
680 | { | |
681 | uint16_t val = s->status; | |
aac443e6 | 682 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
683 | return val; |
684 | } | |
685 | ||
686 | static void eepro100_write_status(EEPRO100State * s, uint16_t val) | |
687 | { | |
aac443e6 | 688 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
689 | s->status = val; |
690 | } | |
691 | #endif | |
692 | ||
693 | /***************************************************************************** | |
694 | * | |
695 | * Command emulation. | |
696 | * | |
697 | ****************************************************************************/ | |
698 | ||
699 | #if 0 | |
700 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
701 | { | |
702 | uint16_t val = 0xffff; | |
aac443e6 | 703 | //~ TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
704 | return val; |
705 | } | |
706 | #endif | |
707 | ||
708 | /* Commands that can be put in a command list entry. */ | |
709 | enum commands { | |
710 | CmdNOp = 0, | |
711 | CmdIASetup = 1, | |
712 | CmdConfigure = 2, | |
713 | CmdMulticastList = 3, | |
714 | CmdTx = 4, | |
715 | CmdTDR = 5, /* load microcode */ | |
716 | CmdDump = 6, | |
717 | CmdDiagnose = 7, | |
718 | ||
719 | /* And some extra flags: */ | |
720 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
721 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
722 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
723 | }; | |
724 | ||
c227f099 | 725 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 TS |
726 | { |
727 | return ((s->mem[SCBStatus] >> 6) & 0x03); | |
728 | } | |
729 | ||
c227f099 | 730 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 TS |
731 | { |
732 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); | |
733 | } | |
734 | ||
c227f099 | 735 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 TS |
736 | { |
737 | return ((s->mem[SCBStatus] >> 2) & 0x0f); | |
738 | } | |
739 | ||
c227f099 | 740 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 TS |
741 | { |
742 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); | |
743 | } | |
744 | ||
745 | static void dump_statistics(EEPRO100State * s) | |
746 | { | |
747 | /* Dump statistical data. Most data is never changed by the emulation | |
748 | * and always 0, so we first just copy the whole block and then those | |
749 | * values which really matter. | |
750 | * Number of data should check configuration!!! | |
751 | */ | |
ba42b646 SW |
752 | cpu_physical_memory_write(s->statsaddr, |
753 | (uint8_t *) & s->statistics, s->stats_size); | |
754 | stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
755 | stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
756 | stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
757 | stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
758 | //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
759 | //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
663e8e51 TS |
760 | //~ missing("CU dump statistical counters"); |
761 | } | |
762 | ||
5fa9a0ae | 763 | static void action_command(EEPRO100State *s) |
663e8e51 | 764 | { |
5fa9a0ae SW |
765 | for (;;) { |
766 | uint32_t cb_address = s->cu_base + s->cu_offset; | |
767 | eepro100_tx_t tx; | |
663e8e51 TS |
768 | cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx)); |
769 | uint16_t status = le16_to_cpu(tx.status); | |
770 | uint16_t command = le16_to_cpu(tx.command); | |
771 | logout | |
772 | ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
773 | val, status, command, tx.link); | |
774 | bool bit_el = ((command & 0x8000) != 0); | |
775 | bool bit_s = ((command & 0x4000) != 0); | |
776 | bool bit_i = ((command & 0x2000) != 0); | |
777 | bool bit_nc = ((command & 0x0010) != 0); | |
7f1e9d4e | 778 | bool success = true; |
663e8e51 TS |
779 | //~ bool bit_sf = ((command & 0x0008) != 0); |
780 | uint16_t cmd = command & 0x0007; | |
781 | s->cu_offset = le32_to_cpu(tx.link); | |
782 | switch (cmd) { | |
783 | case CmdNOp: | |
784 | /* Do nothing. */ | |
785 | break; | |
786 | case CmdIASetup: | |
508ef936 | 787 | cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6); |
aac443e6 | 788 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6))); |
663e8e51 TS |
789 | break; |
790 | case CmdConfigure: | |
791 | cpu_physical_memory_read(cb_address + 8, &s->configuration[0], | |
792 | sizeof(s->configuration)); | |
aac443e6 | 793 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
794 | break; |
795 | case CmdMulticastList: | |
796 | //~ missing("multicast list"); | |
797 | break; | |
798 | case CmdTx: | |
799 | (void)0; | |
800 | uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); | |
801 | uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff); | |
aac443e6 | 802 | TRACE(RXTX, logout |
663e8e51 | 803 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", |
aac443e6 | 804 | tbd_array, tcb_bytes, tx.tbd_count)); |
7f1e9d4e KW |
805 | |
806 | if (bit_nc) { | |
807 | missing("CmdTx: NC = 0"); | |
808 | success = false; | |
809 | break; | |
810 | } | |
663e8e51 | 811 | //~ assert(!bit_sf); |
7f1e9d4e KW |
812 | if (tcb_bytes > 2600) { |
813 | logout("TCB byte count too large, using 2600\n"); | |
814 | tcb_bytes = 2600; | |
815 | } | |
663e8e51 TS |
816 | /* Next assertion fails for local configuration. */ |
817 | //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff)); | |
818 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
819 | logout | |
820 | ("illegal values of TBD array address and TCB byte count!\n"); | |
821 | } | |
24e6f355 RD |
822 | // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes |
823 | uint8_t buf[2600]; | |
663e8e51 TS |
824 | uint16_t size = 0; |
825 | uint32_t tbd_address = cb_address + 0x10; | |
826 | assert(tcb_bytes <= sizeof(buf)); | |
827 | while (size < tcb_bytes) { | |
828 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
829 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
830 | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
831 | tbd_address += 8; | |
aac443e6 | 832 | TRACE(RXTX, logout |
663e8e51 | 833 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 834 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 835 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
836 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
837 | tx_buffer_size); | |
838 | size += tx_buffer_size; | |
839 | } | |
840 | if (tbd_array == 0xffffffff) { | |
841 | /* Simplified mode. Was already handled by code above. */ | |
842 | } else { | |
843 | /* Flexible mode. */ | |
844 | uint8_t tbd_count = 0; | |
ba42b646 | 845 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { |
3f9cb1c1 | 846 | /* Extended Flexible TCB. */ |
663e8e51 TS |
847 | for (; tbd_count < 2; tbd_count++) { |
848 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
849 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
850 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
851 | tbd_address += 8; | |
aac443e6 | 852 | TRACE(RXTX, logout |
3f9cb1c1 | 853 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 854 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 855 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
856 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
857 | tx_buffer_size); | |
858 | size += tx_buffer_size; | |
859 | if (tx_buffer_el & 1) { | |
860 | break; | |
861 | } | |
862 | } | |
863 | } | |
864 | tbd_address = tbd_array; | |
865 | for (; tbd_count < tx.tbd_count; tbd_count++) { | |
866 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
867 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
868 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
869 | tbd_address += 8; | |
aac443e6 | 870 | TRACE(RXTX, logout |
663e8e51 | 871 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", |
aac443e6 | 872 | tx_buffer_address, tx_buffer_size)); |
24e6f355 | 873 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); |
663e8e51 TS |
874 | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
875 | tx_buffer_size); | |
876 | size += tx_buffer_size; | |
877 | if (tx_buffer_el & 1) { | |
878 | break; | |
879 | } | |
880 | } | |
881 | } | |
aac443e6 | 882 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); |
e00e365e | 883 | qemu_send_packet(&s->nic->nc, buf, size); |
663e8e51 TS |
884 | s->statistics.tx_good_frames++; |
885 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
886 | * (82557 only). Emulation never has bad status. */ | |
887 | //~ eepro100_cx_interrupt(s); | |
888 | break; | |
889 | case CmdTDR: | |
aac443e6 | 890 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
891 | /* Starting with offset 8, the command contains |
892 | * 64 dwords microcode which we just ignore here. */ | |
893 | break; | |
894 | default: | |
895 | missing("undefined command"); | |
7f1e9d4e KW |
896 | success = false; |
897 | break; | |
663e8e51 | 898 | } |
7f1e9d4e KW |
899 | /* Write new status. */ |
900 | stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0)); | |
663e8e51 TS |
901 | if (bit_i) { |
902 | /* CU completed action. */ | |
903 | eepro100_cx_interrupt(s); | |
904 | } | |
905 | if (bit_el) { | |
aac443e6 | 906 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
907 | set_cu_state(s, cu_idle); |
908 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 909 | break; |
663e8e51 | 910 | } else if (bit_s) { |
5fa9a0ae | 911 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
912 | set_cu_state(s, cu_suspended); |
913 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 914 | break; |
663e8e51 TS |
915 | } else { |
916 | /* More entries in list. */ | |
aac443e6 | 917 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 918 | } |
5fa9a0ae SW |
919 | } |
920 | TRACE(OTHER, logout("CU list empty\n")); | |
921 | /* List is empty. Now CU is idle or suspended. */ | |
922 | } | |
923 | ||
924 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
925 | { | |
926 | switch (val) { | |
927 | case CU_NOP: | |
928 | /* No operation. */ | |
929 | break; | |
930 | case CU_START: | |
931 | if (get_cu_state(s) != cu_idle) { | |
932 | /* Intel documentation says that CU must be idle for the CU | |
933 | * start command. Intel driver for Linux also starts the CU | |
934 | * from suspended state. */ | |
935 | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle); | |
936 | //~ assert(!"wrong CU state"); | |
937 | } | |
938 | set_cu_state(s, cu_active); | |
939 | s->cu_offset = s->pointer; | |
940 | action_command(s); | |
663e8e51 TS |
941 | break; |
942 | case CU_RESUME: | |
943 | if (get_cu_state(s) != cu_suspended) { | |
944 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
945 | /* Workaround for bad Linux eepro100 driver which resumes | |
946 | * from idle state. */ | |
947 | //~ missing("cu resume"); | |
948 | set_cu_state(s, cu_suspended); | |
949 | } | |
950 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 951 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 952 | set_cu_state(s, cu_active); |
5fa9a0ae | 953 | action_command(s); |
663e8e51 TS |
954 | } |
955 | break; | |
956 | case CU_STATSADDR: | |
957 | /* Load dump counters address. */ | |
958 | s->statsaddr = s->pointer; | |
aac443e6 | 959 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
960 | break; |
961 | case CU_SHOWSTATS: | |
962 | /* Dump statistical counters. */ | |
aac443e6 | 963 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 964 | dump_statistics(s); |
ba42b646 | 965 | stl_le_phys(s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
966 | break; |
967 | case CU_CMD_BASE: | |
968 | /* Load CU base. */ | |
aac443e6 | 969 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
970 | s->cu_base = s->pointer; |
971 | break; | |
972 | case CU_DUMPSTATS: | |
973 | /* Dump and reset statistical counters. */ | |
aac443e6 | 974 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 975 | dump_statistics(s); |
ba42b646 | 976 | stl_le_phys(s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
977 | memset(&s->statistics, 0, sizeof(s->statistics)); |
978 | break; | |
979 | case CU_SRESUME: | |
980 | /* CU static resume. */ | |
981 | missing("CU static resume"); | |
982 | break; | |
983 | default: | |
984 | missing("Undefined CU command"); | |
985 | } | |
986 | } | |
987 | ||
988 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
989 | { | |
990 | switch (val) { | |
991 | case RU_NOP: | |
992 | /* No operation. */ | |
993 | break; | |
994 | case RX_START: | |
995 | /* RU start. */ | |
996 | if (get_ru_state(s) != ru_idle) { | |
997 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
998 | //~ assert(!"wrong RU state"); | |
999 | } | |
1000 | set_ru_state(s, ru_ready); | |
1001 | s->ru_offset = s->pointer; | |
aac443e6 | 1002 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
1003 | break; |
1004 | case RX_RESUME: | |
1005 | /* Restart RU. */ | |
1006 | if (get_ru_state(s) != ru_suspended) { | |
1007 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
1008 | ru_suspended); | |
1009 | //~ assert(!"wrong RU state"); | |
1010 | } | |
1011 | set_ru_state(s, ru_ready); | |
1012 | break; | |
1013 | case RX_ADDR_LOAD: | |
1014 | /* Load RU base. */ | |
aac443e6 | 1015 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
1016 | s->ru_base = s->pointer; |
1017 | break; | |
1018 | default: | |
1019 | logout("val=0x%02x (undefined RU command)\n", val); | |
1020 | missing("Undefined SU command"); | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1025 | { | |
1026 | eepro100_ru_command(s, val & 0x0f); | |
1027 | eepro100_cu_command(s, val & 0xf0); | |
1028 | if ((val) == 0) { | |
aac443e6 | 1029 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1030 | } |
1031 | /* Clear command byte after command was accepted. */ | |
1032 | s->mem[SCBCmd] = 0; | |
1033 | } | |
1034 | ||
1035 | /***************************************************************************** | |
1036 | * | |
1037 | * EEPROM emulation. | |
1038 | * | |
1039 | ****************************************************************************/ | |
1040 | ||
1041 | #define EEPROM_CS 0x02 | |
1042 | #define EEPROM_SK 0x01 | |
1043 | #define EEPROM_DI 0x04 | |
1044 | #define EEPROM_DO 0x08 | |
1045 | ||
1046 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1047 | { | |
1048 | uint16_t val; | |
1049 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
1050 | if (eeprom93xx_read(s->eeprom)) { | |
1051 | val |= EEPROM_DO; | |
1052 | } else { | |
1053 | val &= ~EEPROM_DO; | |
1054 | } | |
aac443e6 | 1055 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1056 | return val; |
1057 | } | |
1058 | ||
c227f099 | 1059 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1060 | { |
aac443e6 | 1061 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1062 | |
1063 | /* mask unwriteable bits */ | |
1064 | //~ val = SET_MASKED(val, 0x31, eeprom->value); | |
1065 | ||
1066 | int eecs = ((val & EEPROM_CS) != 0); | |
1067 | int eesk = ((val & EEPROM_SK) != 0); | |
1068 | int eedi = ((val & EEPROM_DI) != 0); | |
1069 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1070 | } | |
1071 | ||
1072 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
1073 | { | |
1074 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 1075 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
1076 | } |
1077 | ||
1078 | /***************************************************************************** | |
1079 | * | |
1080 | * MDI emulation. | |
1081 | * | |
1082 | ****************************************************************************/ | |
1083 | ||
1084 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1085 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1086 | "opcode 0", |
1087 | "write", | |
1088 | "read", | |
1089 | "opcode 3" | |
1090 | }; | |
1091 | ||
6a0b9cc9 | 1092 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1093 | "Control", |
1094 | "Status", | |
1095 | "PHY Identification (Word 1)", | |
1096 | "PHY Identification (Word 2)", | |
1097 | "Auto-Negotiation Advertisement", | |
1098 | "Auto-Negotiation Link Partner Ability", | |
1099 | "Auto-Negotiation Expansion" | |
1100 | }; | |
aac443e6 SW |
1101 | |
1102 | static const char *reg2name(uint8_t reg) | |
1103 | { | |
1104 | static char buffer[10]; | |
1105 | const char *p = buffer; | |
1106 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1107 | p = mdi_reg_name[reg]; | |
1108 | } else { | |
1109 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1110 | } | |
1111 | return p; | |
1112 | } | |
663e8e51 TS |
1113 | #endif /* DEBUG_EEPRO100 */ |
1114 | ||
1115 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1116 | { | |
1117 | uint32_t val; | |
1118 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
1119 | ||
1120 | #ifdef DEBUG_EEPRO100 | |
1121 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1122 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1123 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1124 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1125 | uint16_t data = (val & BITS(15, 0)); | |
1126 | #endif | |
1127 | /* Emulation takes no time to finish MDI transaction. */ | |
1128 | val |= BIT(28); | |
1129 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1130 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1131 | reg2name(reg), data)); |
663e8e51 TS |
1132 | return val; |
1133 | } | |
1134 | ||
663e8e51 TS |
1135 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1136 | { | |
1137 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1138 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1139 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1140 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1141 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1142 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1143 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1144 | if (phy != 1) { |
1145 | /* Unsupported PHY address. */ | |
1146 | //~ logout("phy must be 1 but is %u\n", phy); | |
1147 | data = 0; | |
1148 | } else if (opcode != 1 && opcode != 2) { | |
1149 | /* Unsupported opcode. */ | |
1150 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1151 | data = 0; | |
1152 | } else if (reg > 6) { | |
1153 | /* Unsupported register. */ | |
1154 | logout("register must be 0...6 but is %u\n", reg); | |
1155 | data = 0; | |
1156 | } else { | |
1157 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1158 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1159 | reg2name(reg), data)); |
663e8e51 TS |
1160 | if (opcode == 1) { |
1161 | /* MDI write */ | |
1162 | switch (reg) { | |
1163 | case 0: /* Control Register */ | |
1164 | if (data & 0x8000) { | |
1165 | /* Reset status and control registers to default. */ | |
1166 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1167 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1168 | data = s->mdimem[reg]; | |
1169 | } else { | |
1170 | /* Restart Auto Configuration = Normal Operation */ | |
1171 | data &= ~0x0200; | |
1172 | } | |
1173 | break; | |
1174 | case 1: /* Status Register */ | |
1175 | missing("not writable"); | |
1176 | data = s->mdimem[reg]; | |
1177 | break; | |
1178 | case 2: /* PHY Identification Register (Word 1) */ | |
1179 | case 3: /* PHY Identification Register (Word 2) */ | |
1180 | missing("not implemented"); | |
1181 | break; | |
1182 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1183 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1184 | break; | |
1185 | case 6: /* Auto-Negotiation Expansion Register */ | |
1186 | default: | |
1187 | missing("not implemented"); | |
1188 | } | |
1189 | s->mdimem[reg] = data; | |
1190 | } else if (opcode == 2) { | |
1191 | /* MDI read */ | |
1192 | switch (reg) { | |
1193 | case 0: /* Control Register */ | |
1194 | if (data & 0x8000) { | |
1195 | /* Reset status and control registers to default. */ | |
1196 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1197 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1198 | } | |
1199 | break; | |
1200 | case 1: /* Status Register */ | |
1201 | s->mdimem[reg] |= 0x0020; | |
1202 | break; | |
1203 | case 2: /* PHY Identification Register (Word 1) */ | |
1204 | case 3: /* PHY Identification Register (Word 2) */ | |
1205 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1206 | break; | |
1207 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1208 | s->mdimem[reg] = 0x41fe; | |
1209 | break; | |
1210 | case 6: /* Auto-Negotiation Expansion Register */ | |
1211 | s->mdimem[reg] = 0x0001; | |
1212 | break; | |
1213 | } | |
1214 | data = s->mdimem[reg]; | |
1215 | } | |
1216 | /* Emulation takes no time to finish MDI transaction. | |
1217 | * Set MDI bit in SCB status register. */ | |
1218 | s->mem[SCBAck] |= 0x08; | |
1219 | val |= BIT(28); | |
1220 | if (raiseint) { | |
1221 | eepro100_mdi_interrupt(s); | |
1222 | } | |
1223 | } | |
1224 | val = (val & 0xffff0000) + data; | |
1225 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1226 | } | |
1227 | ||
1228 | /***************************************************************************** | |
1229 | * | |
1230 | * Port emulation. | |
1231 | * | |
1232 | ****************************************************************************/ | |
1233 | ||
1234 | #define PORT_SOFTWARE_RESET 0 | |
1235 | #define PORT_SELFTEST 1 | |
1236 | #define PORT_SELECTIVE_RESET 2 | |
1237 | #define PORT_DUMP 3 | |
1238 | #define PORT_SELECTION_MASK 3 | |
1239 | ||
1240 | typedef struct { | |
1241 | uint32_t st_sign; /* Self Test Signature */ | |
1242 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1243 | } eepro100_selftest_t; |
663e8e51 TS |
1244 | |
1245 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1246 | { | |
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1251 | { | |
1252 | val = le32_to_cpu(val); | |
1253 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1254 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1255 | switch (selection) { | |
1256 | case PORT_SOFTWARE_RESET: | |
1257 | nic_reset(s); | |
1258 | break; | |
1259 | case PORT_SELFTEST: | |
aac443e6 | 1260 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1261 | eepro100_selftest_t data; |
663e8e51 TS |
1262 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1263 | data.st_sign = 0xffffffff; | |
1264 | data.st_result = 0; | |
1265 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1266 | break; | |
1267 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1268 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1269 | nic_selective_reset(s); |
1270 | break; | |
1271 | default: | |
1272 | logout("val=0x%08x\n", val); | |
1273 | missing("unknown port selection"); | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | /***************************************************************************** | |
1278 | * | |
1279 | * General hardware emulation. | |
1280 | * | |
1281 | ****************************************************************************/ | |
1282 | ||
1283 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1284 | { | |
1285 | uint8_t val; | |
1286 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1287 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1288 | } | |
1289 | ||
1290 | switch (addr) { | |
1291 | case SCBStatus: | |
1292 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1293 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1294 | break; |
1295 | case SCBAck: | |
1296 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1297 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1298 | break; |
1299 | case SCBCmd: | |
aac443e6 | 1300 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1301 | //~ val = eepro100_read_command(s); |
1302 | break; | |
1303 | case SCBIntmask: | |
aac443e6 | 1304 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1305 | break; |
1306 | case SCBPort + 3: | |
aac443e6 | 1307 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1308 | break; |
1309 | case SCBeeprom: | |
1310 | val = eepro100_read_eeprom(s); | |
1311 | break; | |
1312 | case 0x1b: /* PMDR (power management driver register) */ | |
1313 | val = 0; | |
aac443e6 | 1314 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1315 | break; |
1316 | case 0x1d: /* general status register */ | |
1317 | /* 100 Mbps full duplex, valid link */ | |
1318 | val = 0x07; | |
aac443e6 | 1319 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1320 | break; |
1321 | default: | |
1322 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1323 | missing("unknown byte read"); | |
1324 | } | |
1325 | return val; | |
1326 | } | |
1327 | ||
1328 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1329 | { | |
1330 | uint16_t val; | |
1331 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1332 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1333 | } | |
1334 | ||
663e8e51 TS |
1335 | switch (addr) { |
1336 | case SCBStatus: | |
1337 | //~ val = eepro100_read_status(s); | |
dbbaaff6 | 1338 | case SCBCmd: |
aac443e6 | 1339 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1340 | break; |
1341 | case SCBeeprom: | |
1342 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1343 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1344 | break; |
1345 | default: | |
1346 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1347 | missing("unknown word read"); | |
1348 | } | |
1349 | return val; | |
1350 | } | |
1351 | ||
1352 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1353 | { | |
1354 | uint32_t val; | |
1355 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1356 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1357 | } | |
1358 | ||
1359 | switch (addr) { | |
1360 | case SCBStatus: | |
1361 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1362 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1363 | break; |
1364 | case SCBPointer: | |
1365 | //~ val = eepro100_read_pointer(s); | |
aac443e6 | 1366 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1367 | break; |
1368 | case SCBPort: | |
1369 | val = eepro100_read_port(s); | |
aac443e6 | 1370 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1371 | break; |
1372 | case SCBCtrlMDI: | |
1373 | val = eepro100_read_mdi(s); | |
1374 | break; | |
1375 | default: | |
1376 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1377 | missing("unknown longword read"); | |
1378 | } | |
1379 | return val; | |
1380 | } | |
1381 | ||
1382 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1383 | { | |
1384 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1385 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1386 | } | |
1387 | ||
aac443e6 | 1388 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1389 | |
1390 | switch (addr) { | |
1391 | case SCBStatus: | |
1392 | //~ eepro100_write_status(s, val); | |
1393 | break; | |
1394 | case SCBAck: | |
1395 | eepro100_acknowledge(s); | |
1396 | break; | |
1397 | case SCBCmd: | |
1398 | eepro100_write_command(s, val); | |
1399 | break; | |
1400 | case SCBIntmask: | |
1401 | if (val & BIT(1)) { | |
1402 | eepro100_swi_interrupt(s); | |
1403 | } | |
1404 | eepro100_interrupt(s, 0); | |
1405 | break; | |
1406 | case SCBPort + 3: | |
aac443e6 | 1407 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1408 | case SCBFlow + 1: |
1409 | case SCBFlow + 2: | |
1410 | case SCBFlow + 3: | |
aac443e6 | 1411 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1412 | break; |
1413 | case SCBeeprom: | |
1414 | eepro100_write_eeprom(s->eeprom, val); | |
1415 | break; | |
1416 | default: | |
1417 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1418 | missing("unknown byte write"); | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1423 | { | |
1424 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1425 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1426 | } | |
1427 | ||
aac443e6 | 1428 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1429 | |
1430 | switch (addr) { | |
1431 | case SCBStatus: | |
1432 | //~ eepro100_write_status(s, val); | |
1433 | eepro100_acknowledge(s); | |
1434 | break; | |
1435 | case SCBCmd: | |
1436 | eepro100_write_command(s, val); | |
1437 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1438 | break; | |
1439 | case SCBeeprom: | |
1440 | eepro100_write_eeprom(s->eeprom, val); | |
1441 | break; | |
1442 | default: | |
1443 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1444 | missing("unknown word write"); | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1449 | { | |
1450 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1451 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1452 | } | |
1453 | ||
1454 | switch (addr) { | |
1455 | case SCBPointer: | |
1456 | eepro100_write_pointer(s, val); | |
1457 | break; | |
1458 | case SCBPort: | |
aac443e6 | 1459 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1460 | eepro100_write_port(s, val); |
1461 | break; | |
1462 | case SCBCtrlMDI: | |
1463 | eepro100_write_mdi(s, val); | |
1464 | break; | |
1465 | default: | |
1466 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1467 | missing("unknown longword write"); | |
1468 | } | |
1469 | } | |
1470 | ||
aac443e6 SW |
1471 | /***************************************************************************** |
1472 | * | |
1473 | * Port mapped I/O. | |
1474 | * | |
1475 | ****************************************************************************/ | |
1476 | ||
663e8e51 TS |
1477 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1478 | { | |
1479 | EEPRO100State *s = opaque; | |
1480 | //~ logout("addr=%s\n", regname(addr)); | |
1481 | return eepro100_read1(s, addr - s->region[1]); | |
1482 | } | |
1483 | ||
1484 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1485 | { | |
1486 | EEPRO100State *s = opaque; | |
1487 | return eepro100_read2(s, addr - s->region[1]); | |
1488 | } | |
1489 | ||
1490 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1491 | { | |
1492 | EEPRO100State *s = opaque; | |
1493 | return eepro100_read4(s, addr - s->region[1]); | |
1494 | } | |
1495 | ||
1496 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1497 | { | |
1498 | EEPRO100State *s = opaque; | |
1499 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1500 | eepro100_write1(s, addr - s->region[1], val); | |
1501 | } | |
1502 | ||
1503 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1504 | { | |
1505 | EEPRO100State *s = opaque; | |
1506 | eepro100_write2(s, addr - s->region[1], val); | |
1507 | } | |
1508 | ||
1509 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1510 | { | |
1511 | EEPRO100State *s = opaque; | |
1512 | eepro100_write4(s, addr - s->region[1], val); | |
1513 | } | |
1514 | ||
1515 | /***********************************************************/ | |
1516 | /* PCI EEPRO100 definitions */ | |
1517 | ||
663e8e51 | 1518 | static void pci_map(PCIDevice * pci_dev, int region_num, |
6e355d90 | 1519 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1520 | { |
273a2142 | 1521 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1522 | |
89e8b13c IY |
1523 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1524 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1525 | region_num, addr, size, type)); |
663e8e51 TS |
1526 | |
1527 | assert(region_num == 1); | |
1528 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1529 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1530 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1531 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1532 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1533 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1534 | ||
1535 | s->region[region_num] = addr; | |
1536 | } | |
1537 | ||
aac443e6 SW |
1538 | /***************************************************************************** |
1539 | * | |
1540 | * Memory mapped I/O. | |
1541 | * | |
1542 | ****************************************************************************/ | |
1543 | ||
c227f099 | 1544 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1545 | { |
1546 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1547 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1548 | eepro100_write1(s, addr, val); | |
1549 | } | |
1550 | ||
c227f099 | 1551 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1552 | { |
1553 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1554 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1555 | eepro100_write2(s, addr, val); | |
1556 | } | |
1557 | ||
c227f099 | 1558 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1559 | { |
1560 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1561 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1562 | eepro100_write4(s, addr, val); | |
1563 | } | |
1564 | ||
c227f099 | 1565 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1566 | { |
1567 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1568 | //~ logout("addr=%s\n", regname(addr)); |
1569 | return eepro100_read1(s, addr); | |
1570 | } | |
1571 | ||
c227f099 | 1572 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1573 | { |
1574 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1575 | //~ logout("addr=%s\n", regname(addr)); |
1576 | return eepro100_read2(s, addr); | |
1577 | } | |
1578 | ||
c227f099 | 1579 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1580 | { |
1581 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1582 | //~ logout("addr=%s\n", regname(addr)); |
1583 | return eepro100_read4(s, addr); | |
1584 | } | |
1585 | ||
d60efc6b | 1586 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1587 | pci_mmio_writeb, |
1588 | pci_mmio_writew, | |
1589 | pci_mmio_writel | |
1590 | }; | |
1591 | ||
d60efc6b | 1592 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1593 | pci_mmio_readb, |
1594 | pci_mmio_readw, | |
1595 | pci_mmio_readl | |
1596 | }; | |
1597 | ||
1598 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
6e355d90 | 1599 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1600 | { |
273a2142 | 1601 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1602 | |
89e8b13c IY |
1603 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1604 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1605 | region_num, addr, size, type)); |
663e8e51 TS |
1606 | |
1607 | if (region_num == 0) { | |
1608 | /* Map control / status registers. */ | |
273a2142 JQ |
1609 | cpu_register_physical_memory(addr, size, s->mmio_index); |
1610 | s->region[region_num] = addr; | |
663e8e51 TS |
1611 | } |
1612 | } | |
1613 | ||
e00e365e | 1614 | static int nic_can_receive(VLANClientState *nc) |
663e8e51 | 1615 | { |
e00e365e | 1616 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
aac443e6 | 1617 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 TS |
1618 | return get_ru_state(s) == ru_ready; |
1619 | //~ return !eepro100_buffer_full(s); | |
1620 | } | |
1621 | ||
e00e365e | 1622 | static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1623 | { |
1624 | /* TODO: | |
1625 | * - Magic packets should set bit 30 in power management driver register. | |
1626 | * - Interesting packets should set bit 29 in power management driver register. | |
1627 | */ | |
e00e365e | 1628 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
663e8e51 TS |
1629 | uint16_t rfd_status = 0xa000; |
1630 | static const uint8_t broadcast_macaddr[6] = | |
1631 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1632 | ||
1633 | /* TODO: check multiple IA bit. */ | |
7f1e9d4e KW |
1634 | if (s->configuration[20] & BIT(6)) { |
1635 | missing("Multiple IA bit"); | |
1636 | return -1; | |
1637 | } | |
663e8e51 TS |
1638 | |
1639 | if (s->configuration[8] & 0x80) { | |
1640 | /* CSMA is disabled. */ | |
1641 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1642 | return -1; |
663e8e51 TS |
1643 | } else if (size < 64 && (s->configuration[7] & 1)) { |
1644 | /* Short frame and configuration byte 7/0 (discard short receive) set: | |
1645 | * Short frame is discarded */ | |
067d01de | 1646 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1647 | s->statistics.rx_short_frame_errors++; |
4f1c942b | 1648 | //~ return -1; |
663e8e51 TS |
1649 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1650 | /* Long frame and configuration byte 18/3 (long receive ok) not set: | |
1651 | * Long frames are discarded. */ | |
067d01de | 1652 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1653 | return -1; |
508ef936 | 1654 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!! |
663e8e51 TS |
1655 | /* Frame matches individual address. */ |
1656 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1657 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1658 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1659 | /* Broadcast frame. */ | |
067d01de | 1660 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 TS |
1661 | rfd_status |= 0x0002; |
1662 | } else if (buf[0] & 0x01) { // !!! | |
1663 | /* Multicast frame. */ | |
067d01de | 1664 | TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size)); |
663e8e51 | 1665 | /* TODO: check multicast all bit. */ |
7f1e9d4e KW |
1666 | if (s->configuration[21] & BIT(3)) { |
1667 | missing("Multicast All bit"); | |
1668 | } | |
663e8e51 TS |
1669 | int mcast_idx = compute_mcast_idx(buf); |
1670 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { | |
4f1c942b | 1671 | return size; |
663e8e51 TS |
1672 | } |
1673 | rfd_status |= 0x0002; | |
1674 | } else if (s->configuration[15] & 1) { | |
1675 | /* Promiscuous: receive all. */ | |
067d01de | 1676 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1677 | rfd_status |= 0x0004; |
1678 | } else { | |
067d01de | 1679 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1680 | nic_dump(buf, size))); |
4f1c942b | 1681 | return size; |
663e8e51 TS |
1682 | } |
1683 | ||
1684 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1685 | /* No resources available. */ |
1686 | logout("no resources, state=%u\n", get_ru_state(s)); | |
663e8e51 | 1687 | s->statistics.rx_resource_errors++; |
aac443e6 | 1688 | //~ assert(!"no resources"); |
4f1c942b | 1689 | return -1; |
663e8e51 TS |
1690 | } |
1691 | //~ !!! | |
1692 | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} | |
c227f099 | 1693 | eepro100_rx_t rx; |
663e8e51 | 1694 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1695 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1696 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1697 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1698 | |
1699 | if (size > rfd_size) { | |
1700 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1701 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1702 | size = rfd_size; | |
1703 | } | |
663e8e51 TS |
1704 | if (size < 64) { |
1705 | rfd_status |= 0x0080; | |
1706 | } | |
aac443e6 SW |
1707 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1708 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1709 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1710 | rfd_status); |
c227f099 | 1711 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 TS |
1712 | /* Early receive interrupt not supported. */ |
1713 | //~ eepro100_er_interrupt(s); | |
1714 | /* Receive CRC Transfer not supported. */ | |
7f1e9d4e KW |
1715 | if (s->configuration[18] & 4) { |
1716 | missing("Receive CRC Transfer"); | |
1717 | return -1; | |
1718 | } | |
663e8e51 TS |
1719 | /* TODO: check stripping enable bit. */ |
1720 | //~ assert(!(s->configuration[17] & 1)); | |
1721 | cpu_physical_memory_write(s->ru_base + s->ru_offset + | |
c227f099 | 1722 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1723 | s->statistics.rx_good_frames++; |
1724 | eepro100_fr_interrupt(s); | |
1725 | s->ru_offset = le32_to_cpu(rx.link); | |
1726 | if (rfd_command & 0x8000) { | |
1727 | /* EL bit is set, so this was the last frame. */ | |
7f1e9d4e KW |
1728 | logout("receive: Running out of frames\n"); |
1729 | set_ru_state(s, ru_suspended); | |
663e8e51 TS |
1730 | } |
1731 | if (rfd_command & 0x4000) { | |
1732 | /* S bit is set. */ | |
1733 | set_ru_state(s, ru_suspended); | |
1734 | } | |
4f1c942b | 1735 | return size; |
663e8e51 TS |
1736 | } |
1737 | ||
151b2986 JQ |
1738 | static const VMStateDescription vmstate_eepro100 = { |
1739 | .version_id = 3, | |
1740 | .minimum_version_id = 2, | |
1741 | .minimum_version_id_old = 2, | |
1742 | .fields = (VMStateField []) { | |
1743 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1744 | VMSTATE_UNUSED(32), | |
1745 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1746 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1747 | /* Save all members of struct between scb_stat and mem. */ | |
1748 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1749 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1750 | VMSTATE_UNUSED(3*4), | |
1751 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1752 | VMSTATE_UNUSED(19*4), | |
1753 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1754 | /* The eeprom should be saved and restored by its own routines. */ | |
1755 | VMSTATE_UINT32(device, EEPRO100State), | |
1756 | /* TODO check device. */ | |
1757 | VMSTATE_UINT32(pointer, EEPRO100State), | |
1758 | VMSTATE_UINT32(cu_base, EEPRO100State), | |
1759 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1760 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1761 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1762 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1763 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1764 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1765 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1766 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1767 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1768 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1769 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1770 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1771 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1772 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1773 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1774 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1775 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1776 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1777 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1778 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1779 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1780 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1781 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1782 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1783 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1784 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
2657c663 | 1785 | #if 0 |
151b2986 | 1786 | VMSTATE_UINT16(status, EEPRO100State), |
2657c663 | 1787 | #endif |
151b2986 JQ |
1788 | /* Configuration bytes. */ |
1789 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1790 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1791 | } |
151b2986 | 1792 | }; |
663e8e51 | 1793 | |
e00e365e | 1794 | static void nic_cleanup(VLANClientState *nc) |
b946a153 | 1795 | { |
e00e365e | 1796 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b946a153 | 1797 | |
e00e365e | 1798 | s->nic = NULL; |
b946a153 AL |
1799 | } |
1800 | ||
c4c270e2 | 1801 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1802 | { |
c4c270e2 | 1803 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1804 | |
1805 | cpu_unregister_io_memory(s->mmio_index); | |
151b2986 | 1806 | vmstate_unregister(s->vmstate, s); |
508ef936 | 1807 | eeprom93xx_free(s->eeprom); |
e00e365e | 1808 | qemu_del_vlan_client(&s->nic->nc); |
b946a153 AL |
1809 | return 0; |
1810 | } | |
1811 | ||
e00e365e MM |
1812 | static NetClientInfo net_eepro100_info = { |
1813 | .type = NET_CLIENT_TYPE_NIC, | |
1814 | .size = sizeof(NICState), | |
1815 | .can_receive = nic_can_receive, | |
1816 | .receive = nic_receive, | |
1817 | .cleanup = nic_cleanup, | |
1818 | }; | |
1819 | ||
81a322d4 | 1820 | static int nic_init(PCIDevice *pci_dev, uint32_t device) |
663e8e51 | 1821 | { |
273a2142 | 1822 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1823 | |
aac443e6 | 1824 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1825 | |
663e8e51 | 1826 | s->device = device; |
663e8e51 TS |
1827 | |
1828 | pci_reset(s); | |
1829 | ||
1830 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1831 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1832 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1833 | ||
1834 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1835 | s->mmio_index = |
1eed09cb | 1836 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1837 | |
273a2142 | 1838 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
0392a017 IY |
1839 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
1840 | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map); | |
1841 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO, | |
663e8e51 | 1842 | pci_map); |
0392a017 | 1843 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, |
663e8e51 TS |
1844 | pci_mmio_map); |
1845 | ||
508ef936 | 1846 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
663e8e51 TS |
1847 | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1848 | assert(s->region[1] == 0); | |
1849 | ||
1850 | nic_reset(s); | |
1851 | ||
e00e365e MM |
1852 | s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1853 | pci_dev->qdev.info->name, pci_dev->qdev.id, s); | |
663e8e51 | 1854 | |
e00e365e MM |
1855 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1856 | TRACE(OTHER, logout("%s\n", s->nic->nc.info_str)); | |
663e8e51 | 1857 | |
a08d4367 | 1858 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1859 | |
151b2986 JQ |
1860 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
1861 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
e00e365e | 1862 | s->vmstate->name = s->nic->nc.model; |
151b2986 | 1863 | vmstate_register(-1, s->vmstate, s); |
4e9df06a | 1864 | |
81a322d4 | 1865 | return 0; |
663e8e51 TS |
1866 | } |
1867 | ||
c4c270e2 SW |
1868 | static int pci_i82550_init(PCIDevice *pci_dev) |
1869 | { | |
1870 | return nic_init(pci_dev, i82550); | |
1871 | } | |
1872 | ||
1873 | static int pci_i82551_init(PCIDevice *pci_dev) | |
1874 | { | |
1875 | return nic_init(pci_dev, i82551); | |
1876 | } | |
1877 | ||
1878 | static int pci_i82557a_init(PCIDevice *pci_dev) | |
1879 | { | |
1880 | return nic_init(pci_dev, i82557A); | |
1881 | } | |
1882 | ||
1883 | static int pci_i82557b_init(PCIDevice *pci_dev) | |
1884 | { | |
1885 | return nic_init(pci_dev, i82557B); | |
1886 | } | |
1887 | ||
1888 | static int pci_i82557c_init(PCIDevice *pci_dev) | |
1889 | { | |
1890 | return nic_init(pci_dev, i82557C); | |
1891 | } | |
1892 | ||
1893 | static int pci_i82558a_init(PCIDevice *pci_dev) | |
1894 | { | |
1895 | return nic_init(pci_dev, i82558A); | |
1896 | } | |
1897 | ||
1898 | static int pci_i82558b_init(PCIDevice *pci_dev) | |
1899 | { | |
1900 | return nic_init(pci_dev, i82558B); | |
1901 | } | |
1902 | ||
1903 | static int pci_i82559a_init(PCIDevice *pci_dev) | |
1904 | { | |
1905 | return nic_init(pci_dev, i82559A); | |
1906 | } | |
1907 | ||
1908 | static int pci_i82559b_init(PCIDevice *pci_dev) | |
1909 | { | |
1910 | return nic_init(pci_dev, i82559B); | |
1911 | } | |
1912 | ||
1913 | static int pci_i82559c_init(PCIDevice *pci_dev) | |
9d07d757 | 1914 | { |
c4c270e2 | 1915 | return nic_init(pci_dev, i82559C); |
9d07d757 PB |
1916 | } |
1917 | ||
c4c270e2 | 1918 | static int pci_i82559er_init(PCIDevice *pci_dev) |
663e8e51 | 1919 | { |
c4c270e2 | 1920 | return nic_init(pci_dev, i82559ER); |
663e8e51 TS |
1921 | } |
1922 | ||
c4c270e2 | 1923 | static int pci_i82562_init(PCIDevice *pci_dev) |
663e8e51 | 1924 | { |
c4c270e2 | 1925 | return nic_init(pci_dev, i82562); |
663e8e51 TS |
1926 | } |
1927 | ||
0aab0d3a GH |
1928 | static PCIDeviceInfo eepro100_info[] = { |
1929 | { | |
c4c270e2 SW |
1930 | .qdev.name = "i82550", |
1931 | .qdev.size = sizeof(EEPRO100State), | |
1932 | .init = pci_i82550_init, | |
6a90e308 | 1933 | .exit = pci_nic_uninit, |
508ef936 GH |
1934 | .qdev.props = (Property[]) { |
1935 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1936 | DEFINE_PROP_END_OF_LIST(), | |
1937 | }, | |
c4c270e2 | 1938 | },{ |
0aab0d3a | 1939 | .qdev.name = "i82551", |
273a2142 | 1940 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1941 | .init = pci_i82551_init, |
e3936fa5 | 1942 | .exit = pci_nic_uninit, |
508ef936 GH |
1943 | .qdev.props = (Property[]) { |
1944 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1945 | DEFINE_PROP_END_OF_LIST(), | |
1946 | }, | |
c4c270e2 SW |
1947 | },{ |
1948 | .qdev.name = "i82557a", | |
1949 | .qdev.size = sizeof(EEPRO100State), | |
1950 | .init = pci_i82557a_init, | |
6a90e308 | 1951 | .exit = pci_nic_uninit, |
508ef936 GH |
1952 | .qdev.props = (Property[]) { |
1953 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1954 | DEFINE_PROP_END_OF_LIST(), | |
1955 | }, | |
0aab0d3a GH |
1956 | },{ |
1957 | .qdev.name = "i82557b", | |
273a2142 | 1958 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1959 | .init = pci_i82557b_init, |
e3936fa5 | 1960 | .exit = pci_nic_uninit, |
508ef936 GH |
1961 | .qdev.props = (Property[]) { |
1962 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1963 | DEFINE_PROP_END_OF_LIST(), | |
1964 | }, | |
c4c270e2 SW |
1965 | },{ |
1966 | .qdev.name = "i82557c", | |
1967 | .qdev.size = sizeof(EEPRO100State), | |
1968 | .init = pci_i82557c_init, | |
6a90e308 | 1969 | .exit = pci_nic_uninit, |
508ef936 GH |
1970 | .qdev.props = (Property[]) { |
1971 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1972 | DEFINE_PROP_END_OF_LIST(), | |
1973 | }, | |
c4c270e2 SW |
1974 | },{ |
1975 | .qdev.name = "i82558a", | |
1976 | .qdev.size = sizeof(EEPRO100State), | |
1977 | .init = pci_i82558a_init, | |
6a90e308 | 1978 | .exit = pci_nic_uninit, |
508ef936 GH |
1979 | .qdev.props = (Property[]) { |
1980 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1981 | DEFINE_PROP_END_OF_LIST(), | |
1982 | }, | |
c4c270e2 SW |
1983 | },{ |
1984 | .qdev.name = "i82558b", | |
1985 | .qdev.size = sizeof(EEPRO100State), | |
1986 | .init = pci_i82558b_init, | |
6a90e308 | 1987 | .exit = pci_nic_uninit, |
508ef936 GH |
1988 | .qdev.props = (Property[]) { |
1989 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1990 | DEFINE_PROP_END_OF_LIST(), | |
1991 | }, | |
c4c270e2 SW |
1992 | },{ |
1993 | .qdev.name = "i82559a", | |
1994 | .qdev.size = sizeof(EEPRO100State), | |
1995 | .init = pci_i82559a_init, | |
6a90e308 | 1996 | .exit = pci_nic_uninit, |
508ef936 GH |
1997 | .qdev.props = (Property[]) { |
1998 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1999 | DEFINE_PROP_END_OF_LIST(), | |
2000 | }, | |
c4c270e2 SW |
2001 | },{ |
2002 | .qdev.name = "i82559b", | |
2003 | .qdev.size = sizeof(EEPRO100State), | |
2004 | .init = pci_i82559b_init, | |
6a90e308 | 2005 | .exit = pci_nic_uninit, |
508ef936 GH |
2006 | .qdev.props = (Property[]) { |
2007 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2008 | DEFINE_PROP_END_OF_LIST(), | |
2009 | }, | |
c4c270e2 SW |
2010 | },{ |
2011 | .qdev.name = "i82559c", | |
2012 | .qdev.size = sizeof(EEPRO100State), | |
2013 | .init = pci_i82559c_init, | |
6a90e308 | 2014 | .exit = pci_nic_uninit, |
508ef936 GH |
2015 | .qdev.props = (Property[]) { |
2016 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2017 | DEFINE_PROP_END_OF_LIST(), | |
2018 | }, | |
0aab0d3a GH |
2019 | },{ |
2020 | .qdev.name = "i82559er", | |
273a2142 | 2021 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 2022 | .init = pci_i82559er_init, |
e3936fa5 | 2023 | .exit = pci_nic_uninit, |
938a6324 | 2024 | .romfile = "pxe-i82559er.bin", |
508ef936 GH |
2025 | .qdev.props = (Property[]) { |
2026 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2027 | DEFINE_PROP_END_OF_LIST(), | |
2028 | }, | |
c4c270e2 SW |
2029 | },{ |
2030 | .qdev.name = "i82562", | |
2031 | .qdev.size = sizeof(EEPRO100State), | |
2032 | .init = pci_i82562_init, | |
6a90e308 | 2033 | .exit = pci_nic_uninit, |
508ef936 GH |
2034 | .qdev.props = (Property[]) { |
2035 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2036 | DEFINE_PROP_END_OF_LIST(), | |
2037 | }, | |
0aab0d3a GH |
2038 | },{ |
2039 | /* end of list */ | |
2040 | } | |
2041 | }; | |
2042 | ||
9d07d757 | 2043 | static void eepro100_register_devices(void) |
663e8e51 | 2044 | { |
0aab0d3a | 2045 | pci_qdev_register_many(eepro100_info); |
663e8e51 TS |
2046 | } |
2047 | ||
9d07d757 | 2048 | device_init(eepro100_register_devices) |