]>
Commit | Line | Data |
---|---|---|
663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
230a167c | 4 | * Copyright (C) 2006-2010 Stefan Weil |
663e8e51 TS |
5 | * |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
230a167c | 9 | * This program is free software: you can redistribute it and/or modify |
663e8e51 | 10 | * it under the terms of the GNU General Public License as published by |
230a167c SW |
11 | * the Free Software Foundation, either version 2 of the License, or |
12 | * (at your option) version 3 or any later version. | |
663e8e51 TS |
13 | * |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
230a167c | 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
6cded3a4 | 23 | * PXE boot (i386) ok |
663e8e51 TS |
24 | * Linux networking (i386) ok |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
ba19f2de SW |
34 | * |
35 | * TODO: | |
36 | * * PHY emulation should be separated from nic emulation. | |
37 | * Most nic emulations could share the same phy code. | |
38 | * * i82550 is untested. It is programmed like the i82559. | |
39 | * * i82562 is untested. It is programmed like the i82559. | |
40 | * * Power management (i82558 and later) is not implemented. | |
41 | * * Wake-on-LAN is not implemented. | |
663e8e51 TS |
42 | */ |
43 | ||
78728c92 | 44 | #include <stdbool.h> /* bool */ |
663e8e51 | 45 | #include <stddef.h> /* offsetof */ |
87ecb68b PB |
46 | #include "hw.h" |
47 | #include "pci.h" | |
48 | #include "net.h" | |
663e8e51 TS |
49 | #include "eeprom93xx.h" |
50 | ||
663e8e51 TS |
51 | #define KiB 1024 |
52 | ||
aac443e6 | 53 | /* Debug EEPRO100 card. */ |
ce0e58b3 SW |
54 | #if 0 |
55 | # define DEBUG_EEPRO100 | |
56 | #endif | |
663e8e51 TS |
57 | |
58 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 59 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 60 | #else |
001faf32 | 61 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
62 | #endif |
63 | ||
64 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
65 | #define INT 1 /* interrupt related actions */ |
66 | #define MDI 1 /* mdi related actions */ | |
67 | #define OTHER 1 | |
68 | #define RXTX 1 | |
69 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
70 | |
71 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
72 | ||
7f1e9d4e | 73 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
74 | |
75 | #define MAX_ETH_FRAME_SIZE 1514 | |
76 | ||
77 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 78 | #define i82550 0x82550 |
663e8e51 | 79 | #define i82551 0x82551 |
c4c270e2 | 80 | #define i82557A 0x82557a |
663e8e51 TS |
81 | #define i82557B 0x82557b |
82 | #define i82557C 0x82557c | |
c4c270e2 | 83 | #define i82558A 0x82558a |
663e8e51 | 84 | #define i82558B 0x82558b |
c4c270e2 SW |
85 | #define i82559A 0x82559a |
86 | #define i82559B 0x82559b | |
663e8e51 TS |
87 | #define i82559C 0x82559c |
88 | #define i82559ER 0x82559e | |
89 | #define i82562 0x82562 | |
db667a12 | 90 | #define i82801 0x82801 |
663e8e51 | 91 | |
aac443e6 | 92 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
93 | #define EEPROM_SIZE 64 |
94 | ||
95 | #define PCI_MEM_SIZE (4 * KiB) | |
96 | #define PCI_IO_SIZE 64 | |
97 | #define PCI_FLASH_SIZE (128 * KiB) | |
98 | ||
99 | #define BIT(n) (1 << (n)) | |
100 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
101 | ||
102 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
103 | #define CU_NOP 0x0000 /* No operation. */ | |
104 | #define CU_START 0x0010 /* CU start. */ | |
105 | #define CU_RESUME 0x0020 /* CU resume. */ | |
106 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
107 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
108 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
109 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
110 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
111 | ||
112 | #define RU_NOP 0x0000 | |
113 | #define RX_START 0x0001 | |
114 | #define RX_RESUME 0x0002 | |
e824012b | 115 | #define RU_ABORT 0x0004 |
663e8e51 TS |
116 | #define RX_ADDR_LOAD 0x0006 |
117 | #define RX_RESUMENR 0x0007 | |
118 | #define INT_MASK 0x0100 | |
119 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
120 | ||
558c8634 SW |
121 | typedef struct { |
122 | PCIDeviceInfo pci; | |
123 | uint32_t device; | |
124 | uint16_t device_id; | |
125 | uint8_t revision; | |
126 | uint8_t stats_size; | |
127 | bool has_extended_tcb_support; | |
128 | bool power_management; | |
129 | } E100PCIDeviceInfo; | |
130 | ||
663e8e51 TS |
131 | /* Offsets to the various registers. |
132 | All accesses need not be longword aligned. */ | |
133 | enum speedo_offsets { | |
0908bba1 | 134 | SCBStatus = 0, /* Status Word. */ |
663e8e51 TS |
135 | SCBAck = 1, |
136 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
137 | SCBIntmask = 3, | |
138 | SCBPointer = 4, /* General purpose pointer. */ | |
139 | SCBPort = 8, /* Misc. commands and operands. */ | |
0908bba1 SW |
140 | SCBflash = 12, /* Flash memory control. */ |
141 | SCBeeprom = 14, /* EEPROM control. */ | |
663e8e51 TS |
142 | SCBCtrlMDI = 16, /* MDI interface control. */ |
143 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
0908bba1 SW |
144 | SCBFlow = 24, /* Flow Control. */ |
145 | SCBpmdr = 27, /* Power Management Driver. */ | |
146 | SCBgctrl = 28, /* General Control. */ | |
147 | SCBgstat = 29, /* General Status. */ | |
663e8e51 TS |
148 | }; |
149 | ||
150 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
151 | typedef struct { | |
152 | uint16_t status; | |
153 | uint16_t command; | |
154 | uint32_t link; /* void * */ | |
7b8737de | 155 | uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */ |
663e8e51 TS |
156 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ |
157 | uint8_t tx_threshold; /* transmit threshold */ | |
158 | uint8_t tbd_count; /* TBD number */ | |
e7493b25 SW |
159 | #if 0 |
160 | /* This constitutes two "TBD" entries: hdr and data */ | |
161 | uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
162 | int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
163 | uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
164 | int32_t tx_buf_size1; /* Length of Tx data. */ | |
165 | #endif | |
c227f099 | 166 | } eepro100_tx_t; |
663e8e51 TS |
167 | |
168 | /* Receive frame descriptor. */ | |
169 | typedef struct { | |
170 | int16_t status; | |
171 | uint16_t command; | |
172 | uint32_t link; /* struct RxFD * */ | |
173 | uint32_t rx_buf_addr; /* void * */ | |
174 | uint16_t count; | |
175 | uint16_t size; | |
176 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 177 | } eepro100_rx_t; |
663e8e51 | 178 | |
ced5296a SW |
179 | typedef enum { |
180 | COMMAND_EL = BIT(15), | |
181 | COMMAND_S = BIT(14), | |
182 | COMMAND_I = BIT(13), | |
183 | COMMAND_NC = BIT(4), | |
184 | COMMAND_SF = BIT(3), | |
185 | COMMAND_CMD = BITS(2, 0), | |
186 | } scb_command_bit; | |
187 | ||
188 | typedef enum { | |
189 | STATUS_C = BIT(15), | |
190 | STATUS_OK = BIT(13), | |
191 | } scb_status_bit; | |
192 | ||
663e8e51 TS |
193 | typedef struct { |
194 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
cc02c66c SW |
195 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
196 | tx_multiple_collisions, tx_total_collisions; | |
663e8e51 | 197 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
cc02c66c SW |
198 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
199 | rx_short_frame_errors; | |
663e8e51 TS |
200 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
201 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
202 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
203 | uint32_t reserved[4]; | |
c227f099 | 204 | } eepro100_stats_t; |
663e8e51 TS |
205 | |
206 | typedef enum { | |
207 | cu_idle = 0, | |
208 | cu_suspended = 1, | |
209 | cu_active = 2, | |
210 | cu_lpq_active = 2, | |
211 | cu_hqp_active = 3 | |
c227f099 | 212 | } cu_state_t; |
663e8e51 TS |
213 | |
214 | typedef enum { | |
215 | ru_idle = 0, | |
216 | ru_suspended = 1, | |
217 | ru_no_resources = 2, | |
218 | ru_ready = 4 | |
c227f099 | 219 | } ru_state_t; |
663e8e51 | 220 | |
663e8e51 | 221 | typedef struct { |
273a2142 | 222 | PCIDevice dev; |
663e8e51 TS |
223 | uint8_t mult[8]; /* multicast mask array */ |
224 | int mmio_index; | |
e00e365e | 225 | NICState *nic; |
508ef936 | 226 | NICConf conf; |
663e8e51 TS |
227 | uint8_t scb_stat; /* SCB stat/ack byte */ |
228 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 229 | /* region must not be saved by nic_save. */ |
663e8e51 | 230 | uint32_t region[3]; /* PCI region addresses */ |
663e8e51 | 231 | uint16_t mdimem[32]; |
c227f099 | 232 | eeprom_t *eeprom; |
663e8e51 TS |
233 | uint32_t device; /* device variant */ |
234 | uint32_t pointer; | |
235 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
236 | uint32_t cu_base; /* CU base address */ | |
237 | uint32_t cu_offset; /* CU address offset */ | |
238 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
239 | uint32_t ru_base; /* RU base address */ | |
240 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 241 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 | 242 | |
f3a52e50 SW |
243 | /* Temporary status information (no need to save these values), |
244 | * used while processing CU commands. */ | |
245 | eepro100_tx_t tx; /* transmit buffer descriptor */ | |
246 | uint32_t cb_address; /* = cu_base + cu_offset */ | |
247 | ||
ba42b646 SW |
248 | /* Statistical counters. Also used for wake-up packet (i82559). */ |
249 | eepro100_stats_t statistics; | |
250 | ||
663e8e51 TS |
251 | /* Configuration bytes. */ |
252 | uint8_t configuration[22]; | |
253 | ||
254 | /* Data in mem is always in the byte order of the controller (le). */ | |
255 | uint8_t mem[PCI_MEM_SIZE]; | |
151b2986 JQ |
256 | /* vmstate for each particular nic */ |
257 | VMStateDescription *vmstate; | |
ba42b646 SW |
258 | |
259 | /* Quasi static device properties (no need to save them). */ | |
260 | uint16_t stats_size; | |
261 | bool has_extended_tcb_support; | |
663e8e51 TS |
262 | } EEPRO100State; |
263 | ||
6cded3a4 SW |
264 | /* Word indices in EEPROM. */ |
265 | typedef enum { | |
266 | EEPROM_CNFG_MDIX = 0x03, | |
267 | EEPROM_ID = 0x05, | |
268 | EEPROM_PHY_ID = 0x06, | |
269 | EEPROM_VENDOR_ID = 0x0c, | |
270 | EEPROM_CONFIG_ASF = 0x0d, | |
271 | EEPROM_DEVICE_ID = 0x23, | |
272 | EEPROM_SMBUS_ADDR = 0x90, | |
273 | } EEPROMOffset; | |
274 | ||
b1e87018 SW |
275 | /* Bit values for EEPROM ID word. */ |
276 | typedef enum { | |
277 | EEPROM_ID_MDM = BIT(0), /* Modem */ | |
278 | EEPROM_ID_STB = BIT(1), /* Standby Enable */ | |
279 | EEPROM_ID_WMR = BIT(2), /* ??? */ | |
280 | EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ | |
281 | EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ | |
282 | EEPROM_ID_ALT = BIT(7), /* */ | |
283 | /* BITS(10, 8) device revision */ | |
284 | EEPROM_ID_BD = BIT(11), /* boot disable */ | |
285 | EEPROM_ID_ID = BIT(13), /* id bit */ | |
286 | /* BITS(15, 14) signature */ | |
287 | EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ | |
288 | } eeprom_id_bit; | |
289 | ||
663e8e51 TS |
290 | /* Default values for MDI (PHY) registers */ |
291 | static const uint16_t eepro100_mdi_default[] = { | |
292 | /* MDI Registers 0 - 6, 7 */ | |
293 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
294 | /* MDI Registers 8 - 15 */ | |
295 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
296 | /* MDI Registers 16 - 31 */ | |
297 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
298 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
299 | }; | |
300 | ||
301 | /* Readonly mask for MDI (PHY) registers */ | |
302 | static const uint16_t eepro100_mdi_mask[] = { | |
303 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
304 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
305 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
306 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
307 | }; | |
308 | ||
ba42b646 SW |
309 | /* XXX: optimize */ |
310 | static void stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
311 | { | |
312 | val = cpu_to_le32(val); | |
313 | cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); | |
314 | } | |
315 | ||
663e8e51 TS |
316 | #define POLYNOMIAL 0x04c11db6 |
317 | ||
318 | /* From FreeBSD */ | |
319 | /* XXX: optimize */ | |
7b8737de | 320 | static unsigned compute_mcast_idx(const uint8_t * ep) |
663e8e51 TS |
321 | { |
322 | uint32_t crc; | |
323 | int carry, i, j; | |
324 | uint8_t b; | |
325 | ||
326 | crc = 0xffffffff; | |
327 | for (i = 0; i < 6; i++) { | |
328 | b = *ep++; | |
329 | for (j = 0; j < 8; j++) { | |
330 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
331 | crc <<= 1; | |
332 | b >>= 1; | |
aac443e6 | 333 | if (carry) { |
663e8e51 | 334 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 335 | } |
663e8e51 TS |
336 | } |
337 | } | |
7b8737de | 338 | return (crc & BITS(7, 2)) >> 2; |
663e8e51 TS |
339 | } |
340 | ||
341 | #if defined(DEBUG_EEPRO100) | |
342 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
343 | { | |
344 | static char dump[3 * 16 + 1]; | |
345 | char *p = &dump[0]; | |
aac443e6 | 346 | if (size > 16) { |
663e8e51 | 347 | size = 16; |
aac443e6 | 348 | } |
663e8e51 TS |
349 | while (size-- > 0) { |
350 | p += sprintf(p, " %02x", *buf++); | |
351 | } | |
352 | return dump; | |
353 | } | |
354 | #endif /* DEBUG_EEPRO100 */ | |
355 | ||
356 | enum scb_stat_ack { | |
357 | stat_ack_not_ours = 0x00, | |
358 | stat_ack_sw_gen = 0x04, | |
359 | stat_ack_rnr = 0x10, | |
360 | stat_ack_cu_idle = 0x20, | |
361 | stat_ack_frame_rx = 0x40, | |
362 | stat_ack_cu_cmd_done = 0x80, | |
363 | stat_ack_not_present = 0xFF, | |
364 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
365 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
366 | }; | |
367 | ||
368 | static void disable_interrupt(EEPRO100State * s) | |
369 | { | |
370 | if (s->int_stat) { | |
aac443e6 | 371 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 372 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
373 | s->int_stat = 0; |
374 | } | |
375 | } | |
376 | ||
377 | static void enable_interrupt(EEPRO100State * s) | |
378 | { | |
379 | if (!s->int_stat) { | |
aac443e6 | 380 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 381 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
382 | s->int_stat = 1; |
383 | } | |
384 | } | |
385 | ||
386 | static void eepro100_acknowledge(EEPRO100State * s) | |
387 | { | |
388 | s->scb_stat &= ~s->mem[SCBAck]; | |
389 | s->mem[SCBAck] = s->scb_stat; | |
390 | if (s->scb_stat == 0) { | |
391 | disable_interrupt(s); | |
392 | } | |
393 | } | |
394 | ||
e715c8e8 | 395 | static void eepro100_interrupt(EEPRO100State * s, uint8_t status) |
663e8e51 TS |
396 | { |
397 | uint8_t mask = ~s->mem[SCBIntmask]; | |
e715c8e8 SW |
398 | s->mem[SCBAck] |= status; |
399 | status = s->scb_stat = s->mem[SCBAck]; | |
400 | status &= (mask | 0x0f); | |
e7493b25 SW |
401 | #if 0 |
402 | status &= (~s->mem[SCBIntmask] | 0x0xf); | |
403 | #endif | |
e715c8e8 | 404 | if (status && (mask & 0x01)) { |
663e8e51 TS |
405 | /* SCB mask and SCB Bit M do not disable interrupt. */ |
406 | enable_interrupt(s); | |
407 | } else if (s->int_stat) { | |
408 | disable_interrupt(s); | |
409 | } | |
410 | } | |
411 | ||
412 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
413 | { | |
414 | /* CU completed action command. */ | |
415 | /* Transmit not ok (82557 only, not in emulation). */ | |
416 | eepro100_interrupt(s, 0x80); | |
417 | } | |
418 | ||
419 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
420 | { | |
421 | /* CU left the active state. */ | |
422 | eepro100_interrupt(s, 0x20); | |
423 | } | |
424 | ||
425 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
426 | { | |
427 | /* RU received a complete frame. */ | |
428 | eepro100_interrupt(s, 0x40); | |
429 | } | |
430 | ||
663e8e51 TS |
431 | static void eepro100_rnr_interrupt(EEPRO100State * s) |
432 | { | |
433 | /* RU is not ready. */ | |
434 | eepro100_interrupt(s, 0x10); | |
435 | } | |
663e8e51 TS |
436 | |
437 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
438 | { | |
439 | /* MDI completed read or write cycle. */ | |
440 | eepro100_interrupt(s, 0x08); | |
441 | } | |
442 | ||
443 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
444 | { | |
445 | /* Software has requested an interrupt. */ | |
446 | eepro100_interrupt(s, 0x04); | |
447 | } | |
448 | ||
449 | #if 0 | |
450 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
451 | { | |
452 | /* Flow control pause interrupt (82558 and later). */ | |
453 | eepro100_interrupt(s, 0x01); | |
454 | } | |
455 | #endif | |
456 | ||
558c8634 | 457 | static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) |
663e8e51 TS |
458 | { |
459 | uint32_t device = s->device; | |
273a2142 | 460 | uint8_t *pci_conf = s->dev.config; |
663e8e51 | 461 | |
aac443e6 | 462 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
463 | |
464 | /* PCI Vendor ID */ | |
deb54399 | 465 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
558c8634 SW |
466 | /* PCI Device ID */ |
467 | pci_config_set_device_id(pci_conf, e100_device->device_id); | |
663e8e51 | 468 | /* PCI Status */ |
ae543b49 SW |
469 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
470 | PCI_STATUS_FAST_BACK); | |
663e8e51 | 471 | /* PCI Revision ID */ |
558c8634 | 472 | pci_config_set_revision(pci_conf, e100_device->revision); |
173a543b | 473 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 | 474 | /* PCI Latency Timer */ |
15e89f59 | 475 | pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
ae543b49 | 476 | /* Capability Pointer is set by PCI framework. */ |
f62719ca SW |
477 | /* Interrupt Line */ |
478 | /* Interrupt Pin */ | |
479 | pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ | |
663e8e51 | 480 | /* Minimum Grant */ |
15e89f59 | 481 | pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); |
663e8e51 | 482 | /* Maximum Latency */ |
15e89f59 | 483 | pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18); |
663e8e51 | 484 | |
558c8634 SW |
485 | s->stats_size = e100_device->stats_size; |
486 | s->has_extended_tcb_support = e100_device->has_extended_tcb_support; | |
487 | ||
663e8e51 | 488 | switch (device) { |
ba42b646 | 489 | case i82550: |
663e8e51 | 490 | case i82551: |
ba42b646 | 491 | case i82557A: |
663e8e51 | 492 | case i82557B: |
663e8e51 | 493 | case i82557C: |
ba42b646 | 494 | case i82558A: |
663e8e51 | 495 | case i82558B: |
ba42b646 | 496 | case i82559A: |
ba42b646 | 497 | case i82559B: |
558c8634 SW |
498 | case i82559ER: |
499 | case i82562: | |
db667a12 | 500 | case i82801: |
663e8e51 TS |
501 | break; |
502 | case i82559C: | |
ba42b646 | 503 | #if EEPROM_SIZE > 0 |
558c8634 | 504 | pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL); |
15e89f59 | 505 | pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040); |
ba42b646 | 506 | #endif |
663e8e51 | 507 | break; |
663e8e51 TS |
508 | default: |
509 | logout("Device %X is undefined!\n", device); | |
510 | } | |
511 | ||
3dec59a1 SW |
512 | /* Standard TxCB. */ |
513 | s->configuration[6] |= BIT(4); | |
514 | ||
558c8634 | 515 | /* Standard statistical counters. */ |
ba42b646 SW |
516 | s->configuration[6] |= BIT(5); |
517 | ||
518 | if (s->stats_size == 80) { | |
519 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
520 | if (s->configuration[6] & BIT(2)) { | |
521 | /* TCO statistical counters. */ | |
522 | assert(s->configuration[6] & BIT(5)); | |
523 | } else { | |
524 | if (s->configuration[6] & BIT(5)) { | |
525 | /* No extended statistical counters, i82557 compatible. */ | |
526 | s->stats_size = 64; | |
527 | } else { | |
528 | /* i82558 compatible. */ | |
529 | s->stats_size = 76; | |
530 | } | |
531 | } | |
532 | } else { | |
533 | if (s->configuration[6] & BIT(5)) { | |
534 | /* No extended statistical counters. */ | |
535 | s->stats_size = 64; | |
536 | } | |
537 | } | |
538 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
539 | ||
558c8634 | 540 | if (e100_device->power_management) { |
ba42b646 | 541 | /* Power Management Capabilities */ |
ae543b49 SW |
542 | int cfg_offset; |
543 | pci_reserve_capability(&s->dev, PCI_CONFIG_HEADER_SIZE, | |
544 | 0xdc - PCI_CONFIG_HEADER_SIZE); | |
545 | cfg_offset = pci_add_capability(&s->dev, PCI_CAP_ID_PM, PCI_PM_SIZEOF); | |
546 | assert(cfg_offset == 0xdc); | |
547 | if (cfg_offset > 0) { | |
548 | /* Power Management Capabilities */ | |
549 | pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); | |
550 | #if 0 /* TODO: replace dummy code for power management emulation. */ | |
551 | /* TODO: Power Management Control / Status. */ | |
552 | pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); | |
553 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
554 | pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000); | |
555 | #endif | |
556 | } | |
ba42b646 SW |
557 | } |
558 | ||
559 | #if EEPROM_SIZE > 0 | |
663e8e51 | 560 | if (device == i82557C || device == i82558B || device == i82559C) { |
e7493b25 SW |
561 | /* |
562 | TODO: get vendor id from EEPROM for i82557C or later. | |
563 | TODO: get device id from EEPROM for i82557C or later. | |
564 | TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
565 | TODO: header type is determined by EEPROM for i82559. | |
566 | TODO: get subsystem id from EEPROM for i82557C or later. | |
567 | TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
568 | TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
569 | TODO: capability pointer depends on EEPROM for i82558. | |
570 | */ | |
663e8e51 TS |
571 | logout("Get device id and revision from EEPROM!!!\n"); |
572 | } | |
ba42b646 | 573 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
574 | } |
575 | ||
576 | static void nic_selective_reset(EEPRO100State * s) | |
577 | { | |
578 | size_t i; | |
579 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
e7493b25 SW |
580 | #if 0 |
581 | eeprom93xx_reset(s->eeprom); | |
582 | #endif | |
508ef936 | 583 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
b1e87018 | 584 | eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
f4e94dfe URCB |
585 | if (s->device == i82557B || s->device == i82557C) |
586 | eeprom_contents[5] = 0x0100; | |
6cded3a4 | 587 | eeprom_contents[EEPROM_PHY_ID] = 1; |
663e8e51 TS |
588 | uint16_t sum = 0; |
589 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
590 | sum += eeprom_contents[i]; | |
591 | } | |
592 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 593 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
594 | |
595 | memset(s->mem, 0, sizeof(s->mem)); | |
596 | uint32_t val = BIT(21); | |
597 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
598 | ||
599 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
600 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
601 | } | |
602 | ||
603 | static void nic_reset(void *opaque) | |
604 | { | |
769cf7a5 | 605 | EEPRO100State *s = opaque; |
aac443e6 | 606 | TRACE(OTHER, logout("%p\n", s)); |
7b8737de SW |
607 | /* TODO: Clearing of multicast table for selective reset, too? */ |
608 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
663e8e51 TS |
609 | nic_selective_reset(s); |
610 | } | |
611 | ||
612 | #if defined(DEBUG_EEPRO100) | |
b8f6ba0d | 613 | static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
614 | "Command/Status", |
615 | "General Pointer", | |
616 | "Port", | |
617 | "EEPROM/Flash Control", | |
618 | "MDI Control", | |
619 | "Receive DMA Byte Count", | |
b8f6ba0d | 620 | "Flow Control", |
663e8e51 TS |
621 | "General Status/Control" |
622 | }; | |
623 | ||
624 | static char *regname(uint32_t addr) | |
625 | { | |
ec169288 | 626 | static char buf[32]; |
663e8e51 | 627 | if (addr < PCI_IO_SIZE) { |
b8f6ba0d | 628 | const char *r = e100_reg[addr / 4]; |
663e8e51 | 629 | if (r != 0) { |
41cbc23c | 630 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 631 | } else { |
41cbc23c | 632 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
633 | } |
634 | } else { | |
41cbc23c | 635 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
636 | } |
637 | return buf; | |
638 | } | |
639 | #endif /* DEBUG_EEPRO100 */ | |
640 | ||
663e8e51 TS |
641 | /***************************************************************************** |
642 | * | |
643 | * Command emulation. | |
644 | * | |
645 | ****************************************************************************/ | |
646 | ||
647 | #if 0 | |
648 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
649 | { | |
650 | uint16_t val = 0xffff; | |
e7493b25 | 651 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
652 | return val; |
653 | } | |
654 | #endif | |
655 | ||
656 | /* Commands that can be put in a command list entry. */ | |
657 | enum commands { | |
658 | CmdNOp = 0, | |
659 | CmdIASetup = 1, | |
660 | CmdConfigure = 2, | |
661 | CmdMulticastList = 3, | |
662 | CmdTx = 4, | |
663 | CmdTDR = 5, /* load microcode */ | |
664 | CmdDump = 6, | |
665 | CmdDiagnose = 7, | |
666 | ||
667 | /* And some extra flags: */ | |
668 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
669 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
670 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
671 | }; | |
672 | ||
c227f099 | 673 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 | 674 | { |
ced5296a | 675 | return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); |
663e8e51 TS |
676 | } |
677 | ||
c227f099 | 678 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 | 679 | { |
ced5296a | 680 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); |
663e8e51 TS |
681 | } |
682 | ||
c227f099 | 683 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 | 684 | { |
ced5296a | 685 | return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); |
663e8e51 TS |
686 | } |
687 | ||
c227f099 | 688 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 | 689 | { |
ced5296a | 690 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); |
663e8e51 TS |
691 | } |
692 | ||
693 | static void dump_statistics(EEPRO100State * s) | |
694 | { | |
695 | /* Dump statistical data. Most data is never changed by the emulation | |
696 | * and always 0, so we first just copy the whole block and then those | |
697 | * values which really matter. | |
698 | * Number of data should check configuration!!! | |
699 | */ | |
ba42b646 SW |
700 | cpu_physical_memory_write(s->statsaddr, |
701 | (uint8_t *) & s->statistics, s->stats_size); | |
702 | stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
703 | stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
704 | stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
705 | stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
e7493b25 SW |
706 | #if 0 |
707 | stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
708 | stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
709 | missing("CU dump statistical counters"); | |
710 | #endif | |
663e8e51 TS |
711 | } |
712 | ||
3d0f4b9b SW |
713 | static void read_cb(EEPRO100State *s) |
714 | { | |
715 | cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); | |
716 | s->tx.status = le16_to_cpu(s->tx.status); | |
717 | s->tx.command = le16_to_cpu(s->tx.command); | |
718 | s->tx.link = le32_to_cpu(s->tx.link); | |
719 | s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); | |
720 | s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); | |
721 | } | |
722 | ||
f3a52e50 SW |
723 | static void tx_command(EEPRO100State *s) |
724 | { | |
7b8737de | 725 | uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
f3a52e50 SW |
726 | uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff); |
727 | /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */ | |
728 | uint8_t buf[2600]; | |
729 | uint16_t size = 0; | |
730 | uint32_t tbd_address = s->cb_address + 0x10; | |
731 | TRACE(RXTX, logout | |
732 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", | |
733 | tbd_array, tcb_bytes, s->tx.tbd_count)); | |
734 | ||
735 | if (tcb_bytes > 2600) { | |
736 | logout("TCB byte count too large, using 2600\n"); | |
737 | tcb_bytes = 2600; | |
738 | } | |
739 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
740 | logout | |
741 | ("illegal values of TBD array address and TCB byte count!\n"); | |
742 | } | |
743 | assert(tcb_bytes <= sizeof(buf)); | |
744 | while (size < tcb_bytes) { | |
745 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
746 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
e7493b25 SW |
747 | #if 0 |
748 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
749 | #endif | |
f3a52e50 SW |
750 | tbd_address += 8; |
751 | TRACE(RXTX, logout | |
752 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", | |
753 | tx_buffer_address, tx_buffer_size)); | |
754 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
755 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
756 | tx_buffer_size); | |
757 | size += tx_buffer_size; | |
758 | } | |
759 | if (tbd_array == 0xffffffff) { | |
760 | /* Simplified mode. Was already handled by code above. */ | |
761 | } else { | |
762 | /* Flexible mode. */ | |
763 | uint8_t tbd_count = 0; | |
764 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { | |
765 | /* Extended Flexible TCB. */ | |
766 | for (; tbd_count < 2; tbd_count++) { | |
767 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
768 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
769 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
770 | tbd_address += 8; | |
771 | TRACE(RXTX, logout | |
772 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
773 | tx_buffer_address, tx_buffer_size)); | |
774 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
775 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
776 | tx_buffer_size); | |
777 | size += tx_buffer_size; | |
778 | if (tx_buffer_el & 1) { | |
779 | break; | |
780 | } | |
781 | } | |
782 | } | |
783 | tbd_address = tbd_array; | |
784 | for (; tbd_count < s->tx.tbd_count; tbd_count++) { | |
785 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
786 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
787 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
788 | tbd_address += 8; | |
789 | TRACE(RXTX, logout | |
790 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
791 | tx_buffer_address, tx_buffer_size)); | |
792 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
793 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
794 | tx_buffer_size); | |
795 | size += tx_buffer_size; | |
796 | if (tx_buffer_el & 1) { | |
797 | break; | |
798 | } | |
799 | } | |
800 | } | |
801 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); | |
802 | qemu_send_packet(&s->nic->nc, buf, size); | |
803 | s->statistics.tx_good_frames++; | |
804 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
805 | * (82557 only). Emulation never has bad status. */ | |
e7493b25 SW |
806 | #if 0 |
807 | eepro100_cx_interrupt(s); | |
808 | #endif | |
f3a52e50 SW |
809 | } |
810 | ||
7b8737de SW |
811 | static void set_multicast_list(EEPRO100State *s) |
812 | { | |
813 | uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); | |
814 | uint16_t i; | |
815 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
816 | TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); | |
817 | for (i = 0; i < multicast_count; i += 6) { | |
818 | uint8_t multicast_addr[6]; | |
819 | cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); | |
820 | TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); | |
821 | unsigned mcast_idx = compute_mcast_idx(multicast_addr); | |
822 | assert(mcast_idx < 64); | |
823 | s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); | |
824 | } | |
825 | } | |
826 | ||
5fa9a0ae | 827 | static void action_command(EEPRO100State *s) |
663e8e51 | 828 | { |
5fa9a0ae | 829 | for (;;) { |
3d0f4b9b SW |
830 | bool bit_el; |
831 | bool bit_s; | |
832 | bool bit_i; | |
833 | bool bit_nc; | |
75f5a6cc | 834 | uint16_t ok_status = STATUS_OK; |
3d0f4b9b SW |
835 | s->cb_address = s->cu_base + s->cu_offset; |
836 | read_cb(s); | |
837 | bit_el = ((s->tx.command & COMMAND_EL) != 0); | |
838 | bit_s = ((s->tx.command & COMMAND_S) != 0); | |
839 | bit_i = ((s->tx.command & COMMAND_I) != 0); | |
840 | bit_nc = ((s->tx.command & COMMAND_NC) != 0); | |
841 | #if 0 | |
842 | bool bit_sf = ((s->tx.command & COMMAND_SF) != 0); | |
843 | #endif | |
844 | s->cu_offset = s->tx.link; | |
845 | TRACE(OTHER, | |
846 | logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
847 | s->tx.status, s->tx.command, s->tx.link)); | |
848 | switch (s->tx.command & COMMAND_CMD) { | |
663e8e51 TS |
849 | case CmdNOp: |
850 | /* Do nothing. */ | |
851 | break; | |
852 | case CmdIASetup: | |
f3a52e50 | 853 | cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
ce0e58b3 | 854 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
663e8e51 TS |
855 | break; |
856 | case CmdConfigure: | |
f3a52e50 | 857 | cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], |
663e8e51 | 858 | sizeof(s->configuration)); |
aac443e6 | 859 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
860 | break; |
861 | case CmdMulticastList: | |
7b8737de | 862 | set_multicast_list(s); |
663e8e51 TS |
863 | break; |
864 | case CmdTx: | |
7f1e9d4e KW |
865 | if (bit_nc) { |
866 | missing("CmdTx: NC = 0"); | |
75f5a6cc | 867 | ok_status = 0; |
7f1e9d4e KW |
868 | break; |
869 | } | |
f3a52e50 | 870 | tx_command(s); |
663e8e51 TS |
871 | break; |
872 | case CmdTDR: | |
aac443e6 | 873 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
874 | /* Starting with offset 8, the command contains |
875 | * 64 dwords microcode which we just ignore here. */ | |
876 | break; | |
f80a7fc3 SW |
877 | case CmdDiagnose: |
878 | TRACE(OTHER, logout("diagnose\n")); | |
879 | /* Make sure error flag is not set. */ | |
880 | s->tx.status = 0; | |
881 | break; | |
663e8e51 TS |
882 | default: |
883 | missing("undefined command"); | |
75f5a6cc | 884 | ok_status = 0; |
7f1e9d4e | 885 | break; |
663e8e51 | 886 | } |
7f1e9d4e | 887 | /* Write new status. */ |
75f5a6cc | 888 | stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); |
663e8e51 TS |
889 | if (bit_i) { |
890 | /* CU completed action. */ | |
891 | eepro100_cx_interrupt(s); | |
892 | } | |
893 | if (bit_el) { | |
aac443e6 | 894 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
895 | set_cu_state(s, cu_idle); |
896 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 897 | break; |
663e8e51 | 898 | } else if (bit_s) { |
5fa9a0ae | 899 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
900 | set_cu_state(s, cu_suspended); |
901 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 902 | break; |
663e8e51 TS |
903 | } else { |
904 | /* More entries in list. */ | |
aac443e6 | 905 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 906 | } |
5fa9a0ae SW |
907 | } |
908 | TRACE(OTHER, logout("CU list empty\n")); | |
909 | /* List is empty. Now CU is idle or suspended. */ | |
910 | } | |
911 | ||
912 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
913 | { | |
cb25a3fb | 914 | cu_state_t cu_state; |
5fa9a0ae SW |
915 | switch (val) { |
916 | case CU_NOP: | |
917 | /* No operation. */ | |
918 | break; | |
919 | case CU_START: | |
cb25a3fb SW |
920 | cu_state = get_cu_state(s); |
921 | if (cu_state != cu_idle && cu_state != cu_suspended) { | |
922 | /* Intel documentation says that CU must be idle or suspended | |
923 | * for the CU start command. */ | |
924 | logout("unexpected CU state is %u\n", cu_state); | |
5fa9a0ae SW |
925 | } |
926 | set_cu_state(s, cu_active); | |
927 | s->cu_offset = s->pointer; | |
928 | action_command(s); | |
663e8e51 TS |
929 | break; |
930 | case CU_RESUME: | |
931 | if (get_cu_state(s) != cu_suspended) { | |
932 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
933 | /* Workaround for bad Linux eepro100 driver which resumes | |
934 | * from idle state. */ | |
e7493b25 SW |
935 | #if 0 |
936 | missing("cu resume"); | |
937 | #endif | |
663e8e51 TS |
938 | set_cu_state(s, cu_suspended); |
939 | } | |
940 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 941 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 942 | set_cu_state(s, cu_active); |
5fa9a0ae | 943 | action_command(s); |
663e8e51 TS |
944 | } |
945 | break; | |
946 | case CU_STATSADDR: | |
947 | /* Load dump counters address. */ | |
948 | s->statsaddr = s->pointer; | |
aac443e6 | 949 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
950 | break; |
951 | case CU_SHOWSTATS: | |
952 | /* Dump statistical counters. */ | |
aac443e6 | 953 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 954 | dump_statistics(s); |
ba42b646 | 955 | stl_le_phys(s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
956 | break; |
957 | case CU_CMD_BASE: | |
958 | /* Load CU base. */ | |
aac443e6 | 959 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
960 | s->cu_base = s->pointer; |
961 | break; | |
962 | case CU_DUMPSTATS: | |
963 | /* Dump and reset statistical counters. */ | |
aac443e6 | 964 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 965 | dump_statistics(s); |
ba42b646 | 966 | stl_le_phys(s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
967 | memset(&s->statistics, 0, sizeof(s->statistics)); |
968 | break; | |
969 | case CU_SRESUME: | |
970 | /* CU static resume. */ | |
971 | missing("CU static resume"); | |
972 | break; | |
973 | default: | |
974 | missing("Undefined CU command"); | |
975 | } | |
976 | } | |
977 | ||
978 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
979 | { | |
980 | switch (val) { | |
981 | case RU_NOP: | |
982 | /* No operation. */ | |
983 | break; | |
984 | case RX_START: | |
985 | /* RU start. */ | |
986 | if (get_ru_state(s) != ru_idle) { | |
987 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
e7493b25 SW |
988 | #if 0 |
989 | assert(!"wrong RU state"); | |
990 | #endif | |
663e8e51 TS |
991 | } |
992 | set_ru_state(s, ru_ready); | |
993 | s->ru_offset = s->pointer; | |
aac443e6 | 994 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
995 | break; |
996 | case RX_RESUME: | |
997 | /* Restart RU. */ | |
998 | if (get_ru_state(s) != ru_suspended) { | |
999 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
1000 | ru_suspended); | |
e7493b25 SW |
1001 | #if 0 |
1002 | assert(!"wrong RU state"); | |
1003 | #endif | |
663e8e51 TS |
1004 | } |
1005 | set_ru_state(s, ru_ready); | |
1006 | break; | |
e824012b SW |
1007 | case RU_ABORT: |
1008 | /* RU abort. */ | |
1009 | if (get_ru_state(s) == ru_ready) { | |
1010 | eepro100_rnr_interrupt(s); | |
1011 | } | |
1012 | set_ru_state(s, ru_idle); | |
1013 | break; | |
663e8e51 TS |
1014 | case RX_ADDR_LOAD: |
1015 | /* Load RU base. */ | |
aac443e6 | 1016 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
1017 | s->ru_base = s->pointer; |
1018 | break; | |
1019 | default: | |
1020 | logout("val=0x%02x (undefined RU command)\n", val); | |
1021 | missing("Undefined SU command"); | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1026 | { | |
1027 | eepro100_ru_command(s, val & 0x0f); | |
1028 | eepro100_cu_command(s, val & 0xf0); | |
1029 | if ((val) == 0) { | |
aac443e6 | 1030 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1031 | } |
1032 | /* Clear command byte after command was accepted. */ | |
1033 | s->mem[SCBCmd] = 0; | |
1034 | } | |
1035 | ||
1036 | /***************************************************************************** | |
1037 | * | |
1038 | * EEPROM emulation. | |
1039 | * | |
1040 | ****************************************************************************/ | |
1041 | ||
1042 | #define EEPROM_CS 0x02 | |
1043 | #define EEPROM_SK 0x01 | |
1044 | #define EEPROM_DI 0x04 | |
1045 | #define EEPROM_DO 0x08 | |
1046 | ||
1047 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1048 | { | |
1049 | uint16_t val; | |
1050 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
1051 | if (eeprom93xx_read(s->eeprom)) { | |
1052 | val |= EEPROM_DO; | |
1053 | } else { | |
1054 | val &= ~EEPROM_DO; | |
1055 | } | |
aac443e6 | 1056 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1057 | return val; |
1058 | } | |
1059 | ||
c227f099 | 1060 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1061 | { |
aac443e6 | 1062 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1063 | |
1064 | /* mask unwriteable bits */ | |
e7493b25 SW |
1065 | #if 0 |
1066 | val = SET_MASKED(val, 0x31, eeprom->value); | |
1067 | #endif | |
663e8e51 TS |
1068 | |
1069 | int eecs = ((val & EEPROM_CS) != 0); | |
1070 | int eesk = ((val & EEPROM_SK) != 0); | |
1071 | int eedi = ((val & EEPROM_DI) != 0); | |
1072 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1073 | } | |
1074 | ||
1075 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
1076 | { | |
1077 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 1078 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
1079 | } |
1080 | ||
1081 | /***************************************************************************** | |
1082 | * | |
1083 | * MDI emulation. | |
1084 | * | |
1085 | ****************************************************************************/ | |
1086 | ||
1087 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1088 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1089 | "opcode 0", |
1090 | "write", | |
1091 | "read", | |
1092 | "opcode 3" | |
1093 | }; | |
1094 | ||
6a0b9cc9 | 1095 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1096 | "Control", |
1097 | "Status", | |
1098 | "PHY Identification (Word 1)", | |
1099 | "PHY Identification (Word 2)", | |
1100 | "Auto-Negotiation Advertisement", | |
1101 | "Auto-Negotiation Link Partner Ability", | |
1102 | "Auto-Negotiation Expansion" | |
1103 | }; | |
aac443e6 SW |
1104 | |
1105 | static const char *reg2name(uint8_t reg) | |
1106 | { | |
1107 | static char buffer[10]; | |
1108 | const char *p = buffer; | |
1109 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1110 | p = mdi_reg_name[reg]; | |
1111 | } else { | |
1112 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1113 | } | |
1114 | return p; | |
1115 | } | |
663e8e51 TS |
1116 | #endif /* DEBUG_EEPRO100 */ |
1117 | ||
1118 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1119 | { | |
1120 | uint32_t val; | |
1121 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
1122 | ||
1123 | #ifdef DEBUG_EEPRO100 | |
1124 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1125 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1126 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1127 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1128 | uint16_t data = (val & BITS(15, 0)); | |
1129 | #endif | |
1130 | /* Emulation takes no time to finish MDI transaction. */ | |
1131 | val |= BIT(28); | |
1132 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1133 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1134 | reg2name(reg), data)); |
663e8e51 TS |
1135 | return val; |
1136 | } | |
1137 | ||
663e8e51 TS |
1138 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1139 | { | |
1140 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1141 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1142 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1143 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1144 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1145 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1146 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1147 | if (phy != 1) { |
1148 | /* Unsupported PHY address. */ | |
e7493b25 SW |
1149 | #if 0 |
1150 | logout("phy must be 1 but is %u\n", phy); | |
1151 | #endif | |
663e8e51 TS |
1152 | data = 0; |
1153 | } else if (opcode != 1 && opcode != 2) { | |
1154 | /* Unsupported opcode. */ | |
1155 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1156 | data = 0; | |
1157 | } else if (reg > 6) { | |
1158 | /* Unsupported register. */ | |
1159 | logout("register must be 0...6 but is %u\n", reg); | |
1160 | data = 0; | |
1161 | } else { | |
1162 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1163 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1164 | reg2name(reg), data)); |
663e8e51 TS |
1165 | if (opcode == 1) { |
1166 | /* MDI write */ | |
1167 | switch (reg) { | |
1168 | case 0: /* Control Register */ | |
1169 | if (data & 0x8000) { | |
1170 | /* Reset status and control registers to default. */ | |
1171 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1172 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1173 | data = s->mdimem[reg]; | |
1174 | } else { | |
1175 | /* Restart Auto Configuration = Normal Operation */ | |
1176 | data &= ~0x0200; | |
1177 | } | |
1178 | break; | |
1179 | case 1: /* Status Register */ | |
1180 | missing("not writable"); | |
1181 | data = s->mdimem[reg]; | |
1182 | break; | |
1183 | case 2: /* PHY Identification Register (Word 1) */ | |
1184 | case 3: /* PHY Identification Register (Word 2) */ | |
1185 | missing("not implemented"); | |
1186 | break; | |
1187 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1188 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1189 | break; | |
1190 | case 6: /* Auto-Negotiation Expansion Register */ | |
1191 | default: | |
1192 | missing("not implemented"); | |
1193 | } | |
1194 | s->mdimem[reg] = data; | |
1195 | } else if (opcode == 2) { | |
1196 | /* MDI read */ | |
1197 | switch (reg) { | |
1198 | case 0: /* Control Register */ | |
1199 | if (data & 0x8000) { | |
1200 | /* Reset status and control registers to default. */ | |
1201 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1202 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1203 | } | |
1204 | break; | |
1205 | case 1: /* Status Register */ | |
1206 | s->mdimem[reg] |= 0x0020; | |
1207 | break; | |
1208 | case 2: /* PHY Identification Register (Word 1) */ | |
1209 | case 3: /* PHY Identification Register (Word 2) */ | |
1210 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1211 | break; | |
1212 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1213 | s->mdimem[reg] = 0x41fe; | |
1214 | break; | |
1215 | case 6: /* Auto-Negotiation Expansion Register */ | |
1216 | s->mdimem[reg] = 0x0001; | |
1217 | break; | |
1218 | } | |
1219 | data = s->mdimem[reg]; | |
1220 | } | |
1221 | /* Emulation takes no time to finish MDI transaction. | |
1222 | * Set MDI bit in SCB status register. */ | |
1223 | s->mem[SCBAck] |= 0x08; | |
1224 | val |= BIT(28); | |
1225 | if (raiseint) { | |
1226 | eepro100_mdi_interrupt(s); | |
1227 | } | |
1228 | } | |
1229 | val = (val & 0xffff0000) + data; | |
1230 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1231 | } | |
1232 | ||
1233 | /***************************************************************************** | |
1234 | * | |
1235 | * Port emulation. | |
1236 | * | |
1237 | ****************************************************************************/ | |
1238 | ||
1239 | #define PORT_SOFTWARE_RESET 0 | |
1240 | #define PORT_SELFTEST 1 | |
1241 | #define PORT_SELECTIVE_RESET 2 | |
1242 | #define PORT_DUMP 3 | |
1243 | #define PORT_SELECTION_MASK 3 | |
1244 | ||
1245 | typedef struct { | |
1246 | uint32_t st_sign; /* Self Test Signature */ | |
1247 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1248 | } eepro100_selftest_t; |
663e8e51 TS |
1249 | |
1250 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1251 | { | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1256 | { | |
1257 | val = le32_to_cpu(val); | |
1258 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1259 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1260 | switch (selection) { | |
1261 | case PORT_SOFTWARE_RESET: | |
1262 | nic_reset(s); | |
1263 | break; | |
1264 | case PORT_SELFTEST: | |
aac443e6 | 1265 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1266 | eepro100_selftest_t data; |
663e8e51 TS |
1267 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1268 | data.st_sign = 0xffffffff; | |
1269 | data.st_result = 0; | |
1270 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1271 | break; | |
1272 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1273 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1274 | nic_selective_reset(s); |
1275 | break; | |
1276 | default: | |
1277 | logout("val=0x%08x\n", val); | |
1278 | missing("unknown port selection"); | |
1279 | } | |
1280 | } | |
1281 | ||
1282 | /***************************************************************************** | |
1283 | * | |
1284 | * General hardware emulation. | |
1285 | * | |
1286 | ****************************************************************************/ | |
1287 | ||
1288 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1289 | { | |
1290 | uint8_t val; | |
1291 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1292 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1293 | } | |
1294 | ||
1295 | switch (addr) { | |
1296 | case SCBStatus: | |
663e8e51 | 1297 | case SCBAck: |
aac443e6 | 1298 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1299 | break; |
1300 | case SCBCmd: | |
aac443e6 | 1301 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
e7493b25 SW |
1302 | #if 0 |
1303 | val = eepro100_read_command(s); | |
1304 | #endif | |
663e8e51 TS |
1305 | break; |
1306 | case SCBIntmask: | |
aac443e6 | 1307 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1308 | break; |
1309 | case SCBPort + 3: | |
aac443e6 | 1310 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1311 | break; |
1312 | case SCBeeprom: | |
1313 | val = eepro100_read_eeprom(s); | |
1314 | break; | |
0908bba1 | 1315 | case SCBpmdr: /* Power Management Driver Register */ |
663e8e51 | 1316 | val = 0; |
aac443e6 | 1317 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 | 1318 | break; |
0908bba1 | 1319 | case SCBgstat: /* General Status Register */ |
663e8e51 TS |
1320 | /* 100 Mbps full duplex, valid link */ |
1321 | val = 0x07; | |
aac443e6 | 1322 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1323 | break; |
1324 | default: | |
1325 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1326 | missing("unknown byte read"); | |
1327 | } | |
1328 | return val; | |
1329 | } | |
1330 | ||
1331 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1332 | { | |
1333 | uint16_t val; | |
1334 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1335 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1336 | } | |
1337 | ||
663e8e51 TS |
1338 | switch (addr) { |
1339 | case SCBStatus: | |
dbbaaff6 | 1340 | case SCBCmd: |
aac443e6 | 1341 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1342 | break; |
1343 | case SCBeeprom: | |
1344 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1345 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1346 | break; |
1347 | default: | |
1348 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1349 | missing("unknown word read"); | |
1350 | } | |
1351 | return val; | |
1352 | } | |
1353 | ||
1354 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1355 | { | |
1356 | uint32_t val; | |
1357 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1358 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1359 | } | |
1360 | ||
1361 | switch (addr) { | |
1362 | case SCBStatus: | |
aac443e6 | 1363 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1364 | break; |
1365 | case SCBPointer: | |
e7493b25 SW |
1366 | #if 0 |
1367 | val = eepro100_read_pointer(s); | |
1368 | #endif | |
aac443e6 | 1369 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1370 | break; |
1371 | case SCBPort: | |
1372 | val = eepro100_read_port(s); | |
aac443e6 | 1373 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1374 | break; |
1375 | case SCBCtrlMDI: | |
1376 | val = eepro100_read_mdi(s); | |
1377 | break; | |
1378 | default: | |
1379 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1380 | missing("unknown longword read"); | |
1381 | } | |
1382 | return val; | |
1383 | } | |
1384 | ||
1385 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1386 | { | |
e74818f3 SW |
1387 | /* SCBStatus is readonly. */ |
1388 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
663e8e51 TS |
1389 | memcpy(&s->mem[addr], &val, sizeof(val)); |
1390 | } | |
1391 | ||
aac443e6 | 1392 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1393 | |
1394 | switch (addr) { | |
1395 | case SCBStatus: | |
663e8e51 TS |
1396 | break; |
1397 | case SCBAck: | |
1398 | eepro100_acknowledge(s); | |
1399 | break; | |
1400 | case SCBCmd: | |
1401 | eepro100_write_command(s, val); | |
1402 | break; | |
1403 | case SCBIntmask: | |
1404 | if (val & BIT(1)) { | |
1405 | eepro100_swi_interrupt(s); | |
1406 | } | |
1407 | eepro100_interrupt(s, 0); | |
1408 | break; | |
1409 | case SCBPort + 3: | |
aac443e6 | 1410 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1411 | case SCBFlow + 1: |
1412 | case SCBFlow + 2: | |
0908bba1 | 1413 | case SCBpmdr: /* does not exist on 82557 */ |
aac443e6 | 1414 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1415 | break; |
1416 | case SCBeeprom: | |
1417 | eepro100_write_eeprom(s->eeprom, val); | |
1418 | break; | |
1419 | default: | |
1420 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1421 | missing("unknown byte write"); | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1426 | { | |
e74818f3 SW |
1427 | /* SCBStatus is readonly. */ |
1428 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
663e8e51 TS |
1429 | memcpy(&s->mem[addr], &val, sizeof(val)); |
1430 | } | |
1431 | ||
aac443e6 | 1432 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1433 | |
1434 | switch (addr) { | |
1435 | case SCBStatus: | |
e74818f3 | 1436 | s->mem[SCBAck] = (val >> 8); |
663e8e51 TS |
1437 | eepro100_acknowledge(s); |
1438 | break; | |
1439 | case SCBCmd: | |
1440 | eepro100_write_command(s, val); | |
1441 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1442 | break; | |
1443 | case SCBeeprom: | |
1444 | eepro100_write_eeprom(s->eeprom, val); | |
1445 | break; | |
1446 | default: | |
1447 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1448 | missing("unknown word write"); | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1453 | { | |
1454 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1455 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1456 | } | |
1457 | ||
1458 | switch (addr) { | |
1459 | case SCBPointer: | |
1460 | eepro100_write_pointer(s, val); | |
1461 | break; | |
1462 | case SCBPort: | |
aac443e6 | 1463 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1464 | eepro100_write_port(s, val); |
1465 | break; | |
1466 | case SCBCtrlMDI: | |
1467 | eepro100_write_mdi(s, val); | |
1468 | break; | |
1469 | default: | |
1470 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1471 | missing("unknown longword write"); | |
1472 | } | |
1473 | } | |
1474 | ||
aac443e6 SW |
1475 | /***************************************************************************** |
1476 | * | |
1477 | * Port mapped I/O. | |
1478 | * | |
1479 | ****************************************************************************/ | |
1480 | ||
663e8e51 TS |
1481 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1482 | { | |
1483 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1484 | #if 0 |
1485 | logout("addr=%s\n", regname(addr)); | |
1486 | #endif | |
663e8e51 TS |
1487 | return eepro100_read1(s, addr - s->region[1]); |
1488 | } | |
1489 | ||
1490 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1491 | { | |
1492 | EEPRO100State *s = opaque; | |
1493 | return eepro100_read2(s, addr - s->region[1]); | |
1494 | } | |
1495 | ||
1496 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1497 | { | |
1498 | EEPRO100State *s = opaque; | |
1499 | return eepro100_read4(s, addr - s->region[1]); | |
1500 | } | |
1501 | ||
1502 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1503 | { | |
1504 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1505 | #if 0 |
1506 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1507 | #endif | |
663e8e51 TS |
1508 | eepro100_write1(s, addr - s->region[1], val); |
1509 | } | |
1510 | ||
1511 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1512 | { | |
1513 | EEPRO100State *s = opaque; | |
1514 | eepro100_write2(s, addr - s->region[1], val); | |
1515 | } | |
1516 | ||
1517 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1518 | { | |
1519 | EEPRO100State *s = opaque; | |
1520 | eepro100_write4(s, addr - s->region[1], val); | |
1521 | } | |
1522 | ||
1523 | /***********************************************************/ | |
1524 | /* PCI EEPRO100 definitions */ | |
1525 | ||
663e8e51 | 1526 | static void pci_map(PCIDevice * pci_dev, int region_num, |
6e355d90 | 1527 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1528 | { |
273a2142 | 1529 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1530 | |
89e8b13c IY |
1531 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1532 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1533 | region_num, addr, size, type)); |
663e8e51 TS |
1534 | |
1535 | assert(region_num == 1); | |
1536 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1537 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1538 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1539 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1540 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1541 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1542 | ||
1543 | s->region[region_num] = addr; | |
1544 | } | |
1545 | ||
aac443e6 SW |
1546 | /***************************************************************************** |
1547 | * | |
1548 | * Memory mapped I/O. | |
1549 | * | |
1550 | ****************************************************************************/ | |
1551 | ||
c227f099 | 1552 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1553 | { |
1554 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1555 | #if 0 |
1556 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1557 | #endif | |
663e8e51 TS |
1558 | eepro100_write1(s, addr, val); |
1559 | } | |
1560 | ||
c227f099 | 1561 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1562 | { |
1563 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1564 | #if 0 |
1565 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1566 | #endif | |
663e8e51 TS |
1567 | eepro100_write2(s, addr, val); |
1568 | } | |
1569 | ||
c227f099 | 1570 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1571 | { |
1572 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1573 | #if 0 |
1574 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1575 | #endif | |
663e8e51 TS |
1576 | eepro100_write4(s, addr, val); |
1577 | } | |
1578 | ||
c227f099 | 1579 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1580 | { |
1581 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1582 | #if 0 |
1583 | logout("addr=%s\n", regname(addr)); | |
1584 | #endif | |
663e8e51 TS |
1585 | return eepro100_read1(s, addr); |
1586 | } | |
1587 | ||
c227f099 | 1588 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1589 | { |
1590 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1591 | #if 0 |
1592 | logout("addr=%s\n", regname(addr)); | |
1593 | #endif | |
663e8e51 TS |
1594 | return eepro100_read2(s, addr); |
1595 | } | |
1596 | ||
c227f099 | 1597 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1598 | { |
1599 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1600 | #if 0 |
1601 | logout("addr=%s\n", regname(addr)); | |
1602 | #endif | |
663e8e51 TS |
1603 | return eepro100_read4(s, addr); |
1604 | } | |
1605 | ||
d60efc6b | 1606 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1607 | pci_mmio_writeb, |
1608 | pci_mmio_writew, | |
1609 | pci_mmio_writel | |
1610 | }; | |
1611 | ||
d60efc6b | 1612 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1613 | pci_mmio_readb, |
1614 | pci_mmio_readw, | |
1615 | pci_mmio_readl | |
1616 | }; | |
1617 | ||
1618 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
6e355d90 | 1619 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1620 | { |
273a2142 | 1621 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1622 | |
89e8b13c IY |
1623 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1624 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1625 | region_num, addr, size, type)); |
663e8e51 | 1626 | |
269eba07 SW |
1627 | assert(region_num == 0 || region_num == 2); |
1628 | ||
1629 | /* Map control / status registers and flash. */ | |
1630 | cpu_register_physical_memory(addr, size, s->mmio_index); | |
1631 | s->region[region_num] = addr; | |
663e8e51 TS |
1632 | } |
1633 | ||
e00e365e | 1634 | static int nic_can_receive(VLANClientState *nc) |
663e8e51 | 1635 | { |
e00e365e | 1636 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
aac443e6 | 1637 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 | 1638 | return get_ru_state(s) == ru_ready; |
e7493b25 SW |
1639 | #if 0 |
1640 | return !eepro100_buffer_full(s); | |
1641 | #endif | |
663e8e51 TS |
1642 | } |
1643 | ||
e00e365e | 1644 | static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1645 | { |
1646 | /* TODO: | |
1647 | * - Magic packets should set bit 30 in power management driver register. | |
1648 | * - Interesting packets should set bit 29 in power management driver register. | |
1649 | */ | |
e00e365e | 1650 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
663e8e51 TS |
1651 | uint16_t rfd_status = 0xa000; |
1652 | static const uint8_t broadcast_macaddr[6] = | |
1653 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1654 | ||
1655 | /* TODO: check multiple IA bit. */ | |
7f1e9d4e KW |
1656 | if (s->configuration[20] & BIT(6)) { |
1657 | missing("Multiple IA bit"); | |
1658 | return -1; | |
1659 | } | |
663e8e51 TS |
1660 | |
1661 | if (s->configuration[8] & 0x80) { | |
1662 | /* CSMA is disabled. */ | |
1663 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1664 | return -1; |
ced5296a | 1665 | } else if (size < 64 && (s->configuration[7] & BIT(0))) { |
663e8e51 TS |
1666 | /* Short frame and configuration byte 7/0 (discard short receive) set: |
1667 | * Short frame is discarded */ | |
067d01de | 1668 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1669 | s->statistics.rx_short_frame_errors++; |
e7493b25 SW |
1670 | #if 0 |
1671 | return -1; | |
1672 | #endif | |
ced5296a | 1673 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { |
663e8e51 TS |
1674 | /* Long frame and configuration byte 18/3 (long receive ok) not set: |
1675 | * Long frames are discarded. */ | |
067d01de | 1676 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1677 | return -1; |
e7493b25 | 1678 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ |
663e8e51 TS |
1679 | /* Frame matches individual address. */ |
1680 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1681 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1682 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1683 | /* Broadcast frame. */ | |
067d01de | 1684 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 | 1685 | rfd_status |= 0x0002; |
7b8737de | 1686 | } else if (buf[0] & 0x01) { |
663e8e51 | 1687 | /* Multicast frame. */ |
7b8737de | 1688 | TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size))); |
7f1e9d4e | 1689 | if (s->configuration[21] & BIT(3)) { |
7b8737de SW |
1690 | /* Multicast all bit is set, receive all multicast frames. */ |
1691 | } else { | |
1692 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1693 | assert(mcast_idx < 64); | |
1694 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1695 | /* Multicast frame is allowed in hash table. */ | |
ced5296a | 1696 | } else if (s->configuration[15] & BIT(0)) { |
7b8737de SW |
1697 | /* Promiscuous: receive all. */ |
1698 | rfd_status |= 0x0004; | |
1699 | } else { | |
1700 | TRACE(RXTX, logout("%p multicast ignored\n", s)); | |
1701 | return -1; | |
1702 | } | |
663e8e51 | 1703 | } |
7b8737de | 1704 | /* TODO: Next not for promiscuous mode? */ |
663e8e51 | 1705 | rfd_status |= 0x0002; |
ced5296a | 1706 | } else if (s->configuration[15] & BIT(0)) { |
663e8e51 | 1707 | /* Promiscuous: receive all. */ |
067d01de | 1708 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1709 | rfd_status |= 0x0004; |
1710 | } else { | |
067d01de | 1711 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1712 | nic_dump(buf, size))); |
4f1c942b | 1713 | return size; |
663e8e51 TS |
1714 | } |
1715 | ||
1716 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1717 | /* No resources available. */ |
1718 | logout("no resources, state=%u\n", get_ru_state(s)); | |
e824012b SW |
1719 | /* TODO: RNR interrupt only at first failed frame? */ |
1720 | eepro100_rnr_interrupt(s); | |
663e8e51 | 1721 | s->statistics.rx_resource_errors++; |
e7493b25 SW |
1722 | #if 0 |
1723 | assert(!"no resources"); | |
1724 | #endif | |
4f1c942b | 1725 | return -1; |
663e8e51 | 1726 | } |
e7493b25 | 1727 | /* !!! */ |
c227f099 | 1728 | eepro100_rx_t rx; |
663e8e51 | 1729 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1730 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1731 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1732 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1733 | |
1734 | if (size > rfd_size) { | |
1735 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1736 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1737 | size = rfd_size; | |
1738 | } | |
663e8e51 TS |
1739 | if (size < 64) { |
1740 | rfd_status |= 0x0080; | |
1741 | } | |
aac443e6 SW |
1742 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1743 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1744 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1745 | rfd_status); |
c227f099 | 1746 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 | 1747 | /* Early receive interrupt not supported. */ |
e7493b25 SW |
1748 | #if 0 |
1749 | eepro100_er_interrupt(s); | |
1750 | #endif | |
663e8e51 | 1751 | /* Receive CRC Transfer not supported. */ |
ced5296a | 1752 | if (s->configuration[18] & BIT(2)) { |
7f1e9d4e KW |
1753 | missing("Receive CRC Transfer"); |
1754 | return -1; | |
1755 | } | |
663e8e51 | 1756 | /* TODO: check stripping enable bit. */ |
e7493b25 SW |
1757 | #if 0 |
1758 | assert(!(s->configuration[17] & BIT(0))); | |
1759 | #endif | |
663e8e51 | 1760 | cpu_physical_memory_write(s->ru_base + s->ru_offset + |
c227f099 | 1761 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1762 | s->statistics.rx_good_frames++; |
1763 | eepro100_fr_interrupt(s); | |
1764 | s->ru_offset = le32_to_cpu(rx.link); | |
ced5296a | 1765 | if (rfd_command & COMMAND_EL) { |
663e8e51 | 1766 | /* EL bit is set, so this was the last frame. */ |
7f1e9d4e KW |
1767 | logout("receive: Running out of frames\n"); |
1768 | set_ru_state(s, ru_suspended); | |
663e8e51 | 1769 | } |
ced5296a | 1770 | if (rfd_command & COMMAND_S) { |
663e8e51 TS |
1771 | /* S bit is set. */ |
1772 | set_ru_state(s, ru_suspended); | |
1773 | } | |
4f1c942b | 1774 | return size; |
663e8e51 TS |
1775 | } |
1776 | ||
151b2986 JQ |
1777 | static const VMStateDescription vmstate_eepro100 = { |
1778 | .version_id = 3, | |
1779 | .minimum_version_id = 2, | |
1780 | .minimum_version_id_old = 2, | |
1781 | .fields = (VMStateField []) { | |
1782 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1783 | VMSTATE_UNUSED(32), | |
1784 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1785 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1786 | /* Save all members of struct between scb_stat and mem. */ | |
1787 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1788 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1789 | VMSTATE_UNUSED(3*4), | |
1790 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1791 | VMSTATE_UNUSED(19*4), | |
1792 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1793 | /* The eeprom should be saved and restored by its own routines. */ | |
1794 | VMSTATE_UINT32(device, EEPRO100State), | |
1795 | /* TODO check device. */ | |
1796 | VMSTATE_UINT32(pointer, EEPRO100State), | |
1797 | VMSTATE_UINT32(cu_base, EEPRO100State), | |
1798 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1799 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1800 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1801 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1802 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1803 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1804 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1805 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1806 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1807 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1808 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1809 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1810 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1811 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1812 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1813 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1814 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1815 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1816 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1817 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1818 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1819 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1820 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1821 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1822 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1823 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
151b2986 JQ |
1824 | /* Configuration bytes. */ |
1825 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1826 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1827 | } |
151b2986 | 1828 | }; |
663e8e51 | 1829 | |
e00e365e | 1830 | static void nic_cleanup(VLANClientState *nc) |
b946a153 | 1831 | { |
e00e365e | 1832 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b946a153 | 1833 | |
e00e365e | 1834 | s->nic = NULL; |
b946a153 AL |
1835 | } |
1836 | ||
c4c270e2 | 1837 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1838 | { |
c4c270e2 | 1839 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1840 | |
1841 | cpu_unregister_io_memory(s->mmio_index); | |
151b2986 | 1842 | vmstate_unregister(s->vmstate, s); |
508ef936 | 1843 | eeprom93xx_free(s->eeprom); |
e00e365e | 1844 | qemu_del_vlan_client(&s->nic->nc); |
b946a153 AL |
1845 | return 0; |
1846 | } | |
1847 | ||
e00e365e MM |
1848 | static NetClientInfo net_eepro100_info = { |
1849 | .type = NET_CLIENT_TYPE_NIC, | |
1850 | .size = sizeof(NICState), | |
1851 | .can_receive = nic_can_receive, | |
1852 | .receive = nic_receive, | |
1853 | .cleanup = nic_cleanup, | |
1854 | }; | |
1855 | ||
558c8634 | 1856 | static int e100_nic_init(PCIDevice *pci_dev) |
663e8e51 | 1857 | { |
273a2142 | 1858 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
558c8634 SW |
1859 | E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev, |
1860 | pci_dev->qdev.info); | |
663e8e51 | 1861 | |
aac443e6 | 1862 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1863 | |
558c8634 | 1864 | s->device = e100_device->device; |
663e8e51 | 1865 | |
558c8634 | 1866 | e100_pci_reset(s, e100_device); |
663e8e51 TS |
1867 | |
1868 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1869 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1870 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1871 | ||
1872 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1873 | s->mmio_index = |
1eed09cb | 1874 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1875 | |
273a2142 | 1876 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
0392a017 IY |
1877 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
1878 | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map); | |
1879 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO, | |
663e8e51 | 1880 | pci_map); |
0392a017 | 1881 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, |
663e8e51 TS |
1882 | pci_mmio_map); |
1883 | ||
508ef936 | 1884 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
ce0e58b3 | 1885 | logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
663e8e51 TS |
1886 | assert(s->region[1] == 0); |
1887 | ||
1888 | nic_reset(s); | |
1889 | ||
e00e365e MM |
1890 | s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1891 | pci_dev->qdev.info->name, pci_dev->qdev.id, s); | |
663e8e51 | 1892 | |
e00e365e MM |
1893 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1894 | TRACE(OTHER, logout("%s\n", s->nic->nc.info_str)); | |
663e8e51 | 1895 | |
a08d4367 | 1896 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1897 | |
151b2986 JQ |
1898 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
1899 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
e00e365e | 1900 | s->vmstate->name = s->nic->nc.model; |
151b2986 | 1901 | vmstate_register(-1, s->vmstate, s); |
4e9df06a | 1902 | |
81a322d4 | 1903 | return 0; |
663e8e51 TS |
1904 | } |
1905 | ||
558c8634 | 1906 | static E100PCIDeviceInfo e100_devices[] = { |
0aab0d3a | 1907 | { |
558c8634 SW |
1908 | .pci.qdev.name = "i82550", |
1909 | .pci.qdev.desc = "Intel i82550 Ethernet", | |
1910 | .device = i82550, | |
1911 | /* TODO: check device id. */ | |
1912 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
1913 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ | |
1914 | .revision = 0x0e, | |
1915 | /* TODO: check size of statistical counters. */ | |
1916 | .stats_size = 80, | |
1917 | /* TODO: check extended tcb support. */ | |
1918 | .has_extended_tcb_support = true, | |
1919 | .power_management = true, | |
c4c270e2 | 1920 | },{ |
558c8634 SW |
1921 | .pci.qdev.name = "i82551", |
1922 | .pci.qdev.desc = "Intel i82551 Ethernet", | |
1923 | .device = i82551, | |
1924 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
1925 | /* Revision ID: 0x0f, 0x10. */ | |
1926 | .revision = 0x0f, | |
1927 | /* TODO: check size of statistical counters. */ | |
1928 | .stats_size = 80, | |
1929 | .has_extended_tcb_support = true, | |
1930 | .power_management = true, | |
0aab0d3a | 1931 | },{ |
558c8634 SW |
1932 | .pci.qdev.name = "i82557a", |
1933 | .pci.qdev.desc = "Intel i82557A Ethernet", | |
1934 | .device = i82557A, | |
1935 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1936 | .revision = 0x01, | |
1937 | .power_management = false, | |
c4c270e2 | 1938 | },{ |
558c8634 SW |
1939 | .pci.qdev.name = "i82557b", |
1940 | .pci.qdev.desc = "Intel i82557B Ethernet", | |
1941 | .device = i82557B, | |
1942 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1943 | .revision = 0x02, | |
1944 | .power_management = false, | |
c4c270e2 | 1945 | },{ |
558c8634 SW |
1946 | .pci.qdev.name = "i82557c", |
1947 | .pci.qdev.desc = "Intel i82557C Ethernet", | |
1948 | .device = i82557C, | |
1949 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1950 | .revision = 0x03, | |
1951 | .power_management = false, | |
c4c270e2 | 1952 | },{ |
558c8634 SW |
1953 | .pci.qdev.name = "i82558a", |
1954 | .pci.qdev.desc = "Intel i82558A Ethernet", | |
1955 | .device = i82558A, | |
1956 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1957 | .revision = 0x04, | |
1958 | .stats_size = 76, | |
1959 | .has_extended_tcb_support = true, | |
1960 | .power_management = true, | |
c4c270e2 | 1961 | },{ |
558c8634 SW |
1962 | .pci.qdev.name = "i82558b", |
1963 | .pci.qdev.desc = "Intel i82558B Ethernet", | |
1964 | .device = i82558B, | |
1965 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1966 | .revision = 0x05, | |
1967 | .stats_size = 76, | |
1968 | .has_extended_tcb_support = true, | |
1969 | .power_management = true, | |
c4c270e2 | 1970 | },{ |
558c8634 SW |
1971 | .pci.qdev.name = "i82559a", |
1972 | .pci.qdev.desc = "Intel i82559A Ethernet", | |
1973 | .device = i82559A, | |
1974 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1975 | .revision = 0x06, | |
1976 | .stats_size = 80, | |
1977 | .has_extended_tcb_support = true, | |
1978 | .power_management = true, | |
c4c270e2 | 1979 | },{ |
558c8634 SW |
1980 | .pci.qdev.name = "i82559b", |
1981 | .pci.qdev.desc = "Intel i82559B Ethernet", | |
1982 | .device = i82559B, | |
1983 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1984 | .revision = 0x07, | |
1985 | .stats_size = 80, | |
1986 | .has_extended_tcb_support = true, | |
1987 | .power_management = true, | |
0aab0d3a | 1988 | },{ |
558c8634 SW |
1989 | .pci.qdev.name = "i82559c", |
1990 | .pci.qdev.desc = "Intel i82559C Ethernet", | |
1991 | .device = i82559C, | |
1992 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
1993 | #if 0 | |
1994 | .revision = 0x08, | |
1995 | #endif | |
1996 | /* TODO: Windows wants revision id 0x0c. */ | |
1997 | .revision = 0x0c, | |
1998 | .stats_size = 80, | |
1999 | .has_extended_tcb_support = true, | |
2000 | .power_management = true, | |
c4c270e2 | 2001 | },{ |
558c8634 SW |
2002 | .pci.qdev.name = "i82559er", |
2003 | .pci.qdev.desc = "Intel i82559ER Ethernet", | |
2004 | .device = i82559ER, | |
2005 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2006 | .revision = 0x09, | |
2007 | .stats_size = 80, | |
2008 | .has_extended_tcb_support = true, | |
2009 | .power_management = true, | |
0aab0d3a | 2010 | },{ |
558c8634 SW |
2011 | .pci.qdev.name = "i82562", |
2012 | .pci.qdev.desc = "Intel i82562 Ethernet", | |
2013 | .device = i82562, | |
2014 | /* TODO: check device id. */ | |
2015 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2016 | /* TODO: wrong revision id. */ | |
2017 | .revision = 0x0e, | |
2018 | .stats_size = 80, | |
2019 | .has_extended_tcb_support = true, | |
2020 | .power_management = true, | |
db667a12 SW |
2021 | },{ |
2022 | /* Toshiba Tecra 8200. */ | |
2023 | .pci.qdev.name = "i82801", | |
2024 | .pci.qdev.desc = "Intel i82801 Ethernet", | |
2025 | .device = i82801, | |
2026 | .device_id = 0x2449, | |
2027 | .revision = 0x03, | |
2028 | .stats_size = 80, | |
2029 | .has_extended_tcb_support = true, | |
2030 | .power_management = true, | |
0aab0d3a GH |
2031 | } |
2032 | }; | |
2033 | ||
558c8634 SW |
2034 | static Property e100_properties[] = { |
2035 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2036 | DEFINE_PROP_END_OF_LIST(), | |
2037 | }; | |
2038 | ||
9d07d757 | 2039 | static void eepro100_register_devices(void) |
663e8e51 | 2040 | { |
558c8634 SW |
2041 | size_t i; |
2042 | for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { | |
2043 | PCIDeviceInfo *pci_dev = &e100_devices[i].pci; | |
2044 | switch (e100_devices[i].device_id) { | |
2045 | case PCI_DEVICE_ID_INTEL_82551IT: | |
2046 | pci_dev->romfile = "gpxe-eepro100-80861209.rom"; | |
2047 | break; | |
2048 | case PCI_DEVICE_ID_INTEL_82557: | |
2049 | pci_dev->romfile = "gpxe-eepro100-80861229.rom"; | |
2050 | break; | |
db667a12 SW |
2051 | case 0x2449: |
2052 | pci_dev->romfile = "gpxe-eepro100-80862449.rom"; | |
2053 | break; | |
558c8634 SW |
2054 | } |
2055 | pci_dev->init = e100_nic_init; | |
2056 | pci_dev->exit = pci_nic_uninit; | |
2057 | pci_dev->qdev.props = e100_properties; | |
2058 | pci_dev->qdev.size = sizeof(EEPRO100State); | |
2059 | pci_qdev_register(pci_dev); | |
2060 | } | |
663e8e51 TS |
2061 | } |
2062 | ||
9d07d757 | 2063 | device_init(eepro100_register_devices) |