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Commit | Line | Data |
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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
4 | * Copyright (c) 2006-2007 Stefan Weil | |
5 | * | |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
6cded3a4 | 23 | * PXE boot (i386) ok |
663e8e51 TS |
24 | * Linux networking (i386) ok |
25 | * | |
26 | * Untested: | |
27 | * non-i386 platforms | |
28 | * Windows networking | |
29 | * | |
30 | * References: | |
31 | * | |
32 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
33 | * Open Source Software Developer Manual | |
ba19f2de SW |
34 | * |
35 | * TODO: | |
36 | * * PHY emulation should be separated from nic emulation. | |
37 | * Most nic emulations could share the same phy code. | |
38 | * * i82550 is untested. It is programmed like the i82559. | |
39 | * * i82562 is untested. It is programmed like the i82559. | |
40 | * * Power management (i82558 and later) is not implemented. | |
41 | * * Wake-on-LAN is not implemented. | |
663e8e51 TS |
42 | */ |
43 | ||
663e8e51 | 44 | #include <stddef.h> /* offsetof */ |
b84a5c6f | 45 | #include <stdbool.h> |
87ecb68b PB |
46 | #include "hw.h" |
47 | #include "pci.h" | |
48 | #include "net.h" | |
663e8e51 TS |
49 | #include "eeprom93xx.h" |
50 | ||
51 | /* Common declarations for all PCI devices. */ | |
52 | ||
663e8e51 TS |
53 | #define PCI_CONFIG_8(offset, value) \ |
54 | (pci_conf[offset] = (value)) | |
55 | #define PCI_CONFIG_16(offset, value) \ | |
56 | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) | |
57 | #define PCI_CONFIG_32(offset, value) \ | |
58 | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) | |
59 | ||
60 | #define KiB 1024 | |
61 | ||
aac443e6 | 62 | /* Debug EEPRO100 card. */ |
ce0e58b3 SW |
63 | #if 0 |
64 | # define DEBUG_EEPRO100 | |
65 | #endif | |
663e8e51 TS |
66 | |
67 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 68 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 69 | #else |
001faf32 | 70 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
71 | #endif |
72 | ||
73 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
74 | #define INT 1 /* interrupt related actions */ |
75 | #define MDI 1 /* mdi related actions */ | |
76 | #define OTHER 1 | |
77 | #define RXTX 1 | |
78 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
79 | |
80 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
81 | ||
7f1e9d4e | 82 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
83 | |
84 | #define MAX_ETH_FRAME_SIZE 1514 | |
85 | ||
86 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 87 | #define i82550 0x82550 |
663e8e51 | 88 | #define i82551 0x82551 |
c4c270e2 | 89 | #define i82557A 0x82557a |
663e8e51 TS |
90 | #define i82557B 0x82557b |
91 | #define i82557C 0x82557c | |
c4c270e2 | 92 | #define i82558A 0x82558a |
663e8e51 | 93 | #define i82558B 0x82558b |
c4c270e2 SW |
94 | #define i82559A 0x82559a |
95 | #define i82559B 0x82559b | |
663e8e51 TS |
96 | #define i82559C 0x82559c |
97 | #define i82559ER 0x82559e | |
98 | #define i82562 0x82562 | |
99 | ||
aac443e6 | 100 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
101 | #define EEPROM_SIZE 64 |
102 | ||
103 | #define PCI_MEM_SIZE (4 * KiB) | |
104 | #define PCI_IO_SIZE 64 | |
105 | #define PCI_FLASH_SIZE (128 * KiB) | |
106 | ||
107 | #define BIT(n) (1 << (n)) | |
108 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
109 | ||
110 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
111 | #define CU_NOP 0x0000 /* No operation. */ | |
112 | #define CU_START 0x0010 /* CU start. */ | |
113 | #define CU_RESUME 0x0020 /* CU resume. */ | |
114 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
115 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
116 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
117 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
118 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
119 | ||
120 | #define RU_NOP 0x0000 | |
121 | #define RX_START 0x0001 | |
122 | #define RX_RESUME 0x0002 | |
123 | #define RX_ABORT 0x0004 | |
124 | #define RX_ADDR_LOAD 0x0006 | |
125 | #define RX_RESUMENR 0x0007 | |
126 | #define INT_MASK 0x0100 | |
127 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
128 | ||
663e8e51 TS |
129 | /* Offsets to the various registers. |
130 | All accesses need not be longword aligned. */ | |
131 | enum speedo_offsets { | |
0908bba1 | 132 | SCBStatus = 0, /* Status Word. */ |
663e8e51 TS |
133 | SCBAck = 1, |
134 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
135 | SCBIntmask = 3, | |
136 | SCBPointer = 4, /* General purpose pointer. */ | |
137 | SCBPort = 8, /* Misc. commands and operands. */ | |
0908bba1 SW |
138 | SCBflash = 12, /* Flash memory control. */ |
139 | SCBeeprom = 14, /* EEPROM control. */ | |
663e8e51 TS |
140 | SCBCtrlMDI = 16, /* MDI interface control. */ |
141 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
0908bba1 SW |
142 | SCBFlow = 24, /* Flow Control. */ |
143 | SCBpmdr = 27, /* Power Management Driver. */ | |
144 | SCBgctrl = 28, /* General Control. */ | |
145 | SCBgstat = 29, /* General Status. */ | |
663e8e51 TS |
146 | }; |
147 | ||
148 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
149 | typedef struct { | |
150 | uint16_t status; | |
151 | uint16_t command; | |
152 | uint32_t link; /* void * */ | |
7b8737de | 153 | uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */ |
663e8e51 TS |
154 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ |
155 | uint8_t tx_threshold; /* transmit threshold */ | |
156 | uint8_t tbd_count; /* TBD number */ | |
157 | //~ /* This constitutes two "TBD" entries: hdr and data */ | |
158 | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
159 | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
160 | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
161 | //~ int32_t tx_buf_size1; /* Length of Tx data. */ | |
c227f099 | 162 | } eepro100_tx_t; |
663e8e51 TS |
163 | |
164 | /* Receive frame descriptor. */ | |
165 | typedef struct { | |
166 | int16_t status; | |
167 | uint16_t command; | |
168 | uint32_t link; /* struct RxFD * */ | |
169 | uint32_t rx_buf_addr; /* void * */ | |
170 | uint16_t count; | |
171 | uint16_t size; | |
172 | char packet[MAX_ETH_FRAME_SIZE + 4]; | |
c227f099 | 173 | } eepro100_rx_t; |
663e8e51 TS |
174 | |
175 | typedef struct { | |
176 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
177 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, | |
178 | tx_multiple_collisions, tx_total_collisions; | |
179 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, | |
180 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, | |
181 | rx_short_frame_errors; | |
182 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; | |
183 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
184 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
185 | uint32_t reserved[4]; | |
c227f099 | 186 | } eepro100_stats_t; |
663e8e51 TS |
187 | |
188 | typedef enum { | |
189 | cu_idle = 0, | |
190 | cu_suspended = 1, | |
191 | cu_active = 2, | |
192 | cu_lpq_active = 2, | |
193 | cu_hqp_active = 3 | |
c227f099 | 194 | } cu_state_t; |
663e8e51 TS |
195 | |
196 | typedef enum { | |
197 | ru_idle = 0, | |
198 | ru_suspended = 1, | |
199 | ru_no_resources = 2, | |
200 | ru_ready = 4 | |
c227f099 | 201 | } ru_state_t; |
663e8e51 | 202 | |
663e8e51 | 203 | typedef struct { |
273a2142 | 204 | PCIDevice dev; |
663e8e51 TS |
205 | uint8_t mult[8]; /* multicast mask array */ |
206 | int mmio_index; | |
e00e365e | 207 | NICState *nic; |
508ef936 | 208 | NICConf conf; |
663e8e51 TS |
209 | uint8_t scb_stat; /* SCB stat/ack byte */ |
210 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 211 | /* region must not be saved by nic_save. */ |
663e8e51 | 212 | uint32_t region[3]; /* PCI region addresses */ |
663e8e51 | 213 | uint16_t mdimem[32]; |
c227f099 | 214 | eeprom_t *eeprom; |
663e8e51 TS |
215 | uint32_t device; /* device variant */ |
216 | uint32_t pointer; | |
217 | /* (cu_base + cu_offset) address the next command block in the command block list. */ | |
218 | uint32_t cu_base; /* CU base address */ | |
219 | uint32_t cu_offset; /* CU address offset */ | |
220 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
221 | uint32_t ru_base; /* RU base address */ | |
222 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 223 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 | 224 | |
f3a52e50 SW |
225 | /* Temporary status information (no need to save these values), |
226 | * used while processing CU commands. */ | |
227 | eepro100_tx_t tx; /* transmit buffer descriptor */ | |
228 | uint32_t cb_address; /* = cu_base + cu_offset */ | |
229 | ||
ba42b646 SW |
230 | /* Statistical counters. Also used for wake-up packet (i82559). */ |
231 | eepro100_stats_t statistics; | |
232 | ||
663e8e51 TS |
233 | #if 0 |
234 | uint16_t status; | |
235 | #endif | |
236 | ||
237 | /* Configuration bytes. */ | |
238 | uint8_t configuration[22]; | |
239 | ||
240 | /* Data in mem is always in the byte order of the controller (le). */ | |
241 | uint8_t mem[PCI_MEM_SIZE]; | |
151b2986 JQ |
242 | /* vmstate for each particular nic */ |
243 | VMStateDescription *vmstate; | |
ba42b646 SW |
244 | |
245 | /* Quasi static device properties (no need to save them). */ | |
246 | uint16_t stats_size; | |
247 | bool has_extended_tcb_support; | |
663e8e51 TS |
248 | } EEPRO100State; |
249 | ||
6cded3a4 SW |
250 | /* Word indices in EEPROM. */ |
251 | typedef enum { | |
252 | EEPROM_CNFG_MDIX = 0x03, | |
253 | EEPROM_ID = 0x05, | |
254 | EEPROM_PHY_ID = 0x06, | |
255 | EEPROM_VENDOR_ID = 0x0c, | |
256 | EEPROM_CONFIG_ASF = 0x0d, | |
257 | EEPROM_DEVICE_ID = 0x23, | |
258 | EEPROM_SMBUS_ADDR = 0x90, | |
259 | } EEPROMOffset; | |
260 | ||
663e8e51 TS |
261 | /* Default values for MDI (PHY) registers */ |
262 | static const uint16_t eepro100_mdi_default[] = { | |
263 | /* MDI Registers 0 - 6, 7 */ | |
264 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
265 | /* MDI Registers 8 - 15 */ | |
266 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
267 | /* MDI Registers 16 - 31 */ | |
268 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
269 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
270 | }; | |
271 | ||
272 | /* Readonly mask for MDI (PHY) registers */ | |
273 | static const uint16_t eepro100_mdi_mask[] = { | |
274 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
275 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
276 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
277 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
278 | }; | |
279 | ||
ba42b646 SW |
280 | /* XXX: optimize */ |
281 | static void stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
282 | { | |
283 | val = cpu_to_le32(val); | |
284 | cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); | |
285 | } | |
286 | ||
663e8e51 TS |
287 | #define POLYNOMIAL 0x04c11db6 |
288 | ||
289 | /* From FreeBSD */ | |
290 | /* XXX: optimize */ | |
7b8737de | 291 | static unsigned compute_mcast_idx(const uint8_t * ep) |
663e8e51 TS |
292 | { |
293 | uint32_t crc; | |
294 | int carry, i, j; | |
295 | uint8_t b; | |
296 | ||
297 | crc = 0xffffffff; | |
298 | for (i = 0; i < 6; i++) { | |
299 | b = *ep++; | |
300 | for (j = 0; j < 8; j++) { | |
301 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
302 | crc <<= 1; | |
303 | b >>= 1; | |
aac443e6 | 304 | if (carry) { |
663e8e51 | 305 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 306 | } |
663e8e51 TS |
307 | } |
308 | } | |
7b8737de | 309 | return (crc & BITS(7, 2)) >> 2; |
663e8e51 TS |
310 | } |
311 | ||
312 | #if defined(DEBUG_EEPRO100) | |
313 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
314 | { | |
315 | static char dump[3 * 16 + 1]; | |
316 | char *p = &dump[0]; | |
aac443e6 | 317 | if (size > 16) { |
663e8e51 | 318 | size = 16; |
aac443e6 | 319 | } |
663e8e51 TS |
320 | while (size-- > 0) { |
321 | p += sprintf(p, " %02x", *buf++); | |
322 | } | |
323 | return dump; | |
324 | } | |
325 | #endif /* DEBUG_EEPRO100 */ | |
326 | ||
327 | enum scb_stat_ack { | |
328 | stat_ack_not_ours = 0x00, | |
329 | stat_ack_sw_gen = 0x04, | |
330 | stat_ack_rnr = 0x10, | |
331 | stat_ack_cu_idle = 0x20, | |
332 | stat_ack_frame_rx = 0x40, | |
333 | stat_ack_cu_cmd_done = 0x80, | |
334 | stat_ack_not_present = 0xFF, | |
335 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
336 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
337 | }; | |
338 | ||
339 | static void disable_interrupt(EEPRO100State * s) | |
340 | { | |
341 | if (s->int_stat) { | |
aac443e6 | 342 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 343 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
344 | s->int_stat = 0; |
345 | } | |
346 | } | |
347 | ||
348 | static void enable_interrupt(EEPRO100State * s) | |
349 | { | |
350 | if (!s->int_stat) { | |
aac443e6 | 351 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 352 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
353 | s->int_stat = 1; |
354 | } | |
355 | } | |
356 | ||
357 | static void eepro100_acknowledge(EEPRO100State * s) | |
358 | { | |
359 | s->scb_stat &= ~s->mem[SCBAck]; | |
360 | s->mem[SCBAck] = s->scb_stat; | |
361 | if (s->scb_stat == 0) { | |
362 | disable_interrupt(s); | |
363 | } | |
364 | } | |
365 | ||
366 | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) | |
367 | { | |
368 | uint8_t mask = ~s->mem[SCBIntmask]; | |
369 | s->mem[SCBAck] |= stat; | |
370 | stat = s->scb_stat = s->mem[SCBAck]; | |
371 | stat &= (mask | 0x0f); | |
372 | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf); | |
373 | if (stat && (mask & 0x01)) { | |
374 | /* SCB mask and SCB Bit M do not disable interrupt. */ | |
375 | enable_interrupt(s); | |
376 | } else if (s->int_stat) { | |
377 | disable_interrupt(s); | |
378 | } | |
379 | } | |
380 | ||
381 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
382 | { | |
383 | /* CU completed action command. */ | |
384 | /* Transmit not ok (82557 only, not in emulation). */ | |
385 | eepro100_interrupt(s, 0x80); | |
386 | } | |
387 | ||
388 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
389 | { | |
390 | /* CU left the active state. */ | |
391 | eepro100_interrupt(s, 0x20); | |
392 | } | |
393 | ||
394 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
395 | { | |
396 | /* RU received a complete frame. */ | |
397 | eepro100_interrupt(s, 0x40); | |
398 | } | |
399 | ||
400 | #if 0 | |
401 | static void eepro100_rnr_interrupt(EEPRO100State * s) | |
402 | { | |
403 | /* RU is not ready. */ | |
404 | eepro100_interrupt(s, 0x10); | |
405 | } | |
406 | #endif | |
407 | ||
408 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
409 | { | |
410 | /* MDI completed read or write cycle. */ | |
411 | eepro100_interrupt(s, 0x08); | |
412 | } | |
413 | ||
414 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
415 | { | |
416 | /* Software has requested an interrupt. */ | |
417 | eepro100_interrupt(s, 0x04); | |
418 | } | |
419 | ||
420 | #if 0 | |
421 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
422 | { | |
423 | /* Flow control pause interrupt (82558 and later). */ | |
424 | eepro100_interrupt(s, 0x01); | |
425 | } | |
426 | #endif | |
427 | ||
428 | static void pci_reset(EEPRO100State * s) | |
429 | { | |
430 | uint32_t device = s->device; | |
273a2142 | 431 | uint8_t *pci_conf = s->dev.config; |
ba42b646 | 432 | bool power_management = 1; |
663e8e51 | 433 | |
aac443e6 | 434 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
435 | |
436 | /* PCI Vendor ID */ | |
deb54399 | 437 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
d6fd1e66 | 438 | /* PCI Device ID depends on device and is set below. */ |
663e8e51 | 439 | /* PCI Command */ |
508cc6b4 | 440 | /* TODO: this is the default, do not override. */ |
663e8e51 TS |
441 | PCI_CONFIG_16(PCI_COMMAND, 0x0000); |
442 | /* PCI Status */ | |
508cc6b4 | 443 | /* TODO: Value at RST# should be 0. */ |
61702408 | 444 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); |
663e8e51 TS |
445 | /* PCI Revision ID */ |
446 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); | |
508cc6b4 | 447 | /* TODO: this is the default, do not override. */ |
663e8e51 | 448 | /* PCI Class Code */ |
508cc6b4 | 449 | PCI_CONFIG_8(PCI_CLASS_PROG, 0x00); |
173a543b | 450 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 TS |
451 | /* PCI Cache Line Size */ |
452 | /* check cache line size!!! */ | |
453 | //~ PCI_CONFIG_8(0x0c, 0x00); | |
454 | /* PCI Latency Timer */ | |
508cc6b4 | 455 | PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks |
663e8e51 TS |
456 | /* PCI Header Type */ |
457 | /* BIST (built-in self test) */ | |
458 | #if defined(TARGET_I386) | |
459 | // !!! workaround for buggy bios | |
0392a017 | 460 | //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0 |
663e8e51 TS |
461 | #endif |
462 | #if 0 | |
463 | /* PCI Base Address Registers */ | |
464 | /* CSR Memory Mapped Base Address */ | |
465 | PCI_CONFIG_32(PCI_BASE_ADDRESS_0, | |
0392a017 IY |
466 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
467 | PCI_BASE_ADDRESS_MEM_PREFETCH); | |
663e8e51 | 468 | /* CSR I/O Mapped Base Address */ |
0392a017 | 469 | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO); |
663e8e51 TS |
470 | #if 0 |
471 | /* Flash Memory Mapped Base Address */ | |
0392a017 IY |
472 | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, |
473 | 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY); | |
663e8e51 TS |
474 | #endif |
475 | #endif | |
476 | /* Expansion ROM Base Address (depends on boot disable!!!) */ | |
508cc6b4 MT |
477 | /* TODO: not needed, set when BAR is registered */ |
478 | PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
663e8e51 | 479 | /* Capability Pointer */ |
508cc6b4 MT |
480 | /* TODO: revisions with power_management 1 use this but |
481 | * do not set new capability list bit in status register. */ | |
482 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc); | |
aac443e6 | 483 | /* Interrupt Line */ |
663e8e51 | 484 | /* Interrupt Pin */ |
508cc6b4 MT |
485 | /* TODO: RST# value should be 0 */ |
486 | PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0 | |
663e8e51 | 487 | /* Minimum Grant */ |
508cc6b4 | 488 | PCI_CONFIG_8(PCI_MIN_GNT, 0x08); |
663e8e51 | 489 | /* Maximum Latency */ |
508cc6b4 | 490 | PCI_CONFIG_8(PCI_MAX_LAT, 0x18); |
663e8e51 TS |
491 | |
492 | switch (device) { | |
ba42b646 SW |
493 | case i82550: |
494 | // TODO: check device id. | |
495 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
496 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ | |
497 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
498 | // TODO: check size of statistical counters. | |
499 | s->stats_size = 80; | |
500 | // TODO: check extended tcb support. | |
501 | s->has_extended_tcb_support = 1; | |
502 | break; | |
663e8e51 | 503 | case i82551: |
d6fd1e66 | 504 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
ba42b646 | 505 | /* Revision ID: 0x0f, 0x10. */ |
663e8e51 | 506 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
ba42b646 SW |
507 | // TODO: check size of statistical counters. |
508 | s->stats_size = 80; | |
509 | s->has_extended_tcb_support = 1; | |
510 | break; | |
511 | case i82557A: | |
512 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
513 | PCI_CONFIG_8(PCI_REVISION_ID, 0x01); | |
508cc6b4 | 514 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 | 515 | power_management = 0; |
663e8e51 TS |
516 | break; |
517 | case i82557B: | |
d6fd1e66 | 518 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 519 | PCI_CONFIG_8(PCI_REVISION_ID, 0x02); |
508cc6b4 | 520 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 | 521 | power_management = 0; |
663e8e51 TS |
522 | break; |
523 | case i82557C: | |
d6fd1e66 | 524 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
663e8e51 | 525 | PCI_CONFIG_8(PCI_REVISION_ID, 0x03); |
508cc6b4 | 526 | PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00); |
ba42b646 SW |
527 | power_management = 0; |
528 | break; | |
529 | case i82558A: | |
530 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
531 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
532 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
533 | PCI_CONFIG_8(PCI_REVISION_ID, 0x04); |
534 | s->stats_size = 76; | |
535 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
536 | break; |
537 | case i82558B: | |
d6fd1e66 | 538 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
508cc6b4 MT |
539 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
540 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
663e8e51 | 541 | PCI_CONFIG_8(PCI_REVISION_ID, 0x05); |
ba42b646 SW |
542 | s->stats_size = 76; |
543 | s->has_extended_tcb_support = 1; | |
544 | break; | |
545 | case i82559A: | |
546 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
547 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
548 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
549 | PCI_CONFIG_8(PCI_REVISION_ID, 0x06); |
550 | s->stats_size = 80; | |
551 | s->has_extended_tcb_support = 1; | |
552 | break; | |
553 | case i82559B: | |
554 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); | |
508cc6b4 MT |
555 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
556 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
557 | PCI_CONFIG_8(PCI_REVISION_ID, 0x07); |
558 | s->stats_size = 80; | |
559 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
560 | break; |
561 | case i82559C: | |
d6fd1e66 | 562 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
508cc6b4 MT |
563 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
564 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
ba42b646 SW |
565 | PCI_CONFIG_8(PCI_REVISION_ID, 0x08); |
566 | // TODO: Windows wants revision id 0x0c. | |
567 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0c); | |
568 | #if EEPROM_SIZE > 0 | |
569 | PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086); | |
570 | PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040); | |
571 | #endif | |
572 | s->stats_size = 80; | |
573 | s->has_extended_tcb_support = 1; | |
663e8e51 TS |
574 | break; |
575 | case i82559ER: | |
d6fd1e66 | 576 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
508cc6b4 MT |
577 | PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
578 | PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); | |
663e8e51 | 579 | PCI_CONFIG_8(PCI_REVISION_ID, 0x09); |
ba42b646 SW |
580 | s->stats_size = 80; |
581 | s->has_extended_tcb_support = 1; | |
582 | break; | |
583 | case i82562: | |
584 | // TODO: check device id. | |
585 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); | |
586 | /* TODO: wrong revision id. */ | |
587 | PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); | |
588 | s->stats_size = 80; | |
589 | s->has_extended_tcb_support = 1; | |
663e8e51 | 590 | break; |
663e8e51 TS |
591 | default: |
592 | logout("Device %X is undefined!\n", device); | |
593 | } | |
594 | ||
ba42b646 SW |
595 | s->configuration[6] |= BIT(5); |
596 | ||
597 | if (s->stats_size == 80) { | |
598 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
599 | if (s->configuration[6] & BIT(2)) { | |
600 | /* TCO statistical counters. */ | |
601 | assert(s->configuration[6] & BIT(5)); | |
602 | } else { | |
603 | if (s->configuration[6] & BIT(5)) { | |
604 | /* No extended statistical counters, i82557 compatible. */ | |
605 | s->stats_size = 64; | |
606 | } else { | |
607 | /* i82558 compatible. */ | |
608 | s->stats_size = 76; | |
609 | } | |
610 | } | |
611 | } else { | |
612 | if (s->configuration[6] & BIT(5)) { | |
613 | /* No extended statistical counters. */ | |
614 | s->stats_size = 64; | |
615 | } | |
616 | } | |
617 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
618 | ||
619 | if (power_management) { | |
620 | /* Power Management Capabilities */ | |
621 | PCI_CONFIG_8(0xdc, 0x01); | |
622 | /* Next Item Pointer */ | |
623 | /* Capability ID */ | |
624 | PCI_CONFIG_16(0xde, 0x7e21); | |
625 | /* TODO: Power Management Control / Status. */ | |
626 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
627 | } | |
628 | ||
629 | #if EEPROM_SIZE > 0 | |
663e8e51 | 630 | if (device == i82557C || device == i82558B || device == i82559C) { |
ba42b646 SW |
631 | // TODO: get vendor id from EEPROM for i82557C or later. |
632 | // TODO: get device id from EEPROM for i82557C or later. | |
633 | // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
634 | // TODO: header type is determined by EEPROM for i82559. | |
635 | // TODO: get subsystem id from EEPROM for i82557C or later. | |
636 | // TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
637 | // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
638 | // TODO: capability pointer depends on EEPROM for i82558. | |
663e8e51 TS |
639 | logout("Get device id and revision from EEPROM!!!\n"); |
640 | } | |
ba42b646 | 641 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
642 | } |
643 | ||
644 | static void nic_selective_reset(EEPRO100State * s) | |
645 | { | |
646 | size_t i; | |
647 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
648 | //~ eeprom93xx_reset(s->eeprom); | |
508ef936 | 649 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
6cded3a4 | 650 | eeprom_contents[EEPROM_ID] = 0x4000; |
f4e94dfe URCB |
651 | if (s->device == i82557B || s->device == i82557C) |
652 | eeprom_contents[5] = 0x0100; | |
6cded3a4 | 653 | eeprom_contents[EEPROM_PHY_ID] = 1; |
663e8e51 TS |
654 | uint16_t sum = 0; |
655 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
656 | sum += eeprom_contents[i]; | |
657 | } | |
658 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 659 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
660 | |
661 | memset(s->mem, 0, sizeof(s->mem)); | |
662 | uint32_t val = BIT(21); | |
663 | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val)); | |
664 | ||
665 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
666 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
667 | } | |
668 | ||
669 | static void nic_reset(void *opaque) | |
670 | { | |
769cf7a5 | 671 | EEPRO100State *s = opaque; |
aac443e6 | 672 | TRACE(OTHER, logout("%p\n", s)); |
7b8737de SW |
673 | /* TODO: Clearing of multicast table for selective reset, too? */ |
674 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
663e8e51 TS |
675 | nic_selective_reset(s); |
676 | } | |
677 | ||
678 | #if defined(DEBUG_EEPRO100) | |
b8f6ba0d | 679 | static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
680 | "Command/Status", |
681 | "General Pointer", | |
682 | "Port", | |
683 | "EEPROM/Flash Control", | |
684 | "MDI Control", | |
685 | "Receive DMA Byte Count", | |
b8f6ba0d | 686 | "Flow Control", |
663e8e51 TS |
687 | "General Status/Control" |
688 | }; | |
689 | ||
690 | static char *regname(uint32_t addr) | |
691 | { | |
ec169288 | 692 | static char buf[32]; |
663e8e51 | 693 | if (addr < PCI_IO_SIZE) { |
b8f6ba0d | 694 | const char *r = e100_reg[addr / 4]; |
663e8e51 | 695 | if (r != 0) { |
41cbc23c | 696 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 697 | } else { |
41cbc23c | 698 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
699 | } |
700 | } else { | |
41cbc23c | 701 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
702 | } |
703 | return buf; | |
704 | } | |
705 | #endif /* DEBUG_EEPRO100 */ | |
706 | ||
707 | #if 0 | |
708 | static uint16_t eepro100_read_status(EEPRO100State * s) | |
709 | { | |
710 | uint16_t val = s->status; | |
aac443e6 | 711 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
712 | return val; |
713 | } | |
714 | ||
715 | static void eepro100_write_status(EEPRO100State * s, uint16_t val) | |
716 | { | |
aac443e6 | 717 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
718 | s->status = val; |
719 | } | |
720 | #endif | |
721 | ||
722 | /***************************************************************************** | |
723 | * | |
724 | * Command emulation. | |
725 | * | |
726 | ****************************************************************************/ | |
727 | ||
728 | #if 0 | |
729 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
730 | { | |
731 | uint16_t val = 0xffff; | |
aac443e6 | 732 | //~ TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
733 | return val; |
734 | } | |
735 | #endif | |
736 | ||
737 | /* Commands that can be put in a command list entry. */ | |
738 | enum commands { | |
739 | CmdNOp = 0, | |
740 | CmdIASetup = 1, | |
741 | CmdConfigure = 2, | |
742 | CmdMulticastList = 3, | |
743 | CmdTx = 4, | |
744 | CmdTDR = 5, /* load microcode */ | |
745 | CmdDump = 6, | |
746 | CmdDiagnose = 7, | |
747 | ||
748 | /* And some extra flags: */ | |
749 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
750 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
751 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
752 | }; | |
753 | ||
c227f099 | 754 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 TS |
755 | { |
756 | return ((s->mem[SCBStatus] >> 6) & 0x03); | |
757 | } | |
758 | ||
c227f099 | 759 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 TS |
760 | { |
761 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); | |
762 | } | |
763 | ||
c227f099 | 764 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 TS |
765 | { |
766 | return ((s->mem[SCBStatus] >> 2) & 0x0f); | |
767 | } | |
768 | ||
c227f099 | 769 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 TS |
770 | { |
771 | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); | |
772 | } | |
773 | ||
774 | static void dump_statistics(EEPRO100State * s) | |
775 | { | |
776 | /* Dump statistical data. Most data is never changed by the emulation | |
777 | * and always 0, so we first just copy the whole block and then those | |
778 | * values which really matter. | |
779 | * Number of data should check configuration!!! | |
780 | */ | |
ba42b646 SW |
781 | cpu_physical_memory_write(s->statsaddr, |
782 | (uint8_t *) & s->statistics, s->stats_size); | |
783 | stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); | |
784 | stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
785 | stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
786 | stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
787 | //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); | |
788 | //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
663e8e51 TS |
789 | //~ missing("CU dump statistical counters"); |
790 | } | |
791 | ||
f3a52e50 SW |
792 | static void tx_command(EEPRO100State *s) |
793 | { | |
7b8737de | 794 | uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
f3a52e50 SW |
795 | uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff); |
796 | /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */ | |
797 | uint8_t buf[2600]; | |
798 | uint16_t size = 0; | |
799 | uint32_t tbd_address = s->cb_address + 0x10; | |
800 | TRACE(RXTX, logout | |
801 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", | |
802 | tbd_array, tcb_bytes, s->tx.tbd_count)); | |
803 | ||
804 | if (tcb_bytes > 2600) { | |
805 | logout("TCB byte count too large, using 2600\n"); | |
806 | tcb_bytes = 2600; | |
807 | } | |
808 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
809 | logout | |
810 | ("illegal values of TBD array address and TCB byte count!\n"); | |
811 | } | |
812 | assert(tcb_bytes <= sizeof(buf)); | |
813 | while (size < tcb_bytes) { | |
814 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
815 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
816 | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
817 | tbd_address += 8; | |
818 | TRACE(RXTX, logout | |
819 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", | |
820 | tx_buffer_address, tx_buffer_size)); | |
821 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
822 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
823 | tx_buffer_size); | |
824 | size += tx_buffer_size; | |
825 | } | |
826 | if (tbd_array == 0xffffffff) { | |
827 | /* Simplified mode. Was already handled by code above. */ | |
828 | } else { | |
829 | /* Flexible mode. */ | |
830 | uint8_t tbd_count = 0; | |
831 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { | |
832 | /* Extended Flexible TCB. */ | |
833 | for (; tbd_count < 2; tbd_count++) { | |
834 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
835 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
836 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
837 | tbd_address += 8; | |
838 | TRACE(RXTX, logout | |
839 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
840 | tx_buffer_address, tx_buffer_size)); | |
841 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
842 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
843 | tx_buffer_size); | |
844 | size += tx_buffer_size; | |
845 | if (tx_buffer_el & 1) { | |
846 | break; | |
847 | } | |
848 | } | |
849 | } | |
850 | tbd_address = tbd_array; | |
851 | for (; tbd_count < s->tx.tbd_count; tbd_count++) { | |
852 | uint32_t tx_buffer_address = ldl_phys(tbd_address); | |
853 | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); | |
854 | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); | |
855 | tbd_address += 8; | |
856 | TRACE(RXTX, logout | |
857 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
858 | tx_buffer_address, tx_buffer_size)); | |
859 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
860 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
861 | tx_buffer_size); | |
862 | size += tx_buffer_size; | |
863 | if (tx_buffer_el & 1) { | |
864 | break; | |
865 | } | |
866 | } | |
867 | } | |
868 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); | |
869 | qemu_send_packet(&s->nic->nc, buf, size); | |
870 | s->statistics.tx_good_frames++; | |
871 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
872 | * (82557 only). Emulation never has bad status. */ | |
873 | //~ eepro100_cx_interrupt(s); | |
874 | } | |
875 | ||
7b8737de SW |
876 | static void set_multicast_list(EEPRO100State *s) |
877 | { | |
878 | uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); | |
879 | uint16_t i; | |
880 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
881 | TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); | |
882 | for (i = 0; i < multicast_count; i += 6) { | |
883 | uint8_t multicast_addr[6]; | |
884 | cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); | |
885 | TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); | |
886 | unsigned mcast_idx = compute_mcast_idx(multicast_addr); | |
887 | assert(mcast_idx < 64); | |
888 | s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); | |
889 | } | |
890 | } | |
891 | ||
5fa9a0ae | 892 | static void action_command(EEPRO100State *s) |
663e8e51 | 893 | { |
5fa9a0ae | 894 | for (;;) { |
f3a52e50 SW |
895 | s->cb_address = s->cu_base + s->cu_offset; |
896 | cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx)); | |
897 | uint16_t status = le16_to_cpu(s->tx.status); | |
898 | uint16_t command = le16_to_cpu(s->tx.command); | |
ce0e58b3 SW |
899 | logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", |
900 | status, command, s->tx.link); | |
663e8e51 TS |
901 | bool bit_el = ((command & 0x8000) != 0); |
902 | bool bit_s = ((command & 0x4000) != 0); | |
903 | bool bit_i = ((command & 0x2000) != 0); | |
904 | bool bit_nc = ((command & 0x0010) != 0); | |
7f1e9d4e | 905 | bool success = true; |
663e8e51 TS |
906 | //~ bool bit_sf = ((command & 0x0008) != 0); |
907 | uint16_t cmd = command & 0x0007; | |
f3a52e50 | 908 | s->cu_offset = le32_to_cpu(s->tx.link); |
663e8e51 TS |
909 | switch (cmd) { |
910 | case CmdNOp: | |
911 | /* Do nothing. */ | |
912 | break; | |
913 | case CmdIASetup: | |
f3a52e50 | 914 | cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
ce0e58b3 | 915 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
663e8e51 TS |
916 | break; |
917 | case CmdConfigure: | |
f3a52e50 | 918 | cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], |
663e8e51 | 919 | sizeof(s->configuration)); |
aac443e6 | 920 | TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
663e8e51 TS |
921 | break; |
922 | case CmdMulticastList: | |
7b8737de | 923 | set_multicast_list(s); |
663e8e51 TS |
924 | break; |
925 | case CmdTx: | |
7f1e9d4e KW |
926 | if (bit_nc) { |
927 | missing("CmdTx: NC = 0"); | |
928 | success = false; | |
929 | break; | |
930 | } | |
f3a52e50 | 931 | tx_command(s); |
663e8e51 TS |
932 | break; |
933 | case CmdTDR: | |
aac443e6 | 934 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
935 | /* Starting with offset 8, the command contains |
936 | * 64 dwords microcode which we just ignore here. */ | |
937 | break; | |
938 | default: | |
939 | missing("undefined command"); | |
7f1e9d4e KW |
940 | success = false; |
941 | break; | |
663e8e51 | 942 | } |
7f1e9d4e | 943 | /* Write new status. */ |
f3a52e50 | 944 | stw_phys(s->cb_address, status | 0x8000 | (success ? 0x2000 : 0)); |
663e8e51 TS |
945 | if (bit_i) { |
946 | /* CU completed action. */ | |
947 | eepro100_cx_interrupt(s); | |
948 | } | |
949 | if (bit_el) { | |
aac443e6 | 950 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
951 | set_cu_state(s, cu_idle); |
952 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 953 | break; |
663e8e51 | 954 | } else if (bit_s) { |
5fa9a0ae | 955 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
956 | set_cu_state(s, cu_suspended); |
957 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 958 | break; |
663e8e51 TS |
959 | } else { |
960 | /* More entries in list. */ | |
aac443e6 | 961 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 962 | } |
5fa9a0ae SW |
963 | } |
964 | TRACE(OTHER, logout("CU list empty\n")); | |
965 | /* List is empty. Now CU is idle or suspended. */ | |
966 | } | |
967 | ||
968 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
969 | { | |
970 | switch (val) { | |
971 | case CU_NOP: | |
972 | /* No operation. */ | |
973 | break; | |
974 | case CU_START: | |
975 | if (get_cu_state(s) != cu_idle) { | |
976 | /* Intel documentation says that CU must be idle for the CU | |
977 | * start command. Intel driver for Linux also starts the CU | |
978 | * from suspended state. */ | |
979 | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle); | |
980 | //~ assert(!"wrong CU state"); | |
981 | } | |
982 | set_cu_state(s, cu_active); | |
983 | s->cu_offset = s->pointer; | |
984 | action_command(s); | |
663e8e51 TS |
985 | break; |
986 | case CU_RESUME: | |
987 | if (get_cu_state(s) != cu_suspended) { | |
988 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
989 | /* Workaround for bad Linux eepro100 driver which resumes | |
990 | * from idle state. */ | |
991 | //~ missing("cu resume"); | |
992 | set_cu_state(s, cu_suspended); | |
993 | } | |
994 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 995 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 996 | set_cu_state(s, cu_active); |
5fa9a0ae | 997 | action_command(s); |
663e8e51 TS |
998 | } |
999 | break; | |
1000 | case CU_STATSADDR: | |
1001 | /* Load dump counters address. */ | |
1002 | s->statsaddr = s->pointer; | |
aac443e6 | 1003 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
1004 | break; |
1005 | case CU_SHOWSTATS: | |
1006 | /* Dump statistical counters. */ | |
aac443e6 | 1007 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 1008 | dump_statistics(s); |
ba42b646 | 1009 | stl_le_phys(s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
1010 | break; |
1011 | case CU_CMD_BASE: | |
1012 | /* Load CU base. */ | |
aac443e6 | 1013 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
663e8e51 TS |
1014 | s->cu_base = s->pointer; |
1015 | break; | |
1016 | case CU_DUMPSTATS: | |
1017 | /* Dump and reset statistical counters. */ | |
aac443e6 | 1018 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 1019 | dump_statistics(s); |
ba42b646 | 1020 | stl_le_phys(s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
1021 | memset(&s->statistics, 0, sizeof(s->statistics)); |
1022 | break; | |
1023 | case CU_SRESUME: | |
1024 | /* CU static resume. */ | |
1025 | missing("CU static resume"); | |
1026 | break; | |
1027 | default: | |
1028 | missing("Undefined CU command"); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
1033 | { | |
1034 | switch (val) { | |
1035 | case RU_NOP: | |
1036 | /* No operation. */ | |
1037 | break; | |
1038 | case RX_START: | |
1039 | /* RU start. */ | |
1040 | if (get_ru_state(s) != ru_idle) { | |
1041 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
1042 | //~ assert(!"wrong RU state"); | |
1043 | } | |
1044 | set_ru_state(s, ru_ready); | |
1045 | s->ru_offset = s->pointer; | |
aac443e6 | 1046 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
1047 | break; |
1048 | case RX_RESUME: | |
1049 | /* Restart RU. */ | |
1050 | if (get_ru_state(s) != ru_suspended) { | |
1051 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
1052 | ru_suspended); | |
1053 | //~ assert(!"wrong RU state"); | |
1054 | } | |
1055 | set_ru_state(s, ru_ready); | |
1056 | break; | |
1057 | case RX_ADDR_LOAD: | |
1058 | /* Load RU base. */ | |
aac443e6 | 1059 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
663e8e51 TS |
1060 | s->ru_base = s->pointer; |
1061 | break; | |
1062 | default: | |
1063 | logout("val=0x%02x (undefined RU command)\n", val); | |
1064 | missing("Undefined SU command"); | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1069 | { | |
1070 | eepro100_ru_command(s, val & 0x0f); | |
1071 | eepro100_cu_command(s, val & 0xf0); | |
1072 | if ((val) == 0) { | |
aac443e6 | 1073 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1074 | } |
1075 | /* Clear command byte after command was accepted. */ | |
1076 | s->mem[SCBCmd] = 0; | |
1077 | } | |
1078 | ||
1079 | /***************************************************************************** | |
1080 | * | |
1081 | * EEPROM emulation. | |
1082 | * | |
1083 | ****************************************************************************/ | |
1084 | ||
1085 | #define EEPROM_CS 0x02 | |
1086 | #define EEPROM_SK 0x01 | |
1087 | #define EEPROM_DI 0x04 | |
1088 | #define EEPROM_DO 0x08 | |
1089 | ||
1090 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1091 | { | |
1092 | uint16_t val; | |
1093 | memcpy(&val, &s->mem[SCBeeprom], sizeof(val)); | |
1094 | if (eeprom93xx_read(s->eeprom)) { | |
1095 | val |= EEPROM_DO; | |
1096 | } else { | |
1097 | val &= ~EEPROM_DO; | |
1098 | } | |
aac443e6 | 1099 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1100 | return val; |
1101 | } | |
1102 | ||
c227f099 | 1103 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1104 | { |
aac443e6 | 1105 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1106 | |
1107 | /* mask unwriteable bits */ | |
1108 | //~ val = SET_MASKED(val, 0x31, eeprom->value); | |
1109 | ||
1110 | int eecs = ((val & EEPROM_CS) != 0); | |
1111 | int eesk = ((val & EEPROM_SK) != 0); | |
1112 | int eedi = ((val & EEPROM_DI) != 0); | |
1113 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1114 | } | |
1115 | ||
1116 | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) | |
1117 | { | |
1118 | s->pointer = le32_to_cpu(val); | |
aac443e6 | 1119 | TRACE(OTHER, logout("val=0x%08x\n", val)); |
663e8e51 TS |
1120 | } |
1121 | ||
1122 | /***************************************************************************** | |
1123 | * | |
1124 | * MDI emulation. | |
1125 | * | |
1126 | ****************************************************************************/ | |
1127 | ||
1128 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1129 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1130 | "opcode 0", |
1131 | "write", | |
1132 | "read", | |
1133 | "opcode 3" | |
1134 | }; | |
1135 | ||
6a0b9cc9 | 1136 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1137 | "Control", |
1138 | "Status", | |
1139 | "PHY Identification (Word 1)", | |
1140 | "PHY Identification (Word 2)", | |
1141 | "Auto-Negotiation Advertisement", | |
1142 | "Auto-Negotiation Link Partner Ability", | |
1143 | "Auto-Negotiation Expansion" | |
1144 | }; | |
aac443e6 SW |
1145 | |
1146 | static const char *reg2name(uint8_t reg) | |
1147 | { | |
1148 | static char buffer[10]; | |
1149 | const char *p = buffer; | |
1150 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1151 | p = mdi_reg_name[reg]; | |
1152 | } else { | |
1153 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1154 | } | |
1155 | return p; | |
1156 | } | |
663e8e51 TS |
1157 | #endif /* DEBUG_EEPRO100 */ |
1158 | ||
1159 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1160 | { | |
1161 | uint32_t val; | |
1162 | memcpy(&val, &s->mem[0x10], sizeof(val)); | |
1163 | ||
1164 | #ifdef DEBUG_EEPRO100 | |
1165 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1166 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1167 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1168 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1169 | uint16_t data = (val & BITS(15, 0)); | |
1170 | #endif | |
1171 | /* Emulation takes no time to finish MDI transaction. */ | |
1172 | val |= BIT(28); | |
1173 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1174 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1175 | reg2name(reg), data)); |
663e8e51 TS |
1176 | return val; |
1177 | } | |
1178 | ||
663e8e51 TS |
1179 | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1180 | { | |
1181 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1182 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1183 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1184 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1185 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1186 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1187 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1188 | if (phy != 1) { |
1189 | /* Unsupported PHY address. */ | |
1190 | //~ logout("phy must be 1 but is %u\n", phy); | |
1191 | data = 0; | |
1192 | } else if (opcode != 1 && opcode != 2) { | |
1193 | /* Unsupported opcode. */ | |
1194 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1195 | data = 0; | |
1196 | } else if (reg > 6) { | |
1197 | /* Unsupported register. */ | |
1198 | logout("register must be 0...6 but is %u\n", reg); | |
1199 | data = 0; | |
1200 | } else { | |
1201 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1202 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1203 | reg2name(reg), data)); |
663e8e51 TS |
1204 | if (opcode == 1) { |
1205 | /* MDI write */ | |
1206 | switch (reg) { | |
1207 | case 0: /* Control Register */ | |
1208 | if (data & 0x8000) { | |
1209 | /* Reset status and control registers to default. */ | |
1210 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1211 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1212 | data = s->mdimem[reg]; | |
1213 | } else { | |
1214 | /* Restart Auto Configuration = Normal Operation */ | |
1215 | data &= ~0x0200; | |
1216 | } | |
1217 | break; | |
1218 | case 1: /* Status Register */ | |
1219 | missing("not writable"); | |
1220 | data = s->mdimem[reg]; | |
1221 | break; | |
1222 | case 2: /* PHY Identification Register (Word 1) */ | |
1223 | case 3: /* PHY Identification Register (Word 2) */ | |
1224 | missing("not implemented"); | |
1225 | break; | |
1226 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1227 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1228 | break; | |
1229 | case 6: /* Auto-Negotiation Expansion Register */ | |
1230 | default: | |
1231 | missing("not implemented"); | |
1232 | } | |
1233 | s->mdimem[reg] = data; | |
1234 | } else if (opcode == 2) { | |
1235 | /* MDI read */ | |
1236 | switch (reg) { | |
1237 | case 0: /* Control Register */ | |
1238 | if (data & 0x8000) { | |
1239 | /* Reset status and control registers to default. */ | |
1240 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1241 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1242 | } | |
1243 | break; | |
1244 | case 1: /* Status Register */ | |
1245 | s->mdimem[reg] |= 0x0020; | |
1246 | break; | |
1247 | case 2: /* PHY Identification Register (Word 1) */ | |
1248 | case 3: /* PHY Identification Register (Word 2) */ | |
1249 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1250 | break; | |
1251 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1252 | s->mdimem[reg] = 0x41fe; | |
1253 | break; | |
1254 | case 6: /* Auto-Negotiation Expansion Register */ | |
1255 | s->mdimem[reg] = 0x0001; | |
1256 | break; | |
1257 | } | |
1258 | data = s->mdimem[reg]; | |
1259 | } | |
1260 | /* Emulation takes no time to finish MDI transaction. | |
1261 | * Set MDI bit in SCB status register. */ | |
1262 | s->mem[SCBAck] |= 0x08; | |
1263 | val |= BIT(28); | |
1264 | if (raiseint) { | |
1265 | eepro100_mdi_interrupt(s); | |
1266 | } | |
1267 | } | |
1268 | val = (val & 0xffff0000) + data; | |
1269 | memcpy(&s->mem[0x10], &val, sizeof(val)); | |
1270 | } | |
1271 | ||
1272 | /***************************************************************************** | |
1273 | * | |
1274 | * Port emulation. | |
1275 | * | |
1276 | ****************************************************************************/ | |
1277 | ||
1278 | #define PORT_SOFTWARE_RESET 0 | |
1279 | #define PORT_SELFTEST 1 | |
1280 | #define PORT_SELECTIVE_RESET 2 | |
1281 | #define PORT_DUMP 3 | |
1282 | #define PORT_SELECTION_MASK 3 | |
1283 | ||
1284 | typedef struct { | |
1285 | uint32_t st_sign; /* Self Test Signature */ | |
1286 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1287 | } eepro100_selftest_t; |
663e8e51 TS |
1288 | |
1289 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1290 | { | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static void eepro100_write_port(EEPRO100State * s, uint32_t val) | |
1295 | { | |
1296 | val = le32_to_cpu(val); | |
1297 | uint32_t address = (val & ~PORT_SELECTION_MASK); | |
1298 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1299 | switch (selection) { | |
1300 | case PORT_SOFTWARE_RESET: | |
1301 | nic_reset(s); | |
1302 | break; | |
1303 | case PORT_SELFTEST: | |
aac443e6 | 1304 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1305 | eepro100_selftest_t data; |
663e8e51 TS |
1306 | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
1307 | data.st_sign = 0xffffffff; | |
1308 | data.st_result = 0; | |
1309 | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data)); | |
1310 | break; | |
1311 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1312 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1313 | nic_selective_reset(s); |
1314 | break; | |
1315 | default: | |
1316 | logout("val=0x%08x\n", val); | |
1317 | missing("unknown port selection"); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /***************************************************************************** | |
1322 | * | |
1323 | * General hardware emulation. | |
1324 | * | |
1325 | ****************************************************************************/ | |
1326 | ||
1327 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1328 | { | |
1329 | uint8_t val; | |
1330 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1331 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1332 | } | |
1333 | ||
1334 | switch (addr) { | |
1335 | case SCBStatus: | |
1336 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1337 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1338 | break; |
1339 | case SCBAck: | |
1340 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1341 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1342 | break; |
1343 | case SCBCmd: | |
aac443e6 | 1344 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1345 | //~ val = eepro100_read_command(s); |
1346 | break; | |
1347 | case SCBIntmask: | |
aac443e6 | 1348 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1349 | break; |
1350 | case SCBPort + 3: | |
aac443e6 | 1351 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1352 | break; |
1353 | case SCBeeprom: | |
1354 | val = eepro100_read_eeprom(s); | |
1355 | break; | |
0908bba1 | 1356 | case SCBpmdr: /* Power Management Driver Register */ |
663e8e51 | 1357 | val = 0; |
aac443e6 | 1358 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 | 1359 | break; |
0908bba1 | 1360 | case SCBgstat: /* General Status Register */ |
663e8e51 TS |
1361 | /* 100 Mbps full duplex, valid link */ |
1362 | val = 0x07; | |
aac443e6 | 1363 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1364 | break; |
1365 | default: | |
1366 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1367 | missing("unknown byte read"); | |
1368 | } | |
1369 | return val; | |
1370 | } | |
1371 | ||
1372 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1373 | { | |
1374 | uint16_t val; | |
1375 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1376 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1377 | } | |
1378 | ||
663e8e51 TS |
1379 | switch (addr) { |
1380 | case SCBStatus: | |
1381 | //~ val = eepro100_read_status(s); | |
dbbaaff6 | 1382 | case SCBCmd: |
aac443e6 | 1383 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1384 | break; |
1385 | case SCBeeprom: | |
1386 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1387 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1388 | break; |
1389 | default: | |
1390 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1391 | missing("unknown word read"); | |
1392 | } | |
1393 | return val; | |
1394 | } | |
1395 | ||
1396 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1397 | { | |
1398 | uint32_t val; | |
1399 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1400 | memcpy(&val, &s->mem[addr], sizeof(val)); | |
1401 | } | |
1402 | ||
1403 | switch (addr) { | |
1404 | case SCBStatus: | |
1405 | //~ val = eepro100_read_status(s); | |
aac443e6 | 1406 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1407 | break; |
1408 | case SCBPointer: | |
1409 | //~ val = eepro100_read_pointer(s); | |
aac443e6 | 1410 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1411 | break; |
1412 | case SCBPort: | |
1413 | val = eepro100_read_port(s); | |
aac443e6 | 1414 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1415 | break; |
1416 | case SCBCtrlMDI: | |
1417 | val = eepro100_read_mdi(s); | |
1418 | break; | |
1419 | default: | |
1420 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1421 | missing("unknown longword read"); | |
1422 | } | |
1423 | return val; | |
1424 | } | |
1425 | ||
1426 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1427 | { | |
1428 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1429 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1430 | } | |
1431 | ||
aac443e6 | 1432 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1433 | |
1434 | switch (addr) { | |
1435 | case SCBStatus: | |
1436 | //~ eepro100_write_status(s, val); | |
1437 | break; | |
1438 | case SCBAck: | |
1439 | eepro100_acknowledge(s); | |
1440 | break; | |
1441 | case SCBCmd: | |
1442 | eepro100_write_command(s, val); | |
1443 | break; | |
1444 | case SCBIntmask: | |
1445 | if (val & BIT(1)) { | |
1446 | eepro100_swi_interrupt(s); | |
1447 | } | |
1448 | eepro100_interrupt(s, 0); | |
1449 | break; | |
1450 | case SCBPort + 3: | |
aac443e6 | 1451 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1452 | case SCBFlow + 1: |
1453 | case SCBFlow + 2: | |
0908bba1 | 1454 | case SCBpmdr: /* does not exist on 82557 */ |
aac443e6 | 1455 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1456 | break; |
1457 | case SCBeeprom: | |
1458 | eepro100_write_eeprom(s->eeprom, val); | |
1459 | break; | |
1460 | default: | |
1461 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1462 | missing("unknown byte write"); | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1467 | { | |
1468 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1469 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1470 | } | |
1471 | ||
aac443e6 | 1472 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1473 | |
1474 | switch (addr) { | |
1475 | case SCBStatus: | |
1476 | //~ eepro100_write_status(s, val); | |
1477 | eepro100_acknowledge(s); | |
1478 | break; | |
1479 | case SCBCmd: | |
1480 | eepro100_write_command(s, val); | |
1481 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1482 | break; | |
1483 | case SCBeeprom: | |
1484 | eepro100_write_eeprom(s->eeprom, val); | |
1485 | break; | |
1486 | default: | |
1487 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1488 | missing("unknown word write"); | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1493 | { | |
1494 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
1495 | memcpy(&s->mem[addr], &val, sizeof(val)); | |
1496 | } | |
1497 | ||
1498 | switch (addr) { | |
1499 | case SCBPointer: | |
1500 | eepro100_write_pointer(s, val); | |
1501 | break; | |
1502 | case SCBPort: | |
aac443e6 | 1503 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1504 | eepro100_write_port(s, val); |
1505 | break; | |
1506 | case SCBCtrlMDI: | |
1507 | eepro100_write_mdi(s, val); | |
1508 | break; | |
1509 | default: | |
1510 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1511 | missing("unknown longword write"); | |
1512 | } | |
1513 | } | |
1514 | ||
aac443e6 SW |
1515 | /***************************************************************************** |
1516 | * | |
1517 | * Port mapped I/O. | |
1518 | * | |
1519 | ****************************************************************************/ | |
1520 | ||
663e8e51 TS |
1521 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1522 | { | |
1523 | EEPRO100State *s = opaque; | |
1524 | //~ logout("addr=%s\n", regname(addr)); | |
1525 | return eepro100_read1(s, addr - s->region[1]); | |
1526 | } | |
1527 | ||
1528 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1529 | { | |
1530 | EEPRO100State *s = opaque; | |
1531 | return eepro100_read2(s, addr - s->region[1]); | |
1532 | } | |
1533 | ||
1534 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1535 | { | |
1536 | EEPRO100State *s = opaque; | |
1537 | return eepro100_read4(s, addr - s->region[1]); | |
1538 | } | |
1539 | ||
1540 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1541 | { | |
1542 | EEPRO100State *s = opaque; | |
1543 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1544 | eepro100_write1(s, addr - s->region[1], val); | |
1545 | } | |
1546 | ||
1547 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1548 | { | |
1549 | EEPRO100State *s = opaque; | |
1550 | eepro100_write2(s, addr - s->region[1], val); | |
1551 | } | |
1552 | ||
1553 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1554 | { | |
1555 | EEPRO100State *s = opaque; | |
1556 | eepro100_write4(s, addr - s->region[1], val); | |
1557 | } | |
1558 | ||
1559 | /***********************************************************/ | |
1560 | /* PCI EEPRO100 definitions */ | |
1561 | ||
663e8e51 | 1562 | static void pci_map(PCIDevice * pci_dev, int region_num, |
6e355d90 | 1563 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1564 | { |
273a2142 | 1565 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1566 | |
89e8b13c IY |
1567 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1568 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1569 | region_num, addr, size, type)); |
663e8e51 TS |
1570 | |
1571 | assert(region_num == 1); | |
1572 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1573 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1574 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1575 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1576 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1577 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1578 | ||
1579 | s->region[region_num] = addr; | |
1580 | } | |
1581 | ||
aac443e6 SW |
1582 | /***************************************************************************** |
1583 | * | |
1584 | * Memory mapped I/O. | |
1585 | * | |
1586 | ****************************************************************************/ | |
1587 | ||
c227f099 | 1588 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1589 | { |
1590 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1591 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1592 | eepro100_write1(s, addr, val); | |
1593 | } | |
1594 | ||
c227f099 | 1595 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1596 | { |
1597 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1598 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1599 | eepro100_write2(s, addr, val); | |
1600 | } | |
1601 | ||
c227f099 | 1602 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1603 | { |
1604 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1605 | //~ logout("addr=%s val=0x%02x\n", regname(addr), val); |
1606 | eepro100_write4(s, addr, val); | |
1607 | } | |
1608 | ||
c227f099 | 1609 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1610 | { |
1611 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1612 | //~ logout("addr=%s\n", regname(addr)); |
1613 | return eepro100_read1(s, addr); | |
1614 | } | |
1615 | ||
c227f099 | 1616 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1617 | { |
1618 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1619 | //~ logout("addr=%s\n", regname(addr)); |
1620 | return eepro100_read2(s, addr); | |
1621 | } | |
1622 | ||
c227f099 | 1623 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1624 | { |
1625 | EEPRO100State *s = opaque; | |
663e8e51 TS |
1626 | //~ logout("addr=%s\n", regname(addr)); |
1627 | return eepro100_read4(s, addr); | |
1628 | } | |
1629 | ||
d60efc6b | 1630 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1631 | pci_mmio_writeb, |
1632 | pci_mmio_writew, | |
1633 | pci_mmio_writel | |
1634 | }; | |
1635 | ||
d60efc6b | 1636 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1637 | pci_mmio_readb, |
1638 | pci_mmio_readw, | |
1639 | pci_mmio_readl | |
1640 | }; | |
1641 | ||
1642 | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, | |
6e355d90 | 1643 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1644 | { |
273a2142 | 1645 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1646 | |
89e8b13c IY |
1647 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1648 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1649 | region_num, addr, size, type)); |
663e8e51 TS |
1650 | |
1651 | if (region_num == 0) { | |
1652 | /* Map control / status registers. */ | |
273a2142 JQ |
1653 | cpu_register_physical_memory(addr, size, s->mmio_index); |
1654 | s->region[region_num] = addr; | |
663e8e51 TS |
1655 | } |
1656 | } | |
1657 | ||
e00e365e | 1658 | static int nic_can_receive(VLANClientState *nc) |
663e8e51 | 1659 | { |
e00e365e | 1660 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
aac443e6 | 1661 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 TS |
1662 | return get_ru_state(s) == ru_ready; |
1663 | //~ return !eepro100_buffer_full(s); | |
1664 | } | |
1665 | ||
e00e365e | 1666 | static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1667 | { |
1668 | /* TODO: | |
1669 | * - Magic packets should set bit 30 in power management driver register. | |
1670 | * - Interesting packets should set bit 29 in power management driver register. | |
1671 | */ | |
e00e365e | 1672 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
663e8e51 TS |
1673 | uint16_t rfd_status = 0xa000; |
1674 | static const uint8_t broadcast_macaddr[6] = | |
1675 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1676 | ||
1677 | /* TODO: check multiple IA bit. */ | |
7f1e9d4e KW |
1678 | if (s->configuration[20] & BIT(6)) { |
1679 | missing("Multiple IA bit"); | |
1680 | return -1; | |
1681 | } | |
663e8e51 TS |
1682 | |
1683 | if (s->configuration[8] & 0x80) { | |
1684 | /* CSMA is disabled. */ | |
1685 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1686 | return -1; |
663e8e51 TS |
1687 | } else if (size < 64 && (s->configuration[7] & 1)) { |
1688 | /* Short frame and configuration byte 7/0 (discard short receive) set: | |
1689 | * Short frame is discarded */ | |
067d01de | 1690 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1691 | s->statistics.rx_short_frame_errors++; |
4f1c942b | 1692 | //~ return -1; |
663e8e51 TS |
1693 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1694 | /* Long frame and configuration byte 18/3 (long receive ok) not set: | |
1695 | * Long frames are discarded. */ | |
067d01de | 1696 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1697 | return -1; |
508ef936 | 1698 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!! |
663e8e51 TS |
1699 | /* Frame matches individual address. */ |
1700 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1701 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1702 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1703 | /* Broadcast frame. */ | |
067d01de | 1704 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 | 1705 | rfd_status |= 0x0002; |
7b8737de | 1706 | } else if (buf[0] & 0x01) { |
663e8e51 | 1707 | /* Multicast frame. */ |
7b8737de | 1708 | TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size))); |
7f1e9d4e | 1709 | if (s->configuration[21] & BIT(3)) { |
7b8737de SW |
1710 | /* Multicast all bit is set, receive all multicast frames. */ |
1711 | } else { | |
1712 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1713 | assert(mcast_idx < 64); | |
1714 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1715 | /* Multicast frame is allowed in hash table. */ | |
1716 | } else if (s->configuration[15] & 1) { | |
1717 | /* Promiscuous: receive all. */ | |
1718 | rfd_status |= 0x0004; | |
1719 | } else { | |
1720 | TRACE(RXTX, logout("%p multicast ignored\n", s)); | |
1721 | return -1; | |
1722 | } | |
663e8e51 | 1723 | } |
7b8737de | 1724 | /* TODO: Next not for promiscuous mode? */ |
663e8e51 TS |
1725 | rfd_status |= 0x0002; |
1726 | } else if (s->configuration[15] & 1) { | |
1727 | /* Promiscuous: receive all. */ | |
067d01de | 1728 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 TS |
1729 | rfd_status |= 0x0004; |
1730 | } else { | |
067d01de | 1731 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1732 | nic_dump(buf, size))); |
4f1c942b | 1733 | return size; |
663e8e51 TS |
1734 | } |
1735 | ||
1736 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1737 | /* No resources available. */ |
1738 | logout("no resources, state=%u\n", get_ru_state(s)); | |
663e8e51 | 1739 | s->statistics.rx_resource_errors++; |
aac443e6 | 1740 | //~ assert(!"no resources"); |
4f1c942b | 1741 | return -1; |
663e8e51 TS |
1742 | } |
1743 | //~ !!! | |
1744 | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} | |
c227f099 | 1745 | eepro100_rx_t rx; |
663e8e51 | 1746 | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
c227f099 | 1747 | offsetof(eepro100_rx_t, packet)); |
663e8e51 TS |
1748 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1749 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1750 | |
1751 | if (size > rfd_size) { | |
1752 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1753 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1754 | size = rfd_size; | |
1755 | } | |
663e8e51 TS |
1756 | if (size < 64) { |
1757 | rfd_status |= 0x0080; | |
1758 | } | |
aac443e6 SW |
1759 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1760 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
c227f099 | 1761 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
663e8e51 | 1762 | rfd_status); |
c227f099 | 1763 | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
663e8e51 TS |
1764 | /* Early receive interrupt not supported. */ |
1765 | //~ eepro100_er_interrupt(s); | |
1766 | /* Receive CRC Transfer not supported. */ | |
7f1e9d4e KW |
1767 | if (s->configuration[18] & 4) { |
1768 | missing("Receive CRC Transfer"); | |
1769 | return -1; | |
1770 | } | |
663e8e51 TS |
1771 | /* TODO: check stripping enable bit. */ |
1772 | //~ assert(!(s->configuration[17] & 1)); | |
1773 | cpu_physical_memory_write(s->ru_base + s->ru_offset + | |
c227f099 | 1774 | offsetof(eepro100_rx_t, packet), buf, size); |
663e8e51 TS |
1775 | s->statistics.rx_good_frames++; |
1776 | eepro100_fr_interrupt(s); | |
1777 | s->ru_offset = le32_to_cpu(rx.link); | |
1778 | if (rfd_command & 0x8000) { | |
1779 | /* EL bit is set, so this was the last frame. */ | |
7f1e9d4e KW |
1780 | logout("receive: Running out of frames\n"); |
1781 | set_ru_state(s, ru_suspended); | |
663e8e51 TS |
1782 | } |
1783 | if (rfd_command & 0x4000) { | |
1784 | /* S bit is set. */ | |
1785 | set_ru_state(s, ru_suspended); | |
1786 | } | |
4f1c942b | 1787 | return size; |
663e8e51 TS |
1788 | } |
1789 | ||
151b2986 JQ |
1790 | static const VMStateDescription vmstate_eepro100 = { |
1791 | .version_id = 3, | |
1792 | .minimum_version_id = 2, | |
1793 | .minimum_version_id_old = 2, | |
1794 | .fields = (VMStateField []) { | |
1795 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1796 | VMSTATE_UNUSED(32), | |
1797 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1798 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1799 | /* Save all members of struct between scb_stat and mem. */ | |
1800 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1801 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1802 | VMSTATE_UNUSED(3*4), | |
1803 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1804 | VMSTATE_UNUSED(19*4), | |
1805 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1806 | /* The eeprom should be saved and restored by its own routines. */ | |
1807 | VMSTATE_UINT32(device, EEPRO100State), | |
1808 | /* TODO check device. */ | |
1809 | VMSTATE_UINT32(pointer, EEPRO100State), | |
1810 | VMSTATE_UINT32(cu_base, EEPRO100State), | |
1811 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1812 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1813 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1814 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1815 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1816 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1817 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1818 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1819 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1820 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1821 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1822 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1823 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1824 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1825 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1826 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1827 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1828 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1829 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1830 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1831 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1832 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1833 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1834 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1835 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1836 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
2657c663 | 1837 | #if 0 |
151b2986 | 1838 | VMSTATE_UINT16(status, EEPRO100State), |
2657c663 | 1839 | #endif |
151b2986 JQ |
1840 | /* Configuration bytes. */ |
1841 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1842 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1843 | } |
151b2986 | 1844 | }; |
663e8e51 | 1845 | |
e00e365e | 1846 | static void nic_cleanup(VLANClientState *nc) |
b946a153 | 1847 | { |
e00e365e | 1848 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b946a153 | 1849 | |
e00e365e | 1850 | s->nic = NULL; |
b946a153 AL |
1851 | } |
1852 | ||
c4c270e2 | 1853 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1854 | { |
c4c270e2 | 1855 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1856 | |
1857 | cpu_unregister_io_memory(s->mmio_index); | |
151b2986 | 1858 | vmstate_unregister(s->vmstate, s); |
508ef936 | 1859 | eeprom93xx_free(s->eeprom); |
e00e365e | 1860 | qemu_del_vlan_client(&s->nic->nc); |
b946a153 AL |
1861 | return 0; |
1862 | } | |
1863 | ||
e00e365e MM |
1864 | static NetClientInfo net_eepro100_info = { |
1865 | .type = NET_CLIENT_TYPE_NIC, | |
1866 | .size = sizeof(NICState), | |
1867 | .can_receive = nic_can_receive, | |
1868 | .receive = nic_receive, | |
1869 | .cleanup = nic_cleanup, | |
1870 | }; | |
1871 | ||
81a322d4 | 1872 | static int nic_init(PCIDevice *pci_dev, uint32_t device) |
663e8e51 | 1873 | { |
273a2142 | 1874 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1875 | |
aac443e6 | 1876 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1877 | |
663e8e51 | 1878 | s->device = device; |
663e8e51 TS |
1879 | |
1880 | pci_reset(s); | |
1881 | ||
1882 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1883 | * i82559 and later support 64 or 256 word EEPROM. */ | |
1884 | s->eeprom = eeprom93xx_new(EEPROM_SIZE); | |
1885 | ||
1886 | /* Handler for memory-mapped I/O */ | |
273a2142 | 1887 | s->mmio_index = |
1eed09cb | 1888 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
663e8e51 | 1889 | |
273a2142 | 1890 | pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, |
0392a017 IY |
1891 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
1892 | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map); | |
1893 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO, | |
663e8e51 | 1894 | pci_map); |
0392a017 | 1895 | pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, |
663e8e51 TS |
1896 | pci_mmio_map); |
1897 | ||
508ef936 | 1898 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
ce0e58b3 | 1899 | logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
663e8e51 TS |
1900 | assert(s->region[1] == 0); |
1901 | ||
1902 | nic_reset(s); | |
1903 | ||
e00e365e MM |
1904 | s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1905 | pci_dev->qdev.info->name, pci_dev->qdev.id, s); | |
663e8e51 | 1906 | |
e00e365e MM |
1907 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1908 | TRACE(OTHER, logout("%s\n", s->nic->nc.info_str)); | |
663e8e51 | 1909 | |
a08d4367 | 1910 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1911 | |
151b2986 JQ |
1912 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
1913 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
e00e365e | 1914 | s->vmstate->name = s->nic->nc.model; |
151b2986 | 1915 | vmstate_register(-1, s->vmstate, s); |
4e9df06a | 1916 | |
81a322d4 | 1917 | return 0; |
663e8e51 TS |
1918 | } |
1919 | ||
c4c270e2 SW |
1920 | static int pci_i82550_init(PCIDevice *pci_dev) |
1921 | { | |
1922 | return nic_init(pci_dev, i82550); | |
1923 | } | |
1924 | ||
1925 | static int pci_i82551_init(PCIDevice *pci_dev) | |
1926 | { | |
1927 | return nic_init(pci_dev, i82551); | |
1928 | } | |
1929 | ||
1930 | static int pci_i82557a_init(PCIDevice *pci_dev) | |
1931 | { | |
1932 | return nic_init(pci_dev, i82557A); | |
1933 | } | |
1934 | ||
1935 | static int pci_i82557b_init(PCIDevice *pci_dev) | |
1936 | { | |
1937 | return nic_init(pci_dev, i82557B); | |
1938 | } | |
1939 | ||
1940 | static int pci_i82557c_init(PCIDevice *pci_dev) | |
1941 | { | |
1942 | return nic_init(pci_dev, i82557C); | |
1943 | } | |
1944 | ||
1945 | static int pci_i82558a_init(PCIDevice *pci_dev) | |
1946 | { | |
1947 | return nic_init(pci_dev, i82558A); | |
1948 | } | |
1949 | ||
1950 | static int pci_i82558b_init(PCIDevice *pci_dev) | |
1951 | { | |
1952 | return nic_init(pci_dev, i82558B); | |
1953 | } | |
1954 | ||
1955 | static int pci_i82559a_init(PCIDevice *pci_dev) | |
1956 | { | |
1957 | return nic_init(pci_dev, i82559A); | |
1958 | } | |
1959 | ||
1960 | static int pci_i82559b_init(PCIDevice *pci_dev) | |
1961 | { | |
1962 | return nic_init(pci_dev, i82559B); | |
1963 | } | |
1964 | ||
1965 | static int pci_i82559c_init(PCIDevice *pci_dev) | |
9d07d757 | 1966 | { |
c4c270e2 | 1967 | return nic_init(pci_dev, i82559C); |
9d07d757 PB |
1968 | } |
1969 | ||
c4c270e2 | 1970 | static int pci_i82559er_init(PCIDevice *pci_dev) |
663e8e51 | 1971 | { |
c4c270e2 | 1972 | return nic_init(pci_dev, i82559ER); |
663e8e51 TS |
1973 | } |
1974 | ||
c4c270e2 | 1975 | static int pci_i82562_init(PCIDevice *pci_dev) |
663e8e51 | 1976 | { |
c4c270e2 | 1977 | return nic_init(pci_dev, i82562); |
663e8e51 TS |
1978 | } |
1979 | ||
0aab0d3a GH |
1980 | static PCIDeviceInfo eepro100_info[] = { |
1981 | { | |
c4c270e2 SW |
1982 | .qdev.name = "i82550", |
1983 | .qdev.size = sizeof(EEPRO100State), | |
1984 | .init = pci_i82550_init, | |
6a90e308 | 1985 | .exit = pci_nic_uninit, |
da51e79b | 1986 | .romfile = "gpxe-eepro100-80861209.rom", |
508ef936 GH |
1987 | .qdev.props = (Property[]) { |
1988 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1989 | DEFINE_PROP_END_OF_LIST(), | |
1990 | }, | |
c4c270e2 | 1991 | },{ |
0aab0d3a | 1992 | .qdev.name = "i82551", |
273a2142 | 1993 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 1994 | .init = pci_i82551_init, |
e3936fa5 | 1995 | .exit = pci_nic_uninit, |
da51e79b | 1996 | .romfile = "gpxe-eepro100-80861209.rom", |
508ef936 GH |
1997 | .qdev.props = (Property[]) { |
1998 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
1999 | DEFINE_PROP_END_OF_LIST(), | |
2000 | }, | |
c4c270e2 SW |
2001 | },{ |
2002 | .qdev.name = "i82557a", | |
2003 | .qdev.size = sizeof(EEPRO100State), | |
2004 | .init = pci_i82557a_init, | |
6a90e308 | 2005 | .exit = pci_nic_uninit, |
da51e79b | 2006 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2007 | .qdev.props = (Property[]) { |
2008 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2009 | DEFINE_PROP_END_OF_LIST(), | |
2010 | }, | |
0aab0d3a GH |
2011 | },{ |
2012 | .qdev.name = "i82557b", | |
273a2142 | 2013 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 2014 | .init = pci_i82557b_init, |
e3936fa5 | 2015 | .exit = pci_nic_uninit, |
da51e79b | 2016 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2017 | .qdev.props = (Property[]) { |
2018 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2019 | DEFINE_PROP_END_OF_LIST(), | |
2020 | }, | |
c4c270e2 SW |
2021 | },{ |
2022 | .qdev.name = "i82557c", | |
2023 | .qdev.size = sizeof(EEPRO100State), | |
2024 | .init = pci_i82557c_init, | |
6a90e308 | 2025 | .exit = pci_nic_uninit, |
da51e79b | 2026 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2027 | .qdev.props = (Property[]) { |
2028 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2029 | DEFINE_PROP_END_OF_LIST(), | |
2030 | }, | |
c4c270e2 SW |
2031 | },{ |
2032 | .qdev.name = "i82558a", | |
2033 | .qdev.size = sizeof(EEPRO100State), | |
2034 | .init = pci_i82558a_init, | |
6a90e308 | 2035 | .exit = pci_nic_uninit, |
da51e79b | 2036 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2037 | .qdev.props = (Property[]) { |
2038 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2039 | DEFINE_PROP_END_OF_LIST(), | |
2040 | }, | |
c4c270e2 SW |
2041 | },{ |
2042 | .qdev.name = "i82558b", | |
2043 | .qdev.size = sizeof(EEPRO100State), | |
2044 | .init = pci_i82558b_init, | |
6a90e308 | 2045 | .exit = pci_nic_uninit, |
da51e79b | 2046 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2047 | .qdev.props = (Property[]) { |
2048 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2049 | DEFINE_PROP_END_OF_LIST(), | |
2050 | }, | |
c4c270e2 SW |
2051 | },{ |
2052 | .qdev.name = "i82559a", | |
2053 | .qdev.size = sizeof(EEPRO100State), | |
2054 | .init = pci_i82559a_init, | |
6a90e308 | 2055 | .exit = pci_nic_uninit, |
da51e79b | 2056 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2057 | .qdev.props = (Property[]) { |
2058 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2059 | DEFINE_PROP_END_OF_LIST(), | |
2060 | }, | |
c4c270e2 SW |
2061 | },{ |
2062 | .qdev.name = "i82559b", | |
2063 | .qdev.size = sizeof(EEPRO100State), | |
2064 | .init = pci_i82559b_init, | |
6a90e308 | 2065 | .exit = pci_nic_uninit, |
da51e79b | 2066 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2067 | .qdev.props = (Property[]) { |
2068 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2069 | DEFINE_PROP_END_OF_LIST(), | |
2070 | }, | |
c4c270e2 SW |
2071 | },{ |
2072 | .qdev.name = "i82559c", | |
2073 | .qdev.size = sizeof(EEPRO100State), | |
2074 | .init = pci_i82559c_init, | |
6a90e308 | 2075 | .exit = pci_nic_uninit, |
da51e79b | 2076 | .romfile = "gpxe-eepro100-80861229.rom", |
508ef936 GH |
2077 | .qdev.props = (Property[]) { |
2078 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2079 | DEFINE_PROP_END_OF_LIST(), | |
2080 | }, | |
0aab0d3a GH |
2081 | },{ |
2082 | .qdev.name = "i82559er", | |
273a2142 | 2083 | .qdev.size = sizeof(EEPRO100State), |
0aab0d3a | 2084 | .init = pci_i82559er_init, |
e3936fa5 | 2085 | .exit = pci_nic_uninit, |
da51e79b | 2086 | .romfile = "gpxe-eepro100-80861209.rom", |
508ef936 GH |
2087 | .qdev.props = (Property[]) { |
2088 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2089 | DEFINE_PROP_END_OF_LIST(), | |
2090 | }, | |
c4c270e2 SW |
2091 | },{ |
2092 | .qdev.name = "i82562", | |
2093 | .qdev.size = sizeof(EEPRO100State), | |
2094 | .init = pci_i82562_init, | |
6a90e308 | 2095 | .exit = pci_nic_uninit, |
da51e79b | 2096 | .romfile = "gpxe-eepro100-80861209.rom", |
508ef936 GH |
2097 | .qdev.props = (Property[]) { |
2098 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2099 | DEFINE_PROP_END_OF_LIST(), | |
2100 | }, | |
0aab0d3a GH |
2101 | },{ |
2102 | /* end of list */ | |
2103 | } | |
2104 | }; | |
2105 | ||
9d07d757 | 2106 | static void eepro100_register_devices(void) |
663e8e51 | 2107 | { |
0aab0d3a | 2108 | pci_qdev_register_many(eepro100_info); |
663e8e51 TS |
2109 | } |
2110 | ||
9d07d757 | 2111 | device_init(eepro100_register_devices) |