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sun4u: implement interrupt clearing registers
[qemu.git] / hw / es1370.c
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1d14ffa9
FB		 1/*
2 * QEMU ES1370 emulation
3 *
4 * Copyright (c) 2005 Vassili Karpov (malc)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25/* #define DEBUG_ES1370 */
26/* #define VERBOSE_ES1370 */
27#define SILENT_ES1370
28
87ecb68b
PB		 29#include "hw.h"
30#include "audiodev.h"
31#include "audio/audio.h"
32#include "pci.h"
3204db98 33#include "dma.h"
1d14ffa9
FB		 34
35/* Missing stuff:
36 SCTRL_P[12](END|ST)INC
37 SCTRL_P1SCTRLD
38 SCTRL_P2DACSEN
39 CTRL_DAC_SYNC
40 MIDI
41 non looped mode
42 surely more
43*/
44
45/*
46 Following macros and samplerate array were copied verbatim from
47 Linux kernel 2.4.30: drivers/sound/es1370.c
48
49 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
50*/
51
52/* Start blatant GPL violation */
53
54#define ES1370_REG_CONTROL 0x00
55#define ES1370_REG_STATUS 0x04
56#define ES1370_REG_UART_DATA 0x08
57#define ES1370_REG_UART_STATUS 0x09
58#define ES1370_REG_UART_CONTROL 0x09
59#define ES1370_REG_UART_TEST 0x0a
60#define ES1370_REG_MEMPAGE 0x0c
61#define ES1370_REG_CODEC 0x10
62#define ES1370_REG_SERIAL_CONTROL 0x20
63#define ES1370_REG_DAC1_SCOUNT 0x24
64#define ES1370_REG_DAC2_SCOUNT 0x28
65#define ES1370_REG_ADC_SCOUNT 0x2c
66
67#define ES1370_REG_DAC1_FRAMEADR 0xc30
68#define ES1370_REG_DAC1_FRAMECNT 0xc34
69#define ES1370_REG_DAC2_FRAMEADR 0xc38
70#define ES1370_REG_DAC2_FRAMECNT 0xc3c
71#define ES1370_REG_ADC_FRAMEADR 0xd30
72#define ES1370_REG_ADC_FRAMECNT 0xd34
73#define ES1370_REG_PHANTOM_FRAMEADR 0xd38
74#define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
75
76static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
77
78#define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
79#define DAC2_DIVTOSR(x) (1411200/((x)+2))
80
81#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
82#define CTRL_XCTL1 0x40000000 /* electret mic bias */
83#define CTRL_OPEN 0x20000000 /* no function, can be read and written */
84#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
85#define CTRL_SH_PCLKDIV 16
86#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
87#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
88#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
89#define CTRL_SH_WTSRSEL 12
90#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
91#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
92#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
93#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
94#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
95#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
96#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
97#define CTRL_ADC_EN 0x00000010 /* enable ADC */
98#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
99#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
100#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
101#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
102
103#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
104#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
105#define STAT_CBUSY 0x00000200 /* 1 = codec busy */
106#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
107#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
108#define STAT_SH_VC 5
109#define STAT_MCCB 0x00000010 /* CCB int pending */
110#define STAT_UART 0x00000008 /* UART int pending */
111#define STAT_DAC1 0x00000004 /* DAC1 int pending */
112#define STAT_DAC2 0x00000002 /* DAC2 int pending */
113#define STAT_ADC 0x00000001 /* ADC int pending */
114
115#define USTAT_RXINT 0x80 /* UART rx int pending */
116#define USTAT_TXINT 0x04 /* UART tx int pending */
117#define USTAT_TXRDY 0x02 /* UART tx ready */
118#define USTAT_RXRDY 0x01 /* UART rx ready */
119
120#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
121#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
122#define UCTRL_ENA_TXINT 0x20 /* enable TX int */
123#define UCTRL_CNTRL 0x03 /* control field */
124#define UCTRL_CNTRL_SWR 0x03 /* software reset command */
125
126#define SCTRL_P2ENDINC 0x00380000 /* */
127#define SCTRL_SH_P2ENDINC 19
128#define SCTRL_P2STINC 0x00070000 /* */
129#define SCTRL_SH_P2STINC 16
130#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
131#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
132#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
133#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
134#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
135#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
136#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
137#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
138#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
139#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
140#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
141#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
142#define SCTRL_R1FMT 0x00000030 /* format mask */
143#define SCTRL_SH_R1FMT 4
144#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
145#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
146#define SCTRL_P2FMT 0x0000000c /* format mask */
147#define SCTRL_SH_P2FMT 2
148#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
149#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
150#define SCTRL_P1FMT 0x00000003 /* format mask */
151#define SCTRL_SH_P1FMT 0
152
153/* End blatant GPL violation */
154
155#define NB_CHANNELS 3
156#define DAC1_CHANNEL 0
157#define DAC2_CHANNEL 1
158#define ADC_CHANNEL 2
159
160#define IO_READ_PROTO(n) \
161static uint32_t n (void *opaque, uint32_t addr)
162#define IO_WRITE_PROTO(n) \
163static void n (void *opaque, uint32_t addr, uint32_t val)
164
165static void es1370_dac1_callback (void *opaque, int free);
166static void es1370_dac2_callback (void *opaque, int free);
167static void es1370_adc_callback (void *opaque, int avail);
168
169#ifdef DEBUG_ES1370
170
171#define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
172
173static void print_ctl (uint32_t val)
174{
175 char buf[1024];
176
177 buf[0] = '\0';
178#define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
179 a (ADC_STOP);
180 a (XCTL1);
181 a (OPEN);
182 a (MSFMTSEL);
183 a (M_SBB);
184 a (DAC_SYNC);
185 a (CCB_INTRM);
186 a (M_CB);
187 a (XCTL0);
188 a (BREQ);
189 a (DAC1_EN);
190 a (DAC2_EN);
191 a (ADC_EN);
192 a (UART_EN);
193 a (JYSTK_EN);
194 a (CDC_EN);
195 a (SERR_DIS);
196#undef a
197 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
198 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
199 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
200 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
201 buf);
202}
203
204static void print_sctl (uint32_t val)
205{
206 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
207 char buf[1024];
208
209 buf[0] = '\0';
210
211#define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
212#define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
213 b (R1LOOPSEL);
214 b (P2LOOPSEL);
215 b (P1LOOPSEL);
216 a (P2PAUSE);
217 a (P1PAUSE);
218 a (R1INTEN);
219 a (P2INTEN);
220 a (P1INTEN);
221 a (P1SCTRLD);
222 a (P2DACSEN);
223 if (buf[0]) {
224 strcat (buf, "\n ");
225 }
226 else {
227 buf[0] = ' ';
228 buf[1] = '\0';
229 }
230#undef b
231#undef a
232 AUD_log ("es1370",
233 "%s"
234 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
235 buf,
236 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
237 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
238 fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
239 fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
240 fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
241 );
242}
243#else
244#define ldebug(...)
245#define print_ctl(...)
246#define print_sctl(...)
247#endif
248
249#ifdef VERBOSE_ES1370
250#define dolog(...) AUD_log ("es1370", __VA_ARGS__)
251#else
252#define dolog(...)
253#endif
254
255#ifndef SILENT_ES1370
946fc947 256#define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__)
1d14ffa9
FB		 257#else
258#define lwarn(...)
259#endif
260
261struct chan {
262 uint32_t shift;
263 uint32_t leftover;
264 uint32_t scount;
265 uint32_t frame_addr;
266 uint32_t frame_cnt;
267};
268
269typedef struct ES1370State {
e5944641 270 PCIDevice dev;
c0fe3827 271 QEMUSoundCard card;
e1a99dbd 272 MemoryRegion io;
1d14ffa9
FB		 273 struct chan chan[NB_CHANNELS];
274 SWVoiceOut *dac_voice[2];
275 SWVoiceIn *adc_voice;
276
277 uint32_t ctl;
278 uint32_t status;
279 uint32_t mempage;
280 uint32_t codec;
281 uint32_t sctl;
282} ES1370State;
283
1d14ffa9
FB		 284struct chan_bits {
285 uint32_t ctl_en;
286 uint32_t stat_int;
287 uint32_t sctl_pause;
288 uint32_t sctl_inten;
289 uint32_t sctl_fmt;
290 uint32_t sctl_sh_fmt;
291 uint32_t sctl_loopsel;
292 void (*calc_freq) (ES1370State *s, uint32_t ctl,
293 uint32_t *old_freq, uint32_t *new_freq);
294};
295
296static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
297 uint32_t *old_freq, uint32_t *new_freq);
298static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
299 uint32_t *old_freq,
300 uint32_t *new_freq);
301
302static const struct chan_bits es1370_chan_bits[] = {
303 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
304 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
305 es1370_dac1_calc_freq},
306
307 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
308 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
309 es1370_dac2_and_adc_calc_freq},
310
311 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
312 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
313 es1370_dac2_and_adc_calc_freq}
314};
315
316static void es1370_update_status (ES1370State *s, uint32_t new_status)
317{
318 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
319
320 if (level) {
321 s->status = new_status | STAT_INTR;
322 }
323 else {
324 s->status = new_status & ~STAT_INTR;
325 }
e5944641 326 qemu_set_irq (s->dev.irq[0], !!level);
1d14ffa9
FB		 327}
328
329static void es1370_reset (ES1370State *s)
330{
331 size_t i;
332
333 s->ctl = 1;
334 s->status = 0x60;
335 s->mempage = 0;
336 s->codec = 0;
337 s->sctl = 0;
338
339 for (i = 0; i < NB_CHANNELS; ++i) {
340 struct chan *d = &s->chan[i];
341 d->scount = 0;
342 d->leftover = 0;
343 if (i == ADC_CHANNEL) {
c0fe3827 344 AUD_close_in (&s->card, s->adc_voice);
1d14ffa9
FB		 345 s->adc_voice = NULL;
346 }
347 else {
c0fe3827 348 AUD_close_out (&s->card, s->dac_voice[i]);
1d14ffa9
FB		 349 s->dac_voice[i] = NULL;
350 }
351 }
e5944641 352 qemu_irq_lower (s->dev.irq[0]);
1d14ffa9
FB		 353}
354
355static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
356{
357 uint32_t new_status = s->status;
358
359 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
360 new_status &= ~STAT_DAC1;
361 }
362
363 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
364 new_status &= ~STAT_DAC2;
365 }
366
367 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
368 new_status &= ~STAT_ADC;
369 }
370
371 if (new_status != s->status) {
372 es1370_update_status (s, new_status);
373 }
374}
375
376static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
377 uint32_t *old_freq, uint32_t *new_freq)
378
379{
380 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
381 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
382}
383
384static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
385 uint32_t *old_freq,
386 uint32_t *new_freq)
387
388{
389 uint32_t old_pclkdiv, new_pclkdiv;
390
391 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
392 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
393 *new_freq = DAC2_DIVTOSR (new_pclkdiv);
394 *old_freq = DAC2_DIVTOSR (old_pclkdiv);
395}
396
397static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
398{
399 size_t i;
400 uint32_t old_freq, new_freq, old_fmt, new_fmt;
401
402 for (i = 0; i < NB_CHANNELS; ++i) {
403 struct chan *d = &s->chan[i];
404 const struct chan_bits *b = &es1370_chan_bits[i];
405
406 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
407 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
408
409 b->calc_freq (s, ctl, &old_freq, &new_freq);
410
411 if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
412 d->shift = (new_fmt & 1) + (new_fmt >> 1);
413 ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
414 i,
415 new_freq,
416 1 << (new_fmt & 1),
417 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
418 d->shift);
419 if (new_freq) {
1ea879e5 420 struct audsettings as;
c0fe3827
FB		 421
422 as.freq = new_freq;
423 as.nchannels = 1 << (new_fmt & 1);
424 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
d929eba5 425 as.endianness = 0;
c0fe3827 426
1d14ffa9
FB		 427 if (i == ADC_CHANNEL) {
428 s->adc_voice =
429 AUD_open_in (
c0fe3827 430 &s->card,
1d14ffa9
FB		 431 s->adc_voice,
432 "es1370.adc",
433 s,
434 es1370_adc_callback,
d929eba5 435 &as
1d14ffa9
FB		 436 );
437 }
438 else {
439 s->dac_voice[i] =
440 AUD_open_out (
c0fe3827 441 &s->card,
1d14ffa9
FB		 442 s->dac_voice[i],
443 i ? "es1370.dac2" : "es1370.dac1",
444 s,
445 i ? es1370_dac2_callback : es1370_dac1_callback,
d929eba5 446 &as
1d14ffa9
FB		 447 );
448 }
449 }
450 }
451
452 if (((ctl ^ s->ctl) & b->ctl_en)
453 || ((sctl ^ s->sctl) & b->sctl_pause)) {
454 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
455
456 if (i == ADC_CHANNEL) {
457 AUD_set_active_in (s->adc_voice, on);
458 }
459 else {
460 AUD_set_active_out (s->dac_voice[i], on);
461 }
462 }
463 }
464
465 s->ctl = ctl;
466 s->sctl = sctl;
467}
468
469static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
470{
471 addr &= 0xff;
472 if (addr >= 0x30 && addr <= 0x3f)
473 addr |= s->mempage << 8;
474 return addr;
475}
476
477IO_WRITE_PROTO (es1370_writeb)
478{
479 ES1370State *s = opaque;
1d14ffa9
FB		 480 uint32_t shift, mask;
481
8ead62cf
FB		 482 addr = es1370_fixup (s, addr);
483
1d14ffa9
FB		 484 switch (addr) {
485 case ES1370_REG_CONTROL:
486 case ES1370_REG_CONTROL + 1:
487 case ES1370_REG_CONTROL + 2:
488 case ES1370_REG_CONTROL + 3:
489 shift = (addr - ES1370_REG_CONTROL) << 3;
490 mask = 0xff << shift;
491 val = (s->ctl & ~mask) | ((val & 0xff) << shift);
492 es1370_update_voices (s, val, s->sctl);
493 print_ctl (val);
494 break;
495 case ES1370_REG_MEMPAGE:
496 s->mempage = val;
497 break;
498 case ES1370_REG_SERIAL_CONTROL:
499 case ES1370_REG_SERIAL_CONTROL + 1:
500 case ES1370_REG_SERIAL_CONTROL + 2:
501 case ES1370_REG_SERIAL_CONTROL + 3:
502 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
503 mask = 0xff << shift;
504 val = (s->sctl & ~mask) | ((val & 0xff) << shift);
505 es1370_maybe_lower_irq (s, val);
506 es1370_update_voices (s, s->ctl, val);
507 print_sctl (val);
508 break;
509 default:
510 lwarn ("writeb %#x <- %#x\n", addr, val);
511 break;
512 }
513}
514
515IO_WRITE_PROTO (es1370_writew)
516{
517 ES1370State *s = opaque;
518 addr = es1370_fixup (s, addr);
519 uint32_t shift, mask;
520 struct chan *d = &s->chan[0];
521
522 switch (addr) {
523 case ES1370_REG_CODEC:
524 dolog ("ignored codec write address %#x, data %#x\n",
525 (val >> 8) & 0xff, val & 0xff);
526 s->codec = val;
527 break;
528
529 case ES1370_REG_CONTROL:
530 case ES1370_REG_CONTROL + 2:
531 shift = (addr != ES1370_REG_CONTROL) << 4;
532 mask = 0xffff << shift;
533 val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
534 es1370_update_voices (s, val, s->sctl);
535 print_ctl (val);
536 break;
537
538 case ES1370_REG_ADC_SCOUNT:
539 d++;
540 case ES1370_REG_DAC2_SCOUNT:
541 d++;
542 case ES1370_REG_DAC1_SCOUNT:
543 d->scount = (d->scount & ~0xffff) | (val & 0xffff);
544 break;
545
546 default:
547 lwarn ("writew %#x <- %#x\n", addr, val);
548 break;
549 }
550}
551
552IO_WRITE_PROTO (es1370_writel)
553{
554 ES1370State *s = opaque;
555 struct chan *d = &s->chan[0];
556
557 addr = es1370_fixup (s, addr);
558
559 switch (addr) {
560 case ES1370_REG_CONTROL:
561 es1370_update_voices (s, val, s->sctl);
562 print_ctl (val);
563 break;
564
565 case ES1370_REG_MEMPAGE:
566 s->mempage = val & 0xf;
567 break;
568
569 case ES1370_REG_SERIAL_CONTROL:
570 es1370_maybe_lower_irq (s, val);
571 es1370_update_voices (s, s->ctl, val);
572 print_sctl (val);
573 break;
574
575 case ES1370_REG_ADC_SCOUNT:
576 d++;
577 case ES1370_REG_DAC2_SCOUNT:
578 d++;
579 case ES1370_REG_DAC1_SCOUNT:
580 d->scount = (val & 0xffff) | (d->scount & ~0xffff);
581 ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
582 d - &s->chan[0], val >> 16, (val & 0xffff));
583 break;
584
585 case ES1370_REG_ADC_FRAMEADR:
586 d++;
587 case ES1370_REG_DAC2_FRAMEADR:
588 d++;
589 case ES1370_REG_DAC1_FRAMEADR:
590 d->frame_addr = val;
591 ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
592 break;
593
946fc947
FB		 594 case ES1370_REG_PHANTOM_FRAMECNT:
595 lwarn ("writing to phantom frame count %#x\n", val);
596 break;
597 case ES1370_REG_PHANTOM_FRAMEADR:
598 lwarn ("writing to phantom frame address %#x\n", val);
599 break;
600
1d14ffa9
FB		 601 case ES1370_REG_ADC_FRAMECNT:
602 d++;
603 case ES1370_REG_DAC2_FRAMECNT:
604 d++;
605 case ES1370_REG_DAC1_FRAMECNT:
606 d->frame_cnt = val;
607 d->leftover = 0;
608 ldebug ("chan %d frame count %d, buffer size %d\n",
609 d - &s->chan[0], val >> 16, val & 0xffff);
610 break;
611
612 default:
613 lwarn ("writel %#x <- %#x\n", addr, val);
614 break;
615 }
616}
617
618IO_READ_PROTO (es1370_readb)
619{
620 ES1370State *s = opaque;
621 uint32_t val;
622
623 addr = es1370_fixup (s, addr);
624
625 switch (addr) {
626 case 0x1b: /* Legacy */
627 lwarn ("Attempt to read from legacy register\n");
628 val = 5;
629 break;
630 case ES1370_REG_MEMPAGE:
631 val = s->mempage;
632 break;
633 case ES1370_REG_CONTROL + 0:
634 case ES1370_REG_CONTROL + 1:
635 case ES1370_REG_CONTROL + 2:
636 case ES1370_REG_CONTROL + 3:
637 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
638 break;
639 case ES1370_REG_STATUS + 0:
640 case ES1370_REG_STATUS + 1:
641 case ES1370_REG_STATUS + 2:
642 case ES1370_REG_STATUS + 3:
643 val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
644 break;
645 default:
646 val = ~0;
647 lwarn ("readb %#x -> %#x\n", addr, val);
648 break;
649 }
650 return val;
651}
652
653IO_READ_PROTO (es1370_readw)
654{
655 ES1370State *s = opaque;
656 struct chan *d = &s->chan[0];
657 uint32_t val;
658
659 addr = es1370_fixup (s, addr);
660
661 switch (addr) {
662 case ES1370_REG_ADC_SCOUNT + 2:
663 d++;
664 case ES1370_REG_DAC2_SCOUNT + 2:
665 d++;
666 case ES1370_REG_DAC1_SCOUNT + 2:
667 val = d->scount >> 16;
668 break;
669
946fc947
FB		 670 case ES1370_REG_ADC_FRAMECNT:
671 d++;
672 case ES1370_REG_DAC2_FRAMECNT:
673 d++;
674 case ES1370_REG_DAC1_FRAMECNT:
675 val = d->frame_cnt & 0xffff;
676 break;
677
678 case ES1370_REG_ADC_FRAMECNT + 2:
679 d++;
680 case ES1370_REG_DAC2_FRAMECNT + 2:
681 d++;
682 case ES1370_REG_DAC1_FRAMECNT + 2:
683 val = d->frame_cnt >> 16;
684 break;
685
1d14ffa9
FB		 686 default:
687 val = ~0;
688 lwarn ("readw %#x -> %#x\n", addr, val);
689 break;
690 }
691
692 return val;
693}
694
695IO_READ_PROTO (es1370_readl)
696{
697 ES1370State *s = opaque;
698 uint32_t val;
699 struct chan *d = &s->chan[0];
700
701 addr = es1370_fixup (s, addr);
702
703 switch (addr) {
704 case ES1370_REG_CONTROL:
705 val = s->ctl;
706 break;
707 case ES1370_REG_STATUS:
708 val = s->status;
709 break;
710 case ES1370_REG_MEMPAGE:
711 val = s->mempage;
712 break;
713 case ES1370_REG_CODEC:
714 val = s->codec;
715 break;
716 case ES1370_REG_SERIAL_CONTROL:
717 val = s->sctl;
718 break;
719
720 case ES1370_REG_ADC_SCOUNT:
721 d++;
722 case ES1370_REG_DAC2_SCOUNT:
723 d++;
724 case ES1370_REG_DAC1_SCOUNT:
725 val = d->scount;
726#ifdef DEBUG_ES1370
727 {
728 uint32_t curr_count = d->scount >> 16;
729 uint32_t count = d->scount & 0xffff;
730
731 curr_count <<= d->shift;
732 count <<= d->shift;
733 dolog ("read scount curr %d, total %d\n", curr_count, count);
734 }
735#endif
736 break;
737
738 case ES1370_REG_ADC_FRAMECNT:
739 d++;
740 case ES1370_REG_DAC2_FRAMECNT:
741 d++;
742 case ES1370_REG_DAC1_FRAMECNT:
743 val = d->frame_cnt;
744#ifdef DEBUG_ES1370
745 {
746 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
747 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
748 if (curr > size)
749 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
750 curr > size);
751 }
752#endif
753 break;
754
755 case ES1370_REG_ADC_FRAMEADR:
756 d++;
757 case ES1370_REG_DAC2_FRAMEADR:
758 d++;
759 case ES1370_REG_DAC1_FRAMEADR:
760 val = d->frame_addr;
761 break;
762
946fc947
FB		 763 case ES1370_REG_PHANTOM_FRAMECNT:
764 val = ~0U;
765 lwarn ("reading from phantom frame count\n");
766 break;
767 case ES1370_REG_PHANTOM_FRAMEADR:
768 val = ~0U;
769 lwarn ("reading from phantom frame address\n");
770 break;
771
1d14ffa9
FB		 772 default:
773 val = ~0U;
774 lwarn ("readl %#x -> %#x\n", addr, val);
775 break;
776 }
777 return val;
778}
779
1d14ffa9
FB		 780static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
781 int max, int *irq)
782{
783 uint8_t tmpbuf[4096];
784 uint32_t addr = d->frame_addr;
785 int sc = d->scount & 0xffff;
786 int csc = d->scount >> 16;
787 int csc_bytes = (csc + 1) << d->shift;
788 int cnt = d->frame_cnt >> 16;
789 int size = d->frame_cnt & 0xffff;
790 int left = ((size - cnt + 1) << 2) + d->leftover;
a1b6abe7 791 int transferred = 0;
1d14ffa9
FB		 792 int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
793 int index = d - &s->chan[0];
794
795 addr += (cnt << 2) + d->leftover;
796
797 if (index == ADC_CHANNEL) {
798 while (temp) {
799 int acquired, to_copy;
800
c0fe3827 801 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
1d14ffa9
FB		 802 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
803 if (!acquired)
804 break;
805
3204db98 806 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1d14ffa9
FB		 807
808 temp -= acquired;
809 addr += acquired;
a1b6abe7 810 transferred += acquired;
1d14ffa9
FB		 811 }
812 }
813 else {
814 SWVoiceOut *voice = s->dac_voice[index];
815
816 while (temp) {
817 int copied, to_copy;
818
c0fe3827 819 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
3204db98 820 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
1d14ffa9
FB		 821 copied = AUD_write (voice, tmpbuf, to_copy);
822 if (!copied)
823 break;
824 temp -= copied;
825 addr += copied;
a1b6abe7 826 transferred += copied;
1d14ffa9
FB		 827 }
828 }
829
a1b6abe7 830 if (csc_bytes == transferred) {
1d14ffa9
FB		 831 *irq = 1;
832 d->scount = sc | (sc << 16);
833 ldebug ("sc = %d, rate = %f\n",
834 (sc + 1) << d->shift,
835 (sc + 1) / (double) 44100);
836 }
837 else {
838 *irq = 0;
a1b6abe7 839 d->scount = sc | (((csc_bytes - transferred - 1) >> d->shift) << 16);
1d14ffa9
FB		 840 }
841
a1b6abe7 842 cnt += (transferred + d->leftover) >> 2;
1d14ffa9
FB		 843
844 if (s->sctl & loop_sel) {
845 /* Bah, how stupid is that having a 0 represent true value?
846 i just spent few hours on this shit */
946fc947 847 AUD_log ("es1370: warning", "non looping mode\n");
1d14ffa9
FB		 848 }
849 else {
850 d->frame_cnt = size;
851
c0fe3827 852 if ((uint32_t) cnt <= d->frame_cnt)
1d14ffa9
FB		 853 d->frame_cnt |= cnt << 16;
854 }
855
a1b6abe7 856 d->leftover = (transferred + d->leftover) & 3;
1d14ffa9
FB		 857}
858
859static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
860{
861 uint32_t new_status = s->status;
862 int max_bytes, irq;
863 struct chan *d = &s->chan[chan];
864 const struct chan_bits *b = &es1370_chan_bits[chan];
865
866 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
867 return;
868 }
869
870 max_bytes = free_or_avail;
871 max_bytes &= ~((1 << d->shift) - 1);
872 if (!max_bytes) {
873 return;
874 }
875
876 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
877
878 if (irq) {
879 if (s->sctl & b->sctl_inten) {
880 new_status |= b->stat_int;
881 }
882 }
883
884 if (new_status != s->status) {
885 es1370_update_status (s, new_status);
886 }
887}
888
889static void es1370_dac1_callback (void *opaque, int free)
890{
891 ES1370State *s = opaque;
892
893 es1370_run_channel (s, DAC1_CHANNEL, free);
894}
895
896static void es1370_dac2_callback (void *opaque, int free)
897{
898 ES1370State *s = opaque;
899
900 es1370_run_channel (s, DAC2_CHANNEL, free);
901}
902
903static void es1370_adc_callback (void *opaque, int avail)
904{
905 ES1370State *s = opaque;
906
907 es1370_run_channel (s, ADC_CHANNEL, avail);
908}
909
e1a99dbd
AK		 910static const MemoryRegionPortio es1370_portio[] = {
911 { 0, 0x40 * 4, 1, .write = es1370_writeb, },
912 { 0, 0x40 * 2, 2, .write = es1370_writew, },
913 { 0, 0x40, 4, .write = es1370_writel, },
914 { 0, 0x40 * 4, 1, .read = es1370_readb, },
915 { 0, 0x40 * 2, 2, .read = es1370_readw, },
916 { 0, 0x40, 4, .read = es1370_readl, },
cf4dc461 917 PORTIO_END_OF_LIST ()
e1a99dbd 918};
1d14ffa9 919
e1a99dbd
AK		 920static const MemoryRegionOps es1370_io_ops = {
921 .old_portio = es1370_portio,
922 .endianness = DEVICE_LITTLE_ENDIAN,
923};
1d14ffa9 924
3a14c2df
JQ		 925static const VMStateDescription vmstate_es1370_channel = {
926 .name = "es1370_channel",
927 .version_id = 2,
928 .minimum_version_id = 2,
929 .minimum_version_id_old = 2,
930 .fields = (VMStateField []) {
cf4dc461 931 VMSTATE_UINT32 (shift, struct chan),
932 VMSTATE_UINT32 (leftover, struct chan),
933 VMSTATE_UINT32 (scount, struct chan),
934 VMSTATE_UINT32 (frame_addr, struct chan),
935 VMSTATE_UINT32 (frame_cnt, struct chan),
936 VMSTATE_END_OF_LIST ()
1d14ffa9 937 }
3a14c2df 938};
1d14ffa9 939
3a14c2df 940static int es1370_post_load (void *opaque, int version_id)
1d14ffa9
FB		 941{
942 uint32_t ctl, sctl;
943 ES1370State *s = opaque;
944 size_t i;
945
1d14ffa9 946 for (i = 0; i < NB_CHANNELS; ++i) {
1d14ffa9
FB		 947 if (i == ADC_CHANNEL) {
948 if (s->adc_voice) {
c0fe3827 949 AUD_close_in (&s->card, s->adc_voice);
1d14ffa9
FB		 950 s->adc_voice = NULL;
951 }
952 }
953 else {
954 if (s->dac_voice[i]) {
c0fe3827 955 AUD_close_out (&s->card, s->dac_voice[i]);
1d14ffa9
FB		 956 s->dac_voice[i] = NULL;
957 }
958 }
959 }
960
3a14c2df
JQ		 961 ctl = s->ctl;
962 sctl = s->sctl;
1d14ffa9
FB		 963 s->ctl = 0;
964 s->sctl = 0;
965 es1370_update_voices (s, ctl, sctl);
966 return 0;
967}
968
3a14c2df
JQ		 969static const VMStateDescription vmstate_es1370 = {
970 .name = "es1370",
971 .version_id = 2,
972 .minimum_version_id = 2,
973 .minimum_version_id_old = 2,
974 .post_load = es1370_post_load,
975 .fields = (VMStateField []) {
cf4dc461 976 VMSTATE_PCI_DEVICE (dev, ES1370State),
977 VMSTATE_STRUCT_ARRAY (chan, ES1370State, NB_CHANNELS, 2,
978 vmstate_es1370_channel, struct chan),
979 VMSTATE_UINT32 (ctl, ES1370State),
980 VMSTATE_UINT32 (status, ES1370State),
981 VMSTATE_UINT32 (mempage, ES1370State),
982 VMSTATE_UINT32 (codec, ES1370State),
983 VMSTATE_UINT32 (sctl, ES1370State),
984 VMSTATE_END_OF_LIST ()
3a14c2df
JQ		 985 }
986};
987
1d14ffa9
FB		 988static void es1370_on_reset (void *opaque)
989{
990 ES1370State *s = opaque;
991 es1370_reset (s);
992}
993
81a322d4 994static int es1370_initfn (PCIDevice *dev)
1d14ffa9 995{
b6f6d0e2 996 ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
e5944641 997 uint8_t *c = s->dev.config;
1d14ffa9 998
d3e2f135 999 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8;
1d14ffa9 1000
0b8c537f 1001#if 0
d3e2f135
MT		 1002 c[PCI_CAPABILITY_LIST] = 0xdc;
1003 c[PCI_INTERRUPT_LINE] = 10;
1d14ffa9
FB		 1004 c[0xdc] = 0x00;
1005#endif
1006
d3e2f135
MT		 1007 c[PCI_INTERRUPT_PIN] = 1;
1008 c[PCI_MIN_GNT] = 0x0c;
1009 c[PCI_MAX_LAT] = 0x80;
1d14ffa9 1010
e1a99dbd 1011 memory_region_init_io (&s->io, &es1370_io_ops, s, "es1370", 256);
e824b2cc 1012 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
a08d4367 1013 qemu_register_reset (es1370_on_reset, s);
c0fe3827 1014
1a7dafce 1015 AUD_register_card ("es1370", &s->card);
1d14ffa9 1016 es1370_reset (s);
81a322d4 1017 return 0;
6806e595
GH		 1018}
1019
cf4dc461 1020static int es1370_exitfn (PCIDevice *dev)
e1a99dbd
AK		 1021{
1022 ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
1023
1024 memory_region_destroy (&s->io);
1025 return 0;
1026}
1027
6806e595
GH		 1028int es1370_init (PCIBus *bus)
1029{
b6f6d0e2 1030 pci_create_simple (bus, -1, "ES1370");
1d14ffa9
FB		 1031 return 0;
1032}
6806e595 1033
cf4dc461 1034static void es1370_class_init (ObjectClass *klass, void *data)
40021f08 1035{
cf4dc461 1036 DeviceClass *dc = DEVICE_CLASS (klass);
1037 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
40021f08
AL		 1038
1039 k->init = es1370_initfn;
1040 k->exit = es1370_exitfn;
1041 k->vendor_id = PCI_VENDOR_ID_ENSONIQ;
1042 k->device_id = PCI_DEVICE_ID_ENSONIQ_ES1370;
1043 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1044 k->subsystem_vendor_id = 0x4942;
1045 k->subsystem_id = 0x4c4c;
39bffca2
AL		 1046 dc->desc = "ENSONIQ AudioPCI ES1370";
1047 dc->vmsd = &vmstate_es1370;
40021f08
AL		 1048}
1049
39bffca2
AL		 1050static TypeInfo es1370_info = {
1051 .name = "ES1370",
1052 .parent = TYPE_PCI_DEVICE,
1053 .instance_size = sizeof (ES1370State),
1054 .class_init = es1370_class_init,
6806e595
GH		 1055};
1056
83f7d43a 1057static void es1370_register_types (void)
6806e595 1058{
cf4dc461 1059 type_register_static (&es1370_info);
6806e595 1060}
83f7d43a
AF		 1061
1062type_init (es1370_register_types)
6806e595 1063
Qemu copy for testing