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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
5fafdf24 | 5 | * |
6f7e9aec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
5d20fa6b | 24 | |
cfb9de9c | 25 | #include "sysbus.h" |
87ecb68b | 26 | #include "scsi-disk.h" |
8b17de88 | 27 | #include "scsi.h" |
6f7e9aec FB |
28 | |
29 | /* debug ESP card */ | |
2f275b8f | 30 | //#define DEBUG_ESP |
6f7e9aec | 31 | |
67e999be | 32 | /* |
5ad6bb97 BS |
33 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
34 | * also produced as NCR89C100. See | |
67e999be FB |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
36 | * and | |
37 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
38 | */ | |
39 | ||
6f7e9aec | 40 | #ifdef DEBUG_ESP |
001faf32 BS |
41 | #define DPRINTF(fmt, ...) \ |
42 | do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) | |
6f7e9aec | 43 | #else |
001faf32 | 44 | #define DPRINTF(fmt, ...) do {} while (0) |
6f7e9aec FB |
45 | #endif |
46 | ||
001faf32 BS |
47 | #define ESP_ERROR(fmt, ...) \ |
48 | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) | |
8dea1dd4 | 49 | |
5aca8c3b | 50 | #define ESP_REGS 16 |
8dea1dd4 | 51 | #define TI_BUFSZ 16 |
67e999be | 52 | |
4e9aec74 | 53 | typedef struct ESPState ESPState; |
6f7e9aec | 54 | |
4e9aec74 | 55 | struct ESPState { |
cfb9de9c | 56 | SysBusDevice busdev; |
5d20fa6b | 57 | uint32_t it_shift; |
70c0de96 | 58 | qemu_irq irq; |
5aca8c3b BS |
59 | uint8_t rregs[ESP_REGS]; |
60 | uint8_t wregs[ESP_REGS]; | |
67e999be | 61 | int32_t ti_size; |
4f6200f0 | 62 | uint32_t ti_rptr, ti_wptr; |
4f6200f0 | 63 | uint8_t ti_buf[TI_BUFSZ]; |
22548760 BS |
64 | uint32_t sense; |
65 | uint32_t dma; | |
e4bcb14c | 66 | SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
2e5d83bb | 67 | SCSIDevice *current_dev; |
9f149aa9 | 68 | uint8_t cmdbuf[TI_BUFSZ]; |
22548760 BS |
69 | uint32_t cmdlen; |
70 | uint32_t do_cmd; | |
4d611c9a | 71 | |
6787f5fa | 72 | /* The amount of data left in the current DMA transfer. */ |
4d611c9a | 73 | uint32_t dma_left; |
6787f5fa PB |
74 | /* The size of the current DMA transfer. Zero if no transfer is in |
75 | progress. */ | |
76 | uint32_t dma_counter; | |
a917d384 | 77 | uint8_t *async_buf; |
4d611c9a | 78 | uint32_t async_len; |
8b17de88 BS |
79 | |
80 | espdma_memory_read_write dma_memory_read; | |
81 | espdma_memory_read_write dma_memory_write; | |
67e999be | 82 | void *dma_opaque; |
4e9aec74 | 83 | }; |
6f7e9aec | 84 | |
5ad6bb97 BS |
85 | #define ESP_TCLO 0x0 |
86 | #define ESP_TCMID 0x1 | |
87 | #define ESP_FIFO 0x2 | |
88 | #define ESP_CMD 0x3 | |
89 | #define ESP_RSTAT 0x4 | |
90 | #define ESP_WBUSID 0x4 | |
91 | #define ESP_RINTR 0x5 | |
92 | #define ESP_WSEL 0x5 | |
93 | #define ESP_RSEQ 0x6 | |
94 | #define ESP_WSYNTP 0x6 | |
95 | #define ESP_RFLAGS 0x7 | |
96 | #define ESP_WSYNO 0x7 | |
97 | #define ESP_CFG1 0x8 | |
98 | #define ESP_RRES1 0x9 | |
99 | #define ESP_WCCF 0x9 | |
100 | #define ESP_RRES2 0xa | |
101 | #define ESP_WTEST 0xa | |
102 | #define ESP_CFG2 0xb | |
103 | #define ESP_CFG3 0xc | |
104 | #define ESP_RES3 0xd | |
105 | #define ESP_TCHI 0xe | |
106 | #define ESP_RES4 0xf | |
107 | ||
108 | #define CMD_DMA 0x80 | |
109 | #define CMD_CMD 0x7f | |
110 | ||
111 | #define CMD_NOP 0x00 | |
112 | #define CMD_FLUSH 0x01 | |
113 | #define CMD_RESET 0x02 | |
114 | #define CMD_BUSRESET 0x03 | |
115 | #define CMD_TI 0x10 | |
116 | #define CMD_ICCS 0x11 | |
117 | #define CMD_MSGACC 0x12 | |
118 | #define CMD_SATN 0x1a | |
119 | #define CMD_SELATN 0x42 | |
120 | #define CMD_SELATNS 0x43 | |
121 | #define CMD_ENSEL 0x44 | |
122 | ||
2f275b8f FB |
123 | #define STAT_DO 0x00 |
124 | #define STAT_DI 0x01 | |
125 | #define STAT_CD 0x02 | |
126 | #define STAT_ST 0x03 | |
8dea1dd4 BS |
127 | #define STAT_MO 0x06 |
128 | #define STAT_MI 0x07 | |
5ad6bb97 | 129 | #define STAT_PIO_MASK 0x06 |
2f275b8f FB |
130 | |
131 | #define STAT_TC 0x10 | |
4d611c9a PB |
132 | #define STAT_PE 0x20 |
133 | #define STAT_GE 0x40 | |
c73f96fd | 134 | #define STAT_INT 0x80 |
2f275b8f | 135 | |
8dea1dd4 BS |
136 | #define BUSID_DID 0x07 |
137 | ||
2f275b8f FB |
138 | #define INTR_FC 0x08 |
139 | #define INTR_BS 0x10 | |
140 | #define INTR_DC 0x20 | |
9e61bde5 | 141 | #define INTR_RST 0x80 |
2f275b8f FB |
142 | |
143 | #define SEQ_0 0x0 | |
144 | #define SEQ_CD 0x4 | |
145 | ||
5ad6bb97 BS |
146 | #define CFG1_RESREPT 0x40 |
147 | ||
5ad6bb97 BS |
148 | #define TCHI_FAS100A 0x4 |
149 | ||
c73f96fd BS |
150 | static void esp_raise_irq(ESPState *s) |
151 | { | |
152 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
153 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
154 | qemu_irq_raise(s->irq); | |
155 | } | |
156 | } | |
157 | ||
158 | static void esp_lower_irq(ESPState *s) | |
159 | { | |
160 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
161 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
162 | qemu_irq_lower(s->irq); | |
163 | } | |
164 | } | |
165 | ||
22548760 | 166 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 167 | { |
a917d384 | 168 | uint32_t dmalen; |
2f275b8f FB |
169 | int target; |
170 | ||
8dea1dd4 | 171 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 172 | if (s->dma) { |
fc4d65da | 173 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
8b17de88 | 174 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 175 | } else { |
fc4d65da BS |
176 | dmalen = s->ti_size; |
177 | memcpy(buf, s->ti_buf, dmalen); | |
f930d07e | 178 | buf[0] = 0; |
4f6200f0 | 179 | } |
fc4d65da | 180 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); |
2e5d83bb | 181 | |
2f275b8f | 182 | s->ti_size = 0; |
4f6200f0 FB |
183 | s->ti_rptr = 0; |
184 | s->ti_wptr = 0; | |
2f275b8f | 185 | |
a917d384 PB |
186 | if (s->current_dev) { |
187 | /* Started a new command before the old one finished. Cancel it. */ | |
8ccc2ace | 188 | s->current_dev->cancel_io(s->current_dev, 0); |
a917d384 PB |
189 | s->async_len = 0; |
190 | } | |
191 | ||
e4bcb14c | 192 | if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) { |
2e5d83bb | 193 | // No such drive |
c73f96fd | 194 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
195 | s->rregs[ESP_RINTR] = INTR_DC; |
196 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 197 | esp_raise_irq(s); |
f930d07e | 198 | return 0; |
2f275b8f | 199 | } |
2e5d83bb | 200 | s->current_dev = s->scsi_dev[target]; |
9f149aa9 PB |
201 | return dmalen; |
202 | } | |
203 | ||
204 | static void do_cmd(ESPState *s, uint8_t *buf) | |
205 | { | |
206 | int32_t datalen; | |
207 | int lun; | |
208 | ||
209 | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); | |
210 | lun = buf[0] & 7; | |
8ccc2ace | 211 | datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
67e999be FB |
212 | s->ti_size = datalen; |
213 | if (datalen != 0) { | |
c73f96fd | 214 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 215 | s->dma_left = 0; |
6787f5fa | 216 | s->dma_counter = 0; |
2e5d83bb | 217 | if (datalen > 0) { |
5ad6bb97 | 218 | s->rregs[ESP_RSTAT] |= STAT_DI; |
8ccc2ace | 219 | s->current_dev->read_data(s->current_dev, 0); |
2e5d83bb | 220 | } else { |
5ad6bb97 | 221 | s->rregs[ESP_RSTAT] |= STAT_DO; |
8ccc2ace | 222 | s->current_dev->write_data(s->current_dev, 0); |
b9788fc4 | 223 | } |
2f275b8f | 224 | } |
5ad6bb97 BS |
225 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
226 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 227 | esp_raise_irq(s); |
2f275b8f FB |
228 | } |
229 | ||
9f149aa9 PB |
230 | static void handle_satn(ESPState *s) |
231 | { | |
232 | uint8_t buf[32]; | |
233 | int len; | |
234 | ||
235 | len = get_cmd(s, buf); | |
236 | if (len) | |
237 | do_cmd(s, buf); | |
238 | } | |
239 | ||
240 | static void handle_satn_stop(ESPState *s) | |
241 | { | |
242 | s->cmdlen = get_cmd(s, s->cmdbuf); | |
243 | if (s->cmdlen) { | |
244 | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); | |
245 | s->do_cmd = 1; | |
c73f96fd | 246 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
247 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
248 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 249 | esp_raise_irq(s); |
9f149aa9 PB |
250 | } |
251 | } | |
252 | ||
0fc5c15a | 253 | static void write_response(ESPState *s) |
2f275b8f | 254 | { |
0fc5c15a PB |
255 | DPRINTF("Transfer status (sense=%d)\n", s->sense); |
256 | s->ti_buf[0] = s->sense; | |
257 | s->ti_buf[1] = 0; | |
4f6200f0 | 258 | if (s->dma) { |
8b17de88 | 259 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 260 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
261 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
262 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 263 | } else { |
f930d07e BS |
264 | s->ti_size = 2; |
265 | s->ti_rptr = 0; | |
266 | s->ti_wptr = 0; | |
5ad6bb97 | 267 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 268 | } |
c73f96fd | 269 | esp_raise_irq(s); |
2f275b8f | 270 | } |
4f6200f0 | 271 | |
a917d384 PB |
272 | static void esp_dma_done(ESPState *s) |
273 | { | |
c73f96fd | 274 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
275 | s->rregs[ESP_RINTR] = INTR_BS; |
276 | s->rregs[ESP_RSEQ] = 0; | |
277 | s->rregs[ESP_RFLAGS] = 0; | |
278 | s->rregs[ESP_TCLO] = 0; | |
279 | s->rregs[ESP_TCMID] = 0; | |
c73f96fd | 280 | esp_raise_irq(s); |
a917d384 PB |
281 | } |
282 | ||
4d611c9a PB |
283 | static void esp_do_dma(ESPState *s) |
284 | { | |
67e999be | 285 | uint32_t len; |
4d611c9a | 286 | int to_device; |
a917d384 | 287 | |
67e999be | 288 | to_device = (s->ti_size < 0); |
a917d384 | 289 | len = s->dma_left; |
4d611c9a | 290 | if (s->do_cmd) { |
4d611c9a | 291 | DPRINTF("command len %d + %d\n", s->cmdlen, len); |
8b17de88 | 292 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
293 | s->ti_size = 0; |
294 | s->cmdlen = 0; | |
295 | s->do_cmd = 0; | |
296 | do_cmd(s, s->cmdbuf); | |
297 | return; | |
a917d384 PB |
298 | } |
299 | if (s->async_len == 0) { | |
300 | /* Defer until data is available. */ | |
301 | return; | |
302 | } | |
303 | if (len > s->async_len) { | |
304 | len = s->async_len; | |
305 | } | |
306 | if (to_device) { | |
8b17de88 | 307 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 308 | } else { |
8b17de88 | 309 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 310 | } |
a917d384 PB |
311 | s->dma_left -= len; |
312 | s->async_buf += len; | |
313 | s->async_len -= len; | |
6787f5fa PB |
314 | if (to_device) |
315 | s->ti_size += len; | |
316 | else | |
317 | s->ti_size -= len; | |
a917d384 | 318 | if (s->async_len == 0) { |
4d611c9a | 319 | if (to_device) { |
67e999be | 320 | // ti_size is negative |
8ccc2ace | 321 | s->current_dev->write_data(s->current_dev, 0); |
4d611c9a | 322 | } else { |
8ccc2ace | 323 | s->current_dev->read_data(s->current_dev, 0); |
6787f5fa | 324 | /* If there is still data to be read from the device then |
8dea1dd4 | 325 | complete the DMA operation immediately. Otherwise defer |
6787f5fa PB |
326 | until the scsi layer has completed. */ |
327 | if (s->dma_left == 0 && s->ti_size > 0) { | |
328 | esp_dma_done(s); | |
329 | } | |
4d611c9a | 330 | } |
6787f5fa PB |
331 | } else { |
332 | /* Partially filled a scsi buffer. Complete immediately. */ | |
a917d384 PB |
333 | esp_dma_done(s); |
334 | } | |
4d611c9a PB |
335 | } |
336 | ||
a917d384 PB |
337 | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
338 | uint32_t arg) | |
2e5d83bb PB |
339 | { |
340 | ESPState *s = (ESPState *)opaque; | |
341 | ||
4d611c9a PB |
342 | if (reason == SCSI_REASON_DONE) { |
343 | DPRINTF("SCSI Command complete\n"); | |
344 | if (s->ti_size != 0) | |
345 | DPRINTF("SCSI command completed unexpectedly\n"); | |
346 | s->ti_size = 0; | |
a917d384 PB |
347 | s->dma_left = 0; |
348 | s->async_len = 0; | |
349 | if (arg) | |
4d611c9a | 350 | DPRINTF("Command failed\n"); |
a917d384 | 351 | s->sense = arg; |
5ad6bb97 | 352 | s->rregs[ESP_RSTAT] = STAT_ST; |
a917d384 PB |
353 | esp_dma_done(s); |
354 | s->current_dev = NULL; | |
4d611c9a PB |
355 | } else { |
356 | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size); | |
a917d384 | 357 | s->async_len = arg; |
8ccc2ace | 358 | s->async_buf = s->current_dev->get_buf(s->current_dev, 0); |
6787f5fa | 359 | if (s->dma_left) { |
a917d384 | 360 | esp_do_dma(s); |
6787f5fa PB |
361 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
362 | /* If this was the last part of a DMA transfer then the | |
363 | completion interrupt is deferred to here. */ | |
364 | esp_dma_done(s); | |
365 | } | |
4d611c9a | 366 | } |
2e5d83bb PB |
367 | } |
368 | ||
2f275b8f FB |
369 | static void handle_ti(ESPState *s) |
370 | { | |
4d611c9a | 371 | uint32_t dmalen, minlen; |
2f275b8f | 372 | |
5ad6bb97 | 373 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
db59203d PB |
374 | if (dmalen==0) { |
375 | dmalen=0x10000; | |
376 | } | |
6787f5fa | 377 | s->dma_counter = dmalen; |
db59203d | 378 | |
9f149aa9 PB |
379 | if (s->do_cmd) |
380 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
381 | else if (s->ti_size < 0) |
382 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
383 | else |
384 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
db59203d | 385 | DPRINTF("Transfer Information len %d\n", minlen); |
4f6200f0 | 386 | if (s->dma) { |
4d611c9a | 387 | s->dma_left = minlen; |
5ad6bb97 | 388 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 389 | esp_do_dma(s); |
9f149aa9 PB |
390 | } else if (s->do_cmd) { |
391 | DPRINTF("command len %d\n", s->cmdlen); | |
392 | s->ti_size = 0; | |
393 | s->cmdlen = 0; | |
394 | s->do_cmd = 0; | |
395 | do_cmd(s, s->cmdbuf); | |
396 | return; | |
397 | } | |
2f275b8f FB |
398 | } |
399 | ||
5aca8c3b | 400 | static void esp_reset(void *opaque) |
6f7e9aec FB |
401 | { |
402 | ESPState *s = opaque; | |
67e999be | 403 | |
5aca8c3b BS |
404 | memset(s->rregs, 0, ESP_REGS); |
405 | memset(s->wregs, 0, ESP_REGS); | |
5ad6bb97 | 406 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
4e9aec74 PB |
407 | s->ti_size = 0; |
408 | s->ti_rptr = 0; | |
409 | s->ti_wptr = 0; | |
4e9aec74 | 410 | s->dma = 0; |
9f149aa9 | 411 | s->do_cmd = 0; |
8dea1dd4 BS |
412 | |
413 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
414 | } |
415 | ||
2d069bab BS |
416 | static void parent_esp_reset(void *opaque, int irq, int level) |
417 | { | |
418 | if (level) | |
419 | esp_reset(opaque); | |
420 | } | |
421 | ||
6f7e9aec FB |
422 | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
423 | { | |
424 | ESPState *s = opaque; | |
425 | uint32_t saddr; | |
426 | ||
e64d7d59 | 427 | saddr = addr >> s->it_shift; |
9e61bde5 | 428 | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
6f7e9aec | 429 | switch (saddr) { |
5ad6bb97 | 430 | case ESP_FIFO: |
f930d07e BS |
431 | if (s->ti_size > 0) { |
432 | s->ti_size--; | |
5ad6bb97 | 433 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 BS |
434 | /* Data out. */ |
435 | ESP_ERROR("PIO data read not implemented\n"); | |
5ad6bb97 | 436 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 437 | } else { |
5ad6bb97 | 438 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 439 | } |
c73f96fd | 440 | esp_raise_irq(s); |
f930d07e BS |
441 | } |
442 | if (s->ti_size == 0) { | |
4f6200f0 FB |
443 | s->ti_rptr = 0; |
444 | s->ti_wptr = 0; | |
445 | } | |
f930d07e | 446 | break; |
5ad6bb97 | 447 | case ESP_RINTR: |
4d611c9a | 448 | // Clear interrupt/error status bits |
c73f96fd BS |
449 | s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); |
450 | esp_lower_irq(s); | |
9e61bde5 | 451 | break; |
6f7e9aec | 452 | default: |
f930d07e | 453 | break; |
6f7e9aec | 454 | } |
2f275b8f | 455 | return s->rregs[saddr]; |
6f7e9aec FB |
456 | } |
457 | ||
458 | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
459 | { | |
460 | ESPState *s = opaque; | |
461 | uint32_t saddr; | |
462 | ||
e64d7d59 | 463 | saddr = addr >> s->it_shift; |
5ad6bb97 BS |
464 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], |
465 | val); | |
6f7e9aec | 466 | switch (saddr) { |
5ad6bb97 BS |
467 | case ESP_TCLO: |
468 | case ESP_TCMID: | |
469 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 470 | break; |
5ad6bb97 | 471 | case ESP_FIFO: |
9f149aa9 PB |
472 | if (s->do_cmd) { |
473 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 BS |
474 | } else if (s->ti_size == TI_BUFSZ - 1) { |
475 | ESP_ERROR("fifo overrun\n"); | |
2e5d83bb PB |
476 | } else { |
477 | s->ti_size++; | |
478 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
479 | } | |
f930d07e | 480 | break; |
5ad6bb97 | 481 | case ESP_CMD: |
4f6200f0 | 482 | s->rregs[saddr] = val; |
5ad6bb97 | 483 | if (val & CMD_DMA) { |
f930d07e | 484 | s->dma = 1; |
6787f5fa | 485 | /* Reload DMA counter. */ |
5ad6bb97 BS |
486 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
487 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
f930d07e BS |
488 | } else { |
489 | s->dma = 0; | |
490 | } | |
5ad6bb97 BS |
491 | switch(val & CMD_CMD) { |
492 | case CMD_NOP: | |
f930d07e BS |
493 | DPRINTF("NOP (%2.2x)\n", val); |
494 | break; | |
5ad6bb97 | 495 | case CMD_FLUSH: |
f930d07e | 496 | DPRINTF("Flush FIFO (%2.2x)\n", val); |
9e61bde5 | 497 | //s->ti_size = 0; |
5ad6bb97 BS |
498 | s->rregs[ESP_RINTR] = INTR_FC; |
499 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 500 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 501 | break; |
5ad6bb97 | 502 | case CMD_RESET: |
f930d07e BS |
503 | DPRINTF("Chip reset (%2.2x)\n", val); |
504 | esp_reset(s); | |
505 | break; | |
5ad6bb97 | 506 | case CMD_BUSRESET: |
f930d07e | 507 | DPRINTF("Bus reset (%2.2x)\n", val); |
5ad6bb97 BS |
508 | s->rregs[ESP_RINTR] = INTR_RST; |
509 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 510 | esp_raise_irq(s); |
9e61bde5 | 511 | } |
f930d07e | 512 | break; |
5ad6bb97 | 513 | case CMD_TI: |
f930d07e BS |
514 | handle_ti(s); |
515 | break; | |
5ad6bb97 | 516 | case CMD_ICCS: |
f930d07e BS |
517 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); |
518 | write_response(s); | |
4bf5801d BS |
519 | s->rregs[ESP_RINTR] = INTR_FC; |
520 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 521 | break; |
5ad6bb97 | 522 | case CMD_MSGACC: |
f930d07e BS |
523 | DPRINTF("Message Accepted (%2.2x)\n", val); |
524 | write_response(s); | |
5ad6bb97 BS |
525 | s->rregs[ESP_RINTR] = INTR_DC; |
526 | s->rregs[ESP_RSEQ] = 0; | |
f930d07e | 527 | break; |
5ad6bb97 | 528 | case CMD_SATN: |
f930d07e BS |
529 | DPRINTF("Set ATN (%2.2x)\n", val); |
530 | break; | |
5ad6bb97 | 531 | case CMD_SELATN: |
f930d07e BS |
532 | DPRINTF("Set ATN (%2.2x)\n", val); |
533 | handle_satn(s); | |
534 | break; | |
5ad6bb97 | 535 | case CMD_SELATNS: |
f930d07e BS |
536 | DPRINTF("Set ATN & stop (%2.2x)\n", val); |
537 | handle_satn_stop(s); | |
538 | break; | |
5ad6bb97 | 539 | case CMD_ENSEL: |
74ec6048 | 540 | DPRINTF("Enable selection (%2.2x)\n", val); |
e3926838 | 541 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 542 | break; |
f930d07e | 543 | default: |
8dea1dd4 | 544 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val); |
f930d07e BS |
545 | break; |
546 | } | |
547 | break; | |
5ad6bb97 | 548 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 549 | break; |
5ad6bb97 | 550 | case ESP_CFG1: |
4f6200f0 FB |
551 | s->rregs[saddr] = val; |
552 | break; | |
5ad6bb97 | 553 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 554 | break; |
b44c08fa | 555 | case ESP_CFG2 ... ESP_RES4: |
4f6200f0 FB |
556 | s->rregs[saddr] = val; |
557 | break; | |
6f7e9aec | 558 | default: |
8dea1dd4 BS |
559 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr); |
560 | return; | |
6f7e9aec | 561 | } |
2f275b8f | 562 | s->wregs[saddr] = val; |
6f7e9aec FB |
563 | } |
564 | ||
565 | static CPUReadMemoryFunc *esp_mem_read[3] = { | |
566 | esp_mem_readb, | |
7c560456 BS |
567 | NULL, |
568 | NULL, | |
6f7e9aec FB |
569 | }; |
570 | ||
571 | static CPUWriteMemoryFunc *esp_mem_write[3] = { | |
572 | esp_mem_writeb, | |
7c560456 | 573 | NULL, |
daa41b00 | 574 | esp_mem_writeb, |
6f7e9aec FB |
575 | }; |
576 | ||
6f7e9aec FB |
577 | static void esp_save(QEMUFile *f, void *opaque) |
578 | { | |
579 | ESPState *s = opaque; | |
2f275b8f | 580 | |
5aca8c3b BS |
581 | qemu_put_buffer(f, s->rregs, ESP_REGS); |
582 | qemu_put_buffer(f, s->wregs, ESP_REGS); | |
b6c4f71f | 583 | qemu_put_sbe32s(f, &s->ti_size); |
4f6200f0 FB |
584 | qemu_put_be32s(f, &s->ti_rptr); |
585 | qemu_put_be32s(f, &s->ti_wptr); | |
4f6200f0 | 586 | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
5425a216 | 587 | qemu_put_be32s(f, &s->sense); |
4f6200f0 | 588 | qemu_put_be32s(f, &s->dma); |
5425a216 BS |
589 | qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
590 | qemu_put_be32s(f, &s->cmdlen); | |
591 | qemu_put_be32s(f, &s->do_cmd); | |
592 | qemu_put_be32s(f, &s->dma_left); | |
593 | // There should be no transfers in progress, so dma_counter is not saved | |
6f7e9aec FB |
594 | } |
595 | ||
596 | static int esp_load(QEMUFile *f, void *opaque, int version_id) | |
597 | { | |
598 | ESPState *s = opaque; | |
3b46e624 | 599 | |
5425a216 BS |
600 | if (version_id != 3) |
601 | return -EINVAL; // Cannot emulate 2 | |
6f7e9aec | 602 | |
5aca8c3b BS |
603 | qemu_get_buffer(f, s->rregs, ESP_REGS); |
604 | qemu_get_buffer(f, s->wregs, ESP_REGS); | |
b6c4f71f | 605 | qemu_get_sbe32s(f, &s->ti_size); |
4f6200f0 FB |
606 | qemu_get_be32s(f, &s->ti_rptr); |
607 | qemu_get_be32s(f, &s->ti_wptr); | |
4f6200f0 | 608 | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
5425a216 | 609 | qemu_get_be32s(f, &s->sense); |
4f6200f0 | 610 | qemu_get_be32s(f, &s->dma); |
5425a216 BS |
611 | qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
612 | qemu_get_be32s(f, &s->cmdlen); | |
613 | qemu_get_be32s(f, &s->do_cmd); | |
614 | qemu_get_be32s(f, &s->dma_left); | |
2f275b8f | 615 | |
6f7e9aec FB |
616 | return 0; |
617 | } | |
618 | ||
cfb9de9c | 619 | static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id) |
fa1fb14c | 620 | { |
cfb9de9c | 621 | ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host)); |
fa1fb14c TS |
622 | |
623 | if (id < 0) { | |
624 | for (id = 0; id < ESP_MAX_DEVS; id++) { | |
8dea1dd4 BS |
625 | if (id == (s->rregs[ESP_CFG1] & 0x7)) |
626 | continue; | |
fa1fb14c TS |
627 | if (s->scsi_dev[id] == NULL) |
628 | break; | |
629 | } | |
630 | } | |
631 | if (id >= ESP_MAX_DEVS) { | |
632 | DPRINTF("Bad Device ID %d\n", id); | |
633 | return; | |
634 | } | |
635 | if (s->scsi_dev[id]) { | |
636 | DPRINTF("Destroying device %d\n", id); | |
8ccc2ace | 637 | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
fa1fb14c TS |
638 | } |
639 | DPRINTF("Attaching block device %d\n", id); | |
640 | /* Command queueing is not implemented. */ | |
985a03b0 TS |
641 | s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s); |
642 | if (s->scsi_dev[id] == NULL) | |
643 | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s); | |
fa1fb14c TS |
644 | } |
645 | ||
cfb9de9c PB |
646 | void esp_init(target_phys_addr_t espaddr, int it_shift, |
647 | espdma_memory_read_write dma_memory_read, | |
648 | espdma_memory_read_write dma_memory_write, | |
649 | void *dma_opaque, qemu_irq irq, qemu_irq *reset) | |
6f7e9aec | 650 | { |
cfb9de9c PB |
651 | DeviceState *dev; |
652 | SysBusDevice *s; | |
653 | ||
654 | dev = qdev_create(NULL, "esp"); | |
655 | qdev_set_prop_ptr(dev, "dma_memory_read", dma_memory_read); | |
656 | qdev_set_prop_ptr(dev, "dma_memory_write", dma_memory_write); | |
657 | qdev_set_prop_ptr(dev, "dma_opaque", dma_opaque); | |
658 | qdev_set_prop_int(dev, "it_shift", it_shift); | |
659 | qdev_init(dev); | |
660 | s = sysbus_from_qdev(dev); | |
661 | sysbus_connect_irq(s, 0, irq); | |
662 | sysbus_mmio_map(s, 0, espaddr); | |
663 | } | |
6f7e9aec | 664 | |
cfb9de9c PB |
665 | static void esp_init1(SysBusDevice *dev) |
666 | { | |
667 | ESPState *s = FROM_SYSBUS(ESPState, dev); | |
668 | int esp_io_memory; | |
6f7e9aec | 669 | |
cfb9de9c PB |
670 | sysbus_init_irq(dev, &s->irq); |
671 | s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", -1); | |
672 | assert(s->it_shift != -1); | |
673 | s->dma_memory_read = qdev_get_prop_ptr(&dev->qdev, "dma_memory_read"); | |
674 | s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write"); | |
675 | s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque"); | |
6f7e9aec | 676 | |
1eed09cb | 677 | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
cfb9de9c | 678 | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
6f7e9aec | 679 | |
6f7e9aec FB |
680 | esp_reset(s); |
681 | ||
cfb9de9c | 682 | register_savevm("esp", -1, 3, esp_save, esp_load, s); |
a08d4367 | 683 | qemu_register_reset(esp_reset, s); |
6f7e9aec | 684 | |
067a3ddc | 685 | qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1); |
2d069bab | 686 | |
cfb9de9c | 687 | scsi_bus_new(&dev->qdev, esp_scsi_attach); |
67e999be | 688 | } |
cfb9de9c PB |
689 | |
690 | static void esp_register_devices(void) | |
691 | { | |
692 | sysbus_register_dev("esp", sizeof(ESPState), esp_init1); | |
693 | } | |
694 | ||
695 | device_init(esp_register_devices) |