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ETRAX: More DMA context level related fixes.
[qemu.git] / hw / etraxfs_dma.c
CommitLineData
1ba13a5d
EI		 1/*
2 * QEMU ETRAX DMA Controller.
3 *
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include <stdio.h>
25#include <sys/time.h>
26#include "hw.h"
27
28#include "etraxfs_dma.h"
29
30#define D(x)
31
32#define RW_DATA 0x0
33#define RW_SAVED_DATA 0x58
34#define RW_SAVED_DATA_BUF 0x5c
35#define RW_GROUP 0x60
36#define RW_GROUP_DOWN 0x7c
37#define RW_CMD 0x80
38#define RW_CFG 0x84
39#define RW_STAT 0x88
40#define RW_INTR_MASK 0x8c
41#define RW_ACK_INTR 0x90
42#define R_INTR 0x94
43#define R_MASKED_INTR 0x98
44#define RW_STREAM_CMD 0x9c
45
46#define DMA_REG_MAX 0x100
47
48/* descriptors */
49
50// ------------------------------------------------------------ dma_descr_group
51typedef struct dma_descr_group {
52 struct dma_descr_group *next;
53 unsigned eol : 1;
54 unsigned tol : 1;
55 unsigned bol : 1;
56 unsigned : 1;
57 unsigned intr : 1;
58 unsigned : 2;
59 unsigned en : 1;
60 unsigned : 7;
61 unsigned dis : 1;
62 unsigned md : 16;
63 struct dma_descr_group *up;
64 union {
65 struct dma_descr_context *context;
66 struct dma_descr_group *group;
67 } down;
68} dma_descr_group;
69
70// ---------------------------------------------------------- dma_descr_context
71typedef struct dma_descr_context {
72 struct dma_descr_context *next;
73 unsigned eol : 1;
74 unsigned : 3;
75 unsigned intr : 1;
76 unsigned : 1;
77 unsigned store_mode : 1;
78 unsigned en : 1;
79 unsigned : 7;
80 unsigned dis : 1;
81 unsigned md0 : 16;
82 unsigned md1;
83 unsigned md2;
84 unsigned md3;
85 unsigned md4;
86 struct dma_descr_data *saved_data;
87 char *saved_data_buf;
88} dma_descr_context;
89
90// ------------------------------------------------------------- dma_descr_data
91typedef struct dma_descr_data {
92 struct dma_descr_data *next;
93 char *buf;
94 unsigned eol : 1;
95 unsigned : 2;
96 unsigned out_eop : 1;
97 unsigned intr : 1;
98 unsigned wait : 1;
99 unsigned : 2;
100 unsigned : 3;
101 unsigned in_eop : 1;
102 unsigned : 4;
103 unsigned md : 16;
104 char *after;
105} dma_descr_data;
106
107/* Constants */
108enum {
109 regk_dma_ack_pkt = 0x00000100,
110 regk_dma_anytime = 0x00000001,
111 regk_dma_array = 0x00000008,
112 regk_dma_burst = 0x00000020,
113 regk_dma_client = 0x00000002,
114 regk_dma_copy_next = 0x00000010,
115 regk_dma_copy_up = 0x00000020,
116 regk_dma_data_at_eol = 0x00000001,
117 regk_dma_dis_c = 0x00000010,
118 regk_dma_dis_g = 0x00000020,
119 regk_dma_idle = 0x00000001,
120 regk_dma_intern = 0x00000004,
121 regk_dma_load_c = 0x00000200,
122 regk_dma_load_c_n = 0x00000280,
123 regk_dma_load_c_next = 0x00000240,
124 regk_dma_load_d = 0x00000140,
125 regk_dma_load_g = 0x00000300,
126 regk_dma_load_g_down = 0x000003c0,
127 regk_dma_load_g_next = 0x00000340,
128 regk_dma_load_g_up = 0x00000380,
129 regk_dma_next_en = 0x00000010,
130 regk_dma_next_pkt = 0x00000010,
131 regk_dma_no = 0x00000000,
132 regk_dma_only_at_wait = 0x00000000,
133 regk_dma_restore = 0x00000020,
134 regk_dma_rst = 0x00000001,
135 regk_dma_running = 0x00000004,
136 regk_dma_rw_cfg_default = 0x00000000,
137 regk_dma_rw_cmd_default = 0x00000000,
138 regk_dma_rw_intr_mask_default = 0x00000000,
139 regk_dma_rw_stat_default = 0x00000101,
140 regk_dma_rw_stream_cmd_default = 0x00000000,
141 regk_dma_save_down = 0x00000020,
142 regk_dma_save_up = 0x00000020,
143 regk_dma_set_reg = 0x00000050,
144 regk_dma_set_w_size1 = 0x00000190,
145 regk_dma_set_w_size2 = 0x000001a0,
146 regk_dma_set_w_size4 = 0x000001c0,
147 regk_dma_stopped = 0x00000002,
148 regk_dma_store_c = 0x00000002,
149 regk_dma_store_descr = 0x00000000,
150 regk_dma_store_g = 0x00000004,
151 regk_dma_store_md = 0x00000001,
152 regk_dma_sw = 0x00000008,
153 regk_dma_update_down = 0x00000020,
154 regk_dma_yes = 0x00000001
155};
156
157enum dma_ch_state
158{
159 RST = 0,
160 STOPPED = 2,
161 RUNNING = 4
162};
163
164struct fs_dma_channel
165{
166 int regmap;
167 qemu_irq *irq;
168 struct etraxfs_dma_client *client;
169
170
171 /* Internal status. */
172 int stream_cmd_src;
173 enum dma_ch_state state;
174
175 unsigned int input : 1;
176 unsigned int eol : 1;
177
178 struct dma_descr_group current_g;
179 struct dma_descr_context current_c;
180 struct dma_descr_data current_d;
181
182 /* Controll registers. */
183 uint32_t regs[DMA_REG_MAX];
184};
185
186struct fs_dma_ctrl
187{
188 CPUState *env;
189 target_phys_addr_t base;
190
191 int nr_channels;
192 struct fs_dma_channel *channels;
193};
194
195static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
196{
197 return ctrl->channels[c].regs[reg];
198}
199
200static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
201{
202 return channel_reg(ctrl, c, RW_CFG) & 2;
203}
204
205static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
206{
207 return (channel_reg(ctrl, c, RW_CFG) & 1)
208 && ctrl->channels[c].client;
209}
210
211static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
212{
213 /* Every channel has a 0x2000 ctrl register map. */
214 return (addr - base) >> 13;
215}
216
217static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
218{
219 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
220
221 /* Load and decode. FIXME: handle endianness. */
222 cpu_physical_memory_read (addr,
223 (void *) &ctrl->channels[c].current_g,
224 sizeof ctrl->channels[c].current_g);
225}
226
227static void dump_c(int ch, struct dma_descr_context *c)
228{
229 printf("%s ch=%d\n", __func__, ch);
230 printf("next=%x\n", (uint32_t) c->next);
231 printf("saved_data=%x\n", (uint32_t) c->saved_data);
232 printf("saved_data_buf=%x\n", (uint32_t) c->saved_data_buf);
233 printf("eol=%x\n", (uint32_t) c->eol);
234}
235
236static void dump_d(int ch, struct dma_descr_data *d)
237{
238 printf("%s ch=%d\n", __func__, ch);
239 printf("next=%x\n", (uint32_t) d->next);
240 printf("buf=%x\n", (uint32_t) d->buf);
241 printf("after=%x\n", (uint32_t) d->after);
242 printf("intr=%x\n", (uint32_t) d->intr);
243 printf("out_eop=%x\n", (uint32_t) d->out_eop);
244 printf("in_eop=%x\n", (uint32_t) d->in_eop);
245 printf("eol=%x\n", (uint32_t) d->eol);
246}
247
248static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
249{
250 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
251
252 /* Load and decode. FIXME: handle endianness. */
253 cpu_physical_memory_read (addr,
254 (void *) &ctrl->channels[c].current_c,
255 sizeof ctrl->channels[c].current_c);
256
257 D(dump_c(c, &ctrl->channels[c].current_c));
258 /* I guess this should update the current pos. */
259 ctrl->channels[c].regs[RW_SAVED_DATA] =
260 (uint32_t)ctrl->channels[c].current_c.saved_data;
261 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
262 (uint32_t)ctrl->channels[c].current_c.saved_data_buf;
263}
264
265static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
266{
267 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
268
269 /* Load and decode. FIXME: handle endianness. */
a8303d18 270 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
1ba13a5d
EI		 271 cpu_physical_memory_read (addr,
272 (void *) &ctrl->channels[c].current_d,
273 sizeof ctrl->channels[c].current_d);
274
275 D(dump_d(c, &ctrl->channels[c].current_d));
fa1bdde4 276 ctrl->channels[c].regs[RW_DATA] = addr;
a8303d18
EI		 277}
278
279static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
280{
281 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
282
283 /* Encode and store. FIXME: handle endianness. */
284 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
285 D(dump_d(c, &ctrl->channels[c].current_d));
286 cpu_physical_memory_write (addr,
287 (void *) &ctrl->channels[c].current_c,
288 sizeof ctrl->channels[c].current_c);
1ba13a5d
EI		 289}
290
291static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
292{
293 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
294
a8303d18
EI		 295 /* Encode and store. FIXME: handle endianness. */
296 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
1ba13a5d
EI		 297 cpu_physical_memory_write (addr,
298 (void *) &ctrl->channels[c].current_d,
299 sizeof ctrl->channels[c].current_d);
300}
301
302static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
303{
304 /* FIXME: */
305}
306
307static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
308{
309 if (ctrl->channels[c].client)
310 {
311 ctrl->channels[c].eol = 0;
312 ctrl->channels[c].state = RUNNING;
313 } else
314 printf("WARNING: starting DMA ch %d with no client\n", c);
315}
316
317static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
318{
319 if (!channel_en(ctrl, c)
320 || channel_stopped(ctrl, c)
321 || ctrl->channels[c].state != RUNNING
322 /* Only reload the current data descriptor if it has eol set. */
323 || !ctrl->channels[c].current_d.eol) {
324 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
325 c, ctrl->channels[c].state,
326 channel_stopped(ctrl, c),
327 channel_en(ctrl,c),
328 ctrl->channels[c].eol));
329 D(dump_d(c, &ctrl->channels[c].current_d));
330 return;
331 }
332
333 /* Reload the current descriptor. */
334 channel_load_d(ctrl, c);
335
336 /* If the current descriptor cleared the eol flag and we had already
337 reached eol state, do the continue. */
338 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
a8303d18 339 D(printf("continue %d ok %p\n", c,
1ba13a5d
EI		 340 ctrl->channels[c].current_d.next));
341 ctrl->channels[c].regs[RW_SAVED_DATA] =
342 (uint32_t) ctrl->channels[c].current_d.next;
343 channel_load_d(ctrl, c);
344 channel_start(ctrl, c);
345 }
a8303d18
EI		 346 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
347 (uint32_t) ctrl->channels[c].current_d.buf;
1ba13a5d
EI		 348}
349
350static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
351{
352 unsigned int cmd = v & ((1 << 10) - 1);
353
a8303d18
EI		 354 D(printf("%s ch=%d cmd=%x pc=%x\n",
355 __func__, c, cmd, ctrl->env->pc));
1ba13a5d
EI		 356 if (cmd & regk_dma_load_d) {
357 channel_load_d(ctrl, c);
358 if (cmd & regk_dma_burst)
359 channel_start(ctrl, c);
360 }
361
362 if (cmd & regk_dma_load_c) {
363 channel_load_c(ctrl, c);
a8303d18 364 channel_start(ctrl, c);
1ba13a5d
EI		 365 }
366}
367
368static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
369{
370 D(printf("%s %d\n", __func__, c));
371 ctrl->channels[c].regs[R_INTR] &=
372 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
373
374 ctrl->channels[c].regs[R_MASKED_INTR] =
375 ctrl->channels[c].regs[R_INTR]
376 & ctrl->channels[c].regs[RW_INTR_MASK];
377
378 D(printf("%s: chan=%d masked_intr=%x\n", __func__,
379 c,
380 ctrl->channels[c].regs[R_MASKED_INTR]));
381
382 if (ctrl->channels[c].regs[R_MASKED_INTR])
383 qemu_irq_raise(ctrl->channels[c].irq[0]);
384 else
385 qemu_irq_lower(ctrl->channels[c].irq[0]);
386}
387
388static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
389{
390 uint32_t len;
391 uint32_t saved_data_buf;
392 unsigned char buf[2 * 1024];
393
394 if (ctrl->channels[c].eol == 1)
395 return;
396
397 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
398
a8303d18
EI		 399 D(fprintf(logfile, "ch=%d buf=%x after=%x saved_data_buf=%x\n",
400 c,
1ba13a5d
EI		 401 (uint32_t)ctrl->channels[c].current_d.buf,
402 (uint32_t)ctrl->channels[c].current_d.after,
403 saved_data_buf));
404
a8303d18
EI		 405 len = (uint32_t) ctrl->channels[c].current_d.after;
406 len -= saved_data_buf;
407
408 if (len > sizeof buf)
409 len = sizeof buf;
410 cpu_physical_memory_read (saved_data_buf, buf, len);
411
412 D(printf("channel %d pushes %x %u bytes\n", c,
413 saved_data_buf, len));
414
415 if (ctrl->channels[c].client->client.push)
416 ctrl->channels[c].client->client.push(
417 ctrl->channels[c].client->client.opaque, buf, len);
418 else
419 printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
420
421 saved_data_buf += len;
422
1ba13a5d
EI		 423 if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after) {
424 /* Done. Step to next. */
425 if (ctrl->channels[c].current_d.out_eop) {
426 /* TODO: signal eop to the client. */
427 D(printf("signal eop\n"));
428 }
429 if (ctrl->channels[c].current_d.intr) {
430 /* TODO: signal eop to the client. */
431 /* data intr. */
432 D(printf("signal intr\n"));
433 ctrl->channels[c].regs[R_INTR] |= (1 << 2);
434 channel_update_irq(ctrl, c);
435 }
436 if (ctrl->channels[c].current_d.eol) {
437 D(printf("channel %d EOL\n", c));
438 ctrl->channels[c].eol = 1;
a8303d18
EI		 439
440 /* Mark the context as disabled. */
441 ctrl->channels[c].current_c.dis = 1;
442 channel_store_c(ctrl, c);
443
1ba13a5d
EI		 444 channel_stop(ctrl, c);
445 } else {
446 ctrl->channels[c].regs[RW_SAVED_DATA] =
447 (uint32_t) ctrl->channels[c].current_d.next;
448 /* Load new descriptor. */
449 channel_load_d(ctrl, c);
a8303d18
EI		 450 saved_data_buf = (uint32_t)
451 ctrl->channels[c].current_d.buf;
1ba13a5d
EI		 452 }
453
454 channel_store_d(ctrl, c);
a8303d18 455 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
1ba13a5d 456 D(dump_d(c, &ctrl->channels[c].current_d));
1ba13a5d 457 }
a8303d18 458 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
1ba13a5d
EI		 459}
460
461static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
462 unsigned char *buf, int buflen, int eop)
463{
464 uint32_t len;
465 uint32_t saved_data_buf;
466
467 if (ctrl->channels[c].eol == 1)
468 return 0;
469
470 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
471 len = (uint32_t) ctrl->channels[c].current_d.after;
472 len -= saved_data_buf;
473
474 if (len > buflen)
475 len = buflen;
476
477 cpu_physical_memory_write (saved_data_buf, buf, len);
478 saved_data_buf += len;
479
480 if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after
481 || eop) {
482 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
483
484 D(printf("in dscr end len=%d\n",
485 ctrl->channels[c].current_d.after
486 - ctrl->channels[c].current_d.buf));
487 ctrl->channels[c].current_d.after =
488 (void *) saved_data_buf;
489
490 /* Done. Step to next. */
491 if (ctrl->channels[c].current_d.intr) {
492 /* TODO: signal eop to the client. */
493 /* data intr. */
494 ctrl->channels[c].regs[R_INTR] |= 3;
495 }
496 if (eop) {
497 ctrl->channels[c].current_d.in_eop = 1;
498 ctrl->channels[c].regs[R_INTR] |= 8;
499 }
500 if (r_intr != ctrl->channels[c].regs[R_INTR])
501 channel_update_irq(ctrl, c);
502
503 channel_store_d(ctrl, c);
504 D(dump_d(c, &ctrl->channels[c].current_d));
505
506 if (ctrl->channels[c].current_d.eol) {
507 D(printf("channel %d EOL\n", c));
508 ctrl->channels[c].eol = 1;
a8303d18
EI		 509
510 /* Mark the context as disabled. */
511 ctrl->channels[c].current_c.dis = 1;
512 channel_store_c(ctrl, c);
513
1ba13a5d
EI		 514 channel_stop(ctrl, c);
515 } else {
516 ctrl->channels[c].regs[RW_SAVED_DATA] =
517 (uint32_t) ctrl->channels[c].current_d.next;
518 /* Load new descriptor. */
519 channel_load_d(ctrl, c);
a8303d18
EI		 520 saved_data_buf = (uint32_t)
521 ctrl->channels[c].current_d.buf;
1ba13a5d
EI		 522 }
523 }
524
525 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
526 return len;
527}
528
529static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c)
530{
531 if (ctrl->channels[c].client->client.pull)
532 ctrl->channels[c].client->client.pull(
533 ctrl->channels[c].client->client.opaque);
534}
535
536static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
537{
538 struct fs_dma_ctrl *ctrl = opaque;
539 CPUState *env = ctrl->env;
540 cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
541 addr, env->pc);
542 return 0;
543}
544
545static uint32_t
546dma_readl (void *opaque, target_phys_addr_t addr)
547{
548 struct fs_dma_ctrl *ctrl = opaque;
549 int c;
550 uint32_t r = 0;
551
552 /* Make addr relative to this instances base. */
553 c = fs_channel(ctrl->base, addr);
a8303d18 554 addr &= 0x1fff;
1ba13a5d 555 switch (addr)
a8303d18 556 {
1ba13a5d
EI		 557 case RW_STAT:
558 r = ctrl->channels[c].state & 7;
559 r |= ctrl->channels[c].eol << 5;
560 r |= ctrl->channels[c].stream_cmd_src << 8;
561 break;
562
a8303d18 563 default:
1ba13a5d
EI		 564 r = ctrl->channels[c].regs[addr];
565 D(printf ("%s c=%d addr=%x pc=%x\n",
a8303d18
EI		 566 __func__, c, addr, ctrl->env->pc));
567 break;
568 }
1ba13a5d
EI		 569 return r;
570}
571
572static void
573dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
574{
575 struct fs_dma_ctrl *ctrl = opaque;
576 CPUState *env = ctrl->env;
577 cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
578 addr, env->pc);
579}
580
581static void
582dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
583{
584 struct fs_dma_ctrl *ctrl = opaque;
585 int c;
586
587 /* Make addr relative to this instances base. */
588 c = fs_channel(ctrl->base, addr);
589 addr &= 0x1fff;
590 switch (addr)
a8303d18 591 {
1ba13a5d 592 case RW_DATA:
fa1bdde4 593 ctrl->channels[c].regs[addr] = value;
1ba13a5d
EI		 594 break;
595
596 case RW_CFG:
597 ctrl->channels[c].regs[addr] = value;
598 break;
599 case RW_CMD:
600 /* continue. */
601 ctrl->channels[c].regs[addr] = value;
602 channel_continue(ctrl, c);
603 break;
604
605 case RW_SAVED_DATA:
606 case RW_SAVED_DATA_BUF:
607 case RW_GROUP:
608 case RW_GROUP_DOWN:
609 ctrl->channels[c].regs[addr] = value;
610 break;
611
612 case RW_ACK_INTR:
613 case RW_INTR_MASK:
614 ctrl->channels[c].regs[addr] = value;
615 channel_update_irq(ctrl, c);
616 if (addr == RW_ACK_INTR)
617 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
618 break;
619
620 case RW_STREAM_CMD:
621 ctrl->channels[c].regs[addr] = value;
a8303d18
EI		 622 D(printf("stream_cmd ch=%d pc=%x\n",
623 c, ctrl->env->pc));
1ba13a5d
EI		 624 channel_stream_cmd(ctrl, c, value);
625 break;
626
a8303d18
EI		 627 default:
628 D(printf ("%s c=%d %x %x pc=%x\n",
629 __func__, c, addr, value, ctrl->env->pc));
630 break;
1ba13a5d
EI		 631 }
632}
633
634static CPUReadMemoryFunc *dma_read[] = {
635 &dma_rinvalid,
636 &dma_rinvalid,
637 &dma_readl,
638};
639
640static CPUWriteMemoryFunc *dma_write[] = {
641 &dma_winvalid,
642 &dma_winvalid,
643 &dma_writel,
644};
645
646void etraxfs_dmac_run(void *opaque)
647{
648 struct fs_dma_ctrl *ctrl = opaque;
649 int i;
650 int p = 0;
651
652 for (i = 0;
653 i < ctrl->nr_channels;
654 i++)
655 {
656 if (ctrl->channels[i].state == RUNNING)
657 {
658 p++;
659 if (ctrl->channels[i].input)
660 channel_in_run(ctrl, i);
661 else
662 channel_out_run(ctrl, i);
663 }
664 }
665}
666
667int etraxfs_dmac_input(struct etraxfs_dma_client *client,
668 void *buf, int len, int eop)
669{
670 return channel_in_process(client->ctrl, client->channel,
671 buf, len, eop);
672}
673
674/* Connect an IRQ line with a channel. */
675void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
676{
677 struct fs_dma_ctrl *ctrl = opaque;
678 ctrl->channels[c].irq = line;
679 ctrl->channels[c].input = input;
680}
681
682void etraxfs_dmac_connect_client(void *opaque, int c,
683 struct etraxfs_dma_client *cl)
684{
685 struct fs_dma_ctrl *ctrl = opaque;
686 cl->ctrl = ctrl;
687 cl->channel = c;
688 ctrl->channels[c].client = cl;
689}
690
691
fa1bdde4
EI		 692static void *etraxfs_dmac;
693void DMA_run(void)
694{
695 if (etraxfs_dmac)
696 etraxfs_dmac_run(etraxfs_dmac);
697}
698
1ba13a5d
EI		 699void *etraxfs_dmac_init(CPUState *env,
700 target_phys_addr_t base, int nr_channels)
701{
702 struct fs_dma_ctrl *ctrl = NULL;
703 int i;
704
705 ctrl = qemu_mallocz(sizeof *ctrl);
706 if (!ctrl)
707 return NULL;
708
709 ctrl->base = base;
710 ctrl->env = env;
711 ctrl->nr_channels = nr_channels;
712 ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
713 if (!ctrl->channels)
714 goto err;
715
716 for (i = 0; i < nr_channels; i++)
717 {
718 ctrl->channels[i].regmap = cpu_register_io_memory(0,
719 dma_read,
720 dma_write,
721 ctrl);
722 cpu_register_physical_memory (base + i * 0x2000,
723 sizeof ctrl->channels[i].regs,
724 ctrl->channels[i].regmap);
725 }
726
fa1bdde4
EI		 727 /* Hax, we only support one DMA controller at a time. */
728 etraxfs_dmac = ctrl;
1ba13a5d
EI		 729 return ctrl;
730 err:
731 qemu_free(ctrl->channels);
732 qemu_free(ctrl);
733 return NULL;
734}
Qemu copy for testing