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a3ea5df5 EI |
1 | /* |
2 | * QEMU ETRAX Ethernet Controller. | |
3 | * | |
4 | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <stdio.h> | |
26 | #include "hw.h" | |
27 | #include "net.h" | |
28 | ||
29 | #include "etraxfs_dma.h" | |
30 | ||
31 | #define D(x) | |
32 | ||
c6488268 EI |
33 | /* Advertisement control register. */ |
34 | #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ | |
35 | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ | |
36 | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ | |
37 | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ | |
38 | ||
2e56350e EI |
39 | /* |
40 | * The MDIO extensions in the TDK PHY model were reversed engineered from the | |
41 | * linux driver (PHYID and Diagnostics reg). | |
42 | * TODO: Add friendly names for the register nums. | |
43 | */ | |
a3ea5df5 EI |
44 | struct qemu_phy |
45 | { | |
46 | uint32_t regs[32]; | |
47 | ||
94410b78 EI |
48 | int link; |
49 | ||
a3ea5df5 | 50 | unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
2e56350e EI |
51 | void (*write)(struct qemu_phy *phy, unsigned int req, |
52 | unsigned int data); | |
a3ea5df5 EI |
53 | }; |
54 | ||
55 | static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) | |
56 | { | |
57 | int regnum; | |
58 | unsigned r = 0; | |
59 | ||
60 | regnum = req & 0x1f; | |
61 | ||
62 | switch (regnum) { | |
63 | case 1: | |
94410b78 EI |
64 | if (!phy->link) |
65 | break; | |
f6953f13 | 66 | /* MR1. */ |
a3ea5df5 EI |
67 | /* Speeds and modes. */ |
68 | r |= (1 << 13) | (1 << 14); | |
69 | r |= (1 << 11) | (1 << 12); | |
70 | r |= (1 << 5); /* Autoneg complete. */ | |
f6953f13 | 71 | r |= (1 << 3); /* Autoneg able. */ |
94410b78 | 72 | r |= (1 << 2); /* link. */ |
a3ea5df5 | 73 | break; |
2e56350e EI |
74 | case 5: |
75 | /* Link partner ability. | |
76 | We are kind; always agree with whatever best mode | |
77 | the guest advertises. */ | |
78 | r = 1 << 14; /* Success. */ | |
79 | /* Copy advertised modes. */ | |
80 | r |= phy->regs[4] & (15 << 5); | |
81 | /* Autoneg support. */ | |
82 | r |= 1; | |
83 | break; | |
84 | case 18: | |
85 | { | |
86 | /* Diagnostics reg. */ | |
87 | int duplex = 0; | |
88 | int speed_100 = 0; | |
89 | ||
94410b78 EI |
90 | if (!phy->link) |
91 | break; | |
92 | ||
2e56350e | 93 | /* Are we advertising 100 half or 100 duplex ? */ |
c6488268 EI |
94 | speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); |
95 | speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); | |
96 | ||
2e56350e | 97 | /* Are we advertising 10 duplex or 100 duplex ? */ |
c6488268 EI |
98 | duplex = !!(phy->regs[4] & ADVERTISE_100FULL); |
99 | duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); | |
2e56350e EI |
100 | r = (speed_100 << 10) | (duplex << 11); |
101 | } | |
102 | break; | |
103 | ||
a3ea5df5 EI |
104 | default: |
105 | r = phy->regs[regnum]; | |
106 | break; | |
107 | } | |
2e56350e | 108 | D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum)); |
a3ea5df5 EI |
109 | return r; |
110 | } | |
111 | ||
112 | static void | |
113 | tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) | |
114 | { | |
115 | int regnum; | |
116 | ||
117 | regnum = req & 0x1f; | |
118 | D(printf("%s reg[%d] = %x\n", __func__, regnum, data)); | |
119 | switch (regnum) { | |
120 | default: | |
121 | phy->regs[regnum] = data; | |
122 | break; | |
123 | } | |
124 | } | |
125 | ||
126 | static void | |
127 | tdk_init(struct qemu_phy *phy) | |
128 | { | |
2e56350e EI |
129 | phy->regs[0] = 0x3100; |
130 | /* PHY Id. */ | |
131 | phy->regs[2] = 0x0300; | |
132 | phy->regs[3] = 0xe400; | |
133 | /* Autonegotiation advertisement reg. */ | |
134 | phy->regs[4] = 0x01E1; | |
94410b78 | 135 | phy->link = 1; |
2e56350e | 136 | |
a3ea5df5 EI |
137 | phy->read = tdk_read; |
138 | phy->write = tdk_write; | |
139 | } | |
140 | ||
141 | struct qemu_mdio | |
142 | { | |
f6953f13 | 143 | /* bus. */ |
a3ea5df5 EI |
144 | int mdc; |
145 | int mdio; | |
146 | ||
147 | /* decoder. */ | |
148 | enum { | |
149 | PREAMBLE, | |
150 | SOF, | |
151 | OPC, | |
152 | ADDR, | |
153 | REQ, | |
154 | TURNAROUND, | |
155 | DATA | |
156 | } state; | |
157 | unsigned int drive; | |
158 | ||
159 | unsigned int cnt; | |
160 | unsigned int addr; | |
161 | unsigned int opc; | |
162 | unsigned int req; | |
163 | unsigned int data; | |
164 | ||
165 | struct qemu_phy *devs[32]; | |
166 | }; | |
167 | ||
168 | static void | |
169 | mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) | |
170 | { | |
171 | bus->devs[addr & 0x1f] = phy; | |
172 | } | |
173 | ||
d297f464 | 174 | #ifdef USE_THIS_DEAD_CODE |
a3ea5df5 EI |
175 | static void |
176 | mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) | |
177 | { | |
178 | bus->devs[addr & 0x1f] = NULL; | |
179 | } | |
d297f464 | 180 | #endif |
a3ea5df5 EI |
181 | |
182 | static void mdio_read_req(struct qemu_mdio *bus) | |
183 | { | |
184 | struct qemu_phy *phy; | |
185 | ||
186 | phy = bus->devs[bus->addr]; | |
187 | if (phy && phy->read) | |
188 | bus->data = phy->read(phy, bus->req); | |
189 | else | |
190 | bus->data = 0xffff; | |
191 | } | |
192 | ||
193 | static void mdio_write_req(struct qemu_mdio *bus) | |
194 | { | |
195 | struct qemu_phy *phy; | |
196 | ||
197 | phy = bus->devs[bus->addr]; | |
198 | if (phy && phy->write) | |
199 | phy->write(phy, bus->req, bus->data); | |
200 | } | |
201 | ||
202 | static void mdio_cycle(struct qemu_mdio *bus) | |
203 | { | |
204 | bus->cnt++; | |
205 | ||
206 | D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n", | |
207 | bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); | |
208 | #if 0 | |
209 | if (bus->mdc) | |
210 | printf("%d", bus->mdio); | |
211 | #endif | |
212 | switch (bus->state) | |
213 | { | |
214 | case PREAMBLE: | |
215 | if (bus->mdc) { | |
216 | if (bus->cnt >= (32 * 2) && !bus->mdio) { | |
217 | bus->cnt = 0; | |
218 | bus->state = SOF; | |
219 | bus->data = 0; | |
220 | } | |
221 | } | |
222 | break; | |
223 | case SOF: | |
224 | if (bus->mdc) { | |
225 | if (bus->mdio != 1) | |
226 | printf("WARNING: no SOF\n"); | |
227 | if (bus->cnt == 1*2) { | |
228 | bus->cnt = 0; | |
229 | bus->opc = 0; | |
230 | bus->state = OPC; | |
231 | } | |
232 | } | |
233 | break; | |
234 | case OPC: | |
235 | if (bus->mdc) { | |
236 | bus->opc <<= 1; | |
237 | bus->opc |= bus->mdio & 1; | |
238 | if (bus->cnt == 2*2) { | |
239 | bus->cnt = 0; | |
240 | bus->addr = 0; | |
241 | bus->state = ADDR; | |
242 | } | |
243 | } | |
244 | break; | |
245 | case ADDR: | |
246 | if (bus->mdc) { | |
247 | bus->addr <<= 1; | |
248 | bus->addr |= bus->mdio & 1; | |
249 | ||
250 | if (bus->cnt == 5*2) { | |
251 | bus->cnt = 0; | |
252 | bus->req = 0; | |
253 | bus->state = REQ; | |
254 | } | |
255 | } | |
256 | break; | |
257 | case REQ: | |
258 | if (bus->mdc) { | |
259 | bus->req <<= 1; | |
260 | bus->req |= bus->mdio & 1; | |
261 | if (bus->cnt == 5*2) { | |
262 | bus->cnt = 0; | |
263 | bus->state = TURNAROUND; | |
264 | } | |
265 | } | |
266 | break; | |
267 | case TURNAROUND: | |
268 | if (bus->mdc && bus->cnt == 2*2) { | |
269 | bus->mdio = 0; | |
270 | bus->cnt = 0; | |
271 | ||
272 | if (bus->opc == 2) { | |
273 | bus->drive = 1; | |
274 | mdio_read_req(bus); | |
275 | bus->mdio = bus->data & 1; | |
276 | } | |
277 | bus->state = DATA; | |
278 | } | |
279 | break; | |
280 | case DATA: | |
281 | if (!bus->mdc) { | |
282 | if (bus->drive) { | |
2e56350e EI |
283 | bus->mdio = !!(bus->data & (1 << 15)); |
284 | bus->data <<= 1; | |
a3ea5df5 EI |
285 | } |
286 | } else { | |
287 | if (!bus->drive) { | |
288 | bus->data <<= 1; | |
289 | bus->data |= bus->mdio; | |
290 | } | |
291 | if (bus->cnt == 16 * 2) { | |
292 | bus->cnt = 0; | |
293 | bus->state = PREAMBLE; | |
2e56350e EI |
294 | if (!bus->drive) |
295 | mdio_write_req(bus); | |
296 | bus->drive = 0; | |
a3ea5df5 EI |
297 | } |
298 | } | |
299 | break; | |
300 | default: | |
301 | break; | |
302 | } | |
303 | } | |
304 | ||
2e56350e EI |
305 | /* ETRAX-FS Ethernet MAC block starts here. */ |
306 | ||
f6953f13 | 307 | #define RW_MA0_LO 0x00 |
35ef81d6 EI |
308 | #define RW_MA0_HI 0x01 |
309 | #define RW_MA1_LO 0x02 | |
310 | #define RW_MA1_HI 0x03 | |
311 | #define RW_GA_LO 0x04 | |
312 | #define RW_GA_HI 0x05 | |
313 | #define RW_GEN_CTRL 0x06 | |
314 | #define RW_REC_CTRL 0x07 | |
315 | #define RW_TR_CTRL 0x08 | |
316 | #define RW_CLR_ERR 0x09 | |
317 | #define RW_MGM_CTRL 0x0a | |
318 | #define R_STAT 0x0b | |
319 | #define FS_ETH_MAX_REGS 0x17 | |
a3ea5df5 EI |
320 | |
321 | struct fs_eth | |
322 | { | |
f6953f13 | 323 | CPUState *env; |
a3ea5df5 | 324 | qemu_irq *irq; |
a3ea5df5 | 325 | VLANClientState *vc; |
a3ea5df5 EI |
326 | int ethregs; |
327 | ||
f6953f13 EI |
328 | /* Two addrs in the filter. */ |
329 | uint8_t macaddr[2][6]; | |
a3ea5df5 EI |
330 | uint32_t regs[FS_ETH_MAX_REGS]; |
331 | ||
a3ea5df5 EI |
332 | struct etraxfs_dma_client *dma_out; |
333 | struct etraxfs_dma_client *dma_in; | |
334 | ||
335 | /* MDIO bus. */ | |
336 | struct qemu_mdio mdio_bus; | |
c6488268 EI |
337 | unsigned int phyaddr; |
338 | int duplex_mismatch; | |
339 | ||
f6953f13 | 340 | /* PHY. */ |
a3ea5df5 EI |
341 | struct qemu_phy phy; |
342 | }; | |
343 | ||
c6488268 EI |
344 | static void eth_validate_duplex(struct fs_eth *eth) |
345 | { | |
346 | struct qemu_phy *phy; | |
347 | unsigned int phy_duplex; | |
348 | unsigned int mac_duplex; | |
349 | int new_mm = 0; | |
350 | ||
351 | phy = eth->mdio_bus.devs[eth->phyaddr]; | |
352 | phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); | |
353 | mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128); | |
354 | ||
355 | if (mac_duplex != phy_duplex) | |
356 | new_mm = 1; | |
357 | ||
358 | if (eth->regs[RW_GEN_CTRL] & 1) { | |
359 | if (new_mm != eth->duplex_mismatch) { | |
360 | if (new_mm) | |
361 | printf("HW: WARNING " | |
362 | "ETH duplex mismatch MAC=%d PHY=%d\n", | |
363 | mac_duplex, phy_duplex); | |
364 | else | |
365 | printf("HW: ETH duplex ok.\n"); | |
366 | } | |
367 | eth->duplex_mismatch = new_mm; | |
368 | } | |
369 | } | |
370 | ||
a3ea5df5 EI |
371 | static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
372 | { | |
f6953f13 | 373 | struct fs_eth *eth = opaque; |
f6953f13 | 374 | uint32_t r = 0; |
a3ea5df5 | 375 | |
35ef81d6 EI |
376 | addr >>= 2; |
377 | ||
f6953f13 | 378 | switch (addr) { |
a3ea5df5 | 379 | case R_STAT: |
a3ea5df5 EI |
380 | r = eth->mdio_bus.mdio & 1; |
381 | break; | |
f6953f13 | 382 | default: |
a3ea5df5 | 383 | r = eth->regs[addr]; |
35ef81d6 | 384 | D(printf ("%s %x\n", __func__, addr * 4)); |
f6953f13 EI |
385 | break; |
386 | } | |
387 | return r; | |
a3ea5df5 EI |
388 | } |
389 | ||
f6953f13 EI |
390 | static void eth_update_ma(struct fs_eth *eth, int ma) |
391 | { | |
392 | int reg; | |
393 | int i = 0; | |
394 | ||
395 | ma &= 1; | |
396 | ||
397 | reg = RW_MA0_LO; | |
398 | if (ma) | |
399 | reg = RW_MA1_LO; | |
400 | ||
401 | eth->macaddr[ma][i++] = eth->regs[reg]; | |
402 | eth->macaddr[ma][i++] = eth->regs[reg] >> 8; | |
403 | eth->macaddr[ma][i++] = eth->regs[reg] >> 16; | |
404 | eth->macaddr[ma][i++] = eth->regs[reg] >> 24; | |
405 | eth->macaddr[ma][i++] = eth->regs[reg + 4]; | |
406 | eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; | |
407 | ||
408 | D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma, | |
409 | eth->macaddr[ma][0], eth->macaddr[ma][1], | |
410 | eth->macaddr[ma][2], eth->macaddr[ma][3], | |
411 | eth->macaddr[ma][4], eth->macaddr[ma][5])); | |
a3ea5df5 EI |
412 | } |
413 | ||
414 | static void | |
415 | eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
416 | { | |
f6953f13 | 417 | struct fs_eth *eth = opaque; |
f6953f13 | 418 | |
35ef81d6 | 419 | addr >>= 2; |
f6953f13 EI |
420 | switch (addr) |
421 | { | |
422 | case RW_MA0_LO: | |
f6953f13 EI |
423 | case RW_MA0_HI: |
424 | eth->regs[addr] = value; | |
425 | eth_update_ma(eth, 0); | |
426 | break; | |
427 | case RW_MA1_LO: | |
f6953f13 EI |
428 | case RW_MA1_HI: |
429 | eth->regs[addr] = value; | |
430 | eth_update_ma(eth, 1); | |
431 | break; | |
a3ea5df5 | 432 | |
a3ea5df5 EI |
433 | case RW_MGM_CTRL: |
434 | /* Attach an MDIO/PHY abstraction. */ | |
435 | if (value & 2) | |
436 | eth->mdio_bus.mdio = value & 1; | |
c6488268 | 437 | if (eth->mdio_bus.mdc != (value & 4)) { |
a3ea5df5 | 438 | mdio_cycle(ð->mdio_bus); |
c6488268 EI |
439 | eth_validate_duplex(eth); |
440 | } | |
a3ea5df5 EI |
441 | eth->mdio_bus.mdc = !!(value & 4); |
442 | break; | |
443 | ||
c6488268 EI |
444 | case RW_REC_CTRL: |
445 | eth->regs[addr] = value; | |
446 | eth_validate_duplex(eth); | |
447 | break; | |
448 | ||
f6953f13 EI |
449 | default: |
450 | eth->regs[addr] = value; | |
9bcd77d6 EI |
451 | D(printf ("%s %x %x\n", |
452 | __func__, addr, value)); | |
f6953f13 EI |
453 | break; |
454 | } | |
455 | } | |
456 | ||
457 | /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom | |
458 | filter dropping group addresses we have not joined. The filter has 64 | |
459 | bits (m). The has function is a simple nible xor of the group addr. */ | |
460 | static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) | |
461 | { | |
462 | unsigned int hsh; | |
463 | int m_individual = eth->regs[RW_REC_CTRL] & 4; | |
464 | int match; | |
465 | ||
466 | /* First bit on the wire of a MAC address signals multicast or | |
467 | physical address. */ | |
468 | if (!m_individual && !sa[0] & 1) | |
469 | return 0; | |
470 | ||
471 | /* Calculate the hash index for the GA registers. */ | |
472 | hsh = 0; | |
473 | hsh ^= (*sa) & 0x3f; | |
474 | hsh ^= ((*sa) >> 6) & 0x03; | |
475 | ++sa; | |
476 | hsh ^= ((*sa) << 2) & 0x03c; | |
477 | hsh ^= ((*sa) >> 4) & 0xf; | |
478 | ++sa; | |
479 | hsh ^= ((*sa) << 4) & 0x30; | |
480 | hsh ^= ((*sa) >> 2) & 0x3f; | |
481 | ++sa; | |
482 | hsh ^= (*sa) & 0x3f; | |
483 | hsh ^= ((*sa) >> 6) & 0x03; | |
484 | ++sa; | |
485 | hsh ^= ((*sa) << 2) & 0x03c; | |
486 | hsh ^= ((*sa) >> 4) & 0xf; | |
487 | ++sa; | |
488 | hsh ^= ((*sa) << 4) & 0x30; | |
489 | hsh ^= ((*sa) >> 2) & 0x3f; | |
490 | ||
491 | hsh &= 63; | |
492 | if (hsh > 31) | |
493 | match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); | |
494 | else | |
495 | match = eth->regs[RW_GA_LO] & (1 << hsh); | |
496 | D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh, | |
497 | eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); | |
498 | return match; | |
a3ea5df5 EI |
499 | } |
500 | ||
501 | static int eth_can_receive(void *opaque) | |
502 | { | |
aa25cf46 | 503 | return 1; |
a3ea5df5 EI |
504 | } |
505 | ||
506 | static void eth_receive(void *opaque, const uint8_t *buf, int size) | |
507 | { | |
f6953f13 | 508 | unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
a3ea5df5 | 509 | struct fs_eth *eth = opaque; |
f6953f13 EI |
510 | int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
511 | int use_ma1 = eth->regs[RW_REC_CTRL] & 2; | |
512 | int r_bcast = eth->regs[RW_REC_CTRL] & 8; | |
513 | ||
514 | if (size < 12) | |
515 | return; | |
516 | ||
517 | D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n", | |
518 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], | |
519 | use_ma0, use_ma1, r_bcast)); | |
520 | ||
521 | /* Does the frame get through the address filters? */ | |
522 | if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) | |
523 | && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) | |
524 | && (!r_bcast || memcmp(buf, sa_bcast, 6)) | |
525 | && !eth_match_groupaddr(eth, buf)) | |
526 | return; | |
527 | ||
aa25cf46 EI |
528 | /* FIXME: Find another way to pass on the fake csum. */ |
529 | etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1); | |
a3ea5df5 EI |
530 | } |
531 | ||
532 | static int eth_tx_push(void *opaque, unsigned char *buf, int len) | |
533 | { | |
534 | struct fs_eth *eth = opaque; | |
535 | ||
536 | D(printf("%s buf=%p len=%d\n", __func__, buf, len)); | |
537 | qemu_send_packet(eth->vc, buf, len); | |
538 | return len; | |
539 | } | |
540 | ||
94410b78 EI |
541 | static void eth_set_link(VLANClientState *vc) |
542 | { | |
543 | struct fs_eth *eth = vc->opaque; | |
544 | D(printf("%s %d\n", __func__, vc->link_down)); | |
545 | eth->phy.link = !vc->link_down; | |
546 | } | |
547 | ||
a3ea5df5 | 548 | static CPUReadMemoryFunc *eth_read[] = { |
35ef81d6 | 549 | NULL, NULL, |
2e56350e | 550 | ð_readl, |
a3ea5df5 EI |
551 | }; |
552 | ||
553 | static CPUWriteMemoryFunc *eth_write[] = { | |
35ef81d6 | 554 | NULL, NULL, |
2e56350e | 555 | ð_writel, |
a3ea5df5 EI |
556 | }; |
557 | ||
558 | void *etraxfs_eth_init(NICInfo *nd, CPUState *env, | |
94410b78 | 559 | qemu_irq *irq, target_phys_addr_t base, int phyaddr) |
a3ea5df5 EI |
560 | { |
561 | struct etraxfs_dma_client *dma = NULL; | |
562 | struct fs_eth *eth = NULL; | |
563 | ||
0ae18cee AL |
564 | qemu_check_nic_model(nd, "fseth"); |
565 | ||
a3ea5df5 | 566 | dma = qemu_mallocz(sizeof *dma * 2); |
a3ea5df5 EI |
567 | |
568 | eth = qemu_mallocz(sizeof *eth); | |
a3ea5df5 EI |
569 | |
570 | dma[0].client.push = eth_tx_push; | |
571 | dma[0].client.opaque = eth; | |
572 | dma[1].client.opaque = eth; | |
aa25cf46 | 573 | dma[1].client.pull = NULL; |
a3ea5df5 EI |
574 | |
575 | eth->env = env; | |
a3ea5df5 EI |
576 | eth->irq = irq; |
577 | eth->dma_out = dma; | |
578 | eth->dma_in = dma + 1; | |
a3ea5df5 EI |
579 | |
580 | /* Connect the phy. */ | |
94410b78 | 581 | eth->phyaddr = phyaddr & 0x1f; |
a3ea5df5 | 582 | tdk_init(ð->phy); |
c6488268 | 583 | mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr); |
a3ea5df5 EI |
584 | |
585 | eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth); | |
586 | cpu_register_physical_memory (base, 0x5c, eth->ethregs); | |
587 | ||
7a9f6e4a | 588 | eth->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
a3ea5df5 | 589 | eth_receive, eth_can_receive, eth); |
94410b78 EI |
590 | eth->vc->opaque = eth; |
591 | eth->vc->link_status_changed = eth_set_link; | |
a3ea5df5 EI |
592 | |
593 | return dma; | |
a3ea5df5 | 594 | } |