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a3ea5df5 EI |
1 | /* |
2 | * QEMU ETRAX Ethernet Controller. | |
3 | * | |
4 | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <stdio.h> | |
26 | #include "hw.h" | |
27 | #include "net.h" | |
28 | ||
29 | #include "etraxfs_dma.h" | |
30 | ||
31 | #define D(x) | |
32 | ||
2e56350e EI |
33 | /* |
34 | * The MDIO extensions in the TDK PHY model were reversed engineered from the | |
35 | * linux driver (PHYID and Diagnostics reg). | |
36 | * TODO: Add friendly names for the register nums. | |
37 | */ | |
a3ea5df5 EI |
38 | struct qemu_phy |
39 | { | |
40 | uint32_t regs[32]; | |
41 | ||
42 | unsigned int (*read)(struct qemu_phy *phy, unsigned int req); | |
2e56350e EI |
43 | void (*write)(struct qemu_phy *phy, unsigned int req, |
44 | unsigned int data); | |
a3ea5df5 EI |
45 | }; |
46 | ||
47 | static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) | |
48 | { | |
49 | int regnum; | |
50 | unsigned r = 0; | |
51 | ||
52 | regnum = req & 0x1f; | |
53 | ||
54 | switch (regnum) { | |
55 | case 1: | |
f6953f13 | 56 | /* MR1. */ |
a3ea5df5 EI |
57 | /* Speeds and modes. */ |
58 | r |= (1 << 13) | (1 << 14); | |
59 | r |= (1 << 11) | (1 << 12); | |
60 | r |= (1 << 5); /* Autoneg complete. */ | |
f6953f13 EI |
61 | r |= (1 << 3); /* Autoneg able. */ |
62 | r |= (1 << 2); /* Link. */ | |
a3ea5df5 | 63 | break; |
2e56350e EI |
64 | case 5: |
65 | /* Link partner ability. | |
66 | We are kind; always agree with whatever best mode | |
67 | the guest advertises. */ | |
68 | r = 1 << 14; /* Success. */ | |
69 | /* Copy advertised modes. */ | |
70 | r |= phy->regs[4] & (15 << 5); | |
71 | /* Autoneg support. */ | |
72 | r |= 1; | |
73 | break; | |
74 | case 18: | |
75 | { | |
76 | /* Diagnostics reg. */ | |
77 | int duplex = 0; | |
78 | int speed_100 = 0; | |
79 | ||
80 | /* Are we advertising 100 half or 100 duplex ? */ | |
81 | speed_100 = !!(phy->regs[4] & 0x180); | |
82 | /* Are we advertising 10 duplex or 100 duplex ? */ | |
83 | duplex = !!(phy->regs[4] & 0x180); | |
84 | r = (speed_100 << 10) | (duplex << 11); | |
85 | } | |
86 | break; | |
87 | ||
a3ea5df5 EI |
88 | default: |
89 | r = phy->regs[regnum]; | |
90 | break; | |
91 | } | |
2e56350e | 92 | D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum)); |
a3ea5df5 EI |
93 | return r; |
94 | } | |
95 | ||
96 | static void | |
97 | tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) | |
98 | { | |
99 | int regnum; | |
100 | ||
101 | regnum = req & 0x1f; | |
102 | D(printf("%s reg[%d] = %x\n", __func__, regnum, data)); | |
103 | switch (regnum) { | |
104 | default: | |
105 | phy->regs[regnum] = data; | |
106 | break; | |
107 | } | |
108 | } | |
109 | ||
110 | static void | |
111 | tdk_init(struct qemu_phy *phy) | |
112 | { | |
2e56350e EI |
113 | phy->regs[0] = 0x3100; |
114 | /* PHY Id. */ | |
115 | phy->regs[2] = 0x0300; | |
116 | phy->regs[3] = 0xe400; | |
117 | /* Autonegotiation advertisement reg. */ | |
118 | phy->regs[4] = 0x01E1; | |
119 | ||
a3ea5df5 EI |
120 | phy->read = tdk_read; |
121 | phy->write = tdk_write; | |
122 | } | |
123 | ||
124 | struct qemu_mdio | |
125 | { | |
f6953f13 | 126 | /* bus. */ |
a3ea5df5 EI |
127 | int mdc; |
128 | int mdio; | |
129 | ||
130 | /* decoder. */ | |
131 | enum { | |
132 | PREAMBLE, | |
133 | SOF, | |
134 | OPC, | |
135 | ADDR, | |
136 | REQ, | |
137 | TURNAROUND, | |
138 | DATA | |
139 | } state; | |
140 | unsigned int drive; | |
141 | ||
142 | unsigned int cnt; | |
143 | unsigned int addr; | |
144 | unsigned int opc; | |
145 | unsigned int req; | |
146 | unsigned int data; | |
147 | ||
148 | struct qemu_phy *devs[32]; | |
149 | }; | |
150 | ||
151 | static void | |
152 | mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) | |
153 | { | |
154 | bus->devs[addr & 0x1f] = phy; | |
155 | } | |
156 | ||
d297f464 | 157 | #ifdef USE_THIS_DEAD_CODE |
a3ea5df5 EI |
158 | static void |
159 | mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) | |
160 | { | |
161 | bus->devs[addr & 0x1f] = NULL; | |
162 | } | |
d297f464 | 163 | #endif |
a3ea5df5 EI |
164 | |
165 | static void mdio_read_req(struct qemu_mdio *bus) | |
166 | { | |
167 | struct qemu_phy *phy; | |
168 | ||
169 | phy = bus->devs[bus->addr]; | |
170 | if (phy && phy->read) | |
171 | bus->data = phy->read(phy, bus->req); | |
172 | else | |
173 | bus->data = 0xffff; | |
174 | } | |
175 | ||
176 | static void mdio_write_req(struct qemu_mdio *bus) | |
177 | { | |
178 | struct qemu_phy *phy; | |
179 | ||
180 | phy = bus->devs[bus->addr]; | |
181 | if (phy && phy->write) | |
182 | phy->write(phy, bus->req, bus->data); | |
183 | } | |
184 | ||
185 | static void mdio_cycle(struct qemu_mdio *bus) | |
186 | { | |
187 | bus->cnt++; | |
188 | ||
189 | D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n", | |
190 | bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); | |
191 | #if 0 | |
192 | if (bus->mdc) | |
193 | printf("%d", bus->mdio); | |
194 | #endif | |
195 | switch (bus->state) | |
196 | { | |
197 | case PREAMBLE: | |
198 | if (bus->mdc) { | |
199 | if (bus->cnt >= (32 * 2) && !bus->mdio) { | |
200 | bus->cnt = 0; | |
201 | bus->state = SOF; | |
202 | bus->data = 0; | |
203 | } | |
204 | } | |
205 | break; | |
206 | case SOF: | |
207 | if (bus->mdc) { | |
208 | if (bus->mdio != 1) | |
209 | printf("WARNING: no SOF\n"); | |
210 | if (bus->cnt == 1*2) { | |
211 | bus->cnt = 0; | |
212 | bus->opc = 0; | |
213 | bus->state = OPC; | |
214 | } | |
215 | } | |
216 | break; | |
217 | case OPC: | |
218 | if (bus->mdc) { | |
219 | bus->opc <<= 1; | |
220 | bus->opc |= bus->mdio & 1; | |
221 | if (bus->cnt == 2*2) { | |
222 | bus->cnt = 0; | |
223 | bus->addr = 0; | |
224 | bus->state = ADDR; | |
225 | } | |
226 | } | |
227 | break; | |
228 | case ADDR: | |
229 | if (bus->mdc) { | |
230 | bus->addr <<= 1; | |
231 | bus->addr |= bus->mdio & 1; | |
232 | ||
233 | if (bus->cnt == 5*2) { | |
234 | bus->cnt = 0; | |
235 | bus->req = 0; | |
236 | bus->state = REQ; | |
237 | } | |
238 | } | |
239 | break; | |
240 | case REQ: | |
241 | if (bus->mdc) { | |
242 | bus->req <<= 1; | |
243 | bus->req |= bus->mdio & 1; | |
244 | if (bus->cnt == 5*2) { | |
245 | bus->cnt = 0; | |
246 | bus->state = TURNAROUND; | |
247 | } | |
248 | } | |
249 | break; | |
250 | case TURNAROUND: | |
251 | if (bus->mdc && bus->cnt == 2*2) { | |
252 | bus->mdio = 0; | |
253 | bus->cnt = 0; | |
254 | ||
255 | if (bus->opc == 2) { | |
256 | bus->drive = 1; | |
257 | mdio_read_req(bus); | |
258 | bus->mdio = bus->data & 1; | |
259 | } | |
260 | bus->state = DATA; | |
261 | } | |
262 | break; | |
263 | case DATA: | |
264 | if (!bus->mdc) { | |
265 | if (bus->drive) { | |
2e56350e EI |
266 | bus->mdio = !!(bus->data & (1 << 15)); |
267 | bus->data <<= 1; | |
a3ea5df5 EI |
268 | } |
269 | } else { | |
270 | if (!bus->drive) { | |
271 | bus->data <<= 1; | |
272 | bus->data |= bus->mdio; | |
273 | } | |
274 | if (bus->cnt == 16 * 2) { | |
275 | bus->cnt = 0; | |
276 | bus->state = PREAMBLE; | |
2e56350e EI |
277 | if (!bus->drive) |
278 | mdio_write_req(bus); | |
279 | bus->drive = 0; | |
a3ea5df5 EI |
280 | } |
281 | } | |
282 | break; | |
283 | default: | |
284 | break; | |
285 | } | |
286 | } | |
287 | ||
2e56350e EI |
288 | /* ETRAX-FS Ethernet MAC block starts here. */ |
289 | ||
f6953f13 EI |
290 | #define RW_MA0_LO 0x00 |
291 | #define RW_MA0_HI 0x04 | |
292 | #define RW_MA1_LO 0x08 | |
293 | #define RW_MA1_HI 0x0c | |
294 | #define RW_GA_LO 0x10 | |
295 | #define RW_GA_HI 0x14 | |
296 | #define RW_GEN_CTRL 0x18 | |
297 | #define RW_REC_CTRL 0x1c | |
298 | #define RW_TR_CTRL 0x20 | |
299 | #define RW_CLR_ERR 0x24 | |
300 | #define RW_MGM_CTRL 0x28 | |
301 | #define R_STAT 0x2c | |
302 | #define FS_ETH_MAX_REGS 0x5c | |
a3ea5df5 EI |
303 | |
304 | struct fs_eth | |
305 | { | |
f6953f13 | 306 | CPUState *env; |
a3ea5df5 | 307 | qemu_irq *irq; |
f6953f13 | 308 | target_phys_addr_t base; |
a3ea5df5 | 309 | VLANClientState *vc; |
a3ea5df5 EI |
310 | int ethregs; |
311 | ||
f6953f13 EI |
312 | /* Two addrs in the filter. */ |
313 | uint8_t macaddr[2][6]; | |
a3ea5df5 EI |
314 | uint32_t regs[FS_ETH_MAX_REGS]; |
315 | ||
316 | unsigned char rx_fifo[1536]; | |
317 | int rx_fifo_len; | |
318 | int rx_fifo_pos; | |
319 | ||
320 | struct etraxfs_dma_client *dma_out; | |
321 | struct etraxfs_dma_client *dma_in; | |
322 | ||
323 | /* MDIO bus. */ | |
324 | struct qemu_mdio mdio_bus; | |
f6953f13 | 325 | /* PHY. */ |
a3ea5df5 EI |
326 | struct qemu_phy phy; |
327 | }; | |
328 | ||
329 | static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr) | |
330 | { | |
f6953f13 EI |
331 | struct fs_eth *eth = opaque; |
332 | CPUState *env = eth->env; | |
d297f464 EI |
333 | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx |
334 | " pc=%x.\n", addr, env->pc); | |
f6953f13 | 335 | return 0; |
a3ea5df5 EI |
336 | } |
337 | ||
338 | static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) | |
339 | { | |
f6953f13 EI |
340 | struct fs_eth *eth = opaque; |
341 | D(CPUState *env = eth->env); | |
342 | uint32_t r = 0; | |
a3ea5df5 | 343 | |
f6953f13 EI |
344 | /* Make addr relative to this instances base. */ |
345 | addr -= eth->base; | |
346 | switch (addr) { | |
a3ea5df5 EI |
347 | case R_STAT: |
348 | /* Attach an MDIO/PHY abstraction. */ | |
349 | r = eth->mdio_bus.mdio & 1; | |
350 | break; | |
f6953f13 | 351 | default: |
a3ea5df5 | 352 | r = eth->regs[addr]; |
f6953f13 EI |
353 | D(printf ("%s %x p=%x\n", __func__, addr, env->pc)); |
354 | break; | |
355 | } | |
356 | return r; | |
a3ea5df5 EI |
357 | } |
358 | ||
359 | static void | |
360 | eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) | |
361 | { | |
f6953f13 EI |
362 | struct fs_eth *eth = opaque; |
363 | CPUState *env = eth->env; | |
d297f464 EI |
364 | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx |
365 | " pc=%x.\n", addr, env->pc); | |
f6953f13 EI |
366 | } |
367 | ||
368 | static void eth_update_ma(struct fs_eth *eth, int ma) | |
369 | { | |
370 | int reg; | |
371 | int i = 0; | |
372 | ||
373 | ma &= 1; | |
374 | ||
375 | reg = RW_MA0_LO; | |
376 | if (ma) | |
377 | reg = RW_MA1_LO; | |
378 | ||
379 | eth->macaddr[ma][i++] = eth->regs[reg]; | |
380 | eth->macaddr[ma][i++] = eth->regs[reg] >> 8; | |
381 | eth->macaddr[ma][i++] = eth->regs[reg] >> 16; | |
382 | eth->macaddr[ma][i++] = eth->regs[reg] >> 24; | |
383 | eth->macaddr[ma][i++] = eth->regs[reg + 4]; | |
384 | eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; | |
385 | ||
386 | D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma, | |
387 | eth->macaddr[ma][0], eth->macaddr[ma][1], | |
388 | eth->macaddr[ma][2], eth->macaddr[ma][3], | |
389 | eth->macaddr[ma][4], eth->macaddr[ma][5])); | |
a3ea5df5 EI |
390 | } |
391 | ||
392 | static void | |
393 | eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
394 | { | |
f6953f13 | 395 | struct fs_eth *eth = opaque; |
f6953f13 EI |
396 | |
397 | /* Make addr relative to this instances base. */ | |
398 | addr -= eth->base; | |
399 | switch (addr) | |
400 | { | |
401 | case RW_MA0_LO: | |
402 | eth->regs[addr] = value; | |
403 | eth_update_ma(eth, 0); | |
404 | break; | |
405 | case RW_MA0_HI: | |
406 | eth->regs[addr] = value; | |
407 | eth_update_ma(eth, 0); | |
408 | break; | |
409 | case RW_MA1_LO: | |
410 | eth->regs[addr] = value; | |
411 | eth_update_ma(eth, 1); | |
412 | break; | |
413 | case RW_MA1_HI: | |
414 | eth->regs[addr] = value; | |
415 | eth_update_ma(eth, 1); | |
416 | break; | |
a3ea5df5 | 417 | |
a3ea5df5 EI |
418 | case RW_MGM_CTRL: |
419 | /* Attach an MDIO/PHY abstraction. */ | |
420 | if (value & 2) | |
421 | eth->mdio_bus.mdio = value & 1; | |
422 | if (eth->mdio_bus.mdc != (value & 4)) | |
423 | mdio_cycle(ð->mdio_bus); | |
424 | eth->mdio_bus.mdc = !!(value & 4); | |
425 | break; | |
426 | ||
f6953f13 EI |
427 | default: |
428 | eth->regs[addr] = value; | |
9bcd77d6 EI |
429 | D(printf ("%s %x %x\n", |
430 | __func__, addr, value)); | |
f6953f13 EI |
431 | break; |
432 | } | |
433 | } | |
434 | ||
435 | /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom | |
436 | filter dropping group addresses we have not joined. The filter has 64 | |
437 | bits (m). The has function is a simple nible xor of the group addr. */ | |
438 | static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) | |
439 | { | |
440 | unsigned int hsh; | |
441 | int m_individual = eth->regs[RW_REC_CTRL] & 4; | |
442 | int match; | |
443 | ||
444 | /* First bit on the wire of a MAC address signals multicast or | |
445 | physical address. */ | |
446 | if (!m_individual && !sa[0] & 1) | |
447 | return 0; | |
448 | ||
449 | /* Calculate the hash index for the GA registers. */ | |
450 | hsh = 0; | |
451 | hsh ^= (*sa) & 0x3f; | |
452 | hsh ^= ((*sa) >> 6) & 0x03; | |
453 | ++sa; | |
454 | hsh ^= ((*sa) << 2) & 0x03c; | |
455 | hsh ^= ((*sa) >> 4) & 0xf; | |
456 | ++sa; | |
457 | hsh ^= ((*sa) << 4) & 0x30; | |
458 | hsh ^= ((*sa) >> 2) & 0x3f; | |
459 | ++sa; | |
460 | hsh ^= (*sa) & 0x3f; | |
461 | hsh ^= ((*sa) >> 6) & 0x03; | |
462 | ++sa; | |
463 | hsh ^= ((*sa) << 2) & 0x03c; | |
464 | hsh ^= ((*sa) >> 4) & 0xf; | |
465 | ++sa; | |
466 | hsh ^= ((*sa) << 4) & 0x30; | |
467 | hsh ^= ((*sa) >> 2) & 0x3f; | |
468 | ||
469 | hsh &= 63; | |
470 | if (hsh > 31) | |
471 | match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); | |
472 | else | |
473 | match = eth->regs[RW_GA_LO] & (1 << hsh); | |
474 | D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh, | |
475 | eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); | |
476 | return match; | |
a3ea5df5 EI |
477 | } |
478 | ||
479 | static int eth_can_receive(void *opaque) | |
480 | { | |
481 | struct fs_eth *eth = opaque; | |
482 | int r; | |
483 | ||
484 | r = eth->rx_fifo_len == 0; | |
485 | if (!r) { | |
486 | /* TODO: signal fifo overrun. */ | |
487 | printf("PACKET LOSS!\n"); | |
488 | } | |
489 | return r; | |
490 | } | |
491 | ||
492 | static void eth_receive(void *opaque, const uint8_t *buf, int size) | |
493 | { | |
f6953f13 | 494 | unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
a3ea5df5 | 495 | struct fs_eth *eth = opaque; |
f6953f13 EI |
496 | int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
497 | int use_ma1 = eth->regs[RW_REC_CTRL] & 2; | |
498 | int r_bcast = eth->regs[RW_REC_CTRL] & 8; | |
499 | ||
500 | if (size < 12) | |
501 | return; | |
502 | ||
503 | D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n", | |
504 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], | |
505 | use_ma0, use_ma1, r_bcast)); | |
506 | ||
507 | /* Does the frame get through the address filters? */ | |
508 | if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) | |
509 | && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) | |
510 | && (!r_bcast || memcmp(buf, sa_bcast, 6)) | |
511 | && !eth_match_groupaddr(eth, buf)) | |
512 | return; | |
513 | ||
a3ea5df5 | 514 | if (size > sizeof(eth->rx_fifo)) { |
f6953f13 EI |
515 | /* TODO: signal error. */ |
516 | } else if (eth->rx_fifo_len) { | |
517 | /* FIFO overrun. */ | |
a3ea5df5 EI |
518 | } else { |
519 | memcpy(eth->rx_fifo, buf, size); | |
f6953f13 | 520 | /* +4, HW passes the CRC to sw. */ |
a3ea5df5 EI |
521 | eth->rx_fifo_len = size + 4; |
522 | eth->rx_fifo_pos = 0; | |
523 | } | |
524 | } | |
525 | ||
526 | static void eth_rx_pull(void *opaque) | |
527 | { | |
528 | struct fs_eth *eth = opaque; | |
529 | int len; | |
530 | if (eth->rx_fifo_len) { | |
531 | D(printf("%s %d\n", __func__, eth->rx_fifo_len)); | |
532 | #if 0 | |
533 | { | |
534 | int i; | |
535 | for (i = 0; i < 32; i++) | |
536 | printf("%2.2x", eth->rx_fifo[i]); | |
537 | printf("\n"); | |
538 | } | |
539 | #endif | |
540 | len = etraxfs_dmac_input(eth->dma_in, | |
541 | eth->rx_fifo + eth->rx_fifo_pos, | |
542 | eth->rx_fifo_len, 1); | |
543 | eth->rx_fifo_len -= len; | |
544 | eth->rx_fifo_pos += len; | |
545 | } | |
546 | } | |
547 | ||
548 | static int eth_tx_push(void *opaque, unsigned char *buf, int len) | |
549 | { | |
550 | struct fs_eth *eth = opaque; | |
551 | ||
552 | D(printf("%s buf=%p len=%d\n", __func__, buf, len)); | |
553 | qemu_send_packet(eth->vc, buf, len); | |
554 | return len; | |
555 | } | |
556 | ||
557 | static CPUReadMemoryFunc *eth_read[] = { | |
2e56350e EI |
558 | ð_rinvalid, |
559 | ð_rinvalid, | |
560 | ð_readl, | |
a3ea5df5 EI |
561 | }; |
562 | ||
563 | static CPUWriteMemoryFunc *eth_write[] = { | |
2e56350e EI |
564 | ð_winvalid, |
565 | ð_winvalid, | |
566 | ð_writel, | |
a3ea5df5 EI |
567 | }; |
568 | ||
569 | void *etraxfs_eth_init(NICInfo *nd, CPUState *env, | |
570 | qemu_irq *irq, target_phys_addr_t base) | |
571 | { | |
572 | struct etraxfs_dma_client *dma = NULL; | |
573 | struct fs_eth *eth = NULL; | |
574 | ||
575 | dma = qemu_mallocz(sizeof *dma * 2); | |
576 | if (!dma) | |
577 | return NULL; | |
578 | ||
579 | eth = qemu_mallocz(sizeof *eth); | |
580 | if (!eth) | |
581 | goto err; | |
582 | ||
583 | dma[0].client.push = eth_tx_push; | |
584 | dma[0].client.opaque = eth; | |
585 | dma[1].client.opaque = eth; | |
586 | dma[1].client.pull = eth_rx_pull; | |
587 | ||
588 | eth->env = env; | |
589 | eth->base = base; | |
590 | eth->irq = irq; | |
591 | eth->dma_out = dma; | |
592 | eth->dma_in = dma + 1; | |
a3ea5df5 EI |
593 | |
594 | /* Connect the phy. */ | |
595 | tdk_init(ð->phy); | |
596 | mdio_attach(ð->mdio_bus, ð->phy, 0x1); | |
597 | ||
598 | eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth); | |
599 | cpu_register_physical_memory (base, 0x5c, eth->ethregs); | |
600 | ||
601 | eth->vc = qemu_new_vlan_client(nd->vlan, | |
602 | eth_receive, eth_can_receive, eth); | |
603 | ||
604 | return dma; | |
605 | err: | |
606 | qemu_free(eth); | |
607 | qemu_free(dma); | |
608 | return NULL; | |
609 | } |