[qemu.git] / hw / etraxfs_ser.c

/*
 * QEMU ETRAX System Emulator
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdio.h>
#include <ctype.h>
#include "hw.h"
#include "qemu-char.h"

#define D(x)

#define RW_TR_CTRL     0x00
#define RW_TR_DMA_EN   0x04
#define RW_REC_CTRL    0x08
#define RW_DOUT        0x1c
#define RS_STAT_DIN    0x20
#define R_STAT_DIN     0x24
#define RW_INTR_MASK   0x2c
#define RW_ACK_INTR    0x30
#define R_INTR         0x34
#define R_MASKED_INTR  0x38

#define STAT_DAV     16
#define STAT_TR_IDLE 22
#define STAT_TR_RDY  24

struct etrax_serial_t
{
	CPUState *env;
	CharDriverState *chr;
	qemu_irq *irq;

	int pending_tx;

	/* Control registers.  */
	uint32_t rw_tr_ctrl;
	uint32_t rw_tr_dma_en;
	uint32_t rw_rec_ctrl;
	uint32_t rs_stat_din;
	uint32_t r_stat_din;
	uint32_t rw_intr_mask;
	uint32_t rw_ack_intr;
	uint32_t r_intr;
	uint32_t r_masked_intr;
};

static void ser_update_irq(struct etrax_serial_t *s)
{
	uint32_t o_irq = s->r_masked_intr;

	s->r_intr &= ~(s->rw_ack_intr);
	s->r_masked_intr = s->r_intr & s->rw_intr_mask;

	if (o_irq != s->r_masked_intr) {
		D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n", 
			 s->rw_intr_mask, s->r_intr, 
			 s->r_masked_intr, s->rw_ack_intr));
		if (s->r_masked_intr)
			qemu_irq_raise(s->irq[0]);
		else
			qemu_irq_lower(s->irq[0]);
	}
	s->rw_ack_intr = 0;
}


static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
{
	D(CPUState *env = opaque);
	D(printf ("%s %x\n", __func__, addr));
	return 0;
}

static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
	struct etrax_serial_t *s = opaque;
	D(CPUState *env = s->env);
	uint32_t r = 0;

	switch (addr)
	{
		case RW_TR_CTRL:
			r = s->rw_tr_ctrl;
			break;
		case RW_TR_DMA_EN:
			r = s->rw_tr_dma_en;
			break;
		case RS_STAT_DIN:
			r = s->rs_stat_din;
			/* clear dav.  */
			s->rs_stat_din &= ~(1 << STAT_DAV);
			break;
		case R_STAT_DIN:
			r = s->rs_stat_din;
			break;
		case RW_ACK_INTR:
			D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
			r = s->rw_ack_intr;
			break;
		case RW_INTR_MASK:
			r = s->rw_intr_mask;
			break;
		case R_INTR:
			D(printf("load r_intr=%x\n", s->r_intr));
			r = s->r_intr;
			break;
		case R_MASKED_INTR:
			D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
			r = s->r_masked_intr;
			break;

		default:
			D(printf ("%s %x\n", __func__, addr));
			break;
	}
	return r;
}

static void
ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	D(struct etrax_serial_t *s = opaque);
	D(CPUState *env = s->env);
 	D(printf ("%s %x %x\n", __func__, addr, value));
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct etrax_serial_t *s = opaque;
	unsigned char ch = value;
	D(CPUState *env = s->env);

	switch (addr)
	{
		case RW_TR_CTRL:
			D(printf("rw_tr_ctrl=%x\n", value));
			s->rw_tr_ctrl = value;
			break;
		case RW_TR_DMA_EN:
			D(printf("rw_tr_dma_en=%x\n", value));
			s->rw_tr_dma_en = value;
			break;
		case RW_DOUT:
			qemu_chr_write(s->chr, &ch, 1);
			s->r_intr |= 1;
			s->pending_tx = 1;
			break;
		case RW_ACK_INTR:
			D(printf("rw_ack_intr=%x\n", value));
			s->rw_ack_intr = value;
			if (s->pending_tx && (s->rw_ack_intr & 1)) {
				s->r_intr |= 1;
				s->pending_tx = 0;
				s->rw_ack_intr &= ~1;
			}
			break;
		case RW_INTR_MASK:
			D(printf("r_intr_mask=%x\n", value));
			s->rw_intr_mask = value;
			break;
		default:
			D(printf ("%s %x %x\n",  __func__, addr, value));
			break;
	}
	ser_update_irq(s);
}

static CPUReadMemoryFunc *ser_read[] = {
	&ser_readb,
	&ser_readb,
	&ser_readl,
};

static CPUWriteMemoryFunc *ser_write[] = {
	&ser_writeb,
	&ser_writeb,
	&ser_writel,
};

static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
	struct etrax_serial_t *s = opaque;

	s->r_intr |= 8;
	s->rs_stat_din &= ~0xff;
	s->rs_stat_din |= (buf[0] & 0xff);
	s->rs_stat_din |= (1 << STAT_DAV); /* dav.  */
	ser_update_irq(s);
}

static int serial_can_receive(void *opaque)
{
	struct etrax_serial_t *s = opaque;
	int r;

	/* Is the receiver enabled?  */
	r = s->rw_rec_ctrl & 1;

	/* Pending rx data?  */
	r |= !(s->r_intr & 8);
	return r;
}

static void serial_event(void *opaque, int event)
{

}

void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
		      target_phys_addr_t base)
{
	struct etrax_serial_t *s;
	int ser_regs;

	s = qemu_mallocz(sizeof *s);
	if (!s)
		return;

	s->env = env;
	s->irq = irq;
	s->chr = chr;

	/* transmitter begins ready and idle.  */
	s->rs_stat_din |= (1 << STAT_TR_RDY);
	s->rs_stat_din |= (1 << STAT_TR_IDLE);

	qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
			      serial_event, s);

	ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
	cpu_register_physical_memory (base, 0x3c, ser_regs);
}
Commit	Line	Data
83fa1010 TS	1	/*
	2	* QEMU ETRAX System Emulator
	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdio.h>
	26	#include <ctype.h>
87ecb68b	27	#include "hw.h"
f062058f	28	#include "qemu-char.h"
83fa1010	29
bbaf29c7 EI	30	#define D(x)
bbaf29c7 EI	31
f062058f EI	32	#define RW_TR_CTRL 0x00
	33	#define RW_TR_DMA_EN 0x04
	34	#define RW_REC_CTRL 0x08
	35	#define RW_DOUT 0x1c
	36	#define RS_STAT_DIN 0x20
	37	#define R_STAT_DIN 0x24
	38	#define RW_INTR_MASK 0x2c
	39	#define RW_ACK_INTR 0x30
	40	#define R_INTR 0x34
	41	#define R_MASKED_INTR 0x38
83fa1010	42
f062058f EI	43	#define STAT_DAV 16
	44	#define STAT_TR_IDLE 22
	45	#define STAT_TR_RDY 24
	46
	47	struct etrax_serial_t
83fa1010	48	{
f062058f EI	49	CPUState *env;
	50	CharDriverState *chr;
	51	qemu_irq *irq;
	52
f062058f EI	53	int pending_tx;
	54
	55	/* Control registers. */
	56	uint32_t rw_tr_ctrl;
	57	uint32_t rw_tr_dma_en;
	58	uint32_t rw_rec_ctrl;
	59	uint32_t rs_stat_din;
	60	uint32_t r_stat_din;
	61	uint32_t rw_intr_mask;
	62	uint32_t rw_ack_intr;
	63	uint32_t r_intr;
	64	uint32_t r_masked_intr;
	65	};
	66
	67	static void ser_update_irq(struct etrax_serial_t *s)
	68	{
	69	uint32_t o_irq = s->r_masked_intr;
	70
	71	s->r_intr &= ~(s->rw_ack_intr);
	72	s->r_masked_intr = s->r_intr & s->rw_intr_mask;
	73
	74	if (o_irq != s->r_masked_intr) {
	75	D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
	76	s->rw_intr_mask, s->r_intr,
	77	s->r_masked_intr, s->rw_ack_intr));
	78	if (s->r_masked_intr)
	79	qemu_irq_raise(s->irq[0]);
	80	else
	81	qemu_irq_lower(s->irq[0]);
	82	}
	83	s->rw_ack_intr = 0;
83fa1010	84	}
f062058f EI	85
	86
	87	static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
83fa1010	88	{
ca87d03b	89	D(CPUState *env = opaque);
d27b2e50	90	D(printf ("%s %x\n", __func__, addr));
ca87d03b	91	return 0;
83fa1010 TS	92	}
	93
	94	static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
	95	{
f062058f EI	96	struct etrax_serial_t *s = opaque;
f062058f EI	97	D(CPUState *env = s->env);
83fa1010 TS	98	uint32_t r = 0;
83fa1010 TS	99
0db74b07	100	switch (addr)
83fa1010	101	{
f062058f EI	102	case RW_TR_CTRL:
	103	r = s->rw_tr_ctrl;
	104	break;
83fa1010	105	case RW_TR_DMA_EN:
f062058f EI	106	r = s->rw_tr_dma_en;
	107	break;
	108	case RS_STAT_DIN:
	109	r = s->rs_stat_din;
	110	/* clear dav. */
	111	s->rs_stat_din &= ~(1 << STAT_DAV);
83fa1010 TS	112	break;
83fa1010 TS	113	case R_STAT_DIN:
f062058f EI	114	r = s->rs_stat_din;
	115	break;
	116	case RW_ACK_INTR:
	117	D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
	118	r = s->rw_ack_intr;
	119	break;
	120	case RW_INTR_MASK:
	121	r = s->rw_intr_mask;
	122	break;
	123	case R_INTR:
	124	D(printf("load r_intr=%x\n", s->r_intr));
	125	r = s->r_intr;
	126	break;
	127	case R_MASKED_INTR:
	128	D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
	129	r = s->r_masked_intr;
83fa1010 TS	130	break;
	131
	132	default:
d27b2e50	133	D(printf ("%s %x\n", __func__, addr));
83fa1010 TS	134	break;
	135	}
	136	return r;
	137	}
	138
	139	static void
	140	ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	141	{
f062058f EI	142	D(struct etrax_serial_t *s = opaque);
f062058f EI	143	D(CPUState *env = s->env);
d27b2e50	144	D(printf ("%s %x %x\n", __func__, addr, value));
83fa1010 TS	145	}
83fa1010 TS	146	static void
83fa1010 TS	147	ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
83fa1010 TS	148	{
f062058f EI	149	struct etrax_serial_t *s = opaque;
	150	unsigned char ch = value;
	151	D(CPUState *env = s->env);
83fa1010	152
0db74b07	153	switch (addr)
83fa1010	154	{
f062058f EI	155	case RW_TR_CTRL:
	156	D(printf("rw_tr_ctrl=%x\n", value));
	157	s->rw_tr_ctrl = value;
	158	break;
83fa1010	159	case RW_TR_DMA_EN:
f062058f EI	160	D(printf("rw_tr_dma_en=%x\n", value));
f062058f EI	161	s->rw_tr_dma_en = value;
83fa1010 TS	162	break;
83fa1010 TS	163	case RW_DOUT:
f062058f EI	164	qemu_chr_write(s->chr, &ch, 1);
	165	s->r_intr \|= 1;
	166	s->pending_tx = 1;
	167	break;
	168	case RW_ACK_INTR:
	169	D(printf("rw_ack_intr=%x\n", value));
	170	s->rw_ack_intr = value;
	171	if (s->pending_tx && (s->rw_ack_intr & 1)) {
	172	s->r_intr \|= 1;
	173	s->pending_tx = 0;
	174	s->rw_ack_intr &= ~1;
	175	}
	176	break;
	177	case RW_INTR_MASK:
	178	D(printf("r_intr_mask=%x\n", value));
	179	s->rw_intr_mask = value;
83fa1010 TS	180	break;
83fa1010 TS	181	default:
d27b2e50	182	D(printf ("%s %x %x\n", __func__, addr, value));
83fa1010 TS	183	break;
83fa1010 TS	184	}
f062058f	185	ser_update_irq(s);
83fa1010 TS	186	}
	187
	188	static CPUReadMemoryFunc *ser_read[] = {
ca87d03b	189	&ser_readb,
f062058f	190	&ser_readb,
ca87d03b	191	&ser_readl,
83fa1010 TS	192	};
	193
	194	static CPUWriteMemoryFunc *ser_write[] = {
ca87d03b	195	&ser_writeb,
f062058f	196	&ser_writeb,
ca87d03b	197	&ser_writel,
83fa1010 TS	198	};
83fa1010 TS	199
f062058f	200	static void serial_receive(void opaque, const uint8_t buf, int size)
83fa1010	201	{
f062058f EI	202	struct etrax_serial_t *s = opaque;
	203
	204	s->r_intr \|= 8;
	205	s->rs_stat_din &= ~0xff;
	206	s->rs_stat_din \|= (buf[0] & 0xff);
	207	s->rs_stat_din \|= (1 << STAT_DAV); /* dav. */
	208	ser_update_irq(s);
	209	}
	210
	211	static int serial_can_receive(void *opaque)
	212	{
	213	struct etrax_serial_t *s = opaque;
	214	int r;
	215
	216	/* Is the receiver enabled? */
	217	r = s->rw_rec_ctrl & 1;
	218
	219	/* Pending rx data? */
	220	r \|= !(s->r_intr & 8);
	221	return r;
	222	}
	223
	224	static void serial_event(void *opaque, int event)
	225	{
	226
	227	}
	228
	229	void etraxfs_ser_init(CPUState env, qemu_irq irq, CharDriverState *chr,
	230	target_phys_addr_t base)
	231	{
	232	struct etrax_serial_t *s;
83fa1010	233	int ser_regs;
f062058f EI	234
	235	s = qemu_mallocz(sizeof *s);
	236	if (!s)
	237	return;
	238
	239	s->env = env;
	240	s->irq = irq;
f062058f EI	241	s->chr = chr;
	242
	243	/* transmitter begins ready and idle. */
	244	s->rs_stat_din \|= (1 << STAT_TR_RDY);
	245	s->rs_stat_din \|= (1 << STAT_TR_IDLE);
	246
	247	qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
	248	serial_event, s);
	249
	250	ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
ca87d03b	251	cpu_register_physical_memory (base, 0x3c, ser_regs);
83fa1010	252	}