[qemu.git] / hw / etraxfs_ser.c

/*
 * QEMU ETRAX System Emulator
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdio.h>
#include <ctype.h>
#include "hw.h"
#include "qemu-char.h"
#include "etraxfs.h"

#define D(x)

#define RW_TR_CTRL     0x00
#define RW_TR_DMA_EN   0x04
#define RW_REC_CTRL    0x08
#define RW_DOUT        0x1c
#define RS_STAT_DIN    0x20
#define R_STAT_DIN     0x24
#define RW_INTR_MASK   0x2c
#define RW_ACK_INTR    0x30
#define R_INTR         0x34
#define R_MASKED_INTR  0x38

#define STAT_DAV     16
#define STAT_TR_IDLE 22
#define STAT_TR_RDY  24

struct etrax_serial_t
{
	CPUState *env;
	CharDriverState *chr;
	qemu_irq *irq;

	int pending_tx;

	/* Control registers.  */
	uint32_t rw_tr_ctrl;
	uint32_t rw_tr_dma_en;
	uint32_t rw_rec_ctrl;
	uint32_t rs_stat_din;
	uint32_t r_stat_din;
	uint32_t rw_intr_mask;
	uint32_t rw_ack_intr;
	uint32_t r_intr;
	uint32_t r_masked_intr;
};

static void ser_update_irq(struct etrax_serial_t *s)
{
	uint32_t o_irq = s->r_masked_intr;

	s->r_intr &= ~(s->rw_ack_intr);
	s->r_masked_intr = s->r_intr & s->rw_intr_mask;

	if (o_irq != s->r_masked_intr) {
		D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n", 
			 s->rw_intr_mask, s->r_intr, 
			 s->r_masked_intr, s->rw_ack_intr));
		if (s->r_masked_intr)
			qemu_irq_raise(s->irq[0]);
		else
			qemu_irq_lower(s->irq[0]);
	}
	s->rw_ack_intr = 0;
}


static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
{
	D(CPUState *env = opaque);
	D(printf ("%s %x\n", __func__, addr));
	return 0;
}

static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
	struct etrax_serial_t *s = opaque;
	D(CPUState *env = s->env);
	uint32_t r = 0;

	switch (addr)
	{
		case RW_TR_CTRL:
			r = s->rw_tr_ctrl;
			break;
		case RW_TR_DMA_EN:
			r = s->rw_tr_dma_en;
			break;
		case RS_STAT_DIN:
			r = s->rs_stat_din;
			/* clear dav.  */
			s->rs_stat_din &= ~(1 << STAT_DAV);
			break;
		case R_STAT_DIN:
			r = s->rs_stat_din;
			break;
		case RW_ACK_INTR:
			D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
			r = s->rw_ack_intr;
			break;
		case RW_INTR_MASK:
			r = s->rw_intr_mask;
			break;
		case R_INTR:
			D(printf("load r_intr=%x\n", s->r_intr));
			r = s->r_intr;
			break;
		case R_MASKED_INTR:
			D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
			r = s->r_masked_intr;
			break;

		default:
			D(printf ("%s %x\n", __func__, addr));
			break;
	}
	return r;
}

static void
ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	D(struct etrax_serial_t *s = opaque);
	D(CPUState *env = s->env);
 	D(printf ("%s %x %x\n", __func__, addr, value));
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct etrax_serial_t *s = opaque;
	unsigned char ch = value;
	D(CPUState *env = s->env);

	switch (addr)
	{
		case RW_TR_CTRL:
			D(printf("rw_tr_ctrl=%x\n", value));
			s->rw_tr_ctrl = value;
			break;
		case RW_TR_DMA_EN:
			D(printf("rw_tr_dma_en=%x\n", value));
			s->rw_tr_dma_en = value;
			break;
		case RW_DOUT:
			qemu_chr_write(s->chr, &ch, 1);
			s->r_intr |= 1;
			s->pending_tx = 1;
			break;
		case RW_ACK_INTR:
			D(printf("rw_ack_intr=%x\n", value));
			s->rw_ack_intr = value;
			if (s->pending_tx && (s->rw_ack_intr & 1)) {
				s->r_intr |= 1;
				s->pending_tx = 0;
				s->rw_ack_intr &= ~1;
			}
			break;
		case RW_INTR_MASK:
			D(printf("r_intr_mask=%x\n", value));
			s->rw_intr_mask = value;
			break;
		default:
			D(printf ("%s %x %x\n",  __func__, addr, value));
			break;
	}
	ser_update_irq(s);
}

static CPUReadMemoryFunc *ser_read[] = {
	&ser_readb,
	&ser_readb,
	&ser_readl,
};

static CPUWriteMemoryFunc *ser_write[] = {
	&ser_writeb,
	&ser_writeb,
	&ser_writel,
};

static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
	struct etrax_serial_t *s = opaque;

	s->r_intr |= 8;
	s->rs_stat_din &= ~0xff;
	s->rs_stat_din |= (buf[0] & 0xff);
	s->rs_stat_din |= (1 << STAT_DAV); /* dav.  */
	ser_update_irq(s);
}

static int serial_can_receive(void *opaque)
{
	struct etrax_serial_t *s = opaque;
	int r;

	/* Is the receiver enabled?  */
	r = s->rw_rec_ctrl & 1;

	/* Pending rx data?  */
	r |= !(s->r_intr & 8);
	return r;
}

static void serial_event(void *opaque, int event)
{

}

void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
		      target_phys_addr_t base)
{
	struct etrax_serial_t *s;
	int ser_regs;

	s = qemu_mallocz(sizeof *s);

	s->env = env;
	s->irq = irq;
	s->chr = chr;

	/* transmitter begins ready and idle.  */
	s->rs_stat_din |= (1 << STAT_TR_RDY);
	s->rs_stat_din |= (1 << STAT_TR_IDLE);

	qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
			      serial_event, s);

	ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
	cpu_register_physical_memory (base, 0x3c, ser_regs);
}
Commit	Line	Data
83fa1010 TS	1	/*
	2	* QEMU ETRAX System Emulator
	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdio.h>
	26	#include <ctype.h>
87ecb68b	27	#include "hw.h"
f062058f	28	#include "qemu-char.h"
cc53adbc	29	#include "etraxfs.h"
83fa1010	30
bbaf29c7 EI	31	#define D(x)
bbaf29c7 EI	32
f062058f EI	33	#define RW_TR_CTRL 0x00
	34	#define RW_TR_DMA_EN 0x04
	35	#define RW_REC_CTRL 0x08
	36	#define RW_DOUT 0x1c
	37	#define RS_STAT_DIN 0x20
	38	#define R_STAT_DIN 0x24
	39	#define RW_INTR_MASK 0x2c
	40	#define RW_ACK_INTR 0x30
	41	#define R_INTR 0x34
	42	#define R_MASKED_INTR 0x38
83fa1010	43
f062058f EI	44	#define STAT_DAV 16
	45	#define STAT_TR_IDLE 22
	46	#define STAT_TR_RDY 24
	47
	48	struct etrax_serial_t
83fa1010	49	{
f062058f EI	50	CPUState *env;
	51	CharDriverState *chr;
	52	qemu_irq *irq;
	53
f062058f EI	54	int pending_tx;
	55
	56	/* Control registers. */
	57	uint32_t rw_tr_ctrl;
	58	uint32_t rw_tr_dma_en;
	59	uint32_t rw_rec_ctrl;
	60	uint32_t rs_stat_din;
	61	uint32_t r_stat_din;
	62	uint32_t rw_intr_mask;
	63	uint32_t rw_ack_intr;
	64	uint32_t r_intr;
	65	uint32_t r_masked_intr;
	66	};
	67
	68	static void ser_update_irq(struct etrax_serial_t *s)
	69	{
	70	uint32_t o_irq = s->r_masked_intr;
	71
	72	s->r_intr &= ~(s->rw_ack_intr);
	73	s->r_masked_intr = s->r_intr & s->rw_intr_mask;
	74
	75	if (o_irq != s->r_masked_intr) {
	76	D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
	77	s->rw_intr_mask, s->r_intr,
	78	s->r_masked_intr, s->rw_ack_intr));
	79	if (s->r_masked_intr)
	80	qemu_irq_raise(s->irq[0]);
	81	else
	82	qemu_irq_lower(s->irq[0]);
	83	}
	84	s->rw_ack_intr = 0;
83fa1010	85	}
f062058f EI	86
	87
	88	static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
83fa1010	89	{
ca87d03b	90	D(CPUState *env = opaque);
d27b2e50	91	D(printf ("%s %x\n", __func__, addr));
ca87d03b	92	return 0;
83fa1010 TS	93	}
	94
	95	static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
	96	{
f062058f EI	97	struct etrax_serial_t *s = opaque;
f062058f EI	98	D(CPUState *env = s->env);
83fa1010 TS	99	uint32_t r = 0;
83fa1010 TS	100
0db74b07	101	switch (addr)
83fa1010	102	{
f062058f EI	103	case RW_TR_CTRL:
	104	r = s->rw_tr_ctrl;
	105	break;
83fa1010	106	case RW_TR_DMA_EN:
f062058f EI	107	r = s->rw_tr_dma_en;
	108	break;
	109	case RS_STAT_DIN:
	110	r = s->rs_stat_din;
	111	/* clear dav. */
	112	s->rs_stat_din &= ~(1 << STAT_DAV);
83fa1010 TS	113	break;
83fa1010 TS	114	case R_STAT_DIN:
f062058f EI	115	r = s->rs_stat_din;
	116	break;
	117	case RW_ACK_INTR:
	118	D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
	119	r = s->rw_ack_intr;
	120	break;
	121	case RW_INTR_MASK:
	122	r = s->rw_intr_mask;
	123	break;
	124	case R_INTR:
	125	D(printf("load r_intr=%x\n", s->r_intr));
	126	r = s->r_intr;
	127	break;
	128	case R_MASKED_INTR:
	129	D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
	130	r = s->r_masked_intr;
83fa1010 TS	131	break;
	132
	133	default:
d27b2e50	134	D(printf ("%s %x\n", __func__, addr));
83fa1010 TS	135	break;
	136	}
	137	return r;
	138	}
	139
	140	static void
	141	ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	142	{
f062058f EI	143	D(struct etrax_serial_t *s = opaque);
f062058f EI	144	D(CPUState *env = s->env);
d27b2e50	145	D(printf ("%s %x %x\n", __func__, addr, value));
83fa1010 TS	146	}
83fa1010 TS	147	static void
83fa1010 TS	148	ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
83fa1010 TS	149	{
f062058f EI	150	struct etrax_serial_t *s = opaque;
	151	unsigned char ch = value;
	152	D(CPUState *env = s->env);
83fa1010	153
0db74b07	154	switch (addr)
83fa1010	155	{
f062058f EI	156	case RW_TR_CTRL:
	157	D(printf("rw_tr_ctrl=%x\n", value));
	158	s->rw_tr_ctrl = value;
	159	break;
83fa1010	160	case RW_TR_DMA_EN:
f062058f EI	161	D(printf("rw_tr_dma_en=%x\n", value));
f062058f EI	162	s->rw_tr_dma_en = value;
83fa1010 TS	163	break;
83fa1010 TS	164	case RW_DOUT:
f062058f EI	165	qemu_chr_write(s->chr, &ch, 1);
	166	s->r_intr \|= 1;
	167	s->pending_tx = 1;
	168	break;
	169	case RW_ACK_INTR:
	170	D(printf("rw_ack_intr=%x\n", value));
	171	s->rw_ack_intr = value;
	172	if (s->pending_tx && (s->rw_ack_intr & 1)) {
	173	s->r_intr \|= 1;
	174	s->pending_tx = 0;
	175	s->rw_ack_intr &= ~1;
	176	}
	177	break;
	178	case RW_INTR_MASK:
	179	D(printf("r_intr_mask=%x\n", value));
	180	s->rw_intr_mask = value;
83fa1010 TS	181	break;
83fa1010 TS	182	default:
d27b2e50	183	D(printf ("%s %x %x\n", __func__, addr, value));
83fa1010 TS	184	break;
83fa1010 TS	185	}
f062058f	186	ser_update_irq(s);
83fa1010 TS	187	}
	188
	189	static CPUReadMemoryFunc *ser_read[] = {
ca87d03b	190	&ser_readb,
f062058f	191	&ser_readb,
ca87d03b	192	&ser_readl,
83fa1010 TS	193	};
	194
	195	static CPUWriteMemoryFunc *ser_write[] = {
ca87d03b	196	&ser_writeb,
f062058f	197	&ser_writeb,
ca87d03b	198	&ser_writel,
83fa1010 TS	199	};
83fa1010 TS	200
f062058f	201	static void serial_receive(void opaque, const uint8_t buf, int size)
83fa1010	202	{
f062058f EI	203	struct etrax_serial_t *s = opaque;
	204
	205	s->r_intr \|= 8;
	206	s->rs_stat_din &= ~0xff;
	207	s->rs_stat_din \|= (buf[0] & 0xff);
	208	s->rs_stat_din \|= (1 << STAT_DAV); /* dav. */
	209	ser_update_irq(s);
	210	}
	211
	212	static int serial_can_receive(void *opaque)
	213	{
	214	struct etrax_serial_t *s = opaque;
	215	int r;
	216
	217	/* Is the receiver enabled? */
	218	r = s->rw_rec_ctrl & 1;
	219
	220	/* Pending rx data? */
	221	r \|= !(s->r_intr & 8);
	222	return r;
	223	}
	224
	225	static void serial_event(void *opaque, int event)
	226	{
	227
	228	}
	229
	230	void etraxfs_ser_init(CPUState env, qemu_irq irq, CharDriverState *chr,
	231	target_phys_addr_t base)
	232	{
	233	struct etrax_serial_t *s;
83fa1010	234	int ser_regs;
f062058f EI	235
f062058f EI	236	s = qemu_mallocz(sizeof *s);
f062058f EI	237
	238	s->env = env;
	239	s->irq = irq;
f062058f EI	240	s->chr = chr;
	241
	242	/* transmitter begins ready and idle. */
	243	s->rs_stat_din \|= (1 << STAT_TR_RDY);
	244	s->rs_stat_din \|= (1 << STAT_TR_IDLE);
	245
	246	qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
	247	serial_event, s);
	248
	249	ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
ca87d03b	250	cpu_register_physical_memory (base, 0x3c, ser_regs);
83fa1010	251	}