]>
Commit | Line | Data |
---|---|---|
8977f3c1 | 1 | /* |
890fa6be | 2 | * QEMU Floppy disk emulator (Intel 82078) |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003, 2007 Jocelyn Mayer |
bcc4e41f | 5 | * Copyright (c) 2008 Hervé Poussineau |
5fafdf24 | 6 | * |
8977f3c1 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
e80cfcfc FB |
25 | /* |
26 | * The controller is used in Sun4m systems in a slightly different | |
27 | * way. There are changes in DOR register and DMA is not available. | |
28 | */ | |
f64ab228 | 29 | |
87ecb68b PB |
30 | #include "hw.h" |
31 | #include "fdc.h" | |
b47b3525 | 32 | #include "qemu-error.h" |
87ecb68b PB |
33 | #include "qemu-timer.h" |
34 | #include "isa.h" | |
f64ab228 | 35 | #include "sysbus.h" |
e8133762 | 36 | #include "qdev-addr.h" |
2446333c | 37 | #include "blockdev.h" |
1ca4d09a | 38 | #include "sysemu.h" |
8977f3c1 FB |
39 | |
40 | /********************************************************/ | |
41 | /* debug Floppy devices */ | |
42 | //#define DEBUG_FLOPPY | |
43 | ||
44 | #ifdef DEBUG_FLOPPY | |
001faf32 BS |
45 | #define FLOPPY_DPRINTF(fmt, ...) \ |
46 | do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) | |
8977f3c1 | 47 | #else |
001faf32 | 48 | #define FLOPPY_DPRINTF(fmt, ...) |
8977f3c1 FB |
49 | #endif |
50 | ||
001faf32 BS |
51 | #define FLOPPY_ERROR(fmt, ...) \ |
52 | do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) | |
8977f3c1 FB |
53 | |
54 | /********************************************************/ | |
55 | /* Floppy drive emulation */ | |
56 | ||
cefec4f5 BS |
57 | #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) |
58 | #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) | |
59 | ||
8977f3c1 | 60 | /* Will always be a fixed parameter for us */ |
f2d81b33 BS |
61 | #define FD_SECTOR_LEN 512 |
62 | #define FD_SECTOR_SC 2 /* Sector size code */ | |
63 | #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ | |
8977f3c1 FB |
64 | |
65 | /* Floppy disk drive emulation */ | |
5c02c033 | 66 | typedef enum FDiskFlags { |
baca51fa | 67 | FDISK_DBL_SIDES = 0x01, |
5c02c033 | 68 | } FDiskFlags; |
baca51fa | 69 | |
5c02c033 | 70 | typedef struct FDrive { |
8977f3c1 FB |
71 | BlockDriverState *bs; |
72 | /* Drive status */ | |
5c02c033 | 73 | FDriveType drive; |
8977f3c1 | 74 | uint8_t perpendicular; /* 2.88 MB access mode */ |
8977f3c1 FB |
75 | /* Position */ |
76 | uint8_t head; | |
77 | uint8_t track; | |
78 | uint8_t sect; | |
8977f3c1 | 79 | /* Media */ |
5c02c033 | 80 | FDiskFlags flags; |
8977f3c1 FB |
81 | uint8_t last_sect; /* Nb sector per track */ |
82 | uint8_t max_track; /* Nb of tracks */ | |
baca51fa | 83 | uint16_t bps; /* Bytes per sector */ |
8977f3c1 | 84 | uint8_t ro; /* Is read-only */ |
7d905f71 | 85 | uint8_t media_changed; /* Is media changed */ |
5c02c033 | 86 | } FDrive; |
8977f3c1 | 87 | |
5c02c033 | 88 | static void fd_init(FDrive *drv) |
8977f3c1 FB |
89 | { |
90 | /* Drive */ | |
b939777c | 91 | drv->drive = FDRIVE_DRV_NONE; |
8977f3c1 | 92 | drv->perpendicular = 0; |
8977f3c1 | 93 | /* Disk */ |
baca51fa | 94 | drv->last_sect = 0; |
8977f3c1 FB |
95 | drv->max_track = 0; |
96 | } | |
97 | ||
08388273 HP |
98 | #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) |
99 | ||
7859cb98 | 100 | static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, |
08388273 | 101 | uint8_t last_sect, uint8_t num_sides) |
8977f3c1 | 102 | { |
08388273 | 103 | return (((track * num_sides) + head) * last_sect) + sect - 1; |
8977f3c1 FB |
104 | } |
105 | ||
106 | /* Returns current position, in sectors, for given drive */ | |
5c02c033 | 107 | static int fd_sector(FDrive *drv) |
8977f3c1 | 108 | { |
08388273 HP |
109 | return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, |
110 | NUM_SIDES(drv)); | |
8977f3c1 FB |
111 | } |
112 | ||
77370520 BS |
113 | /* Seek to a new position: |
114 | * returns 0 if already on right track | |
115 | * returns 1 if track changed | |
116 | * returns 2 if track is invalid | |
117 | * returns 3 if sector is invalid | |
118 | * returns 4 if seek is disabled | |
119 | */ | |
5c02c033 BS |
120 | static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, |
121 | int enable_seek) | |
8977f3c1 FB |
122 | { |
123 | uint32_t sector; | |
baca51fa FB |
124 | int ret; |
125 | ||
126 | if (track > drv->max_track || | |
4f431960 | 127 | (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
ed5fd2cc FB |
128 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
129 | head, track, sect, 1, | |
130 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
131 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
132 | return 2; |
133 | } | |
134 | if (sect > drv->last_sect) { | |
ed5fd2cc FB |
135 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
136 | head, track, sect, 1, | |
137 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
138 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
139 | return 3; |
140 | } | |
08388273 | 141 | sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); |
baca51fa | 142 | ret = 0; |
8977f3c1 FB |
143 | if (sector != fd_sector(drv)) { |
144 | #if 0 | |
145 | if (!enable_seek) { | |
146 | FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n", | |
147 | head, track, sect, 1, drv->max_track, drv->last_sect); | |
148 | return 4; | |
149 | } | |
150 | #endif | |
151 | drv->head = head; | |
4f431960 JM |
152 | if (drv->track != track) |
153 | ret = 1; | |
8977f3c1 FB |
154 | drv->track = track; |
155 | drv->sect = sect; | |
8977f3c1 FB |
156 | } |
157 | ||
baca51fa | 158 | return ret; |
8977f3c1 FB |
159 | } |
160 | ||
161 | /* Set drive back to track 0 */ | |
5c02c033 | 162 | static void fd_recalibrate(FDrive *drv) |
8977f3c1 FB |
163 | { |
164 | FLOPPY_DPRINTF("recalibrate\n"); | |
165 | drv->head = 0; | |
166 | drv->track = 0; | |
167 | drv->sect = 1; | |
8977f3c1 FB |
168 | } |
169 | ||
170 | /* Revalidate a disk drive after a disk change */ | |
5c02c033 | 171 | static void fd_revalidate(FDrive *drv) |
8977f3c1 | 172 | { |
baca51fa | 173 | int nb_heads, max_track, last_sect, ro; |
5bbdbb46 | 174 | FDriveType drive; |
f8d3d128 | 175 | FDriveRate rate; |
8977f3c1 FB |
176 | |
177 | FLOPPY_DPRINTF("revalidate\n"); | |
a541f297 | 178 | if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { |
4f431960 | 179 | ro = bdrv_is_read_only(drv->bs); |
5bbdbb46 | 180 | bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track, |
f8d3d128 | 181 | &last_sect, drv->drive, &drive, &rate); |
4f431960 JM |
182 | if (nb_heads != 0 && max_track != 0 && last_sect != 0) { |
183 | FLOPPY_DPRINTF("User defined disk (%d %d %d)", | |
ed5fd2cc | 184 | nb_heads - 1, max_track, last_sect); |
4f431960 | 185 | } else { |
5bbdbb46 BS |
186 | FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads, |
187 | max_track, last_sect, ro ? "ro" : "rw"); | |
4f431960 JM |
188 | } |
189 | if (nb_heads == 1) { | |
190 | drv->flags &= ~FDISK_DBL_SIDES; | |
191 | } else { | |
192 | drv->flags |= FDISK_DBL_SIDES; | |
193 | } | |
194 | drv->max_track = max_track; | |
195 | drv->last_sect = last_sect; | |
196 | drv->ro = ro; | |
5bbdbb46 | 197 | drv->drive = drive; |
8977f3c1 | 198 | } else { |
4f431960 | 199 | FLOPPY_DPRINTF("No disk in drive\n"); |
baca51fa | 200 | drv->last_sect = 0; |
4f431960 JM |
201 | drv->max_track = 0; |
202 | drv->flags &= ~FDISK_DBL_SIDES; | |
8977f3c1 | 203 | } |
caed8802 FB |
204 | } |
205 | ||
8977f3c1 | 206 | /********************************************************/ |
4b19ec0c | 207 | /* Intel 82078 floppy disk controller emulation */ |
8977f3c1 | 208 | |
63ffb564 BS |
209 | typedef struct FDCtrl FDCtrl; |
210 | ||
5c02c033 BS |
211 | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); |
212 | static void fdctrl_reset_fifo(FDCtrl *fdctrl); | |
85571bc7 | 213 | static int fdctrl_transfer_handler (void *opaque, int nchan, |
c227f099 | 214 | int dma_pos, int dma_len); |
5c02c033 BS |
215 | static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0); |
216 | ||
217 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); | |
218 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); | |
219 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); | |
220 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); | |
221 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); | |
222 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); | |
223 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); | |
224 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); | |
225 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl); | |
226 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); | |
227 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); | |
a758f8f4 | 228 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); |
8977f3c1 | 229 | |
8977f3c1 FB |
230 | enum { |
231 | FD_DIR_WRITE = 0, | |
232 | FD_DIR_READ = 1, | |
233 | FD_DIR_SCANE = 2, | |
234 | FD_DIR_SCANL = 3, | |
235 | FD_DIR_SCANH = 4, | |
236 | }; | |
237 | ||
238 | enum { | |
b9b3d225 BS |
239 | FD_STATE_MULTI = 0x01, /* multi track flag */ |
240 | FD_STATE_FORMAT = 0x02, /* format flag */ | |
241 | FD_STATE_SEEK = 0x04, /* seek flag */ | |
8977f3c1 FB |
242 | }; |
243 | ||
9fea808a | 244 | enum { |
8c6a4d77 BS |
245 | FD_REG_SRA = 0x00, |
246 | FD_REG_SRB = 0x01, | |
9fea808a BS |
247 | FD_REG_DOR = 0x02, |
248 | FD_REG_TDR = 0x03, | |
249 | FD_REG_MSR = 0x04, | |
250 | FD_REG_DSR = 0x04, | |
251 | FD_REG_FIFO = 0x05, | |
252 | FD_REG_DIR = 0x07, | |
a758f8f4 | 253 | FD_REG_CCR = 0x07, |
9fea808a BS |
254 | }; |
255 | ||
256 | enum { | |
65cef780 | 257 | FD_CMD_READ_TRACK = 0x02, |
9fea808a BS |
258 | FD_CMD_SPECIFY = 0x03, |
259 | FD_CMD_SENSE_DRIVE_STATUS = 0x04, | |
65cef780 BS |
260 | FD_CMD_WRITE = 0x05, |
261 | FD_CMD_READ = 0x06, | |
9fea808a BS |
262 | FD_CMD_RECALIBRATE = 0x07, |
263 | FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, | |
65cef780 BS |
264 | FD_CMD_WRITE_DELETED = 0x09, |
265 | FD_CMD_READ_ID = 0x0a, | |
266 | FD_CMD_READ_DELETED = 0x0c, | |
267 | FD_CMD_FORMAT_TRACK = 0x0d, | |
9fea808a BS |
268 | FD_CMD_DUMPREG = 0x0e, |
269 | FD_CMD_SEEK = 0x0f, | |
270 | FD_CMD_VERSION = 0x10, | |
65cef780 | 271 | FD_CMD_SCAN_EQUAL = 0x11, |
9fea808a BS |
272 | FD_CMD_PERPENDICULAR_MODE = 0x12, |
273 | FD_CMD_CONFIGURE = 0x13, | |
65cef780 BS |
274 | FD_CMD_LOCK = 0x14, |
275 | FD_CMD_VERIFY = 0x16, | |
9fea808a BS |
276 | FD_CMD_POWERDOWN_MODE = 0x17, |
277 | FD_CMD_PART_ID = 0x18, | |
65cef780 BS |
278 | FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, |
279 | FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, | |
bb350a5e | 280 | FD_CMD_SAVE = 0x2e, |
9fea808a | 281 | FD_CMD_OPTION = 0x33, |
bb350a5e | 282 | FD_CMD_RESTORE = 0x4e, |
9fea808a BS |
283 | FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, |
284 | FD_CMD_RELATIVE_SEEK_OUT = 0x8f, | |
9fea808a BS |
285 | FD_CMD_FORMAT_AND_WRITE = 0xcd, |
286 | FD_CMD_RELATIVE_SEEK_IN = 0xcf, | |
287 | }; | |
288 | ||
289 | enum { | |
290 | FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ | |
291 | FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ | |
292 | FD_CONFIG_POLL = 0x10, /* Poll enabled */ | |
293 | FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ | |
294 | FD_CONFIG_EIS = 0x40, /* No implied seeks */ | |
295 | }; | |
296 | ||
297 | enum { | |
298 | FD_SR0_EQPMT = 0x10, | |
299 | FD_SR0_SEEK = 0x20, | |
300 | FD_SR0_ABNTERM = 0x40, | |
301 | FD_SR0_INVCMD = 0x80, | |
302 | FD_SR0_RDYCHG = 0xc0, | |
303 | }; | |
304 | ||
77370520 | 305 | enum { |
8510854e | 306 | FD_SR1_NW = 0x02, /* Not writable */ |
77370520 BS |
307 | FD_SR1_EC = 0x80, /* End of cylinder */ |
308 | }; | |
309 | ||
310 | enum { | |
311 | FD_SR2_SNS = 0x04, /* Scan not satisfied */ | |
312 | FD_SR2_SEH = 0x08, /* Scan equal hit */ | |
313 | }; | |
314 | ||
8c6a4d77 BS |
315 | enum { |
316 | FD_SRA_DIR = 0x01, | |
317 | FD_SRA_nWP = 0x02, | |
318 | FD_SRA_nINDX = 0x04, | |
319 | FD_SRA_HDSEL = 0x08, | |
320 | FD_SRA_nTRK0 = 0x10, | |
321 | FD_SRA_STEP = 0x20, | |
322 | FD_SRA_nDRV2 = 0x40, | |
323 | FD_SRA_INTPEND = 0x80, | |
324 | }; | |
325 | ||
326 | enum { | |
327 | FD_SRB_MTR0 = 0x01, | |
328 | FD_SRB_MTR1 = 0x02, | |
329 | FD_SRB_WGATE = 0x04, | |
330 | FD_SRB_RDATA = 0x08, | |
331 | FD_SRB_WDATA = 0x10, | |
332 | FD_SRB_DR0 = 0x20, | |
333 | }; | |
334 | ||
9fea808a | 335 | enum { |
78ae820c BS |
336 | #if MAX_FD == 4 |
337 | FD_DOR_SELMASK = 0x03, | |
338 | #else | |
9fea808a | 339 | FD_DOR_SELMASK = 0x01, |
78ae820c | 340 | #endif |
9fea808a BS |
341 | FD_DOR_nRESET = 0x04, |
342 | FD_DOR_DMAEN = 0x08, | |
343 | FD_DOR_MOTEN0 = 0x10, | |
344 | FD_DOR_MOTEN1 = 0x20, | |
345 | FD_DOR_MOTEN2 = 0x40, | |
346 | FD_DOR_MOTEN3 = 0x80, | |
347 | }; | |
348 | ||
349 | enum { | |
78ae820c | 350 | #if MAX_FD == 4 |
9fea808a | 351 | FD_TDR_BOOTSEL = 0x0c, |
78ae820c BS |
352 | #else |
353 | FD_TDR_BOOTSEL = 0x04, | |
354 | #endif | |
9fea808a BS |
355 | }; |
356 | ||
357 | enum { | |
358 | FD_DSR_DRATEMASK= 0x03, | |
359 | FD_DSR_PWRDOWN = 0x40, | |
360 | FD_DSR_SWRESET = 0x80, | |
361 | }; | |
362 | ||
363 | enum { | |
364 | FD_MSR_DRV0BUSY = 0x01, | |
365 | FD_MSR_DRV1BUSY = 0x02, | |
366 | FD_MSR_DRV2BUSY = 0x04, | |
367 | FD_MSR_DRV3BUSY = 0x08, | |
368 | FD_MSR_CMDBUSY = 0x10, | |
369 | FD_MSR_NONDMA = 0x20, | |
370 | FD_MSR_DIO = 0x40, | |
371 | FD_MSR_RQM = 0x80, | |
372 | }; | |
373 | ||
374 | enum { | |
375 | FD_DIR_DSKCHG = 0x80, | |
376 | }; | |
377 | ||
8977f3c1 FB |
378 | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) |
379 | #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK) | |
baca51fa | 380 | #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) |
8977f3c1 | 381 | |
5c02c033 | 382 | struct FDCtrl { |
dc6c1b37 | 383 | MemoryRegion iomem; |
d537cf6c | 384 | qemu_irq irq; |
4b19ec0c | 385 | /* Controller state */ |
ed5fd2cc | 386 | QEMUTimer *result_timer; |
242cca4f BS |
387 | int dma_chann; |
388 | /* Controller's identification */ | |
389 | uint8_t version; | |
390 | /* HW */ | |
8c6a4d77 BS |
391 | uint8_t sra; |
392 | uint8_t srb; | |
368df94d | 393 | uint8_t dor; |
d7a6c270 | 394 | uint8_t dor_vmstate; /* only used as temp during vmstate */ |
46d3233b | 395 | uint8_t tdr; |
b9b3d225 | 396 | uint8_t dsr; |
368df94d | 397 | uint8_t msr; |
8977f3c1 | 398 | uint8_t cur_drv; |
77370520 BS |
399 | uint8_t status0; |
400 | uint8_t status1; | |
401 | uint8_t status2; | |
8977f3c1 | 402 | /* Command FIFO */ |
33f00271 | 403 | uint8_t *fifo; |
d7a6c270 | 404 | int32_t fifo_size; |
8977f3c1 FB |
405 | uint32_t data_pos; |
406 | uint32_t data_len; | |
407 | uint8_t data_state; | |
408 | uint8_t data_dir; | |
890fa6be | 409 | uint8_t eot; /* last wanted sector */ |
8977f3c1 | 410 | /* States kept only to be returned back */ |
8977f3c1 FB |
411 | /* precompensation */ |
412 | uint8_t precomp_trk; | |
413 | uint8_t config; | |
414 | uint8_t lock; | |
415 | /* Power down config (also with status regB access mode */ | |
416 | uint8_t pwrd; | |
417 | /* Floppy drives */ | |
d7a6c270 | 418 | uint8_t num_floppies; |
242cca4f BS |
419 | /* Sun4m quirks? */ |
420 | int sun4m; | |
5c02c033 | 421 | FDrive drives[MAX_FD]; |
f2d81b33 | 422 | int reset_sensei; |
09c6d585 | 423 | uint32_t check_media_rate; |
242cca4f BS |
424 | /* Timers state */ |
425 | uint8_t timer0; | |
426 | uint8_t timer1; | |
baca51fa FB |
427 | }; |
428 | ||
5c02c033 | 429 | typedef struct FDCtrlSysBus { |
8baf73ad | 430 | SysBusDevice busdev; |
5c02c033 BS |
431 | struct FDCtrl state; |
432 | } FDCtrlSysBus; | |
8baf73ad | 433 | |
5c02c033 | 434 | typedef struct FDCtrlISABus { |
8baf73ad | 435 | ISADevice busdev; |
5c02c033 | 436 | struct FDCtrl state; |
1ca4d09a GN |
437 | int32_t bootindexA; |
438 | int32_t bootindexB; | |
5c02c033 | 439 | } FDCtrlISABus; |
8baf73ad | 440 | |
baca51fa FB |
441 | static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
442 | { | |
5c02c033 | 443 | FDCtrl *fdctrl = opaque; |
baca51fa FB |
444 | uint32_t retval; |
445 | ||
a18e67f5 | 446 | reg &= 7; |
e64d7d59 | 447 | switch (reg) { |
8c6a4d77 BS |
448 | case FD_REG_SRA: |
449 | retval = fdctrl_read_statusA(fdctrl); | |
4f431960 | 450 | break; |
8c6a4d77 | 451 | case FD_REG_SRB: |
4f431960 JM |
452 | retval = fdctrl_read_statusB(fdctrl); |
453 | break; | |
9fea808a | 454 | case FD_REG_DOR: |
4f431960 JM |
455 | retval = fdctrl_read_dor(fdctrl); |
456 | break; | |
9fea808a | 457 | case FD_REG_TDR: |
baca51fa | 458 | retval = fdctrl_read_tape(fdctrl); |
4f431960 | 459 | break; |
9fea808a | 460 | case FD_REG_MSR: |
baca51fa | 461 | retval = fdctrl_read_main_status(fdctrl); |
4f431960 | 462 | break; |
9fea808a | 463 | case FD_REG_FIFO: |
baca51fa | 464 | retval = fdctrl_read_data(fdctrl); |
4f431960 | 465 | break; |
9fea808a | 466 | case FD_REG_DIR: |
baca51fa | 467 | retval = fdctrl_read_dir(fdctrl); |
4f431960 | 468 | break; |
a541f297 | 469 | default: |
4f431960 JM |
470 | retval = (uint32_t)(-1); |
471 | break; | |
a541f297 | 472 | } |
ed5fd2cc | 473 | FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
baca51fa FB |
474 | |
475 | return retval; | |
476 | } | |
477 | ||
478 | static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) | |
479 | { | |
5c02c033 | 480 | FDCtrl *fdctrl = opaque; |
baca51fa | 481 | |
ed5fd2cc FB |
482 | FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
483 | ||
a18e67f5 | 484 | reg &= 7; |
e64d7d59 | 485 | switch (reg) { |
9fea808a | 486 | case FD_REG_DOR: |
4f431960 JM |
487 | fdctrl_write_dor(fdctrl, value); |
488 | break; | |
9fea808a | 489 | case FD_REG_TDR: |
baca51fa | 490 | fdctrl_write_tape(fdctrl, value); |
4f431960 | 491 | break; |
9fea808a | 492 | case FD_REG_DSR: |
baca51fa | 493 | fdctrl_write_rate(fdctrl, value); |
4f431960 | 494 | break; |
9fea808a | 495 | case FD_REG_FIFO: |
baca51fa | 496 | fdctrl_write_data(fdctrl, value); |
4f431960 | 497 | break; |
a758f8f4 HP |
498 | case FD_REG_CCR: |
499 | fdctrl_write_ccr(fdctrl, value); | |
500 | break; | |
a541f297 | 501 | default: |
4f431960 | 502 | break; |
a541f297 | 503 | } |
baca51fa FB |
504 | } |
505 | ||
dc6c1b37 AK |
506 | static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg, |
507 | unsigned ize) | |
62a46c61 | 508 | { |
5dcb6b91 | 509 | return fdctrl_read(opaque, (uint32_t)reg); |
62a46c61 FB |
510 | } |
511 | ||
dc6c1b37 AK |
512 | static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg, |
513 | uint64_t value, unsigned size) | |
62a46c61 | 514 | { |
5dcb6b91 | 515 | fdctrl_write(opaque, (uint32_t)reg, value); |
62a46c61 FB |
516 | } |
517 | ||
dc6c1b37 AK |
518 | static const MemoryRegionOps fdctrl_mem_ops = { |
519 | .read = fdctrl_read_mem, | |
520 | .write = fdctrl_write_mem, | |
521 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e80cfcfc FB |
522 | }; |
523 | ||
dc6c1b37 AK |
524 | static const MemoryRegionOps fdctrl_mem_strict_ops = { |
525 | .read = fdctrl_read_mem, | |
526 | .write = fdctrl_write_mem, | |
527 | .endianness = DEVICE_NATIVE_ENDIAN, | |
528 | .valid = { | |
529 | .min_access_size = 1, | |
530 | .max_access_size = 1, | |
531 | }, | |
7c560456 BS |
532 | }; |
533 | ||
7d905f71 JW |
534 | static bool fdrive_media_changed_needed(void *opaque) |
535 | { | |
536 | FDrive *drive = opaque; | |
537 | ||
8e49ca46 | 538 | return (drive->bs != NULL && drive->media_changed != 1); |
7d905f71 JW |
539 | } |
540 | ||
541 | static const VMStateDescription vmstate_fdrive_media_changed = { | |
542 | .name = "fdrive/media_changed", | |
543 | .version_id = 1, | |
544 | .minimum_version_id = 1, | |
545 | .minimum_version_id_old = 1, | |
7d905f71 JW |
546 | .fields = (VMStateField[]) { |
547 | VMSTATE_UINT8(media_changed, FDrive), | |
548 | VMSTATE_END_OF_LIST() | |
549 | } | |
550 | }; | |
551 | ||
d7a6c270 JQ |
552 | static const VMStateDescription vmstate_fdrive = { |
553 | .name = "fdrive", | |
554 | .version_id = 1, | |
555 | .minimum_version_id = 1, | |
556 | .minimum_version_id_old = 1, | |
7d905f71 | 557 | .fields = (VMStateField[]) { |
5c02c033 BS |
558 | VMSTATE_UINT8(head, FDrive), |
559 | VMSTATE_UINT8(track, FDrive), | |
560 | VMSTATE_UINT8(sect, FDrive), | |
d7a6c270 | 561 | VMSTATE_END_OF_LIST() |
7d905f71 JW |
562 | }, |
563 | .subsections = (VMStateSubsection[]) { | |
564 | { | |
565 | .vmsd = &vmstate_fdrive_media_changed, | |
566 | .needed = &fdrive_media_changed_needed, | |
567 | } , { | |
568 | /* empty */ | |
569 | } | |
d7a6c270 JQ |
570 | } |
571 | }; | |
3ccacc4a | 572 | |
d4bfa4d7 | 573 | static void fdc_pre_save(void *opaque) |
3ccacc4a | 574 | { |
5c02c033 | 575 | FDCtrl *s = opaque; |
3ccacc4a | 576 | |
d7a6c270 | 577 | s->dor_vmstate = s->dor | GET_CUR_DRV(s); |
3ccacc4a BS |
578 | } |
579 | ||
e59fb374 | 580 | static int fdc_post_load(void *opaque, int version_id) |
3ccacc4a | 581 | { |
5c02c033 | 582 | FDCtrl *s = opaque; |
3ccacc4a | 583 | |
d7a6c270 JQ |
584 | SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); |
585 | s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; | |
3ccacc4a BS |
586 | return 0; |
587 | } | |
588 | ||
d7a6c270 | 589 | static const VMStateDescription vmstate_fdc = { |
aef30c3c | 590 | .name = "fdc", |
d7a6c270 JQ |
591 | .version_id = 2, |
592 | .minimum_version_id = 2, | |
593 | .minimum_version_id_old = 2, | |
594 | .pre_save = fdc_pre_save, | |
595 | .post_load = fdc_post_load, | |
596 | .fields = (VMStateField []) { | |
597 | /* Controller State */ | |
5c02c033 BS |
598 | VMSTATE_UINT8(sra, FDCtrl), |
599 | VMSTATE_UINT8(srb, FDCtrl), | |
600 | VMSTATE_UINT8(dor_vmstate, FDCtrl), | |
601 | VMSTATE_UINT8(tdr, FDCtrl), | |
602 | VMSTATE_UINT8(dsr, FDCtrl), | |
603 | VMSTATE_UINT8(msr, FDCtrl), | |
604 | VMSTATE_UINT8(status0, FDCtrl), | |
605 | VMSTATE_UINT8(status1, FDCtrl), | |
606 | VMSTATE_UINT8(status2, FDCtrl), | |
d7a6c270 | 607 | /* Command FIFO */ |
8ec68b06 BS |
608 | VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, |
609 | uint8_t), | |
5c02c033 BS |
610 | VMSTATE_UINT32(data_pos, FDCtrl), |
611 | VMSTATE_UINT32(data_len, FDCtrl), | |
612 | VMSTATE_UINT8(data_state, FDCtrl), | |
613 | VMSTATE_UINT8(data_dir, FDCtrl), | |
614 | VMSTATE_UINT8(eot, FDCtrl), | |
d7a6c270 | 615 | /* States kept only to be returned back */ |
5c02c033 BS |
616 | VMSTATE_UINT8(timer0, FDCtrl), |
617 | VMSTATE_UINT8(timer1, FDCtrl), | |
618 | VMSTATE_UINT8(precomp_trk, FDCtrl), | |
619 | VMSTATE_UINT8(config, FDCtrl), | |
620 | VMSTATE_UINT8(lock, FDCtrl), | |
621 | VMSTATE_UINT8(pwrd, FDCtrl), | |
622 | VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), | |
623 | VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, | |
624 | vmstate_fdrive, FDrive), | |
d7a6c270 | 625 | VMSTATE_END_OF_LIST() |
78ae820c | 626 | } |
d7a6c270 | 627 | }; |
3ccacc4a | 628 | |
2be37833 | 629 | static void fdctrl_external_reset_sysbus(DeviceState *d) |
3ccacc4a | 630 | { |
5c02c033 BS |
631 | FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev); |
632 | FDCtrl *s = &sys->state; | |
2be37833 BS |
633 | |
634 | fdctrl_reset(s, 0); | |
635 | } | |
636 | ||
637 | static void fdctrl_external_reset_isa(DeviceState *d) | |
638 | { | |
5c02c033 BS |
639 | FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev); |
640 | FDCtrl *s = &isa->state; | |
3ccacc4a BS |
641 | |
642 | fdctrl_reset(s, 0); | |
643 | } | |
644 | ||
2be17ebd BS |
645 | static void fdctrl_handle_tc(void *opaque, int irq, int level) |
646 | { | |
5c02c033 | 647 | //FDCtrl *s = opaque; |
2be17ebd BS |
648 | |
649 | if (level) { | |
650 | // XXX | |
651 | FLOPPY_DPRINTF("TC pulsed\n"); | |
652 | } | |
653 | } | |
654 | ||
8977f3c1 | 655 | /* Change IRQ state */ |
5c02c033 | 656 | static void fdctrl_reset_irq(FDCtrl *fdctrl) |
8977f3c1 | 657 | { |
8c6a4d77 BS |
658 | if (!(fdctrl->sra & FD_SRA_INTPEND)) |
659 | return; | |
ed5fd2cc | 660 | FLOPPY_DPRINTF("Reset interrupt\n"); |
d537cf6c | 661 | qemu_set_irq(fdctrl->irq, 0); |
8c6a4d77 | 662 | fdctrl->sra &= ~FD_SRA_INTPEND; |
8977f3c1 FB |
663 | } |
664 | ||
5c02c033 | 665 | static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0) |
8977f3c1 | 666 | { |
b9b3d225 BS |
667 | /* Sparc mutation */ |
668 | if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) { | |
669 | /* XXX: not sure */ | |
670 | fdctrl->msr &= ~FD_MSR_CMDBUSY; | |
671 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; | |
77370520 | 672 | fdctrl->status0 = status0; |
4f431960 | 673 | return; |
6f7e9aec | 674 | } |
8c6a4d77 | 675 | if (!(fdctrl->sra & FD_SRA_INTPEND)) { |
d537cf6c | 676 | qemu_set_irq(fdctrl->irq, 1); |
8c6a4d77 | 677 | fdctrl->sra |= FD_SRA_INTPEND; |
8977f3c1 | 678 | } |
f2d81b33 | 679 | fdctrl->reset_sensei = 0; |
77370520 BS |
680 | fdctrl->status0 = status0; |
681 | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); | |
8977f3c1 FB |
682 | } |
683 | ||
4b19ec0c | 684 | /* Reset controller */ |
5c02c033 | 685 | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) |
8977f3c1 FB |
686 | { |
687 | int i; | |
688 | ||
4b19ec0c | 689 | FLOPPY_DPRINTF("reset controller\n"); |
baca51fa | 690 | fdctrl_reset_irq(fdctrl); |
4b19ec0c | 691 | /* Initialise controller */ |
8c6a4d77 BS |
692 | fdctrl->sra = 0; |
693 | fdctrl->srb = 0xc0; | |
694 | if (!fdctrl->drives[1].bs) | |
695 | fdctrl->sra |= FD_SRA_nDRV2; | |
baca51fa | 696 | fdctrl->cur_drv = 0; |
1c346df2 | 697 | fdctrl->dor = FD_DOR_nRESET; |
368df94d | 698 | fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
b9b3d225 | 699 | fdctrl->msr = FD_MSR_RQM; |
8977f3c1 | 700 | /* FIFO state */ |
baca51fa FB |
701 | fdctrl->data_pos = 0; |
702 | fdctrl->data_len = 0; | |
b9b3d225 | 703 | fdctrl->data_state = 0; |
baca51fa | 704 | fdctrl->data_dir = FD_DIR_WRITE; |
8977f3c1 | 705 | for (i = 0; i < MAX_FD; i++) |
1c346df2 | 706 | fd_recalibrate(&fdctrl->drives[i]); |
baca51fa | 707 | fdctrl_reset_fifo(fdctrl); |
77370520 | 708 | if (do_irq) { |
9fea808a | 709 | fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG); |
f2d81b33 | 710 | fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
77370520 | 711 | } |
baca51fa FB |
712 | } |
713 | ||
5c02c033 | 714 | static inline FDrive *drv0(FDCtrl *fdctrl) |
baca51fa | 715 | { |
46d3233b | 716 | return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
baca51fa FB |
717 | } |
718 | ||
5c02c033 | 719 | static inline FDrive *drv1(FDCtrl *fdctrl) |
baca51fa | 720 | { |
46d3233b BS |
721 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
722 | return &fdctrl->drives[1]; | |
723 | else | |
724 | return &fdctrl->drives[0]; | |
baca51fa FB |
725 | } |
726 | ||
78ae820c | 727 | #if MAX_FD == 4 |
5c02c033 | 728 | static inline FDrive *drv2(FDCtrl *fdctrl) |
78ae820c BS |
729 | { |
730 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) | |
731 | return &fdctrl->drives[2]; | |
732 | else | |
733 | return &fdctrl->drives[1]; | |
734 | } | |
735 | ||
5c02c033 | 736 | static inline FDrive *drv3(FDCtrl *fdctrl) |
78ae820c BS |
737 | { |
738 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) | |
739 | return &fdctrl->drives[3]; | |
740 | else | |
741 | return &fdctrl->drives[2]; | |
742 | } | |
743 | #endif | |
744 | ||
5c02c033 | 745 | static FDrive *get_cur_drv(FDCtrl *fdctrl) |
baca51fa | 746 | { |
78ae820c BS |
747 | switch (fdctrl->cur_drv) { |
748 | case 0: return drv0(fdctrl); | |
749 | case 1: return drv1(fdctrl); | |
750 | #if MAX_FD == 4 | |
751 | case 2: return drv2(fdctrl); | |
752 | case 3: return drv3(fdctrl); | |
753 | #endif | |
754 | default: return NULL; | |
755 | } | |
8977f3c1 FB |
756 | } |
757 | ||
8c6a4d77 | 758 | /* Status A register : 0x00 (read-only) */ |
5c02c033 | 759 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) |
8c6a4d77 BS |
760 | { |
761 | uint32_t retval = fdctrl->sra; | |
762 | ||
763 | FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); | |
764 | ||
765 | return retval; | |
766 | } | |
767 | ||
8977f3c1 | 768 | /* Status B register : 0x01 (read-only) */ |
5c02c033 | 769 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) |
8977f3c1 | 770 | { |
8c6a4d77 BS |
771 | uint32_t retval = fdctrl->srb; |
772 | ||
773 | FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); | |
774 | ||
775 | return retval; | |
8977f3c1 FB |
776 | } |
777 | ||
778 | /* Digital output register : 0x02 */ | |
5c02c033 | 779 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) |
8977f3c1 | 780 | { |
1c346df2 | 781 | uint32_t retval = fdctrl->dor; |
8977f3c1 | 782 | |
8977f3c1 | 783 | /* Selected drive */ |
baca51fa | 784 | retval |= fdctrl->cur_drv; |
8977f3c1 FB |
785 | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); |
786 | ||
787 | return retval; | |
788 | } | |
789 | ||
5c02c033 | 790 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 791 | { |
8977f3c1 | 792 | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); |
8c6a4d77 BS |
793 | |
794 | /* Motors */ | |
795 | if (value & FD_DOR_MOTEN0) | |
796 | fdctrl->srb |= FD_SRB_MTR0; | |
797 | else | |
798 | fdctrl->srb &= ~FD_SRB_MTR0; | |
799 | if (value & FD_DOR_MOTEN1) | |
800 | fdctrl->srb |= FD_SRB_MTR1; | |
801 | else | |
802 | fdctrl->srb &= ~FD_SRB_MTR1; | |
803 | ||
804 | /* Drive */ | |
805 | if (value & 1) | |
806 | fdctrl->srb |= FD_SRB_DR0; | |
807 | else | |
808 | fdctrl->srb &= ~FD_SRB_DR0; | |
809 | ||
8977f3c1 | 810 | /* Reset */ |
9fea808a | 811 | if (!(value & FD_DOR_nRESET)) { |
1c346df2 | 812 | if (fdctrl->dor & FD_DOR_nRESET) { |
4b19ec0c | 813 | FLOPPY_DPRINTF("controller enter RESET state\n"); |
8977f3c1 FB |
814 | } |
815 | } else { | |
1c346df2 | 816 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 817 | FLOPPY_DPRINTF("controller out of RESET state\n"); |
fb6cf1d0 | 818 | fdctrl_reset(fdctrl, 1); |
b9b3d225 | 819 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
8977f3c1 FB |
820 | } |
821 | } | |
822 | /* Selected drive */ | |
9fea808a | 823 | fdctrl->cur_drv = value & FD_DOR_SELMASK; |
368df94d BS |
824 | |
825 | fdctrl->dor = value; | |
8977f3c1 FB |
826 | } |
827 | ||
828 | /* Tape drive register : 0x03 */ | |
5c02c033 | 829 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) |
8977f3c1 | 830 | { |
46d3233b | 831 | uint32_t retval = fdctrl->tdr; |
8977f3c1 | 832 | |
8977f3c1 FB |
833 | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); |
834 | ||
835 | return retval; | |
836 | } | |
837 | ||
5c02c033 | 838 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 839 | { |
8977f3c1 | 840 | /* Reset mode */ |
1c346df2 | 841 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 842 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
843 | return; |
844 | } | |
845 | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); | |
846 | /* Disk boot selection indicator */ | |
46d3233b | 847 | fdctrl->tdr = value & FD_TDR_BOOTSEL; |
8977f3c1 FB |
848 | /* Tape indicators: never allow */ |
849 | } | |
850 | ||
851 | /* Main status register : 0x04 (read) */ | |
5c02c033 | 852 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) |
8977f3c1 | 853 | { |
b9b3d225 | 854 | uint32_t retval = fdctrl->msr; |
8977f3c1 | 855 | |
b9b3d225 | 856 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1c346df2 | 857 | fdctrl->dor |= FD_DOR_nRESET; |
b9b3d225 | 858 | |
82407d1a AT |
859 | /* Sparc mutation */ |
860 | if (fdctrl->sun4m) { | |
861 | retval |= FD_MSR_DIO; | |
862 | fdctrl_reset_irq(fdctrl); | |
863 | }; | |
864 | ||
8977f3c1 FB |
865 | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); |
866 | ||
867 | return retval; | |
868 | } | |
869 | ||
870 | /* Data select rate register : 0x04 (write) */ | |
5c02c033 | 871 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 872 | { |
8977f3c1 | 873 | /* Reset mode */ |
1c346df2 | 874 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4f431960 JM |
875 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
876 | return; | |
877 | } | |
8977f3c1 FB |
878 | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); |
879 | /* Reset: autoclear */ | |
9fea808a | 880 | if (value & FD_DSR_SWRESET) { |
1c346df2 | 881 | fdctrl->dor &= ~FD_DOR_nRESET; |
baca51fa | 882 | fdctrl_reset(fdctrl, 1); |
1c346df2 | 883 | fdctrl->dor |= FD_DOR_nRESET; |
8977f3c1 | 884 | } |
9fea808a | 885 | if (value & FD_DSR_PWRDOWN) { |
baca51fa | 886 | fdctrl_reset(fdctrl, 1); |
8977f3c1 | 887 | } |
b9b3d225 | 888 | fdctrl->dsr = value; |
8977f3c1 FB |
889 | } |
890 | ||
a758f8f4 HP |
891 | /* Configuration control register: 0x07 (write) */ |
892 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) | |
893 | { | |
894 | /* Reset mode */ | |
895 | if (!(fdctrl->dor & FD_DOR_nRESET)) { | |
896 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); | |
897 | return; | |
898 | } | |
899 | FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); | |
900 | ||
901 | /* Only the rate selection bits used in AT mode, and we | |
902 | * store those in the DSR. | |
903 | */ | |
904 | fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | | |
905 | (value & FD_DSR_DRATEMASK); | |
906 | } | |
907 | ||
5c02c033 | 908 | static int fdctrl_media_changed(FDrive *drv) |
ea185bbd FB |
909 | { |
910 | int ret; | |
4f431960 | 911 | |
5fafdf24 | 912 | if (!drv->bs) |
ea185bbd | 913 | return 0; |
18d90055 MA |
914 | if (drv->media_changed) { |
915 | drv->media_changed = 0; | |
916 | ret = 1; | |
917 | } else { | |
918 | ret = bdrv_media_changed(drv->bs); | |
919 | if (ret < 0) { | |
920 | ret = 0; /* we don't know, assume no */ | |
921 | } | |
8e49ca46 | 922 | } |
ea185bbd FB |
923 | if (ret) { |
924 | fd_revalidate(drv); | |
925 | } | |
926 | return ret; | |
927 | } | |
928 | ||
8977f3c1 | 929 | /* Digital input register : 0x07 (read-only) */ |
5c02c033 | 930 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) |
8977f3c1 | 931 | { |
8977f3c1 FB |
932 | uint32_t retval = 0; |
933 | ||
78ae820c BS |
934 | if (fdctrl_media_changed(drv0(fdctrl)) |
935 | || fdctrl_media_changed(drv1(fdctrl)) | |
936 | #if MAX_FD == 4 | |
937 | || fdctrl_media_changed(drv2(fdctrl)) | |
938 | || fdctrl_media_changed(drv3(fdctrl)) | |
939 | #endif | |
940 | ) | |
9fea808a | 941 | retval |= FD_DIR_DSKCHG; |
3c83eb4f | 942 | if (retval != 0) { |
baca51fa | 943 | FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); |
3c83eb4f | 944 | } |
8977f3c1 FB |
945 | |
946 | return retval; | |
947 | } | |
948 | ||
949 | /* FIFO state control */ | |
5c02c033 | 950 | static void fdctrl_reset_fifo(FDCtrl *fdctrl) |
8977f3c1 | 951 | { |
baca51fa FB |
952 | fdctrl->data_dir = FD_DIR_WRITE; |
953 | fdctrl->data_pos = 0; | |
b9b3d225 | 954 | fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
8977f3c1 FB |
955 | } |
956 | ||
957 | /* Set FIFO status for the host to read */ | |
5c02c033 | 958 | static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq) |
8977f3c1 | 959 | { |
baca51fa FB |
960 | fdctrl->data_dir = FD_DIR_READ; |
961 | fdctrl->data_len = fifo_len; | |
962 | fdctrl->data_pos = 0; | |
b9b3d225 | 963 | fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
8977f3c1 | 964 | if (do_irq) |
baca51fa | 965 | fdctrl_raise_irq(fdctrl, 0x00); |
8977f3c1 FB |
966 | } |
967 | ||
968 | /* Set an error: unimplemented/unknown command */ | |
5c02c033 | 969 | static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) |
8977f3c1 | 970 | { |
77370520 | 971 | FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); |
9fea808a | 972 | fdctrl->fifo[0] = FD_SR0_INVCMD; |
baca51fa | 973 | fdctrl_set_fifo(fdctrl, 1, 0); |
8977f3c1 FB |
974 | } |
975 | ||
746d6de7 | 976 | /* Seek to next sector */ |
5c02c033 | 977 | static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) |
746d6de7 BS |
978 | { |
979 | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", | |
980 | cur_drv->head, cur_drv->track, cur_drv->sect, | |
981 | fd_sector(cur_drv)); | |
982 | /* XXX: cur_drv->sect >= cur_drv->last_sect should be an | |
983 | error in fact */ | |
984 | if (cur_drv->sect >= cur_drv->last_sect || | |
985 | cur_drv->sect == fdctrl->eot) { | |
986 | cur_drv->sect = 1; | |
987 | if (FD_MULTI_TRACK(fdctrl->data_state)) { | |
988 | if (cur_drv->head == 0 && | |
989 | (cur_drv->flags & FDISK_DBL_SIDES) != 0) { | |
990 | cur_drv->head = 1; | |
991 | } else { | |
992 | cur_drv->head = 0; | |
993 | cur_drv->track++; | |
994 | if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) | |
995 | return 0; | |
996 | } | |
997 | } else { | |
998 | cur_drv->track++; | |
999 | return 0; | |
1000 | } | |
1001 | FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", | |
1002 | cur_drv->head, cur_drv->track, | |
1003 | cur_drv->sect, fd_sector(cur_drv)); | |
1004 | } else { | |
1005 | cur_drv->sect++; | |
1006 | } | |
1007 | return 1; | |
1008 | } | |
1009 | ||
8977f3c1 | 1010 | /* Callback for transfer end (stop or abort) */ |
5c02c033 BS |
1011 | static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, |
1012 | uint8_t status1, uint8_t status2) | |
8977f3c1 | 1013 | { |
5c02c033 | 1014 | FDrive *cur_drv; |
8977f3c1 | 1015 | |
baca51fa | 1016 | cur_drv = get_cur_drv(fdctrl); |
8977f3c1 FB |
1017 | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", |
1018 | status0, status1, status2, | |
cefec4f5 BS |
1019 | status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl)); |
1020 | fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); | |
baca51fa FB |
1021 | fdctrl->fifo[1] = status1; |
1022 | fdctrl->fifo[2] = status2; | |
1023 | fdctrl->fifo[3] = cur_drv->track; | |
1024 | fdctrl->fifo[4] = cur_drv->head; | |
1025 | fdctrl->fifo[5] = cur_drv->sect; | |
1026 | fdctrl->fifo[6] = FD_SECTOR_SC; | |
1027 | fdctrl->data_dir = FD_DIR_READ; | |
368df94d | 1028 | if (!(fdctrl->msr & FD_MSR_NONDMA)) { |
baca51fa | 1029 | DMA_release_DREQ(fdctrl->dma_chann); |
ed5fd2cc | 1030 | } |
b9b3d225 | 1031 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
368df94d | 1032 | fdctrl->msr &= ~FD_MSR_NONDMA; |
baca51fa | 1033 | fdctrl_set_fifo(fdctrl, 7, 1); |
8977f3c1 FB |
1034 | } |
1035 | ||
1036 | /* Prepare a data transfer (either DMA or FIFO) */ | |
5c02c033 | 1037 | static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1038 | { |
5c02c033 | 1039 | FDrive *cur_drv; |
8977f3c1 | 1040 | uint8_t kh, kt, ks; |
77370520 | 1041 | int did_seek = 0; |
8977f3c1 | 1042 | |
cefec4f5 | 1043 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1044 | cur_drv = get_cur_drv(fdctrl); |
1045 | kt = fdctrl->fifo[2]; | |
1046 | kh = fdctrl->fifo[3]; | |
1047 | ks = fdctrl->fifo[4]; | |
4b19ec0c | 1048 | FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", |
cefec4f5 | 1049 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1050 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1051 | NUM_SIDES(cur_drv))); | |
77370520 | 1052 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
8977f3c1 FB |
1053 | case 2: |
1054 | /* sect too big */ | |
9fea808a | 1055 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1056 | fdctrl->fifo[3] = kt; |
1057 | fdctrl->fifo[4] = kh; | |
1058 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1059 | return; |
1060 | case 3: | |
1061 | /* track too big */ | |
77370520 | 1062 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1063 | fdctrl->fifo[3] = kt; |
1064 | fdctrl->fifo[4] = kh; | |
1065 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1066 | return; |
1067 | case 4: | |
1068 | /* No seek enabled */ | |
9fea808a | 1069 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1070 | fdctrl->fifo[3] = kt; |
1071 | fdctrl->fifo[4] = kh; | |
1072 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1073 | return; |
1074 | case 1: | |
1075 | did_seek = 1; | |
1076 | break; | |
1077 | default: | |
1078 | break; | |
1079 | } | |
b9b3d225 | 1080 | |
8977f3c1 | 1081 | /* Set the FIFO state */ |
baca51fa FB |
1082 | fdctrl->data_dir = direction; |
1083 | fdctrl->data_pos = 0; | |
b9b3d225 | 1084 | fdctrl->msr |= FD_MSR_CMDBUSY; |
baca51fa FB |
1085 | if (fdctrl->fifo[0] & 0x80) |
1086 | fdctrl->data_state |= FD_STATE_MULTI; | |
1087 | else | |
1088 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
8977f3c1 | 1089 | if (did_seek) |
baca51fa FB |
1090 | fdctrl->data_state |= FD_STATE_SEEK; |
1091 | else | |
1092 | fdctrl->data_state &= ~FD_STATE_SEEK; | |
1093 | if (fdctrl->fifo[5] == 00) { | |
1094 | fdctrl->data_len = fdctrl->fifo[8]; | |
1095 | } else { | |
4f431960 | 1096 | int tmp; |
3bcb80f1 | 1097 | fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
771effeb | 1098 | tmp = (fdctrl->fifo[6] - ks + 1); |
baca51fa | 1099 | if (fdctrl->fifo[0] & 0x80) |
771effeb | 1100 | tmp += fdctrl->fifo[6]; |
4f431960 | 1101 | fdctrl->data_len *= tmp; |
baca51fa | 1102 | } |
890fa6be | 1103 | fdctrl->eot = fdctrl->fifo[6]; |
368df94d | 1104 | if (fdctrl->dor & FD_DOR_DMAEN) { |
8977f3c1 FB |
1105 | int dma_mode; |
1106 | /* DMA transfer are enabled. Check if DMA channel is well programmed */ | |
baca51fa | 1107 | dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
8977f3c1 | 1108 | dma_mode = (dma_mode >> 2) & 3; |
baca51fa | 1109 | FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", |
4f431960 | 1110 | dma_mode, direction, |
baca51fa | 1111 | (128 << fdctrl->fifo[5]) * |
4f431960 | 1112 | (cur_drv->last_sect - ks + 1), fdctrl->data_len); |
8977f3c1 FB |
1113 | if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || |
1114 | direction == FD_DIR_SCANH) && dma_mode == 0) || | |
1115 | (direction == FD_DIR_WRITE && dma_mode == 2) || | |
1116 | (direction == FD_DIR_READ && dma_mode == 1)) { | |
1117 | /* No access is allowed until DMA transfer has completed */ | |
b9b3d225 | 1118 | fdctrl->msr &= ~FD_MSR_RQM; |
4b19ec0c | 1119 | /* Now, we just have to wait for the DMA controller to |
8977f3c1 FB |
1120 | * recall us... |
1121 | */ | |
baca51fa FB |
1122 | DMA_hold_DREQ(fdctrl->dma_chann); |
1123 | DMA_schedule(fdctrl->dma_chann); | |
8977f3c1 | 1124 | return; |
baca51fa | 1125 | } else { |
4f431960 | 1126 | FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction); |
8977f3c1 FB |
1127 | } |
1128 | } | |
1129 | FLOPPY_DPRINTF("start non-DMA transfer\n"); | |
368df94d | 1130 | fdctrl->msr |= FD_MSR_NONDMA; |
b9b3d225 BS |
1131 | if (direction != FD_DIR_WRITE) |
1132 | fdctrl->msr |= FD_MSR_DIO; | |
8977f3c1 | 1133 | /* IO based transfer: calculate len */ |
baca51fa | 1134 | fdctrl_raise_irq(fdctrl, 0x00); |
8977f3c1 FB |
1135 | |
1136 | return; | |
1137 | } | |
1138 | ||
1139 | /* Prepare a transfer of deleted data */ | |
5c02c033 | 1140 | static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1141 | { |
77370520 BS |
1142 | FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n"); |
1143 | ||
8977f3c1 FB |
1144 | /* We don't handle deleted data, |
1145 | * so we don't return *ANYTHING* | |
1146 | */ | |
9fea808a | 1147 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
8977f3c1 FB |
1148 | } |
1149 | ||
1150 | /* handlers for DMA transfers */ | |
85571bc7 FB |
1151 | static int fdctrl_transfer_handler (void *opaque, int nchan, |
1152 | int dma_pos, int dma_len) | |
8977f3c1 | 1153 | { |
5c02c033 BS |
1154 | FDCtrl *fdctrl; |
1155 | FDrive *cur_drv; | |
baca51fa | 1156 | int len, start_pos, rel_pos; |
8977f3c1 FB |
1157 | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
1158 | ||
baca51fa | 1159 | fdctrl = opaque; |
b9b3d225 | 1160 | if (fdctrl->msr & FD_MSR_RQM) { |
8977f3c1 FB |
1161 | FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); |
1162 | return 0; | |
1163 | } | |
baca51fa FB |
1164 | cur_drv = get_cur_drv(fdctrl); |
1165 | if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || | |
1166 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1167 | status2 = FD_SR2_SNS; |
85571bc7 FB |
1168 | if (dma_len > fdctrl->data_len) |
1169 | dma_len = fdctrl->data_len; | |
890fa6be | 1170 | if (cur_drv->bs == NULL) { |
4f431960 | 1171 | if (fdctrl->data_dir == FD_DIR_WRITE) |
9fea808a | 1172 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
4f431960 | 1173 | else |
9fea808a | 1174 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
4f431960 | 1175 | len = 0; |
890fa6be FB |
1176 | goto transfer_error; |
1177 | } | |
baca51fa | 1178 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
85571bc7 FB |
1179 | for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { |
1180 | len = dma_len - fdctrl->data_pos; | |
baca51fa FB |
1181 | if (len + rel_pos > FD_SECTOR_LEN) |
1182 | len = FD_SECTOR_LEN - rel_pos; | |
6f7e9aec FB |
1183 | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " |
1184 | "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, | |
cefec4f5 | 1185 | fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
baca51fa | 1186 | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
9fea808a | 1187 | fd_sector(cur_drv) * FD_SECTOR_LEN); |
baca51fa | 1188 | if (fdctrl->data_dir != FD_DIR_WRITE || |
4f431960 | 1189 | len < FD_SECTOR_LEN || rel_pos != 0) { |
baca51fa FB |
1190 | /* READ & SCAN commands and realign to a sector for WRITE */ |
1191 | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), | |
4f431960 | 1192 | fdctrl->fifo, 1) < 0) { |
8977f3c1 FB |
1193 | FLOPPY_DPRINTF("Floppy: error getting sector %d\n", |
1194 | fd_sector(cur_drv)); | |
1195 | /* Sure, image size is too small... */ | |
baca51fa | 1196 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); |
8977f3c1 | 1197 | } |
890fa6be | 1198 | } |
4f431960 JM |
1199 | switch (fdctrl->data_dir) { |
1200 | case FD_DIR_READ: | |
1201 | /* READ commands */ | |
85571bc7 FB |
1202 | DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
1203 | fdctrl->data_pos, len); | |
4f431960 JM |
1204 | break; |
1205 | case FD_DIR_WRITE: | |
baca51fa | 1206 | /* WRITE commands */ |
8510854e HP |
1207 | if (cur_drv->ro) { |
1208 | /* Handle readonly medium early, no need to do DMA, touch the | |
1209 | * LED or attempt any writes. A real floppy doesn't attempt | |
1210 | * to write to readonly media either. */ | |
1211 | fdctrl_stop_transfer(fdctrl, | |
1212 | FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, | |
1213 | 0x00); | |
1214 | goto transfer_error; | |
1215 | } | |
1216 | ||
85571bc7 FB |
1217 | DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
1218 | fdctrl->data_pos, len); | |
baca51fa | 1219 | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), |
4f431960 | 1220 | fdctrl->fifo, 1) < 0) { |
77370520 | 1221 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv)); |
9fea808a | 1222 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1223 | goto transfer_error; |
890fa6be | 1224 | } |
4f431960 JM |
1225 | break; |
1226 | default: | |
1227 | /* SCAN commands */ | |
baca51fa | 1228 | { |
4f431960 | 1229 | uint8_t tmpbuf[FD_SECTOR_LEN]; |
baca51fa | 1230 | int ret; |
85571bc7 | 1231 | DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
baca51fa | 1232 | ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
8977f3c1 | 1233 | if (ret == 0) { |
77370520 | 1234 | status2 = FD_SR2_SEH; |
8977f3c1 FB |
1235 | goto end_transfer; |
1236 | } | |
baca51fa FB |
1237 | if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1238 | (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { | |
8977f3c1 FB |
1239 | status2 = 0x00; |
1240 | goto end_transfer; | |
1241 | } | |
1242 | } | |
4f431960 | 1243 | break; |
8977f3c1 | 1244 | } |
4f431960 JM |
1245 | fdctrl->data_pos += len; |
1246 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; | |
baca51fa | 1247 | if (rel_pos == 0) { |
8977f3c1 | 1248 | /* Seek to next sector */ |
746d6de7 BS |
1249 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) |
1250 | break; | |
8977f3c1 FB |
1251 | } |
1252 | } | |
4f431960 | 1253 | end_transfer: |
baca51fa FB |
1254 | len = fdctrl->data_pos - start_pos; |
1255 | FLOPPY_DPRINTF("end transfer %d %d %d\n", | |
4f431960 | 1256 | fdctrl->data_pos, len, fdctrl->data_len); |
baca51fa FB |
1257 | if (fdctrl->data_dir == FD_DIR_SCANE || |
1258 | fdctrl->data_dir == FD_DIR_SCANL || | |
1259 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1260 | status2 = FD_SR2_SEH; |
baca51fa | 1261 | if (FD_DID_SEEK(fdctrl->data_state)) |
9fea808a | 1262 | status0 |= FD_SR0_SEEK; |
baca51fa | 1263 | fdctrl->data_len -= len; |
890fa6be | 1264 | fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
4f431960 | 1265 | transfer_error: |
8977f3c1 | 1266 | |
baca51fa | 1267 | return len; |
8977f3c1 FB |
1268 | } |
1269 | ||
8977f3c1 | 1270 | /* Data register : 0x05 */ |
5c02c033 | 1271 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl) |
8977f3c1 | 1272 | { |
5c02c033 | 1273 | FDrive *cur_drv; |
8977f3c1 | 1274 | uint32_t retval = 0; |
746d6de7 | 1275 | int pos; |
8977f3c1 | 1276 | |
baca51fa | 1277 | cur_drv = get_cur_drv(fdctrl); |
b9b3d225 BS |
1278 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1279 | if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { | |
1280 | FLOPPY_ERROR("controller not ready for reading\n"); | |
8977f3c1 FB |
1281 | return 0; |
1282 | } | |
baca51fa | 1283 | pos = fdctrl->data_pos; |
368df94d | 1284 | if (fdctrl->msr & FD_MSR_NONDMA) { |
8977f3c1 FB |
1285 | pos %= FD_SECTOR_LEN; |
1286 | if (pos == 0) { | |
746d6de7 BS |
1287 | if (fdctrl->data_pos != 0) |
1288 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { | |
1289 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
1290 | fd_sector(cur_drv)); | |
1291 | return 0; | |
1292 | } | |
77370520 BS |
1293 | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1294 | FLOPPY_DPRINTF("error getting sector %d\n", | |
1295 | fd_sector(cur_drv)); | |
1296 | /* Sure, image size is too small... */ | |
1297 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
1298 | } | |
8977f3c1 FB |
1299 | } |
1300 | } | |
baca51fa FB |
1301 | retval = fdctrl->fifo[pos]; |
1302 | if (++fdctrl->data_pos == fdctrl->data_len) { | |
1303 | fdctrl->data_pos = 0; | |
890fa6be | 1304 | /* Switch from transfer mode to status mode |
8977f3c1 FB |
1305 | * then from status mode to command mode |
1306 | */ | |
368df94d | 1307 | if (fdctrl->msr & FD_MSR_NONDMA) { |
9fea808a | 1308 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
ed5fd2cc | 1309 | } else { |
baca51fa | 1310 | fdctrl_reset_fifo(fdctrl); |
ed5fd2cc FB |
1311 | fdctrl_reset_irq(fdctrl); |
1312 | } | |
8977f3c1 FB |
1313 | } |
1314 | FLOPPY_DPRINTF("data register: 0x%02x\n", retval); | |
1315 | ||
1316 | return retval; | |
1317 | } | |
1318 | ||
5c02c033 | 1319 | static void fdctrl_format_sector(FDCtrl *fdctrl) |
8977f3c1 | 1320 | { |
5c02c033 | 1321 | FDrive *cur_drv; |
baca51fa | 1322 | uint8_t kh, kt, ks; |
8977f3c1 | 1323 | |
cefec4f5 | 1324 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1325 | cur_drv = get_cur_drv(fdctrl); |
1326 | kt = fdctrl->fifo[6]; | |
1327 | kh = fdctrl->fifo[7]; | |
1328 | ks = fdctrl->fifo[8]; | |
1329 | FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", | |
cefec4f5 | 1330 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1331 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1332 | NUM_SIDES(cur_drv))); | |
9fea808a | 1333 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
baca51fa FB |
1334 | case 2: |
1335 | /* sect too big */ | |
9fea808a | 1336 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1337 | fdctrl->fifo[3] = kt; |
1338 | fdctrl->fifo[4] = kh; | |
1339 | fdctrl->fifo[5] = ks; | |
1340 | return; | |
1341 | case 3: | |
1342 | /* track too big */ | |
77370520 | 1343 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1344 | fdctrl->fifo[3] = kt; |
1345 | fdctrl->fifo[4] = kh; | |
1346 | fdctrl->fifo[5] = ks; | |
1347 | return; | |
1348 | case 4: | |
1349 | /* No seek enabled */ | |
9fea808a | 1350 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1351 | fdctrl->fifo[3] = kt; |
1352 | fdctrl->fifo[4] = kh; | |
1353 | fdctrl->fifo[5] = ks; | |
1354 | return; | |
1355 | case 1: | |
baca51fa FB |
1356 | fdctrl->data_state |= FD_STATE_SEEK; |
1357 | break; | |
1358 | default: | |
1359 | break; | |
1360 | } | |
1361 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
1362 | if (cur_drv->bs == NULL || | |
1363 | bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { | |
37a4c539 | 1364 | FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv)); |
9fea808a | 1365 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1366 | } else { |
4f431960 JM |
1367 | if (cur_drv->sect == cur_drv->last_sect) { |
1368 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1369 | /* Last sector done */ | |
1370 | if (FD_DID_SEEK(fdctrl->data_state)) | |
9fea808a | 1371 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
4f431960 JM |
1372 | else |
1373 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
1374 | } else { | |
1375 | /* More to do */ | |
1376 | fdctrl->data_pos = 0; | |
1377 | fdctrl->data_len = 4; | |
1378 | } | |
baca51fa FB |
1379 | } |
1380 | } | |
1381 | ||
5c02c033 | 1382 | static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1383 | { |
1384 | fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; | |
1385 | fdctrl->fifo[0] = fdctrl->lock << 4; | |
a005186c | 1386 | fdctrl_set_fifo(fdctrl, 1, 0); |
65cef780 BS |
1387 | } |
1388 | ||
5c02c033 | 1389 | static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) |
65cef780 | 1390 | { |
5c02c033 | 1391 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1392 | |
1393 | /* Drives position */ | |
1394 | fdctrl->fifo[0] = drv0(fdctrl)->track; | |
1395 | fdctrl->fifo[1] = drv1(fdctrl)->track; | |
78ae820c BS |
1396 | #if MAX_FD == 4 |
1397 | fdctrl->fifo[2] = drv2(fdctrl)->track; | |
1398 | fdctrl->fifo[3] = drv3(fdctrl)->track; | |
1399 | #else | |
65cef780 BS |
1400 | fdctrl->fifo[2] = 0; |
1401 | fdctrl->fifo[3] = 0; | |
78ae820c | 1402 | #endif |
65cef780 BS |
1403 | /* timers */ |
1404 | fdctrl->fifo[4] = fdctrl->timer0; | |
368df94d | 1405 | fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
65cef780 BS |
1406 | fdctrl->fifo[6] = cur_drv->last_sect; |
1407 | fdctrl->fifo[7] = (fdctrl->lock << 7) | | |
1408 | (cur_drv->perpendicular << 2); | |
1409 | fdctrl->fifo[8] = fdctrl->config; | |
1410 | fdctrl->fifo[9] = fdctrl->precomp_trk; | |
1411 | fdctrl_set_fifo(fdctrl, 10, 0); | |
1412 | } | |
1413 | ||
5c02c033 | 1414 | static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1415 | { |
1416 | /* Controller's version */ | |
1417 | fdctrl->fifo[0] = fdctrl->version; | |
a005186c | 1418 | fdctrl_set_fifo(fdctrl, 1, 0); |
65cef780 BS |
1419 | } |
1420 | ||
5c02c033 | 1421 | static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1422 | { |
1423 | fdctrl->fifo[0] = 0x41; /* Stepping 1 */ | |
1424 | fdctrl_set_fifo(fdctrl, 1, 0); | |
1425 | } | |
1426 | ||
5c02c033 | 1427 | static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) |
65cef780 | 1428 | { |
5c02c033 | 1429 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1430 | |
1431 | /* Drives position */ | |
1432 | drv0(fdctrl)->track = fdctrl->fifo[3]; | |
1433 | drv1(fdctrl)->track = fdctrl->fifo[4]; | |
78ae820c BS |
1434 | #if MAX_FD == 4 |
1435 | drv2(fdctrl)->track = fdctrl->fifo[5]; | |
1436 | drv3(fdctrl)->track = fdctrl->fifo[6]; | |
1437 | #endif | |
65cef780 BS |
1438 | /* timers */ |
1439 | fdctrl->timer0 = fdctrl->fifo[7]; | |
1440 | fdctrl->timer1 = fdctrl->fifo[8]; | |
1441 | cur_drv->last_sect = fdctrl->fifo[9]; | |
1442 | fdctrl->lock = fdctrl->fifo[10] >> 7; | |
1443 | cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; | |
1444 | fdctrl->config = fdctrl->fifo[11]; | |
1445 | fdctrl->precomp_trk = fdctrl->fifo[12]; | |
1446 | fdctrl->pwrd = fdctrl->fifo[13]; | |
1447 | fdctrl_reset_fifo(fdctrl); | |
1448 | } | |
1449 | ||
5c02c033 | 1450 | static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) |
65cef780 | 1451 | { |
5c02c033 | 1452 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1453 | |
1454 | fdctrl->fifo[0] = 0; | |
1455 | fdctrl->fifo[1] = 0; | |
1456 | /* Drives position */ | |
1457 | fdctrl->fifo[2] = drv0(fdctrl)->track; | |
1458 | fdctrl->fifo[3] = drv1(fdctrl)->track; | |
78ae820c BS |
1459 | #if MAX_FD == 4 |
1460 | fdctrl->fifo[4] = drv2(fdctrl)->track; | |
1461 | fdctrl->fifo[5] = drv3(fdctrl)->track; | |
1462 | #else | |
65cef780 BS |
1463 | fdctrl->fifo[4] = 0; |
1464 | fdctrl->fifo[5] = 0; | |
78ae820c | 1465 | #endif |
65cef780 BS |
1466 | /* timers */ |
1467 | fdctrl->fifo[6] = fdctrl->timer0; | |
1468 | fdctrl->fifo[7] = fdctrl->timer1; | |
1469 | fdctrl->fifo[8] = cur_drv->last_sect; | |
1470 | fdctrl->fifo[9] = (fdctrl->lock << 7) | | |
1471 | (cur_drv->perpendicular << 2); | |
1472 | fdctrl->fifo[10] = fdctrl->config; | |
1473 | fdctrl->fifo[11] = fdctrl->precomp_trk; | |
1474 | fdctrl->fifo[12] = fdctrl->pwrd; | |
1475 | fdctrl->fifo[13] = 0; | |
1476 | fdctrl->fifo[14] = 0; | |
a005186c | 1477 | fdctrl_set_fifo(fdctrl, 15, 0); |
65cef780 BS |
1478 | } |
1479 | ||
5c02c033 | 1480 | static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) |
65cef780 | 1481 | { |
5c02c033 | 1482 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1483 | |
65cef780 BS |
1484 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1485 | qemu_mod_timer(fdctrl->result_timer, | |
74475455 | 1486 | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50)); |
65cef780 BS |
1487 | } |
1488 | ||
5c02c033 | 1489 | static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) |
65cef780 | 1490 | { |
5c02c033 | 1491 | FDrive *cur_drv; |
65cef780 | 1492 | |
cefec4f5 | 1493 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1494 | cur_drv = get_cur_drv(fdctrl); |
1495 | fdctrl->data_state |= FD_STATE_FORMAT; | |
1496 | if (fdctrl->fifo[0] & 0x80) | |
1497 | fdctrl->data_state |= FD_STATE_MULTI; | |
1498 | else | |
1499 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
1500 | fdctrl->data_state &= ~FD_STATE_SEEK; | |
1501 | cur_drv->bps = | |
1502 | fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; | |
1503 | #if 0 | |
1504 | cur_drv->last_sect = | |
1505 | cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : | |
1506 | fdctrl->fifo[3] / 2; | |
1507 | #else | |
1508 | cur_drv->last_sect = fdctrl->fifo[3]; | |
1509 | #endif | |
1510 | /* TODO: implement format using DMA expected by the Bochs BIOS | |
1511 | * and Linux fdformat (read 3 bytes per sector via DMA and fill | |
1512 | * the sector with the specified fill byte | |
1513 | */ | |
1514 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1515 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
1516 | } | |
1517 | ||
5c02c033 | 1518 | static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1519 | { |
1520 | fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; | |
1521 | fdctrl->timer1 = fdctrl->fifo[2] >> 1; | |
368df94d BS |
1522 | if (fdctrl->fifo[2] & 1) |
1523 | fdctrl->dor &= ~FD_DOR_DMAEN; | |
1524 | else | |
1525 | fdctrl->dor |= FD_DOR_DMAEN; | |
65cef780 BS |
1526 | /* No result back */ |
1527 | fdctrl_reset_fifo(fdctrl); | |
1528 | } | |
1529 | ||
5c02c033 | 1530 | static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) |
65cef780 | 1531 | { |
5c02c033 | 1532 | FDrive *cur_drv; |
65cef780 | 1533 | |
cefec4f5 | 1534 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1535 | cur_drv = get_cur_drv(fdctrl); |
1536 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; | |
1537 | /* 1 Byte status back */ | |
1538 | fdctrl->fifo[0] = (cur_drv->ro << 6) | | |
1539 | (cur_drv->track == 0 ? 0x10 : 0x00) | | |
1540 | (cur_drv->head << 2) | | |
cefec4f5 | 1541 | GET_CUR_DRV(fdctrl) | |
65cef780 BS |
1542 | 0x28; |
1543 | fdctrl_set_fifo(fdctrl, 1, 0); | |
1544 | } | |
1545 | ||
5c02c033 | 1546 | static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) |
65cef780 | 1547 | { |
5c02c033 | 1548 | FDrive *cur_drv; |
65cef780 | 1549 | |
cefec4f5 | 1550 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1551 | cur_drv = get_cur_drv(fdctrl); |
1552 | fd_recalibrate(cur_drv); | |
1553 | fdctrl_reset_fifo(fdctrl); | |
1554 | /* Raise Interrupt */ | |
1555 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); | |
1556 | } | |
1557 | ||
5c02c033 | 1558 | static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) |
65cef780 | 1559 | { |
5c02c033 | 1560 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1561 | |
f2d81b33 BS |
1562 | if(fdctrl->reset_sensei > 0) { |
1563 | fdctrl->fifo[0] = | |
1564 | FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; | |
1565 | fdctrl->reset_sensei--; | |
1566 | } else { | |
1567 | /* XXX: status0 handling is broken for read/write | |
1568 | commands, so we do this hack. It should be suppressed | |
1569 | ASAP */ | |
1570 | fdctrl->fifo[0] = | |
1571 | FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); | |
1572 | } | |
1573 | ||
65cef780 BS |
1574 | fdctrl->fifo[1] = cur_drv->track; |
1575 | fdctrl_set_fifo(fdctrl, 2, 0); | |
1576 | fdctrl_reset_irq(fdctrl); | |
77370520 | 1577 | fdctrl->status0 = FD_SR0_RDYCHG; |
65cef780 BS |
1578 | } |
1579 | ||
5c02c033 | 1580 | static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) |
65cef780 | 1581 | { |
5c02c033 | 1582 | FDrive *cur_drv; |
65cef780 | 1583 | |
cefec4f5 | 1584 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1585 | cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1586 | fdctrl_reset_fifo(fdctrl); |
1587 | if (fdctrl->fifo[2] > cur_drv->max_track) { | |
1588 | fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK); | |
1589 | } else { | |
1590 | cur_drv->track = fdctrl->fifo[2]; | |
1591 | /* Raise Interrupt */ | |
1592 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); | |
1593 | } | |
1594 | } | |
1595 | ||
5c02c033 | 1596 | static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) |
65cef780 | 1597 | { |
5c02c033 | 1598 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1599 | |
1600 | if (fdctrl->fifo[1] & 0x80) | |
1601 | cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; | |
1602 | /* No result back */ | |
1c346df2 | 1603 | fdctrl_reset_fifo(fdctrl); |
65cef780 BS |
1604 | } |
1605 | ||
5c02c033 | 1606 | static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1607 | { |
1608 | fdctrl->config = fdctrl->fifo[2]; | |
1609 | fdctrl->precomp_trk = fdctrl->fifo[3]; | |
1610 | /* No result back */ | |
1611 | fdctrl_reset_fifo(fdctrl); | |
1612 | } | |
1613 | ||
5c02c033 | 1614 | static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1615 | { |
1616 | fdctrl->pwrd = fdctrl->fifo[1]; | |
1617 | fdctrl->fifo[0] = fdctrl->fifo[1]; | |
a005186c | 1618 | fdctrl_set_fifo(fdctrl, 1, 0); |
65cef780 BS |
1619 | } |
1620 | ||
5c02c033 | 1621 | static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1622 | { |
1623 | /* No result back */ | |
1624 | fdctrl_reset_fifo(fdctrl); | |
1625 | } | |
1626 | ||
5c02c033 | 1627 | static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) |
65cef780 | 1628 | { |
5c02c033 | 1629 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1630 | |
1631 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { | |
1632 | /* Command parameters done */ | |
1633 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { | |
1634 | fdctrl->fifo[0] = fdctrl->fifo[1]; | |
1635 | fdctrl->fifo[2] = 0; | |
1636 | fdctrl->fifo[3] = 0; | |
a005186c | 1637 | fdctrl_set_fifo(fdctrl, 4, 0); |
65cef780 BS |
1638 | } else { |
1639 | fdctrl_reset_fifo(fdctrl); | |
1640 | } | |
1641 | } else if (fdctrl->data_len > 7) { | |
1642 | /* ERROR */ | |
1643 | fdctrl->fifo[0] = 0x80 | | |
cefec4f5 | 1644 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
a005186c | 1645 | fdctrl_set_fifo(fdctrl, 1, 0); |
65cef780 BS |
1646 | } |
1647 | } | |
1648 | ||
5c02c033 | 1649 | static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) |
65cef780 | 1650 | { |
5c02c033 | 1651 | FDrive *cur_drv; |
65cef780 | 1652 | |
cefec4f5 | 1653 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1654 | cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1655 | if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
1656 | cur_drv->track = cur_drv->max_track - 1; | |
1657 | } else { | |
1658 | cur_drv->track += fdctrl->fifo[2]; | |
1659 | } | |
1660 | fdctrl_reset_fifo(fdctrl); | |
77370520 | 1661 | /* Raise Interrupt */ |
65cef780 BS |
1662 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1663 | } | |
1664 | ||
5c02c033 | 1665 | static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) |
65cef780 | 1666 | { |
5c02c033 | 1667 | FDrive *cur_drv; |
65cef780 | 1668 | |
cefec4f5 | 1669 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1670 | cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1671 | if (fdctrl->fifo[2] > cur_drv->track) { |
1672 | cur_drv->track = 0; | |
1673 | } else { | |
1674 | cur_drv->track -= fdctrl->fifo[2]; | |
1675 | } | |
1676 | fdctrl_reset_fifo(fdctrl); | |
1677 | /* Raise Interrupt */ | |
1678 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); | |
1679 | } | |
1680 | ||
678803ab BS |
1681 | static const struct { |
1682 | uint8_t value; | |
1683 | uint8_t mask; | |
1684 | const char* name; | |
1685 | int parameters; | |
5c02c033 | 1686 | void (*handler)(FDCtrl *fdctrl, int direction); |
678803ab BS |
1687 | int direction; |
1688 | } handlers[] = { | |
1689 | { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, | |
1690 | { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, | |
1691 | { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, | |
1692 | { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, | |
1693 | { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, | |
1694 | { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, | |
1695 | { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, | |
1696 | { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ | |
1697 | { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ | |
1698 | { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, | |
1699 | { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, | |
1700 | { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented }, | |
1701 | { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, | |
1702 | { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, | |
1703 | { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, | |
1704 | { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, | |
1705 | { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, | |
1706 | { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, | |
1707 | { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, | |
1708 | { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, | |
1709 | { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, | |
1710 | { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, | |
1711 | { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, | |
1712 | { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, | |
1713 | { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, | |
1714 | { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, | |
1715 | { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, | |
1716 | { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, | |
1717 | { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, | |
1718 | { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, | |
1719 | { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ | |
1720 | { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ | |
1721 | }; | |
1722 | /* Associate command to an index in the 'handlers' array */ | |
1723 | static uint8_t command_to_handler[256]; | |
1724 | ||
5c02c033 | 1725 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) |
baca51fa | 1726 | { |
5c02c033 | 1727 | FDrive *cur_drv; |
65cef780 | 1728 | int pos; |
baca51fa | 1729 | |
8977f3c1 | 1730 | /* Reset mode */ |
1c346df2 | 1731 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 1732 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
1733 | return; |
1734 | } | |
b9b3d225 BS |
1735 | if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { |
1736 | FLOPPY_ERROR("controller not ready for writing\n"); | |
8977f3c1 FB |
1737 | return; |
1738 | } | |
b9b3d225 | 1739 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
8977f3c1 | 1740 | /* Is it write command time ? */ |
368df94d | 1741 | if (fdctrl->msr & FD_MSR_NONDMA) { |
8977f3c1 | 1742 | /* FIFO data write */ |
b3bc1540 BS |
1743 | pos = fdctrl->data_pos++; |
1744 | pos %= FD_SECTOR_LEN; | |
1745 | fdctrl->fifo[pos] = value; | |
1746 | if (pos == FD_SECTOR_LEN - 1 || | |
baca51fa | 1747 | fdctrl->data_pos == fdctrl->data_len) { |
77370520 BS |
1748 | cur_drv = get_cur_drv(fdctrl); |
1749 | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { | |
1750 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv)); | |
1751 | return; | |
1752 | } | |
746d6de7 BS |
1753 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { |
1754 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
1755 | fd_sector(cur_drv)); | |
1756 | return; | |
1757 | } | |
8977f3c1 | 1758 | } |
890fa6be | 1759 | /* Switch from transfer mode to status mode |
8977f3c1 FB |
1760 | * then from status mode to command mode |
1761 | */ | |
b9b3d225 | 1762 | if (fdctrl->data_pos == fdctrl->data_len) |
9fea808a | 1763 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
8977f3c1 FB |
1764 | return; |
1765 | } | |
baca51fa | 1766 | if (fdctrl->data_pos == 0) { |
8977f3c1 | 1767 | /* Command */ |
678803ab BS |
1768 | pos = command_to_handler[value & 0xff]; |
1769 | FLOPPY_DPRINTF("%s command\n", handlers[pos].name); | |
1770 | fdctrl->data_len = handlers[pos].parameters + 1; | |
1457a758 | 1771 | fdctrl->msr |= FD_MSR_CMDBUSY; |
8977f3c1 | 1772 | } |
678803ab | 1773 | |
baca51fa | 1774 | FLOPPY_DPRINTF("%s: %02x\n", __func__, value); |
77370520 BS |
1775 | fdctrl->fifo[fdctrl->data_pos++] = value; |
1776 | if (fdctrl->data_pos == fdctrl->data_len) { | |
8977f3c1 FB |
1777 | /* We now have all parameters |
1778 | * and will be able to treat the command | |
1779 | */ | |
4f431960 JM |
1780 | if (fdctrl->data_state & FD_STATE_FORMAT) { |
1781 | fdctrl_format_sector(fdctrl); | |
8977f3c1 FB |
1782 | return; |
1783 | } | |
65cef780 | 1784 | |
678803ab BS |
1785 | pos = command_to_handler[fdctrl->fifo[0] & 0xff]; |
1786 | FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name); | |
1787 | (*handlers[pos].handler)(fdctrl, handlers[pos].direction); | |
8977f3c1 FB |
1788 | } |
1789 | } | |
ed5fd2cc FB |
1790 | |
1791 | static void fdctrl_result_timer(void *opaque) | |
1792 | { | |
5c02c033 BS |
1793 | FDCtrl *fdctrl = opaque; |
1794 | FDrive *cur_drv = get_cur_drv(fdctrl); | |
4f431960 | 1795 | |
b7ffa3b1 TS |
1796 | /* Pretend we are spinning. |
1797 | * This is needed for Coherent, which uses READ ID to check for | |
1798 | * sector interleaving. | |
1799 | */ | |
1800 | if (cur_drv->last_sect != 0) { | |
1801 | cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; | |
1802 | } | |
ed5fd2cc FB |
1803 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1804 | } | |
678803ab | 1805 | |
7d4b4ba5 | 1806 | static void fdctrl_change_cb(void *opaque, bool load) |
8e49ca46 MA |
1807 | { |
1808 | FDrive *drive = opaque; | |
1809 | ||
1810 | drive->media_changed = 1; | |
1811 | } | |
1812 | ||
1813 | static const BlockDevOps fdctrl_block_ops = { | |
1814 | .change_media_cb = fdctrl_change_cb, | |
1815 | }; | |
1816 | ||
678803ab | 1817 | /* Init functions */ |
b47b3525 | 1818 | static int fdctrl_connect_drives(FDCtrl *fdctrl) |
678803ab | 1819 | { |
12a71a02 | 1820 | unsigned int i; |
7d0d6950 | 1821 | FDrive *drive; |
678803ab | 1822 | |
678803ab | 1823 | for (i = 0; i < MAX_FD; i++) { |
7d0d6950 MA |
1824 | drive = &fdctrl->drives[i]; |
1825 | ||
b47b3525 MA |
1826 | if (drive->bs) { |
1827 | if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) { | |
1828 | error_report("fdc doesn't support drive option werror"); | |
1829 | return -1; | |
1830 | } | |
1831 | if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) { | |
1832 | error_report("fdc doesn't support drive option rerror"); | |
1833 | return -1; | |
1834 | } | |
1835 | } | |
1836 | ||
7d0d6950 MA |
1837 | fd_init(drive); |
1838 | fd_revalidate(drive); | |
1839 | if (drive->bs) { | |
8e49ca46 | 1840 | drive->media_changed = 1; |
8e49ca46 | 1841 | bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive); |
7d0d6950 | 1842 | } |
678803ab | 1843 | } |
b47b3525 | 1844 | return 0; |
678803ab BS |
1845 | } |
1846 | ||
63ffb564 BS |
1847 | void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, |
1848 | target_phys_addr_t mmio_base, DriveInfo **fds) | |
2091ba23 | 1849 | { |
5c02c033 | 1850 | FDCtrl *fdctrl; |
2091ba23 | 1851 | DeviceState *dev; |
5c02c033 | 1852 | FDCtrlSysBus *sys; |
2091ba23 GH |
1853 | |
1854 | dev = qdev_create(NULL, "sysbus-fdc"); | |
5c02c033 | 1855 | sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
99244fa1 GH |
1856 | fdctrl = &sys->state; |
1857 | fdctrl->dma_chann = dma_chann; /* FIXME */ | |
995bf0ca | 1858 | if (fds[0]) { |
18846dee | 1859 | qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); |
995bf0ca GH |
1860 | } |
1861 | if (fds[1]) { | |
18846dee | 1862 | qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); |
995bf0ca | 1863 | } |
e23a1b33 | 1864 | qdev_init_nofail(dev); |
2091ba23 GH |
1865 | sysbus_connect_irq(&sys->busdev, 0, irq); |
1866 | sysbus_mmio_map(&sys->busdev, 0, mmio_base); | |
678803ab BS |
1867 | } |
1868 | ||
63ffb564 BS |
1869 | void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base, |
1870 | DriveInfo **fds, qemu_irq *fdc_tc) | |
678803ab | 1871 | { |
f64ab228 | 1872 | DeviceState *dev; |
5c02c033 | 1873 | FDCtrlSysBus *sys; |
678803ab | 1874 | |
12a71a02 | 1875 | dev = qdev_create(NULL, "SUNW,fdtwo"); |
995bf0ca | 1876 | if (fds[0]) { |
18846dee | 1877 | qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); |
995bf0ca | 1878 | } |
e23a1b33 | 1879 | qdev_init_nofail(dev); |
5c02c033 | 1880 | sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
8baf73ad GH |
1881 | sysbus_connect_irq(&sys->busdev, 0, irq); |
1882 | sysbus_mmio_map(&sys->busdev, 0, io_base); | |
f64ab228 | 1883 | *fdc_tc = qdev_get_gpio_in(dev, 0); |
678803ab | 1884 | } |
f64ab228 | 1885 | |
a64405d1 | 1886 | static int fdctrl_init_common(FDCtrl *fdctrl) |
f64ab228 | 1887 | { |
12a71a02 BS |
1888 | int i, j; |
1889 | static int command_tables_inited = 0; | |
f64ab228 | 1890 | |
12a71a02 BS |
1891 | /* Fill 'command_to_handler' lookup table */ |
1892 | if (!command_tables_inited) { | |
1893 | command_tables_inited = 1; | |
1894 | for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { | |
1895 | for (j = 0; j < sizeof(command_to_handler); j++) { | |
1896 | if ((j & handlers[i].mask) == handlers[i].value) { | |
1897 | command_to_handler[j] = i; | |
1898 | } | |
1899 | } | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | FLOPPY_DPRINTF("init controller\n"); | |
1904 | fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); | |
d7a6c270 | 1905 | fdctrl->fifo_size = 512; |
74475455 | 1906 | fdctrl->result_timer = qemu_new_timer_ns(vm_clock, |
12a71a02 BS |
1907 | fdctrl_result_timer, fdctrl); |
1908 | ||
1909 | fdctrl->version = 0x90; /* Intel 82078 controller */ | |
1910 | fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ | |
d7a6c270 | 1911 | fdctrl->num_floppies = MAX_FD; |
12a71a02 | 1912 | |
99244fa1 GH |
1913 | if (fdctrl->dma_chann != -1) |
1914 | DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); | |
b47b3525 | 1915 | return fdctrl_connect_drives(fdctrl); |
f64ab228 BS |
1916 | } |
1917 | ||
212ec7ba | 1918 | static const MemoryRegionPortio fdc_portio_list[] = { |
2f290a8c | 1919 | { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, |
212ec7ba RH |
1920 | { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, |
1921 | PORTIO_END_OF_LIST(), | |
2f290a8c RH |
1922 | }; |
1923 | ||
81a322d4 | 1924 | static int isabus_fdc_init1(ISADevice *dev) |
8baf73ad | 1925 | { |
5c02c033 BS |
1926 | FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); |
1927 | FDCtrl *fdctrl = &isa->state; | |
86c86157 | 1928 | int iobase = 0x3f0; |
2e15e23b | 1929 | int isairq = 6; |
99244fa1 | 1930 | int dma_chann = 2; |
2be37833 | 1931 | int ret; |
8baf73ad | 1932 | |
212ec7ba | 1933 | isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc"); |
dee41d58 | 1934 | |
2e15e23b | 1935 | isa_init_irq(&isa->busdev, &fdctrl->irq, isairq); |
99244fa1 | 1936 | fdctrl->dma_chann = dma_chann; |
8baf73ad | 1937 | |
a64405d1 JK |
1938 | qdev_set_legacy_instance_id(&dev->qdev, iobase, 2); |
1939 | ret = fdctrl_init_common(fdctrl); | |
2be37833 | 1940 | |
1ca4d09a GN |
1941 | add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0"); |
1942 | add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1"); | |
1943 | ||
2be37833 | 1944 | return ret; |
8baf73ad GH |
1945 | } |
1946 | ||
81a322d4 | 1947 | static int sysbus_fdc_init1(SysBusDevice *dev) |
12a71a02 | 1948 | { |
5c02c033 BS |
1949 | FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev); |
1950 | FDCtrl *fdctrl = &sys->state; | |
2be37833 | 1951 | int ret; |
12a71a02 | 1952 | |
dc6c1b37 | 1953 | memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08); |
750ecd44 | 1954 | sysbus_init_mmio(dev, &fdctrl->iomem); |
8baf73ad GH |
1955 | sysbus_init_irq(dev, &fdctrl->irq); |
1956 | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); | |
99244fa1 | 1957 | fdctrl->dma_chann = -1; |
8baf73ad | 1958 | |
dc6c1b37 | 1959 | qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ |
a64405d1 | 1960 | ret = fdctrl_init_common(fdctrl); |
2be37833 BS |
1961 | |
1962 | return ret; | |
12a71a02 BS |
1963 | } |
1964 | ||
81a322d4 | 1965 | static int sun4m_fdc_init1(SysBusDevice *dev) |
12a71a02 | 1966 | { |
5c02c033 | 1967 | FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state); |
12a71a02 | 1968 | |
dc6c1b37 AK |
1969 | memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl, |
1970 | "fdctrl", 0x08); | |
750ecd44 | 1971 | sysbus_init_mmio(dev, &fdctrl->iomem); |
8baf73ad GH |
1972 | sysbus_init_irq(dev, &fdctrl->irq); |
1973 | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); | |
1974 | ||
1975 | fdctrl->sun4m = 1; | |
dc6c1b37 | 1976 | qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ |
a64405d1 | 1977 | return fdctrl_init_common(fdctrl); |
12a71a02 | 1978 | } |
f64ab228 | 1979 | |
34d4260e KW |
1980 | void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev) |
1981 | { | |
1982 | FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); | |
1983 | FDCtrl *fdctrl = &isa->state; | |
1984 | int i; | |
1985 | ||
1986 | for (i = 0; i < MAX_FD; i++) { | |
1987 | bs[i] = fdctrl->drives[i].bs; | |
1988 | } | |
1989 | } | |
1990 | ||
1991 | ||
a64405d1 JK |
1992 | static const VMStateDescription vmstate_isa_fdc ={ |
1993 | .name = "fdc", | |
1994 | .version_id = 2, | |
1995 | .minimum_version_id = 2, | |
1996 | .fields = (VMStateField []) { | |
1997 | VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), | |
1998 | VMSTATE_END_OF_LIST() | |
1999 | } | |
2000 | }; | |
2001 | ||
39bffca2 AL |
2002 | static Property isa_fdc_properties[] = { |
2003 | DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), | |
2004 | DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), | |
2005 | DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), | |
2006 | DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), | |
09c6d585 HP |
2007 | DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, |
2008 | 0, true), | |
39bffca2 AL |
2009 | DEFINE_PROP_END_OF_LIST(), |
2010 | }; | |
2011 | ||
8f04ee08 AL |
2012 | static void isabus_fdc_class_init1(ObjectClass *klass, void *data) |
2013 | { | |
39bffca2 | 2014 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
2015 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
2016 | ic->init = isabus_fdc_init1; | |
39bffca2 AL |
2017 | dc->fw_name = "fdc"; |
2018 | dc->no_user = 1; | |
2019 | dc->reset = fdctrl_external_reset_isa; | |
2020 | dc->vmsd = &vmstate_isa_fdc; | |
2021 | dc->props = isa_fdc_properties; | |
2022 | } | |
2023 | ||
2024 | static TypeInfo isa_fdc_info = { | |
2025 | .name = "isa-fdc", | |
2026 | .parent = TYPE_ISA_DEVICE, | |
2027 | .instance_size = sizeof(FDCtrlISABus), | |
2028 | .class_init = isabus_fdc_class_init1, | |
8baf73ad GH |
2029 | }; |
2030 | ||
a64405d1 JK |
2031 | static const VMStateDescription vmstate_sysbus_fdc ={ |
2032 | .name = "fdc", | |
2033 | .version_id = 2, | |
2034 | .minimum_version_id = 2, | |
2035 | .fields = (VMStateField []) { | |
2036 | VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), | |
2037 | VMSTATE_END_OF_LIST() | |
2038 | } | |
2039 | }; | |
2040 | ||
999e12bb AL |
2041 | static Property sysbus_fdc_properties[] = { |
2042 | DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), | |
2043 | DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), | |
2044 | DEFINE_PROP_END_OF_LIST(), | |
12a71a02 BS |
2045 | }; |
2046 | ||
999e12bb AL |
2047 | static void sysbus_fdc_class_init(ObjectClass *klass, void *data) |
2048 | { | |
39bffca2 | 2049 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
2050 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
2051 | ||
2052 | k->init = sysbus_fdc_init1; | |
39bffca2 AL |
2053 | dc->reset = fdctrl_external_reset_sysbus; |
2054 | dc->vmsd = &vmstate_sysbus_fdc; | |
2055 | dc->props = sysbus_fdc_properties; | |
999e12bb AL |
2056 | } |
2057 | ||
39bffca2 AL |
2058 | static TypeInfo sysbus_fdc_info = { |
2059 | .name = "sysbus-fdc", | |
2060 | .parent = TYPE_SYS_BUS_DEVICE, | |
2061 | .instance_size = sizeof(FDCtrlSysBus), | |
2062 | .class_init = sysbus_fdc_class_init, | |
999e12bb AL |
2063 | }; |
2064 | ||
2065 | static Property sun4m_fdc_properties[] = { | |
2066 | DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), | |
2067 | DEFINE_PROP_END_OF_LIST(), | |
2068 | }; | |
2069 | ||
2070 | static void sun4m_fdc_class_init(ObjectClass *klass, void *data) | |
2071 | { | |
39bffca2 | 2072 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
2073 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
2074 | ||
2075 | k->init = sun4m_fdc_init1; | |
39bffca2 AL |
2076 | dc->reset = fdctrl_external_reset_sysbus; |
2077 | dc->vmsd = &vmstate_sysbus_fdc; | |
2078 | dc->props = sun4m_fdc_properties; | |
999e12bb AL |
2079 | } |
2080 | ||
39bffca2 AL |
2081 | static TypeInfo sun4m_fdc_info = { |
2082 | .name = "SUNW,fdtwo", | |
2083 | .parent = TYPE_SYS_BUS_DEVICE, | |
2084 | .instance_size = sizeof(FDCtrlSysBus), | |
2085 | .class_init = sun4m_fdc_class_init, | |
f64ab228 BS |
2086 | }; |
2087 | ||
83f7d43a | 2088 | static void fdc_register_types(void) |
f64ab228 | 2089 | { |
39bffca2 AL |
2090 | type_register_static(&isa_fdc_info); |
2091 | type_register_static(&sysbus_fdc_info); | |
2092 | type_register_static(&sun4m_fdc_info); | |
f64ab228 BS |
2093 | } |
2094 | ||
83f7d43a | 2095 | type_init(fdc_register_types) |